1 /* 2 * Copyright 2018-2024 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_discovery.h" 28 #include "soc15_hw_ip.h" 29 #include "discovery.h" 30 #include "amdgpu_ras.h" 31 32 #include "soc15.h" 33 #include "gfx_v9_0.h" 34 #include "gfx_v9_4_3.h" 35 #include "gmc_v9_0.h" 36 #include "df_v1_7.h" 37 #include "df_v3_6.h" 38 #include "df_v4_3.h" 39 #include "df_v4_6_2.h" 40 #include "df_v4_15.h" 41 #include "nbio_v6_1.h" 42 #include "nbio_v7_0.h" 43 #include "nbio_v7_4.h" 44 #include "nbio_v7_9.h" 45 #include "nbio_v7_11.h" 46 #include "hdp_v4_0.h" 47 #include "vega10_ih.h" 48 #include "vega20_ih.h" 49 #include "sdma_v4_0.h" 50 #include "sdma_v4_4_2.h" 51 #include "uvd_v7_0.h" 52 #include "vce_v4_0.h" 53 #include "vcn_v1_0.h" 54 #include "vcn_v2_5.h" 55 #include "jpeg_v2_5.h" 56 #include "smuio_v9_0.h" 57 #include "gmc_v10_0.h" 58 #include "gmc_v11_0.h" 59 #include "gmc_v12_0.h" 60 #include "gfxhub_v2_0.h" 61 #include "mmhub_v2_0.h" 62 #include "nbio_v2_3.h" 63 #include "nbio_v4_3.h" 64 #include "nbio_v7_2.h" 65 #include "nbio_v7_7.h" 66 #include "nbif_v6_3_1.h" 67 #include "nbio_v6_3_2.h" 68 #include "hdp_v5_0.h" 69 #include "hdp_v5_2.h" 70 #include "hdp_v6_0.h" 71 #include "hdp_v7_0.h" 72 #include "nv.h" 73 #include "soc21.h" 74 #include "soc24.h" 75 #include "soc_v1_0.h" 76 #include "navi10_ih.h" 77 #include "ih_v6_0.h" 78 #include "ih_v6_1.h" 79 #include "ih_v7_0.h" 80 #include "gfx_v10_0.h" 81 #include "gfx_v11_0.h" 82 #include "gfx_v12_0.h" 83 #include "gfx_v12_1.h" 84 #include "sdma_v5_0.h" 85 #include "sdma_v5_2.h" 86 #include "sdma_v6_0.h" 87 #include "sdma_v7_0.h" 88 #include "sdma_v7_1.h" 89 #include "lsdma_v6_0.h" 90 #include "lsdma_v7_0.h" 91 #include "lsdma_v7_1.h" 92 #include "vcn_v2_0.h" 93 #include "jpeg_v2_0.h" 94 #include "vcn_v3_0.h" 95 #include "jpeg_v3_0.h" 96 #include "vcn_v4_0.h" 97 #include "jpeg_v4_0.h" 98 #include "vcn_v4_0_3.h" 99 #include "jpeg_v4_0_3.h" 100 #include "vcn_v4_0_5.h" 101 #include "jpeg_v4_0_5.h" 102 #include "amdgpu_vkms.h" 103 #include "mes_v11_0.h" 104 #include "mes_v12_0.h" 105 #include "mes_v12_1.h" 106 #include "smuio_v11_0.h" 107 #include "smuio_v11_0_6.h" 108 #include "smuio_v13_0.h" 109 #include "smuio_v13_0_3.h" 110 #include "smuio_v13_0_6.h" 111 #include "smuio_v14_0_2.h" 112 #include "smuio_v15_0_0.h" 113 #include "smuio_v15_0_8.h" 114 #include "vcn_v5_0_0.h" 115 #include "vcn_v5_0_1.h" 116 #include "vcn_v5_0_2.h" 117 #include "jpeg_v5_0_0.h" 118 #include "jpeg_v5_0_1.h" 119 #include "jpeg_v5_0_2.h" 120 #include "jpeg_v5_3_0.h" 121 122 #include "amdgpu_ras_mgr.h" 123 124 #include "amdgpu_vpe.h" 125 #if defined(CONFIG_DRM_AMD_ISP) 126 #include "amdgpu_isp.h" 127 #endif 128 129 MODULE_FIRMWARE("amdgpu/ip_discovery.bin"); 130 MODULE_FIRMWARE("amdgpu/vega10_ip_discovery.bin"); 131 MODULE_FIRMWARE("amdgpu/vega12_ip_discovery.bin"); 132 MODULE_FIRMWARE("amdgpu/vega20_ip_discovery.bin"); 133 MODULE_FIRMWARE("amdgpu/raven_ip_discovery.bin"); 134 MODULE_FIRMWARE("amdgpu/raven2_ip_discovery.bin"); 135 MODULE_FIRMWARE("amdgpu/picasso_ip_discovery.bin"); 136 MODULE_FIRMWARE("amdgpu/arcturus_ip_discovery.bin"); 137 MODULE_FIRMWARE("amdgpu/aldebaran_ip_discovery.bin"); 138 139 /* Note: These registers are consistent across all the SOCs */ 140 #define mmIP_DISCOVERY_VERSION 0x16A00 141 #define mmRCC_CONFIG_MEMSIZE 0xde3 142 #define mmMP0_SMN_C2PMSG_33 0x16061 143 #define mmMM_INDEX 0x0 144 #define mmMM_INDEX_HI 0x6 145 #define mmMM_DATA 0x1 146 147 #define mmDRIVER_SCRATCH_0 0x94 148 #define mmDRIVER_SCRATCH_1 0x95 149 #define mmDRIVER_SCRATCH_2 0x96 150 151 static const char *hw_id_names[HW_ID_MAX] = { 152 [MP1_HWID] = "MP1", 153 [MP2_HWID] = "MP2", 154 [THM_HWID] = "THM", 155 [SMUIO_HWID] = "SMUIO", 156 [FUSE_HWID] = "FUSE", 157 [CLKA_HWID] = "CLKA", 158 [PWR_HWID] = "PWR", 159 [GC_HWID] = "GC", 160 [UVD_HWID] = "UVD", 161 [AUDIO_AZ_HWID] = "AUDIO_AZ", 162 [ACP_HWID] = "ACP", 163 [DCI_HWID] = "DCI", 164 [DMU_HWID] = "DMU", 165 [DCO_HWID] = "DCO", 166 [DIO_HWID] = "DIO", 167 [XDMA_HWID] = "XDMA", 168 [DCEAZ_HWID] = "DCEAZ", 169 [DAZ_HWID] = "DAZ", 170 [SDPMUX_HWID] = "SDPMUX", 171 [NTB_HWID] = "NTB", 172 [IOHC_HWID] = "IOHC", 173 [L2IMU_HWID] = "L2IMU", 174 [VCE_HWID] = "VCE", 175 [MMHUB_HWID] = "MMHUB", 176 [ATHUB_HWID] = "ATHUB", 177 [DBGU_NBIO_HWID] = "DBGU_NBIO", 178 [DFX_HWID] = "DFX", 179 [DBGU0_HWID] = "DBGU0", 180 [DBGU1_HWID] = "DBGU1", 181 [OSSSYS_HWID] = "OSSSYS", 182 [HDP_HWID] = "HDP", 183 [SDMA0_HWID] = "SDMA0", 184 [SDMA1_HWID] = "SDMA1", 185 [SDMA2_HWID] = "SDMA2", 186 [SDMA3_HWID] = "SDMA3", 187 [LSDMA_HWID] = "LSDMA", 188 [ISP_HWID] = "ISP", 189 [DBGU_IO_HWID] = "DBGU_IO", 190 [DF_HWID] = "DF", 191 [CLKB_HWID] = "CLKB", 192 [FCH_HWID] = "FCH", 193 [DFX_DAP_HWID] = "DFX_DAP", 194 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 195 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 196 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 197 [L1IMU3_HWID] = "L1IMU3", 198 [L1IMU4_HWID] = "L1IMU4", 199 [L1IMU5_HWID] = "L1IMU5", 200 [L1IMU6_HWID] = "L1IMU6", 201 [L1IMU7_HWID] = "L1IMU7", 202 [L1IMU8_HWID] = "L1IMU8", 203 [L1IMU9_HWID] = "L1IMU9", 204 [L1IMU10_HWID] = "L1IMU10", 205 [L1IMU11_HWID] = "L1IMU11", 206 [L1IMU12_HWID] = "L1IMU12", 207 [L1IMU13_HWID] = "L1IMU13", 208 [L1IMU14_HWID] = "L1IMU14", 209 [L1IMU15_HWID] = "L1IMU15", 210 [WAFLC_HWID] = "WAFLC", 211 [FCH_USB_PD_HWID] = "FCH_USB_PD", 212 [PCIE_HWID] = "PCIE", 213 [PCS_HWID] = "PCS", 214 [DDCL_HWID] = "DDCL", 215 [SST_HWID] = "SST", 216 [IOAGR_HWID] = "IOAGR", 217 [NBIF_HWID] = "NBIF", 218 [IOAPIC_HWID] = "IOAPIC", 219 [SYSTEMHUB_HWID] = "SYSTEMHUB", 220 [NTBCCP_HWID] = "NTBCCP", 221 [UMC_HWID] = "UMC", 222 [SATA_HWID] = "SATA", 223 [USB_HWID] = "USB", 224 [CCXSEC_HWID] = "CCXSEC", 225 [XGMI_HWID] = "XGMI", 226 [XGBE_HWID] = "XGBE", 227 [MP0_HWID] = "MP0", 228 [VPE_HWID] = "VPE", 229 [ATU_HWID] = "ATU", 230 [AIGC_HWID] = "AIGC", 231 }; 232 233 static int hw_id_map[MAX_HWIP] = { 234 [GC_HWIP] = GC_HWID, 235 [HDP_HWIP] = HDP_HWID, 236 [SDMA0_HWIP] = SDMA0_HWID, 237 [SDMA1_HWIP] = SDMA1_HWID, 238 [SDMA2_HWIP] = SDMA2_HWID, 239 [SDMA3_HWIP] = SDMA3_HWID, 240 [LSDMA_HWIP] = LSDMA_HWID, 241 [MMHUB_HWIP] = MMHUB_HWID, 242 [ATHUB_HWIP] = ATHUB_HWID, 243 [NBIO_HWIP] = NBIF_HWID, 244 [MP0_HWIP] = MP0_HWID, 245 [MP1_HWIP] = MP1_HWID, 246 [UVD_HWIP] = UVD_HWID, 247 [VCE_HWIP] = VCE_HWID, 248 [DF_HWIP] = DF_HWID, 249 [DCE_HWIP] = DMU_HWID, 250 [OSSSYS_HWIP] = OSSSYS_HWID, 251 [SMUIO_HWIP] = SMUIO_HWID, 252 [PWR_HWIP] = PWR_HWID, 253 [NBIF_HWIP] = NBIF_HWID, 254 [THM_HWIP] = THM_HWID, 255 [CLK_HWIP] = CLKA_HWID, 256 [UMC_HWIP] = UMC_HWID, 257 [XGMI_HWIP] = XGMI_HWID, 258 [DCI_HWIP] = DCI_HWID, 259 [PCIE_HWIP] = PCIE_HWID, 260 [VPE_HWIP] = VPE_HWID, 261 [ISP_HWIP] = ISP_HWID, 262 [ATU_HWIP] = ATU_HWID, 263 }; 264 265 static int amdgpu_discovery_get_tmr_info(struct amdgpu_device *adev, 266 bool *is_tmr_in_sysmem) 267 { 268 u64 vram_size, tmr_offset, tmr_size; 269 u32 msg, tmr_offset_lo, tmr_offset_hi; 270 int i, ret; 271 272 if (!amdgpu_sriov_vf(adev)) { 273 /* It can take up to two second for IFWI init to complete on some dGPUs, 274 * but generally it should be in the 60-100ms range. Normally this starts 275 * as soon as the device gets power so by the time the OS loads this has long 276 * completed. However, when a card is hotplugged via e.g., USB4, we need to 277 * wait for this to complete. Once the C2PMSG is updated, we can 278 * continue. 279 */ 280 281 for (i = 0; i < 2000; i++) { 282 msg = RREG32(mmMP0_SMN_C2PMSG_33); 283 if (msg & 0x80000000) 284 break; 285 msleep(1); 286 } 287 } 288 289 vram_size = RREG32(mmRCC_CONFIG_MEMSIZE); 290 if (vram_size == U32_MAX) 291 return -ENXIO; 292 else if (!vram_size) 293 *is_tmr_in_sysmem = true; 294 else 295 *is_tmr_in_sysmem = false; 296 297 /* init the default tmr size and offset */ 298 adev->discovery.size = DISCOVERY_TMR_SIZE; 299 if (vram_size) 300 adev->discovery.offset = (vram_size << 20) - DISCOVERY_TMR_OFFSET; 301 302 if (amdgpu_sriov_vf(adev)) { 303 if (adev->virt.is_dynamic_crit_regn_enabled) { 304 adev->discovery.offset = 305 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].offset; 306 adev->discovery.size = 307 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].size_kb << 10; 308 if (!adev->discovery.size) 309 return -EINVAL; 310 } else { 311 goto out; 312 } 313 } else { 314 tmr_size = RREG32(mmDRIVER_SCRATCH_2); 315 if (tmr_size) { 316 /* It's preferred to transition to PSP mailbox reg interface 317 * for both bare-metal and passthrough if available */ 318 adev->discovery.size = (u32)tmr_size; 319 tmr_offset_lo = RREG32(mmDRIVER_SCRATCH_0); 320 tmr_offset_hi = RREG32(mmDRIVER_SCRATCH_1); 321 adev->discovery.offset = ((u64)le32_to_cpu(tmr_offset_hi) << 32 | 322 le32_to_cpu(tmr_offset_lo)); 323 } else if (!vram_size) { 324 /* fall back to apci approach to query tmr offset if vram_size is 0 */ 325 ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size); 326 if (ret) 327 return ret; 328 adev->discovery.size = DISCOVERY_TMR_SIZE; 329 adev->discovery.offset = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET; 330 } 331 } 332 out: 333 adev->discovery.bin = kzalloc(adev->discovery.size, GFP_KERNEL); 334 if (!adev->discovery.bin) 335 return -ENOMEM; 336 adev->discovery.debugfs_blob.data = adev->discovery.bin; 337 adev->discovery.debugfs_blob.size = adev->discovery.size; 338 339 return 0; 340 } 341 342 static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary) 343 { 344 void *discv_regn; 345 346 /* This region is read-only and reserved from system use */ 347 discv_regn = memremap(adev->discovery.offset, adev->discovery.size, MEMREMAP_WC); 348 if (discv_regn) { 349 memcpy(binary, discv_regn, adev->discovery.size); 350 memunmap(discv_regn); 351 return 0; 352 } 353 354 return -ENOENT; 355 } 356 357 #define IP_DISCOVERY_V2 2 358 #define IP_DISCOVERY_V4 4 359 360 static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, 361 uint8_t *binary, 362 bool is_tmr_in_sysmem) 363 { 364 int ret = 0; 365 366 if (!is_tmr_in_sysmem) { 367 if (amdgpu_sriov_vf(adev) && 368 amdgpu_sriov_xgmi_connected_to_cpu(adev)) { 369 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); 370 } else { 371 amdgpu_device_vram_access(adev, adev->discovery.offset, 372 (uint32_t *)binary, 373 adev->discovery.size, false); 374 adev->discovery.reserve_tmr = true; 375 } 376 } else { 377 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); 378 } 379 380 return ret; 381 } 382 383 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, 384 uint8_t *binary, 385 const char *fw_name) 386 { 387 const struct firmware *fw; 388 int r; 389 390 r = firmware_request_nowarn(&fw, fw_name, adev->dev); 391 if (r) { 392 if (amdgpu_discovery == 2) 393 dev_err(adev->dev, "can't load firmware \"%s\"\n", fw_name); 394 else 395 drm_info(&adev->ddev, "Optional firmware \"%s\" was not found\n", fw_name); 396 return r; 397 } 398 399 memcpy((u8 *)binary, (u8 *)fw->data, fw->size); 400 release_firmware(fw); 401 402 return 0; 403 } 404 405 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 406 { 407 uint16_t checksum = 0; 408 int i; 409 410 for (i = 0; i < size; i++) 411 checksum += data[i]; 412 413 return checksum; 414 } 415 416 static inline bool amdgpu_discovery_verify_checksum(struct amdgpu_device *adev, 417 uint8_t *data, uint32_t size, 418 uint16_t expected) 419 { 420 uint16_t calculated; 421 422 calculated = amdgpu_discovery_calculate_checksum(data, size); 423 424 if (calculated != expected) { 425 dev_err(adev->dev, "Discovery checksum failed: calc 0x%04x != exp 0x%04x, size %u.\n", 426 calculated, expected, size); 427 return false; 428 } 429 430 return true; 431 } 432 433 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 434 { 435 struct binary_header *bhdr; 436 bhdr = (struct binary_header *)binary; 437 438 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 439 } 440 441 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) 442 { 443 /* 444 * So far, apply this quirk only on those Navy Flounder boards which 445 * have a bad harvest table of VCN config. 446 */ 447 if ((amdgpu_ip_version(adev, UVD_HWIP, 1) == IP_VERSION(3, 0, 1)) && 448 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 2))) { 449 switch (adev->pdev->revision) { 450 case 0xC1: 451 case 0xC2: 452 case 0xC3: 453 case 0xC5: 454 case 0xC7: 455 case 0xCF: 456 case 0xDF: 457 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 458 adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1; 459 break; 460 default: 461 break; 462 } 463 } 464 } 465 466 static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev, 467 struct table_info *info) 468 { 469 uint8_t *discovery_bin = adev->discovery.bin; 470 uint16_t checksum; 471 uint16_t offset; 472 473 offset = le16_to_cpu(info->offset); 474 checksum = le16_to_cpu(info->checksum); 475 476 struct nps_info_header *nhdr = 477 (struct nps_info_header *)(discovery_bin + offset); 478 479 if (le32_to_cpu(nhdr->table_id) != NPS_INFO_TABLE_ID) { 480 dev_dbg(adev->dev, "invalid ip discovery nps info table id\n"); 481 return -EINVAL; 482 } 483 484 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, 485 le32_to_cpu(nhdr->size_bytes), 486 checksum)) { 487 dev_dbg(adev->dev, "invalid nps info data table checksum\n"); 488 return -EINVAL; 489 } 490 491 return 0; 492 } 493 494 static const char *amdgpu_discovery_get_fw_name(struct amdgpu_device *adev) 495 { 496 if (amdgpu_discovery == 2) { 497 /* Assume there is valid discovery TMR in VRAM even if binary is sideloaded */ 498 adev->discovery.reserve_tmr = true; 499 return "amdgpu/ip_discovery.bin"; 500 } 501 502 switch (adev->asic_type) { 503 case CHIP_VEGA10: 504 return "amdgpu/vega10_ip_discovery.bin"; 505 case CHIP_VEGA12: 506 return "amdgpu/vega12_ip_discovery.bin"; 507 case CHIP_RAVEN: 508 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 509 return "amdgpu/raven2_ip_discovery.bin"; 510 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 511 return "amdgpu/picasso_ip_discovery.bin"; 512 else 513 return "amdgpu/raven_ip_discovery.bin"; 514 case CHIP_VEGA20: 515 return "amdgpu/vega20_ip_discovery.bin"; 516 case CHIP_ARCTURUS: 517 return "amdgpu/arcturus_ip_discovery.bin"; 518 case CHIP_ALDEBARAN: 519 return "amdgpu/aldebaran_ip_discovery.bin"; 520 default: 521 return NULL; 522 } 523 } 524 525 static int amdgpu_discovery_get_table_info(struct amdgpu_device *adev, 526 struct table_info **info, 527 uint16_t table_id) 528 { 529 struct binary_header *bhdr = 530 (struct binary_header *)adev->discovery.bin; 531 struct binary_header_v2 *bhdrv2; 532 533 switch (bhdr->version_major) { 534 case 2: 535 bhdrv2 = (struct binary_header_v2 *)adev->discovery.bin; 536 *info = &bhdrv2->table_list[table_id]; 537 break; 538 case 1: 539 case 0: 540 *info = &bhdr->table_list[table_id]; 541 break; 542 default: 543 dev_err(adev->dev, "Invalid ip discovery table version %d\n",bhdr->version_major); 544 return -EINVAL; 545 } 546 547 return 0; 548 } 549 550 static int amdgpu_discovery_table_check(struct amdgpu_device *adev, 551 uint8_t *discovery_bin, 552 uint16_t table_id) 553 { 554 int r, act_val, exp_val, table_size; 555 uint16_t offset, checksum; 556 struct table_info *info; 557 bool check_table = true; 558 char *table_name; 559 560 r = amdgpu_discovery_get_table_info(adev, &info, table_id); 561 if (r) 562 return r; 563 offset = le16_to_cpu(info->offset); 564 checksum = le16_to_cpu(info->checksum); 565 566 switch (table_id) { 567 case IP_DISCOVERY: { 568 struct ip_discovery_header *ihdr = 569 (struct ip_discovery_header *)(discovery_bin + offset); 570 act_val = le32_to_cpu(ihdr->signature); 571 exp_val = DISCOVERY_TABLE_SIGNATURE; 572 table_size = le16_to_cpu(ihdr->size); 573 table_name = "data table"; 574 break; 575 } 576 case GC: { 577 struct gpu_info_header *ghdr = 578 (struct gpu_info_header *)(discovery_bin + offset); 579 act_val = le32_to_cpu(ghdr->table_id); 580 exp_val = GC_TABLE_ID; 581 table_size = le16_to_cpu(ghdr->size); 582 table_name = "gc table"; 583 break; 584 } 585 case HARVEST_INFO: { 586 struct harvest_info_header *hhdr = 587 (struct harvest_info_header *)(discovery_bin + offset); 588 act_val = le32_to_cpu(hhdr->signature); 589 exp_val = HARVEST_TABLE_SIGNATURE; 590 table_size = sizeof(struct harvest_table); 591 table_name = "harvest table"; 592 break; 593 } 594 case VCN_INFO: { 595 struct vcn_info_header *vhdr = 596 (struct vcn_info_header *)(discovery_bin + offset); 597 act_val = le32_to_cpu(vhdr->table_id); 598 exp_val = VCN_INFO_TABLE_ID; 599 table_size = le32_to_cpu(vhdr->size_bytes); 600 table_name = "vcn table"; 601 break; 602 } 603 case MALL_INFO: { 604 struct mall_info_header *mhdr = 605 (struct mall_info_header *)(discovery_bin + offset); 606 act_val = le32_to_cpu(mhdr->table_id); 607 exp_val = MALL_INFO_TABLE_ID; 608 table_size = le32_to_cpu(mhdr->size_bytes); 609 table_name = "mall table"; 610 check_table = false; 611 break; 612 } 613 default: 614 dev_err(adev->dev, "invalid ip discovery table id %d specified\n", table_id); 615 check_table = false; 616 break; 617 } 618 619 if (check_table && offset) { 620 if (act_val != exp_val) { 621 dev_err(adev->dev, "invalid ip discovery %s signature\n", table_name); 622 return -EINVAL; 623 } 624 625 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, 626 table_size, checksum)) { 627 dev_err(adev->dev, "invalid ip discovery %s checksum\n", table_name); 628 return -EINVAL; 629 } 630 } 631 632 return 0; 633 } 634 635 static int amdgpu_discovery_init(struct amdgpu_device *adev) 636 { 637 struct binary_header *bhdr; 638 uint8_t *discovery_bin; 639 const char *fw_name; 640 uint16_t offset; 641 uint16_t size; 642 uint16_t checksum; 643 uint16_t table_id; 644 bool is_tmr_in_sysmem; 645 int r; 646 647 r = amdgpu_discovery_get_tmr_info(adev, &is_tmr_in_sysmem); 648 if (r) 649 return r; 650 651 discovery_bin = adev->discovery.bin; 652 /* Read from file if it is the preferred option */ 653 fw_name = amdgpu_discovery_get_fw_name(adev); 654 if (fw_name != NULL) { 655 drm_dbg(&adev->ddev, "use ip discovery information from file"); 656 r = amdgpu_discovery_read_binary_from_file(adev, discovery_bin, 657 fw_name); 658 if (r) 659 goto out; 660 } else { 661 drm_dbg(&adev->ddev, "use ip discovery information from memory"); 662 r = amdgpu_discovery_read_binary_from_mem(adev, discovery_bin, 663 is_tmr_in_sysmem); 664 if (r) 665 goto out; 666 } 667 668 /* check the ip discovery binary signature */ 669 if (!amdgpu_discovery_verify_binary_signature(discovery_bin)) { 670 dev_err(adev->dev, 671 "get invalid ip discovery binary signature\n"); 672 r = -EINVAL; 673 goto out; 674 } 675 676 bhdr = (struct binary_header *)discovery_bin; 677 678 offset = offsetof(struct binary_header, binary_checksum) + 679 sizeof(bhdr->binary_checksum); 680 size = le16_to_cpu(bhdr->binary_size) - offset; 681 checksum = le16_to_cpu(bhdr->binary_checksum); 682 683 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, size, 684 checksum)) { 685 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 686 r = -EINVAL; 687 goto out; 688 } 689 690 for (table_id = 0; table_id <= MALL_INFO; table_id++) { 691 r = amdgpu_discovery_table_check(adev, discovery_bin, table_id); 692 if (r) 693 goto out; 694 } 695 696 return 0; 697 698 out: 699 kfree(adev->discovery.bin); 700 adev->discovery.bin = NULL; 701 if ((amdgpu_discovery != 2) && 702 (RREG32(mmIP_DISCOVERY_VERSION) == 4)) 703 amdgpu_ras_query_boot_status(adev, 4); 704 return r; 705 } 706 707 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev); 708 709 void amdgpu_discovery_fini(struct amdgpu_device *adev) 710 { 711 amdgpu_discovery_sysfs_fini(adev); 712 kfree(adev->discovery.bin); 713 adev->discovery.bin = NULL; 714 } 715 716 static int amdgpu_discovery_validate_ip(struct amdgpu_device *adev, 717 uint8_t instance, uint16_t hw_id) 718 { 719 if (instance >= HWIP_MAX_INSTANCE) { 720 dev_err(adev->dev, 721 "Unexpected instance_number (%d) from ip discovery blob\n", 722 instance); 723 return -EINVAL; 724 } 725 if (hw_id >= HW_ID_MAX) { 726 dev_err(adev->dev, 727 "Unexpected hw_id (%d) from ip discovery blob\n", 728 hw_id); 729 return -EINVAL; 730 } 731 732 return 0; 733 } 734 735 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev, 736 uint32_t *vcn_harvest_count) 737 { 738 uint8_t *discovery_bin = adev->discovery.bin; 739 struct binary_header *bhdr; 740 struct ip_discovery_header *ihdr; 741 struct die_header *dhdr; 742 struct ip *ip; 743 uint16_t die_offset, ip_offset, num_dies, num_ips; 744 uint16_t hw_id; 745 uint8_t inst; 746 int i, j; 747 748 bhdr = (struct binary_header *)discovery_bin; 749 ihdr = (struct ip_discovery_header 750 *)(discovery_bin + 751 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 752 num_dies = le16_to_cpu(ihdr->num_dies); 753 754 /* scan harvest bit of all IP data structures */ 755 for (i = 0; i < num_dies; i++) { 756 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 757 dhdr = (struct die_header *)(discovery_bin + die_offset); 758 num_ips = le16_to_cpu(dhdr->num_ips); 759 ip_offset = die_offset + sizeof(*dhdr); 760 761 for (j = 0; j < num_ips; j++) { 762 ip = (struct ip *)(discovery_bin + ip_offset); 763 inst = ip->number_instance; 764 hw_id = le16_to_cpu(ip->hw_id); 765 if (amdgpu_discovery_validate_ip(adev, inst, hw_id)) 766 goto next_ip; 767 768 if (ip->harvest == 1) { 769 switch (hw_id) { 770 case VCN_HWID: 771 (*vcn_harvest_count)++; 772 if (inst == 0) { 773 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 774 adev->vcn.inst_mask &= 775 ~AMDGPU_VCN_HARVEST_VCN0; 776 adev->jpeg.inst_mask &= 777 ~AMDGPU_VCN_HARVEST_VCN0; 778 } else { 779 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 780 adev->vcn.inst_mask &= 781 ~AMDGPU_VCN_HARVEST_VCN1; 782 adev->jpeg.inst_mask &= 783 ~AMDGPU_VCN_HARVEST_VCN1; 784 } 785 break; 786 case DMU_HWID: 787 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 788 break; 789 default: 790 break; 791 } 792 } 793 next_ip: 794 ip_offset += struct_size(ip, base_address, 795 ip->num_base_address); 796 } 797 } 798 } 799 800 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, 801 uint32_t *vcn_harvest_count, 802 uint32_t *umc_harvest_count) 803 { 804 uint8_t *discovery_bin = adev->discovery.bin; 805 struct table_info *info; 806 struct harvest_table *harvest_info; 807 u16 offset; 808 int i; 809 u64 umc_harvest_config = 0; 810 811 if (amdgpu_discovery_get_table_info(adev, &info, HARVEST_INFO)) 812 return; 813 offset = le16_to_cpu(info->offset); 814 815 if (!offset) { 816 dev_err(adev->dev, "invalid harvest table offset\n"); 817 return; 818 } 819 820 harvest_info = (struct harvest_table *)(discovery_bin + offset); 821 822 for (i = 0; i < 32; i++) { 823 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) 824 break; 825 826 switch (le16_to_cpu(harvest_info->list[i].hw_id)) { 827 case VCN_HWID: 828 (*vcn_harvest_count)++; 829 adev->vcn.harvest_config |= 830 (1 << harvest_info->list[i].number_instance); 831 adev->jpeg.harvest_config |= 832 (1 << harvest_info->list[i].number_instance); 833 834 adev->vcn.inst_mask &= 835 ~(1U << harvest_info->list[i].number_instance); 836 adev->jpeg.inst_mask &= 837 ~(1U << harvest_info->list[i].number_instance); 838 break; 839 case DMU_HWID: 840 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 841 break; 842 case UMC_HWID: 843 umc_harvest_config |= 844 1 << (le16_to_cpu(harvest_info->list[i].number_instance)); 845 (*umc_harvest_count)++; 846 break; 847 case GC_HWID: 848 adev->gfx.xcc_mask &= 849 ~(1U << harvest_info->list[i].number_instance); 850 break; 851 case SDMA0_HWID: 852 adev->sdma.sdma_mask &= 853 ~(1U << harvest_info->list[i].number_instance); 854 break; 855 #if defined(CONFIG_DRM_AMD_ISP) 856 case ISP_HWID: 857 adev->isp.harvest_config |= 858 ~(1U << harvest_info->list[i].number_instance); 859 break; 860 #endif 861 default: 862 break; 863 } 864 } 865 866 adev->umc.active_mask = ((1ULL << adev->umc.node_inst_num) - 1ULL) & 867 ~umc_harvest_config; 868 } 869 870 /* ================================================== */ 871 872 struct ip_hw_instance { 873 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */ 874 875 int hw_id; 876 u8 num_instance; 877 u8 major, minor, revision; 878 u8 harvest; 879 880 int num_base_addresses; 881 u32 base_addr[] __counted_by(num_base_addresses); 882 }; 883 884 struct ip_hw_id { 885 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */ 886 int hw_id; 887 }; 888 889 struct ip_die_entry { 890 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */ 891 u16 num_ips; 892 }; 893 894 /* -------------------------------------------------- */ 895 896 struct ip_hw_instance_attr { 897 struct attribute attr; 898 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf); 899 }; 900 901 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf) 902 { 903 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id); 904 } 905 906 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf) 907 { 908 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance); 909 } 910 911 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf) 912 { 913 return sysfs_emit(buf, "%d\n", ip_hw_instance->major); 914 } 915 916 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf) 917 { 918 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor); 919 } 920 921 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf) 922 { 923 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision); 924 } 925 926 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf) 927 { 928 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest); 929 } 930 931 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf) 932 { 933 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses); 934 } 935 936 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) 937 { 938 ssize_t at; 939 int ii; 940 941 for (at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 942 /* Here we satisfy the condition that, at + size <= PAGE_SIZE. 943 */ 944 if (at + 12 > PAGE_SIZE) 945 break; 946 at += sysfs_emit_at(buf, at, "0x%08X\n", 947 ip_hw_instance->base_addr[ii]); 948 } 949 950 return at; 951 } 952 953 static struct ip_hw_instance_attr ip_hw_attr[] = { 954 __ATTR_RO(hw_id), 955 __ATTR_RO(num_instance), 956 __ATTR_RO(major), 957 __ATTR_RO(minor), 958 __ATTR_RO(revision), 959 __ATTR_RO(harvest), 960 __ATTR_RO(num_base_addresses), 961 __ATTR_RO(base_addr), 962 }; 963 964 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; 965 ATTRIBUTE_GROUPS(ip_hw_instance); 966 967 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) 968 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) 969 970 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj, 971 struct attribute *attr, 972 char *buf) 973 { 974 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 975 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr); 976 977 if (!ip_hw_attr->show) 978 return -EIO; 979 980 return ip_hw_attr->show(ip_hw_instance, buf); 981 } 982 983 static const struct sysfs_ops ip_hw_instance_sysfs_ops = { 984 .show = ip_hw_instance_attr_show, 985 }; 986 987 static void ip_hw_instance_release(struct kobject *kobj) 988 { 989 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 990 991 kfree(ip_hw_instance); 992 } 993 994 static const struct kobj_type ip_hw_instance_ktype = { 995 .release = ip_hw_instance_release, 996 .sysfs_ops = &ip_hw_instance_sysfs_ops, 997 .default_groups = ip_hw_instance_groups, 998 }; 999 1000 /* -------------------------------------------------- */ 1001 1002 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset) 1003 1004 static void ip_hw_id_release(struct kobject *kobj) 1005 { 1006 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj); 1007 1008 if (!list_empty(&ip_hw_id->hw_id_kset.list)) 1009 DRM_ERROR("ip_hw_id->hw_id_kset is not empty"); 1010 kfree(ip_hw_id); 1011 } 1012 1013 static const struct kobj_type ip_hw_id_ktype = { 1014 .release = ip_hw_id_release, 1015 .sysfs_ops = &kobj_sysfs_ops, 1016 }; 1017 1018 /* -------------------------------------------------- */ 1019 1020 static void die_kobj_release(struct kobject *kobj); 1021 static void ip_disc_release(struct kobject *kobj); 1022 1023 struct ip_die_entry_attribute { 1024 struct attribute attr; 1025 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf); 1026 }; 1027 1028 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr) 1029 1030 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf) 1031 { 1032 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips); 1033 } 1034 1035 /* If there are more ip_die_entry attrs, other than the number of IPs, 1036 * we can make this intro an array of attrs, and then initialize 1037 * ip_die_entry_attrs in a loop. 1038 */ 1039 static struct ip_die_entry_attribute num_ips_attr = 1040 __ATTR_RO(num_ips); 1041 1042 static struct attribute *ip_die_entry_attrs[] = { 1043 &num_ips_attr.attr, 1044 NULL, 1045 }; 1046 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ 1047 1048 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) 1049 1050 static ssize_t ip_die_entry_attr_show(struct kobject *kobj, 1051 struct attribute *attr, 1052 char *buf) 1053 { 1054 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr); 1055 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 1056 1057 if (!ip_die_entry_attr->show) 1058 return -EIO; 1059 1060 return ip_die_entry_attr->show(ip_die_entry, buf); 1061 } 1062 1063 static void ip_die_entry_release(struct kobject *kobj) 1064 { 1065 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 1066 1067 if (!list_empty(&ip_die_entry->ip_kset.list)) 1068 DRM_ERROR("ip_die_entry->ip_kset is not empty"); 1069 kfree(ip_die_entry); 1070 } 1071 1072 static const struct sysfs_ops ip_die_entry_sysfs_ops = { 1073 .show = ip_die_entry_attr_show, 1074 }; 1075 1076 static const struct kobj_type ip_die_entry_ktype = { 1077 .release = ip_die_entry_release, 1078 .sysfs_ops = &ip_die_entry_sysfs_ops, 1079 .default_groups = ip_die_entry_groups, 1080 }; 1081 1082 static const struct kobj_type die_kobj_ktype = { 1083 .release = die_kobj_release, 1084 .sysfs_ops = &kobj_sysfs_ops, 1085 }; 1086 1087 static const struct kobj_type ip_discovery_ktype = { 1088 .release = ip_disc_release, 1089 .sysfs_ops = &kobj_sysfs_ops, 1090 }; 1091 1092 struct ip_discovery_top { 1093 struct kobject kobj; /* ip_discovery/ */ 1094 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */ 1095 struct amdgpu_device *adev; 1096 }; 1097 1098 static void die_kobj_release(struct kobject *kobj) 1099 { 1100 struct ip_discovery_top *ip_top = container_of(to_kset(kobj), 1101 struct ip_discovery_top, 1102 die_kset); 1103 if (!list_empty(&ip_top->die_kset.list)) 1104 DRM_ERROR("ip_top->die_kset is not empty"); 1105 } 1106 1107 static void ip_disc_release(struct kobject *kobj) 1108 { 1109 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top, 1110 kobj); 1111 struct amdgpu_device *adev = ip_top->adev; 1112 1113 kfree(ip_top); 1114 adev->discovery.ip_top = NULL; 1115 } 1116 1117 static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev, 1118 uint16_t hw_id, uint8_t inst) 1119 { 1120 uint8_t harvest = 0; 1121 1122 /* Until a uniform way is figured, get mask based on hwid */ 1123 switch (hw_id) { 1124 case VCN_HWID: 1125 /* VCN vs UVD+VCE */ 1126 if (!amdgpu_ip_version(adev, VCE_HWIP, 0)) 1127 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0; 1128 break; 1129 case DMU_HWID: 1130 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK) 1131 harvest = 0x1; 1132 break; 1133 case UMC_HWID: 1134 /* TODO: It needs another parsing; for now, ignore.*/ 1135 break; 1136 case GC_HWID: 1137 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; 1138 break; 1139 case SDMA0_HWID: 1140 harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0; 1141 break; 1142 default: 1143 break; 1144 } 1145 1146 return harvest; 1147 } 1148 1149 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, 1150 struct ip_die_entry *ip_die_entry, 1151 const size_t _ip_offset, const int num_ips, 1152 bool reg_base_64) 1153 { 1154 uint8_t *discovery_bin = adev->discovery.bin; 1155 int ii, jj, kk, res; 1156 uint16_t hw_id; 1157 uint8_t inst; 1158 1159 DRM_DEBUG("num_ips:%d", num_ips); 1160 1161 /* Find all IPs of a given HW ID, and add their instance to 1162 * #die/#hw_id/#instance/<attributes> 1163 */ 1164 for (ii = 0; ii < HW_ID_MAX; ii++) { 1165 struct ip_hw_id *ip_hw_id = NULL; 1166 size_t ip_offset = _ip_offset; 1167 1168 for (jj = 0; jj < num_ips; jj++) { 1169 struct ip_v4 *ip; 1170 struct ip_hw_instance *ip_hw_instance; 1171 1172 ip = (struct ip_v4 *)(discovery_bin + ip_offset); 1173 inst = ip->instance_number; 1174 hw_id = le16_to_cpu(ip->hw_id); 1175 if (amdgpu_discovery_validate_ip(adev, inst, hw_id) || 1176 hw_id != ii) 1177 goto next_ip; 1178 1179 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset); 1180 1181 /* We have a hw_id match; register the hw 1182 * block if not yet registered. 1183 */ 1184 if (!ip_hw_id) { 1185 ip_hw_id = kzalloc_obj(*ip_hw_id); 1186 if (!ip_hw_id) 1187 return -ENOMEM; 1188 ip_hw_id->hw_id = ii; 1189 1190 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii); 1191 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset; 1192 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype; 1193 res = kset_register(&ip_hw_id->hw_id_kset); 1194 if (res) { 1195 DRM_ERROR("Couldn't register ip_hw_id kset"); 1196 kfree(ip_hw_id); 1197 return res; 1198 } 1199 if (hw_id_names[ii]) { 1200 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj, 1201 &ip_hw_id->hw_id_kset.kobj, 1202 hw_id_names[ii]); 1203 if (res) { 1204 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n", 1205 hw_id_names[ii], 1206 kobject_name(&ip_die_entry->ip_kset.kobj)); 1207 } 1208 } 1209 } 1210 1211 /* Now register its instance. 1212 */ 1213 ip_hw_instance = kzalloc_flex(*ip_hw_instance, 1214 base_addr, 1215 ip->num_base_address); 1216 if (!ip_hw_instance) { 1217 DRM_ERROR("no memory for ip_hw_instance"); 1218 return -ENOMEM; 1219 } 1220 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */ 1221 ip_hw_instance->num_instance = ip->instance_number; 1222 ip_hw_instance->major = ip->major; 1223 ip_hw_instance->minor = ip->minor; 1224 ip_hw_instance->revision = ip->revision; 1225 ip_hw_instance->harvest = 1226 amdgpu_discovery_get_harvest_info( 1227 adev, ip_hw_instance->hw_id, 1228 ip_hw_instance->num_instance); 1229 ip_hw_instance->num_base_addresses = ip->num_base_address; 1230 1231 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) 1232 ip_hw_instance->base_addr[kk] = ip->base_address[kk]; 1233 1234 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); 1235 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; 1236 res = kobject_add(&ip_hw_instance->kobj, NULL, 1237 "%d", ip_hw_instance->num_instance); 1238 next_ip: 1239 if (reg_base_64) 1240 ip_offset += struct_size(ip, base_address_64, 1241 ip->num_base_address); 1242 else 1243 ip_offset += struct_size(ip, base_address, 1244 ip->num_base_address); 1245 } 1246 } 1247 1248 return 0; 1249 } 1250 1251 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) 1252 { 1253 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1254 uint8_t *discovery_bin = adev->discovery.bin; 1255 struct table_info *info; 1256 struct ip_discovery_header *ihdr; 1257 struct die_header *dhdr; 1258 struct kset *die_kset = &ip_top->die_kset; 1259 u16 num_dies, die_offset, num_ips; 1260 size_t ip_offset; 1261 int ii, res; 1262 1263 res = amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY); 1264 if (res) 1265 return res; 1266 ihdr = (struct ip_discovery_header 1267 *)(discovery_bin + 1268 le16_to_cpu(info->offset)); 1269 num_dies = le16_to_cpu(ihdr->num_dies); 1270 1271 DRM_DEBUG("number of dies: %d\n", num_dies); 1272 1273 for (ii = 0; ii < num_dies; ii++) { 1274 struct ip_die_entry *ip_die_entry; 1275 1276 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); 1277 dhdr = (struct die_header *)(discovery_bin + die_offset); 1278 num_ips = le16_to_cpu(dhdr->num_ips); 1279 ip_offset = die_offset + sizeof(*dhdr); 1280 1281 /* Add the die to the kset. 1282 * 1283 * dhdr->die_id == ii, which was checked in 1284 * amdgpu_discovery_reg_base_init(). 1285 */ 1286 1287 ip_die_entry = kzalloc_obj(*ip_die_entry); 1288 if (!ip_die_entry) 1289 return -ENOMEM; 1290 1291 ip_die_entry->num_ips = num_ips; 1292 1293 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id)); 1294 ip_die_entry->ip_kset.kobj.kset = die_kset; 1295 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype; 1296 res = kset_register(&ip_die_entry->ip_kset); 1297 if (res) { 1298 DRM_ERROR("Couldn't register ip_die_entry kset"); 1299 kfree(ip_die_entry); 1300 return res; 1301 } 1302 1303 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips, !!ihdr->base_addr_64_bit); 1304 } 1305 1306 return 0; 1307 } 1308 1309 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) 1310 { 1311 uint8_t *discovery_bin = adev->discovery.bin; 1312 struct ip_discovery_top *ip_top; 1313 struct kset *die_kset; 1314 int res, ii; 1315 1316 if (!discovery_bin) 1317 return -EINVAL; 1318 1319 ip_top = kzalloc_obj(*ip_top); 1320 if (!ip_top) 1321 return -ENOMEM; 1322 1323 ip_top->adev = adev; 1324 adev->discovery.ip_top = ip_top; 1325 res = kobject_init_and_add(&ip_top->kobj, &ip_discovery_ktype, 1326 &adev->dev->kobj, "ip_discovery"); 1327 if (res) { 1328 DRM_ERROR("Couldn't init and add ip_discovery/"); 1329 goto Err; 1330 } 1331 1332 die_kset = &ip_top->die_kset; 1333 kobject_set_name(&die_kset->kobj, "%s", "die"); 1334 die_kset->kobj.parent = &ip_top->kobj; 1335 die_kset->kobj.ktype = &die_kobj_ktype; 1336 res = kset_register(&ip_top->die_kset); 1337 if (res) { 1338 DRM_ERROR("Couldn't register die_kset"); 1339 goto Err; 1340 } 1341 1342 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++) 1343 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr; 1344 ip_hw_instance_attrs[ii] = NULL; 1345 1346 res = amdgpu_discovery_sysfs_recurse(adev); 1347 1348 return res; 1349 Err: 1350 kobject_put(&ip_top->kobj); 1351 return res; 1352 } 1353 1354 /* -------------------------------------------------- */ 1355 1356 #define list_to_kobj(el) container_of(el, struct kobject, entry) 1357 1358 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id) 1359 { 1360 struct list_head *el, *tmp; 1361 struct kset *hw_id_kset; 1362 1363 hw_id_kset = &ip_hw_id->hw_id_kset; 1364 spin_lock(&hw_id_kset->list_lock); 1365 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) { 1366 list_del_init(el); 1367 spin_unlock(&hw_id_kset->list_lock); 1368 /* kobject is embedded in ip_hw_instance */ 1369 kobject_put(list_to_kobj(el)); 1370 spin_lock(&hw_id_kset->list_lock); 1371 } 1372 spin_unlock(&hw_id_kset->list_lock); 1373 kobject_put(&ip_hw_id->hw_id_kset.kobj); 1374 } 1375 1376 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry) 1377 { 1378 struct list_head *el, *tmp; 1379 struct kset *ip_kset; 1380 1381 ip_kset = &ip_die_entry->ip_kset; 1382 spin_lock(&ip_kset->list_lock); 1383 list_for_each_prev_safe(el, tmp, &ip_kset->list) { 1384 list_del_init(el); 1385 spin_unlock(&ip_kset->list_lock); 1386 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el))); 1387 spin_lock(&ip_kset->list_lock); 1388 } 1389 spin_unlock(&ip_kset->list_lock); 1390 kobject_put(&ip_die_entry->ip_kset.kobj); 1391 } 1392 1393 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) 1394 { 1395 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1396 struct list_head *el, *tmp; 1397 struct kset *die_kset; 1398 1399 if (!ip_top) 1400 return; 1401 1402 die_kset = &ip_top->die_kset; 1403 spin_lock(&die_kset->list_lock); 1404 list_for_each_prev_safe(el, tmp, &die_kset->list) { 1405 list_del_init(el); 1406 spin_unlock(&die_kset->list_lock); 1407 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 1408 spin_lock(&die_kset->list_lock); 1409 } 1410 spin_unlock(&die_kset->list_lock); 1411 kobject_put(&ip_top->die_kset.kobj); 1412 kobject_put(&ip_top->kobj); 1413 } 1414 1415 /* devcoredump support */ 1416 void amdgpu_discovery_dump(struct amdgpu_device *adev, struct drm_printer *p) 1417 { 1418 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1419 struct ip_die_entry *ip_die_entry; 1420 struct list_head *el_die, *el_hw_id, *el_hw_inst; 1421 struct ip_hw_id *hw_id; 1422 struct kset *die_kset; 1423 struct ip_hw_instance *ip_inst; 1424 int i = 0, j; 1425 1426 if (!ip_top) 1427 return; 1428 1429 die_kset = &ip_top->die_kset; 1430 1431 drm_printf(p, "\nHW IP Discovery\n"); 1432 1433 spin_lock(&die_kset->list_lock); 1434 list_for_each(el_die, &die_kset->list) { 1435 drm_printf(p, "die %d\n", i++); 1436 ip_die_entry = to_ip_die_entry(list_to_kobj(el_die)); 1437 1438 list_for_each(el_hw_id, &ip_die_entry->ip_kset.list) { 1439 hw_id = to_ip_hw_id(list_to_kobj(el_hw_id)); 1440 drm_printf(p, "hw_id %d %s\n", hw_id->hw_id, hw_id_names[hw_id->hw_id]); 1441 1442 list_for_each(el_hw_inst, &hw_id->hw_id_kset.list) { 1443 ip_inst = to_ip_hw_instance(list_to_kobj(el_hw_inst)); 1444 drm_printf(p, "\tinstance %d\n", ip_inst->num_instance); 1445 drm_printf(p, "\tmajor %d\n", ip_inst->major); 1446 drm_printf(p, "\tminor %d\n", ip_inst->minor); 1447 drm_printf(p, "\trevision %d\n", ip_inst->revision); 1448 drm_printf(p, "\tharvest 0x%01X\n", ip_inst->harvest); 1449 drm_printf(p, "\tnum_base_addresses %d\n", 1450 ip_inst->num_base_addresses); 1451 for (j = 0; j < ip_inst->num_base_addresses; j++) 1452 drm_printf(p, "\tbase_addr[%d] 0x%08X\n", 1453 j, ip_inst->base_addr[j]); 1454 } 1455 } 1456 } 1457 spin_unlock(&die_kset->list_lock); 1458 } 1459 1460 1461 /* ================================================== */ 1462 1463 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 1464 { 1465 uint8_t num_base_address, subrev, variant; 1466 struct table_info *info; 1467 struct ip_discovery_header *ihdr; 1468 struct die_header *dhdr; 1469 uint8_t *discovery_bin; 1470 struct ip_v4 *ip; 1471 uint16_t die_offset; 1472 uint16_t ip_offset; 1473 uint16_t num_dies; 1474 uint32_t wafl_ver; 1475 uint16_t num_ips; 1476 uint16_t hw_id; 1477 uint8_t inst; 1478 int hw_ip; 1479 int i, j, k; 1480 int r; 1481 1482 r = amdgpu_discovery_init(adev); 1483 if (r) 1484 return r; 1485 discovery_bin = adev->discovery.bin; 1486 wafl_ver = 0; 1487 adev->gfx.xcc_mask = 0; 1488 adev->sdma.sdma_mask = 0; 1489 adev->vcn.inst_mask = 0; 1490 adev->jpeg.inst_mask = 0; 1491 r = amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY); 1492 if (r) 1493 return r; 1494 ihdr = (struct ip_discovery_header 1495 *)(discovery_bin + 1496 le16_to_cpu(info->offset)); 1497 num_dies = le16_to_cpu(ihdr->num_dies); 1498 1499 DRM_DEBUG("number of dies: %d\n", num_dies); 1500 1501 for (i = 0; i < num_dies; i++) { 1502 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1503 dhdr = (struct die_header *)(discovery_bin + die_offset); 1504 num_ips = le16_to_cpu(dhdr->num_ips); 1505 ip_offset = die_offset + sizeof(*dhdr); 1506 1507 if (le16_to_cpu(dhdr->die_id) != i) { 1508 DRM_ERROR("invalid die id %d, expected %d\n", 1509 le16_to_cpu(dhdr->die_id), i); 1510 return -EINVAL; 1511 } 1512 1513 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 1514 le16_to_cpu(dhdr->die_id), num_ips); 1515 1516 for (j = 0; j < num_ips; j++) { 1517 ip = (struct ip_v4 *)(discovery_bin + ip_offset); 1518 1519 inst = ip->instance_number; 1520 hw_id = le16_to_cpu(ip->hw_id); 1521 if (amdgpu_discovery_validate_ip(adev, inst, hw_id)) 1522 goto next_ip; 1523 1524 num_base_address = ip->num_base_address; 1525 1526 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 1527 hw_id_names[le16_to_cpu(ip->hw_id)], 1528 le16_to_cpu(ip->hw_id), 1529 ip->instance_number, 1530 ip->major, ip->minor, 1531 ip->revision); 1532 1533 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 1534 /* Bit [5:0]: original revision value 1535 * Bit [7:6]: en/decode capability: 1536 * 0b00 : VCN function normally 1537 * 0b10 : encode is disabled 1538 * 0b01 : decode is disabled 1539 */ 1540 if (adev->vcn.num_vcn_inst < 1541 AMDGPU_MAX_VCN_INSTANCES) { 1542 adev->vcn.inst[adev->vcn.num_vcn_inst].vcn_config = 1543 ip->revision & 0xc0; 1544 adev->vcn.num_vcn_inst++; 1545 adev->vcn.inst_mask |= 1546 (1U << ip->instance_number); 1547 adev->jpeg.inst_mask |= 1548 (1U << ip->instance_number); 1549 } else { 1550 dev_err(adev->dev, "Too many VCN instances: %d vs %d\n", 1551 adev->vcn.num_vcn_inst + 1, 1552 AMDGPU_MAX_VCN_INSTANCES); 1553 } 1554 ip->revision &= ~0xc0; 1555 } 1556 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 1557 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 1558 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 1559 le16_to_cpu(ip->hw_id) == SDMA3_HWID) { 1560 if (adev->sdma.num_instances < 1561 AMDGPU_MAX_SDMA_INSTANCES) { 1562 adev->sdma.num_instances++; 1563 adev->sdma.sdma_mask |= 1564 (1U << ip->instance_number); 1565 } else { 1566 dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n", 1567 adev->sdma.num_instances + 1, 1568 AMDGPU_MAX_SDMA_INSTANCES); 1569 } 1570 } 1571 1572 if (le16_to_cpu(ip->hw_id) == VPE_HWID) { 1573 if (adev->vpe.num_instances < AMDGPU_MAX_VPE_INSTANCES) 1574 adev->vpe.num_instances++; 1575 else 1576 dev_err(adev->dev, "Too many VPE instances: %d vs %d\n", 1577 adev->vpe.num_instances + 1, 1578 AMDGPU_MAX_VPE_INSTANCES); 1579 } 1580 1581 if (le16_to_cpu(ip->hw_id) == UMC_HWID) { 1582 adev->gmc.num_umc++; 1583 adev->umc.node_inst_num++; 1584 } 1585 1586 if (le16_to_cpu(ip->hw_id) == GC_HWID) 1587 adev->gfx.xcc_mask |= 1588 (1U << ip->instance_number); 1589 1590 if (!wafl_ver && le16_to_cpu(ip->hw_id) == WAFLC_HWID) 1591 wafl_ver = IP_VERSION_FULL(ip->major, ip->minor, 1592 ip->revision, 0, 0); 1593 1594 for (k = 0; k < num_base_address; k++) { 1595 /* 1596 * convert the endianness of base addresses in place, 1597 * so that we don't need to convert them when accessing adev->reg_offset. 1598 */ 1599 if (ihdr->base_addr_64_bit) 1600 /* Truncate the 64bit base address from ip discovery 1601 * and only store lower 32bit ip base in reg_offset[]. 1602 * Bits > 32 follows ASIC specific format, thus just 1603 * discard them and handle it within specific ASIC. 1604 * By this way reg_offset[] and related helpers can 1605 * stay unchanged. 1606 * The base address is in dwords, thus clear the 1607 * highest 2 bits to store. 1608 */ 1609 ip->base_address[k] = 1610 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF; 1611 else 1612 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 1613 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 1614 } 1615 1616 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 1617 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) && 1618 hw_id_map[hw_ip] != 0) { 1619 DRM_DEBUG("set register base offset for %s\n", 1620 hw_id_names[le16_to_cpu(ip->hw_id)]); 1621 adev->reg_offset[hw_ip][ip->instance_number] = 1622 ip->base_address; 1623 /* Instance support is somewhat inconsistent. 1624 * SDMA is a good example. Sienna cichlid has 4 total 1625 * SDMA instances, each enumerated separately (HWIDs 1626 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 1627 * but they are enumerated as multiple instances of the 1628 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 1629 * example. On most chips there are multiple instances 1630 * with the same HWID. 1631 */ 1632 1633 if (ihdr->version < 3) { 1634 subrev = 0; 1635 variant = 0; 1636 } else { 1637 subrev = ip->sub_revision; 1638 variant = ip->variant; 1639 } 1640 1641 adev->ip_versions[hw_ip] 1642 [ip->instance_number] = 1643 IP_VERSION_FULL(ip->major, 1644 ip->minor, 1645 ip->revision, 1646 variant, 1647 subrev); 1648 } 1649 } 1650 1651 next_ip: 1652 if (ihdr->base_addr_64_bit) 1653 ip_offset += struct_size(ip, base_address_64, ip->num_base_address); 1654 else 1655 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1656 } 1657 } 1658 1659 if (wafl_ver && !adev->ip_versions[XGMI_HWIP][0]) 1660 adev->ip_versions[XGMI_HWIP][0] = wafl_ver; 1661 1662 return 0; 1663 } 1664 1665 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 1666 { 1667 uint8_t *discovery_bin = adev->discovery.bin; 1668 struct ip_discovery_header *ihdr; 1669 struct table_info *info; 1670 int vcn_harvest_count = 0; 1671 int umc_harvest_count = 0; 1672 uint16_t ihdr_ver; 1673 1674 if (amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY)) 1675 return; 1676 ihdr = (struct ip_discovery_header *)(discovery_bin + 1677 le16_to_cpu(info->offset)); 1678 ihdr_ver = le16_to_cpu(ihdr->version); 1679 /* 1680 * Harvest table does not fit Navi1x and legacy GPUs, 1681 * so read harvest bit per IP data structure to set 1682 * harvest configuration. 1683 */ 1684 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 2, 0) && 1685 ihdr_ver <= 2) { 1686 if ((adev->pdev->device == 0x731E && 1687 (adev->pdev->revision == 0xC6 || 1688 adev->pdev->revision == 0xC7)) || 1689 (adev->pdev->device == 0x7340 && 1690 adev->pdev->revision == 0xC9) || 1691 (adev->pdev->device == 0x7360 && 1692 adev->pdev->revision == 0xC7)) 1693 amdgpu_discovery_read_harvest_bit_per_ip(adev, 1694 &vcn_harvest_count); 1695 } else { 1696 amdgpu_discovery_read_from_harvest_table(adev, 1697 &vcn_harvest_count, 1698 &umc_harvest_count); 1699 } 1700 1701 amdgpu_discovery_harvest_config_quirk(adev); 1702 1703 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 1704 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 1705 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 1706 } 1707 1708 if (umc_harvest_count < adev->gmc.num_umc) { 1709 adev->gmc.num_umc -= umc_harvest_count; 1710 } 1711 } 1712 1713 union gc_info { 1714 struct gc_info_v1_0 v1; 1715 struct gc_info_v1_1 v1_1; 1716 struct gc_info_v1_2 v1_2; 1717 struct gc_info_v1_3 v1_3; 1718 struct gc_info_v2_0 v2; 1719 struct gc_info_v2_1 v2_1; 1720 }; 1721 1722 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 1723 { 1724 uint8_t *discovery_bin = adev->discovery.bin; 1725 struct table_info *info; 1726 union gc_info *gc_info; 1727 u16 offset; 1728 1729 if (!discovery_bin) { 1730 DRM_ERROR("ip discovery uninitialized\n"); 1731 return -EINVAL; 1732 } 1733 1734 if (amdgpu_discovery_get_table_info(adev, &info, GC)) 1735 return -EINVAL; 1736 offset = le16_to_cpu(info->offset); 1737 1738 if (!offset) 1739 return 0; 1740 1741 gc_info = (union gc_info *)(discovery_bin + offset); 1742 1743 switch (le16_to_cpu(gc_info->v1.header.version_major)) { 1744 case 1: 1745 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); 1746 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 1747 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); 1748 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1749 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); 1750 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); 1751 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); 1752 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); 1753 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); 1754 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); 1755 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); 1756 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); 1757 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); 1758 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); 1759 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); 1760 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / 1761 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1762 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); 1763 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 1) { 1764 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa); 1765 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface); 1766 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps); 1767 } 1768 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 2) { 1769 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg); 1770 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size); 1771 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp); 1772 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc); 1773 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc); 1774 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa); 1775 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance); 1776 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu); 1777 } 1778 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 3) { 1779 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v1_3.gc_tcp_size_per_cu); 1780 adev->gfx.config.gc_tcp_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcp_cache_line_size); 1781 adev->gfx.config.gc_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_size_per_sqc); 1782 adev->gfx.config.gc_instruction_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_line_size); 1783 adev->gfx.config.gc_scalar_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_size_per_sqc); 1784 adev->gfx.config.gc_scalar_data_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_line_size); 1785 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v1_3.gc_tcc_size); 1786 adev->gfx.config.gc_tcc_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcc_cache_line_size); 1787 } 1788 break; 1789 case 2: 1790 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); 1791 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); 1792 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1793 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); 1794 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); 1795 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); 1796 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); 1797 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); 1798 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); 1799 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); 1800 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); 1801 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); 1802 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); 1803 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); 1804 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / 1805 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1806 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); 1807 if (le16_to_cpu(gc_info->v2.header.version_minor) == 1) { 1808 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh); 1809 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu); 1810 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XCD */ 1811 adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc); 1812 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_cache_size_per_sqc); 1813 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_size_per_sqc); 1814 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */ 1815 } 1816 break; 1817 default: 1818 dev_err(adev->dev, 1819 "Unhandled GC info table %d.%d\n", 1820 le16_to_cpu(gc_info->v1.header.version_major), 1821 le16_to_cpu(gc_info->v1.header.version_minor)); 1822 return -EINVAL; 1823 } 1824 return 0; 1825 } 1826 1827 union mall_info { 1828 struct mall_info_v1_0 v1; 1829 struct mall_info_v2_0 v2; 1830 }; 1831 1832 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) 1833 { 1834 uint8_t *discovery_bin = adev->discovery.bin; 1835 struct table_info *info; 1836 union mall_info *mall_info; 1837 u32 u, mall_size_per_umc, m_s_present, half_use; 1838 u64 mall_size; 1839 u16 offset; 1840 1841 if (!discovery_bin) { 1842 DRM_ERROR("ip discovery uninitialized\n"); 1843 return -EINVAL; 1844 } 1845 1846 if (amdgpu_discovery_get_table_info(adev, &info, MALL_INFO)) 1847 return -EINVAL; 1848 offset = le16_to_cpu(info->offset); 1849 1850 if (!offset) 1851 return 0; 1852 1853 mall_info = (union mall_info *)(discovery_bin + offset); 1854 1855 switch (le16_to_cpu(mall_info->v1.header.version_major)) { 1856 case 1: 1857 mall_size = 0; 1858 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m); 1859 m_s_present = le32_to_cpu(mall_info->v1.m_s_present); 1860 half_use = le32_to_cpu(mall_info->v1.m_half_use); 1861 for (u = 0; u < adev->gmc.num_umc; u++) { 1862 if (m_s_present & (1 << u)) 1863 mall_size += mall_size_per_umc * 2; 1864 else if (half_use & (1 << u)) 1865 mall_size += mall_size_per_umc / 2; 1866 else 1867 mall_size += mall_size_per_umc; 1868 } 1869 adev->gmc.mall_size = mall_size; 1870 adev->gmc.m_half_use = half_use; 1871 break; 1872 case 2: 1873 mall_size_per_umc = le32_to_cpu(mall_info->v2.mall_size_per_umc); 1874 adev->gmc.mall_size = (uint64_t)mall_size_per_umc * adev->gmc.num_umc; 1875 break; 1876 default: 1877 dev_err(adev->dev, 1878 "Unhandled MALL info table %d.%d\n", 1879 le16_to_cpu(mall_info->v1.header.version_major), 1880 le16_to_cpu(mall_info->v1.header.version_minor)); 1881 return -EINVAL; 1882 } 1883 return 0; 1884 } 1885 1886 union vcn_info { 1887 struct vcn_info_v1_0 v1; 1888 }; 1889 1890 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) 1891 { 1892 uint8_t *discovery_bin = adev->discovery.bin; 1893 struct table_info *info; 1894 union vcn_info *vcn_info; 1895 u16 offset; 1896 int v; 1897 1898 if (!discovery_bin) { 1899 DRM_ERROR("ip discovery uninitialized\n"); 1900 return -EINVAL; 1901 } 1902 1903 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1904 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES 1905 * but that may change in the future with new GPUs so keep this 1906 * check for defensive purposes. 1907 */ 1908 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { 1909 dev_err(adev->dev, "invalid vcn instances\n"); 1910 return -EINVAL; 1911 } 1912 1913 if (amdgpu_discovery_get_table_info(adev, &info, VCN_INFO)) 1914 return -EINVAL; 1915 offset = le16_to_cpu(info->offset); 1916 1917 if (!offset) 1918 return 0; 1919 1920 vcn_info = (union vcn_info *)(discovery_bin + offset); 1921 1922 switch (le16_to_cpu(vcn_info->v1.header.version_major)) { 1923 case 1: 1924 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1925 * so this won't overflow. 1926 */ 1927 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { 1928 adev->vcn.inst[v].vcn_codec_disable_mask = 1929 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits); 1930 } 1931 break; 1932 default: 1933 dev_err(adev->dev, 1934 "Unhandled VCN info table %d.%d\n", 1935 le16_to_cpu(vcn_info->v1.header.version_major), 1936 le16_to_cpu(vcn_info->v1.header.version_minor)); 1937 return -EINVAL; 1938 } 1939 return 0; 1940 } 1941 1942 union nps_info { 1943 struct nps_info_v1_0 v1; 1944 }; 1945 1946 static int amdgpu_discovery_refresh_nps_info(struct amdgpu_device *adev, 1947 union nps_info *nps_data) 1948 { 1949 uint64_t vram_size, pos, offset; 1950 struct nps_info_header *nhdr; 1951 struct binary_header bhdr; 1952 struct binary_header_v2 bhdrv2; 1953 uint16_t checksum; 1954 1955 vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 1956 pos = vram_size - DISCOVERY_TMR_OFFSET; 1957 amdgpu_device_vram_access(adev, pos, &bhdr, sizeof(bhdr), false); 1958 1959 switch (bhdr.version_major) { 1960 case 2: 1961 amdgpu_device_vram_access(adev, pos, &bhdrv2, sizeof(bhdrv2), false); 1962 offset = le16_to_cpu(bhdrv2.table_list[NPS_INFO].offset); 1963 checksum = le16_to_cpu(bhdrv2.table_list[NPS_INFO].checksum); 1964 break; 1965 case 1: 1966 offset = le16_to_cpu(bhdr.table_list[NPS_INFO].offset); 1967 checksum = le16_to_cpu(bhdr.table_list[NPS_INFO].checksum); 1968 break; 1969 default: 1970 return -EINVAL; 1971 } 1972 1973 amdgpu_device_vram_access(adev, (pos + offset), nps_data, 1974 sizeof(*nps_data), false); 1975 1976 nhdr = (struct nps_info_header *)(nps_data); 1977 if (!amdgpu_discovery_verify_checksum(adev, (uint8_t *)nps_data, 1978 le32_to_cpu(nhdr->size_bytes), 1979 checksum)) { 1980 dev_err(adev->dev, "nps data refresh, checksum mismatch\n"); 1981 return -EINVAL; 1982 } 1983 1984 return 0; 1985 } 1986 1987 int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, 1988 uint32_t *nps_type, 1989 struct amdgpu_gmc_memrange *ranges, 1990 int *range_cnt, bool refresh) 1991 { 1992 uint8_t *discovery_bin = adev->discovery.bin; 1993 struct table_info *info; 1994 union nps_info *nps_info; 1995 union nps_info nps_data; 1996 u16 offset; 1997 int i, r; 1998 1999 if (!nps_type || !range_cnt || !ranges) 2000 return -EINVAL; 2001 2002 if (refresh) { 2003 r = amdgpu_discovery_refresh_nps_info(adev, &nps_data); 2004 if (r) 2005 return r; 2006 nps_info = &nps_data; 2007 } else { 2008 if (!discovery_bin) { 2009 dev_err(adev->dev, 2010 "fetch mem range failed, ip discovery uninitialized\n"); 2011 return -EINVAL; 2012 } 2013 2014 if (amdgpu_discovery_get_table_info(adev, &info, NPS_INFO)) 2015 return -EINVAL; 2016 offset = le16_to_cpu(info->offset); 2017 2018 if (!offset) 2019 return -ENOENT; 2020 2021 /* If verification fails, return as if NPS table doesn't exist */ 2022 if (amdgpu_discovery_verify_npsinfo(adev, info)) 2023 return -ENOENT; 2024 2025 nps_info = (union nps_info *)(discovery_bin + offset); 2026 } 2027 2028 switch (le16_to_cpu(nps_info->v1.header.version_major)) { 2029 case 1: 2030 *nps_type = nps_info->v1.nps_type; 2031 if (*range_cnt < nps_info->v1.count) { 2032 dev_dbg(adev->dev, 2033 "not enough space for nps ranges: %d < %d\n", 2034 *range_cnt, nps_info->v1.count); 2035 return -ENOSPC; 2036 } 2037 *range_cnt = nps_info->v1.count; 2038 for (i = 0; i < *range_cnt; i++) { 2039 ranges[i].base_address = 2040 nps_info->v1.instance_info[i].base_address; 2041 ranges[i].limit_address = 2042 nps_info->v1.instance_info[i].limit_address; 2043 ranges[i].nid_mask = -1; 2044 ranges[i].flags = 0; 2045 } 2046 break; 2047 default: 2048 dev_err(adev->dev, "Unhandled NPS info table %d.%d\n", 2049 le16_to_cpu(nps_info->v1.header.version_major), 2050 le16_to_cpu(nps_info->v1.header.version_minor)); 2051 return -EINVAL; 2052 } 2053 2054 return 0; 2055 } 2056 2057 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 2058 { 2059 /* what IP to use for this? */ 2060 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2061 case IP_VERSION(9, 0, 1): 2062 case IP_VERSION(9, 1, 0): 2063 case IP_VERSION(9, 2, 1): 2064 case IP_VERSION(9, 2, 2): 2065 case IP_VERSION(9, 3, 0): 2066 case IP_VERSION(9, 4, 0): 2067 case IP_VERSION(9, 4, 1): 2068 case IP_VERSION(9, 4, 2): 2069 case IP_VERSION(9, 4, 3): 2070 case IP_VERSION(9, 4, 4): 2071 case IP_VERSION(9, 5, 0): 2072 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 2073 break; 2074 case IP_VERSION(10, 1, 10): 2075 case IP_VERSION(10, 1, 1): 2076 case IP_VERSION(10, 1, 2): 2077 case IP_VERSION(10, 1, 3): 2078 case IP_VERSION(10, 1, 4): 2079 case IP_VERSION(10, 3, 0): 2080 case IP_VERSION(10, 3, 1): 2081 case IP_VERSION(10, 3, 2): 2082 case IP_VERSION(10, 3, 3): 2083 case IP_VERSION(10, 3, 4): 2084 case IP_VERSION(10, 3, 5): 2085 case IP_VERSION(10, 3, 6): 2086 case IP_VERSION(10, 3, 7): 2087 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 2088 break; 2089 case IP_VERSION(11, 0, 0): 2090 case IP_VERSION(11, 0, 1): 2091 case IP_VERSION(11, 0, 2): 2092 case IP_VERSION(11, 0, 3): 2093 case IP_VERSION(11, 0, 4): 2094 case IP_VERSION(11, 5, 0): 2095 case IP_VERSION(11, 5, 1): 2096 case IP_VERSION(11, 5, 2): 2097 case IP_VERSION(11, 5, 3): 2098 case IP_VERSION(11, 5, 4): 2099 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); 2100 break; 2101 case IP_VERSION(12, 0, 0): 2102 case IP_VERSION(12, 0, 1): 2103 amdgpu_device_ip_block_add(adev, &soc24_common_ip_block); 2104 break; 2105 case IP_VERSION(12, 1, 0): 2106 amdgpu_device_ip_block_add(adev, &soc_v1_0_common_ip_block); 2107 break; 2108 default: 2109 dev_err(adev->dev, 2110 "Failed to add common ip block(GC_HWIP:0x%x)\n", 2111 amdgpu_ip_version(adev, GC_HWIP, 0)); 2112 return -EINVAL; 2113 } 2114 return 0; 2115 } 2116 2117 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 2118 { 2119 /* use GC or MMHUB IP version */ 2120 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2121 case IP_VERSION(9, 0, 1): 2122 case IP_VERSION(9, 1, 0): 2123 case IP_VERSION(9, 2, 1): 2124 case IP_VERSION(9, 2, 2): 2125 case IP_VERSION(9, 3, 0): 2126 case IP_VERSION(9, 4, 0): 2127 case IP_VERSION(9, 4, 1): 2128 case IP_VERSION(9, 4, 2): 2129 case IP_VERSION(9, 4, 3): 2130 case IP_VERSION(9, 4, 4): 2131 case IP_VERSION(9, 5, 0): 2132 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 2133 break; 2134 case IP_VERSION(10, 1, 10): 2135 case IP_VERSION(10, 1, 1): 2136 case IP_VERSION(10, 1, 2): 2137 case IP_VERSION(10, 1, 3): 2138 case IP_VERSION(10, 1, 4): 2139 case IP_VERSION(10, 3, 0): 2140 case IP_VERSION(10, 3, 1): 2141 case IP_VERSION(10, 3, 2): 2142 case IP_VERSION(10, 3, 3): 2143 case IP_VERSION(10, 3, 4): 2144 case IP_VERSION(10, 3, 5): 2145 case IP_VERSION(10, 3, 6): 2146 case IP_VERSION(10, 3, 7): 2147 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 2148 break; 2149 case IP_VERSION(11, 0, 0): 2150 case IP_VERSION(11, 0, 1): 2151 case IP_VERSION(11, 0, 2): 2152 case IP_VERSION(11, 0, 3): 2153 case IP_VERSION(11, 0, 4): 2154 case IP_VERSION(11, 5, 0): 2155 case IP_VERSION(11, 5, 1): 2156 case IP_VERSION(11, 5, 2): 2157 case IP_VERSION(11, 5, 3): 2158 case IP_VERSION(11, 5, 4): 2159 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block); 2160 break; 2161 case IP_VERSION(12, 0, 0): 2162 case IP_VERSION(12, 0, 1): 2163 case IP_VERSION(12, 1, 0): 2164 amdgpu_device_ip_block_add(adev, &gmc_v12_0_ip_block); 2165 break; 2166 default: 2167 dev_err(adev->dev, "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 2168 amdgpu_ip_version(adev, GC_HWIP, 0)); 2169 return -EINVAL; 2170 } 2171 return 0; 2172 } 2173 2174 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 2175 { 2176 switch (amdgpu_ip_version(adev, OSSSYS_HWIP, 0)) { 2177 case IP_VERSION(4, 0, 0): 2178 case IP_VERSION(4, 0, 1): 2179 case IP_VERSION(4, 1, 0): 2180 case IP_VERSION(4, 1, 1): 2181 case IP_VERSION(4, 3, 0): 2182 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 2183 break; 2184 case IP_VERSION(4, 2, 0): 2185 case IP_VERSION(4, 2, 1): 2186 case IP_VERSION(4, 4, 0): 2187 case IP_VERSION(4, 4, 2): 2188 case IP_VERSION(4, 4, 5): 2189 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 2190 break; 2191 case IP_VERSION(5, 0, 0): 2192 case IP_VERSION(5, 0, 1): 2193 case IP_VERSION(5, 0, 2): 2194 case IP_VERSION(5, 0, 3): 2195 case IP_VERSION(5, 2, 0): 2196 case IP_VERSION(5, 2, 1): 2197 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 2198 break; 2199 case IP_VERSION(6, 0, 0): 2200 case IP_VERSION(6, 0, 1): 2201 case IP_VERSION(6, 0, 2): 2202 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block); 2203 break; 2204 case IP_VERSION(6, 1, 0): 2205 case IP_VERSION(6, 1, 1): 2206 amdgpu_device_ip_block_add(adev, &ih_v6_1_ip_block); 2207 break; 2208 case IP_VERSION(7, 0, 0): 2209 case IP_VERSION(7, 1, 0): 2210 amdgpu_device_ip_block_add(adev, &ih_v7_0_ip_block); 2211 break; 2212 default: 2213 dev_err(adev->dev, 2214 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 2215 amdgpu_ip_version(adev, OSSSYS_HWIP, 0)); 2216 return -EINVAL; 2217 } 2218 return 0; 2219 } 2220 2221 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 2222 { 2223 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 2224 case IP_VERSION(9, 0, 0): 2225 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 2226 break; 2227 case IP_VERSION(10, 0, 0): 2228 case IP_VERSION(10, 0, 1): 2229 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 2230 break; 2231 case IP_VERSION(11, 0, 0): 2232 case IP_VERSION(11, 0, 2): 2233 case IP_VERSION(11, 0, 4): 2234 case IP_VERSION(11, 0, 5): 2235 case IP_VERSION(11, 0, 9): 2236 case IP_VERSION(11, 0, 7): 2237 case IP_VERSION(11, 0, 11): 2238 case IP_VERSION(11, 0, 12): 2239 case IP_VERSION(11, 0, 13): 2240 case IP_VERSION(11, 5, 0): 2241 case IP_VERSION(11, 5, 2): 2242 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 2243 break; 2244 case IP_VERSION(11, 0, 8): 2245 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 2246 break; 2247 case IP_VERSION(11, 0, 3): 2248 case IP_VERSION(12, 0, 1): 2249 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 2250 break; 2251 case IP_VERSION(13, 0, 0): 2252 case IP_VERSION(13, 0, 1): 2253 case IP_VERSION(13, 0, 2): 2254 case IP_VERSION(13, 0, 3): 2255 case IP_VERSION(13, 0, 5): 2256 case IP_VERSION(13, 0, 6): 2257 case IP_VERSION(13, 0, 7): 2258 case IP_VERSION(13, 0, 8): 2259 case IP_VERSION(13, 0, 10): 2260 case IP_VERSION(13, 0, 11): 2261 case IP_VERSION(13, 0, 12): 2262 case IP_VERSION(13, 0, 14): 2263 case IP_VERSION(13, 0, 15): 2264 case IP_VERSION(14, 0, 0): 2265 case IP_VERSION(14, 0, 1): 2266 case IP_VERSION(14, 0, 4): 2267 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 2268 break; 2269 case IP_VERSION(13, 0, 4): 2270 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block); 2271 break; 2272 case IP_VERSION(14, 0, 2): 2273 case IP_VERSION(14, 0, 3): 2274 case IP_VERSION(14, 0, 5): 2275 amdgpu_device_ip_block_add(adev, &psp_v14_0_ip_block); 2276 break; 2277 case IP_VERSION(15, 0, 0): 2278 amdgpu_device_ip_block_add(adev, &psp_v15_0_ip_block); 2279 break; 2280 case IP_VERSION(15, 0, 8): 2281 amdgpu_device_ip_block_add(adev, &psp_v15_0_8_ip_block); 2282 break; 2283 default: 2284 dev_err(adev->dev, 2285 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 2286 amdgpu_ip_version(adev, MP0_HWIP, 0)); 2287 return -EINVAL; 2288 } 2289 return 0; 2290 } 2291 2292 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 2293 { 2294 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2295 case IP_VERSION(9, 0, 0): 2296 case IP_VERSION(10, 0, 0): 2297 case IP_VERSION(10, 0, 1): 2298 case IP_VERSION(11, 0, 2): 2299 if (adev->asic_type == CHIP_ARCTURUS) 2300 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2301 else 2302 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 2303 break; 2304 case IP_VERSION(11, 0, 0): 2305 case IP_VERSION(11, 0, 5): 2306 case IP_VERSION(11, 0, 9): 2307 case IP_VERSION(11, 0, 7): 2308 case IP_VERSION(11, 0, 11): 2309 case IP_VERSION(11, 0, 12): 2310 case IP_VERSION(11, 0, 13): 2311 case IP_VERSION(11, 5, 0): 2312 case IP_VERSION(11, 5, 2): 2313 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2314 break; 2315 case IP_VERSION(11, 0, 8): 2316 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) 2317 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2318 break; 2319 case IP_VERSION(12, 0, 0): 2320 case IP_VERSION(12, 0, 1): 2321 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 2322 break; 2323 case IP_VERSION(13, 0, 0): 2324 case IP_VERSION(13, 0, 1): 2325 case IP_VERSION(13, 0, 2): 2326 case IP_VERSION(13, 0, 3): 2327 case IP_VERSION(13, 0, 4): 2328 case IP_VERSION(13, 0, 5): 2329 case IP_VERSION(13, 0, 6): 2330 case IP_VERSION(13, 0, 7): 2331 case IP_VERSION(13, 0, 8): 2332 case IP_VERSION(13, 0, 10): 2333 case IP_VERSION(13, 0, 11): 2334 case IP_VERSION(13, 0, 14): 2335 case IP_VERSION(13, 0, 12): 2336 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 2337 break; 2338 case IP_VERSION(14, 0, 0): 2339 case IP_VERSION(14, 0, 1): 2340 case IP_VERSION(14, 0, 2): 2341 case IP_VERSION(14, 0, 3): 2342 case IP_VERSION(14, 0, 4): 2343 case IP_VERSION(14, 0, 5): 2344 amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block); 2345 break; 2346 case IP_VERSION(15, 0, 0): 2347 case IP_VERSION(15, 0, 8): 2348 amdgpu_device_ip_block_add(adev, &smu_v15_0_ip_block); 2349 break; 2350 default: 2351 dev_err(adev->dev, 2352 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 2353 amdgpu_ip_version(adev, MP1_HWIP, 0)); 2354 return -EINVAL; 2355 } 2356 return 0; 2357 } 2358 2359 #if defined(CONFIG_DRM_AMD_DC) 2360 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev) 2361 { 2362 amdgpu_device_set_sriov_virtual_display(adev); 2363 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2364 } 2365 #endif 2366 2367 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 2368 { 2369 if (adev->enable_virtual_display) { 2370 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2371 return 0; 2372 } 2373 2374 if (!amdgpu_device_has_dc_support(adev)) 2375 return 0; 2376 2377 #if defined(CONFIG_DRM_AMD_DC) 2378 if (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2379 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2380 case IP_VERSION(1, 0, 0): 2381 case IP_VERSION(1, 0, 1): 2382 case IP_VERSION(2, 0, 2): 2383 case IP_VERSION(2, 0, 0): 2384 case IP_VERSION(2, 0, 3): 2385 case IP_VERSION(2, 1, 0): 2386 case IP_VERSION(3, 0, 0): 2387 case IP_VERSION(3, 0, 2): 2388 case IP_VERSION(3, 0, 3): 2389 case IP_VERSION(3, 0, 1): 2390 case IP_VERSION(3, 1, 2): 2391 case IP_VERSION(3, 1, 3): 2392 case IP_VERSION(3, 1, 4): 2393 case IP_VERSION(3, 1, 5): 2394 case IP_VERSION(3, 1, 6): 2395 case IP_VERSION(3, 2, 0): 2396 case IP_VERSION(3, 2, 1): 2397 case IP_VERSION(3, 5, 0): 2398 case IP_VERSION(3, 5, 1): 2399 case IP_VERSION(3, 6, 0): 2400 case IP_VERSION(4, 1, 0): 2401 case IP_VERSION(4, 2, 0): 2402 /* TODO: Fix IP version. DC code expects version 4.0.1 */ 2403 if (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(4, 1, 0)) 2404 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(4, 0, 1); 2405 2406 if (amdgpu_sriov_vf(adev)) 2407 amdgpu_discovery_set_sriov_display(adev); 2408 else 2409 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2410 break; 2411 default: 2412 dev_err(adev->dev, 2413 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 2414 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2415 return -EINVAL; 2416 } 2417 } else if (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2418 switch (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2419 case IP_VERSION(12, 0, 0): 2420 case IP_VERSION(12, 0, 1): 2421 case IP_VERSION(12, 1, 0): 2422 if (amdgpu_sriov_vf(adev)) 2423 amdgpu_discovery_set_sriov_display(adev); 2424 else 2425 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2426 break; 2427 default: 2428 dev_err(adev->dev, 2429 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 2430 amdgpu_ip_version(adev, DCI_HWIP, 0)); 2431 return -EINVAL; 2432 } 2433 } 2434 #endif 2435 return 0; 2436 } 2437 2438 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 2439 { 2440 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2441 case IP_VERSION(9, 0, 1): 2442 case IP_VERSION(9, 1, 0): 2443 case IP_VERSION(9, 2, 1): 2444 case IP_VERSION(9, 2, 2): 2445 case IP_VERSION(9, 3, 0): 2446 case IP_VERSION(9, 4, 0): 2447 case IP_VERSION(9, 4, 1): 2448 case IP_VERSION(9, 4, 2): 2449 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 2450 break; 2451 case IP_VERSION(9, 4, 3): 2452 case IP_VERSION(9, 4, 4): 2453 case IP_VERSION(9, 5, 0): 2454 amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block); 2455 break; 2456 case IP_VERSION(10, 1, 10): 2457 case IP_VERSION(10, 1, 2): 2458 case IP_VERSION(10, 1, 1): 2459 case IP_VERSION(10, 1, 3): 2460 case IP_VERSION(10, 1, 4): 2461 case IP_VERSION(10, 3, 0): 2462 case IP_VERSION(10, 3, 2): 2463 case IP_VERSION(10, 3, 1): 2464 case IP_VERSION(10, 3, 4): 2465 case IP_VERSION(10, 3, 5): 2466 case IP_VERSION(10, 3, 6): 2467 case IP_VERSION(10, 3, 3): 2468 case IP_VERSION(10, 3, 7): 2469 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 2470 break; 2471 case IP_VERSION(11, 0, 0): 2472 case IP_VERSION(11, 0, 1): 2473 case IP_VERSION(11, 0, 2): 2474 case IP_VERSION(11, 0, 3): 2475 case IP_VERSION(11, 0, 4): 2476 case IP_VERSION(11, 5, 0): 2477 case IP_VERSION(11, 5, 1): 2478 case IP_VERSION(11, 5, 2): 2479 case IP_VERSION(11, 5, 3): 2480 case IP_VERSION(11, 5, 4): 2481 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); 2482 break; 2483 case IP_VERSION(12, 0, 0): 2484 case IP_VERSION(12, 0, 1): 2485 amdgpu_device_ip_block_add(adev, &gfx_v12_0_ip_block); 2486 break; 2487 case IP_VERSION(12, 1, 0): 2488 amdgpu_device_ip_block_add(adev, &gfx_v12_1_ip_block); 2489 break; 2490 default: 2491 dev_err(adev->dev, "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 2492 amdgpu_ip_version(adev, GC_HWIP, 0)); 2493 return -EINVAL; 2494 } 2495 return 0; 2496 } 2497 2498 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 2499 { 2500 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 2501 case IP_VERSION(4, 0, 0): 2502 case IP_VERSION(4, 0, 1): 2503 case IP_VERSION(4, 1, 0): 2504 case IP_VERSION(4, 1, 1): 2505 case IP_VERSION(4, 1, 2): 2506 case IP_VERSION(4, 2, 0): 2507 case IP_VERSION(4, 2, 2): 2508 case IP_VERSION(4, 4, 0): 2509 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 2510 break; 2511 case IP_VERSION(4, 4, 2): 2512 case IP_VERSION(4, 4, 5): 2513 case IP_VERSION(4, 4, 4): 2514 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block); 2515 break; 2516 case IP_VERSION(5, 0, 0): 2517 case IP_VERSION(5, 0, 1): 2518 case IP_VERSION(5, 0, 2): 2519 case IP_VERSION(5, 0, 5): 2520 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 2521 break; 2522 case IP_VERSION(5, 2, 0): 2523 case IP_VERSION(5, 2, 2): 2524 case IP_VERSION(5, 2, 4): 2525 case IP_VERSION(5, 2, 5): 2526 case IP_VERSION(5, 2, 6): 2527 case IP_VERSION(5, 2, 3): 2528 case IP_VERSION(5, 2, 1): 2529 case IP_VERSION(5, 2, 7): 2530 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 2531 break; 2532 case IP_VERSION(6, 0, 0): 2533 case IP_VERSION(6, 0, 1): 2534 case IP_VERSION(6, 0, 2): 2535 case IP_VERSION(6, 0, 3): 2536 case IP_VERSION(6, 1, 0): 2537 case IP_VERSION(6, 1, 1): 2538 case IP_VERSION(6, 1, 2): 2539 case IP_VERSION(6, 1, 3): 2540 case IP_VERSION(6, 1, 4): 2541 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block); 2542 break; 2543 case IP_VERSION(7, 0, 0): 2544 case IP_VERSION(7, 0, 1): 2545 amdgpu_device_ip_block_add(adev, &sdma_v7_0_ip_block); 2546 break; 2547 case IP_VERSION(7, 1, 0): 2548 amdgpu_device_ip_block_add(adev, &sdma_v7_1_ip_block); 2549 break; 2550 default: 2551 dev_err(adev->dev, 2552 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 2553 amdgpu_ip_version(adev, SDMA0_HWIP, 0)); 2554 return -EINVAL; 2555 } 2556 2557 return 0; 2558 } 2559 2560 static int amdgpu_discovery_set_ras_ip_blocks(struct amdgpu_device *adev) 2561 { 2562 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 2563 case IP_VERSION(13, 0, 6): 2564 case IP_VERSION(13, 0, 12): 2565 case IP_VERSION(13, 0, 14): 2566 amdgpu_device_ip_block_add(adev, &ras_v1_0_ip_block); 2567 break; 2568 default: 2569 break; 2570 } 2571 return 0; 2572 } 2573 2574 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 2575 { 2576 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2577 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2578 case IP_VERSION(7, 0, 0): 2579 case IP_VERSION(7, 2, 0): 2580 /* UVD is not supported on vega20 SR-IOV */ 2581 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2582 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 2583 break; 2584 default: 2585 dev_err(adev->dev, 2586 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 2587 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2588 return -EINVAL; 2589 } 2590 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2591 case IP_VERSION(4, 0, 0): 2592 case IP_VERSION(4, 1, 0): 2593 /* VCE is not supported on vega20 SR-IOV */ 2594 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2595 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 2596 break; 2597 default: 2598 dev_err(adev->dev, 2599 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 2600 amdgpu_ip_version(adev, VCE_HWIP, 0)); 2601 return -EINVAL; 2602 } 2603 } else { 2604 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2605 case IP_VERSION(1, 0, 0): 2606 case IP_VERSION(1, 0, 1): 2607 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 2608 break; 2609 case IP_VERSION(2, 0, 0): 2610 case IP_VERSION(2, 0, 2): 2611 case IP_VERSION(2, 2, 0): 2612 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 2613 if (!amdgpu_sriov_vf(adev)) 2614 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 2615 break; 2616 case IP_VERSION(2, 0, 3): 2617 break; 2618 case IP_VERSION(2, 5, 0): 2619 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 2620 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 2621 break; 2622 case IP_VERSION(2, 6, 0): 2623 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 2624 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 2625 break; 2626 case IP_VERSION(3, 0, 0): 2627 case IP_VERSION(3, 0, 16): 2628 case IP_VERSION(3, 1, 1): 2629 case IP_VERSION(3, 1, 2): 2630 case IP_VERSION(3, 0, 2): 2631 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2632 if (!amdgpu_sriov_vf(adev)) 2633 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 2634 break; 2635 case IP_VERSION(3, 0, 33): 2636 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2637 break; 2638 case IP_VERSION(4, 0, 0): 2639 case IP_VERSION(4, 0, 2): 2640 case IP_VERSION(4, 0, 4): 2641 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block); 2642 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block); 2643 break; 2644 case IP_VERSION(4, 0, 3): 2645 amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block); 2646 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block); 2647 break; 2648 case IP_VERSION(4, 0, 5): 2649 case IP_VERSION(4, 0, 6): 2650 amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block); 2651 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block); 2652 break; 2653 case IP_VERSION(5, 0, 0): 2654 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block); 2655 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block); 2656 break; 2657 case IP_VERSION(5, 3, 0): 2658 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block); 2659 amdgpu_device_ip_block_add(adev, &jpeg_v5_3_0_ip_block); 2660 break; 2661 case IP_VERSION(5, 0, 1): 2662 amdgpu_device_ip_block_add(adev, &vcn_v5_0_1_ip_block); 2663 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_1_ip_block); 2664 break; 2665 case IP_VERSION(5, 0, 2): 2666 amdgpu_device_ip_block_add(adev, &vcn_v5_0_2_ip_block); 2667 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_2_ip_block); 2668 break; 2669 default: 2670 dev_err(adev->dev, 2671 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 2672 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2673 return -EINVAL; 2674 } 2675 } 2676 return 0; 2677 } 2678 2679 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 2680 { 2681 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2682 case IP_VERSION(11, 0, 0): 2683 case IP_VERSION(11, 0, 1): 2684 case IP_VERSION(11, 0, 2): 2685 case IP_VERSION(11, 0, 3): 2686 case IP_VERSION(11, 0, 4): 2687 case IP_VERSION(11, 5, 0): 2688 case IP_VERSION(11, 5, 1): 2689 case IP_VERSION(11, 5, 2): 2690 case IP_VERSION(11, 5, 3): 2691 case IP_VERSION(11, 5, 4): 2692 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block); 2693 adev->enable_mes = true; 2694 adev->enable_mes_kiq = true; 2695 break; 2696 case IP_VERSION(12, 0, 0): 2697 case IP_VERSION(12, 0, 1): 2698 amdgpu_device_ip_block_add(adev, &mes_v12_0_ip_block); 2699 adev->enable_mes = true; 2700 adev->enable_mes_kiq = true; 2701 if (amdgpu_uni_mes) 2702 adev->enable_uni_mes = true; 2703 break; 2704 case IP_VERSION(12, 1, 0): 2705 amdgpu_device_ip_block_add(adev, &mes_v12_1_ip_block); 2706 adev->enable_mes = true; 2707 adev->enable_mes_kiq = true; 2708 if (amdgpu_uni_mes) 2709 adev->enable_uni_mes = true; 2710 break; 2711 default: 2712 break; 2713 } 2714 return 0; 2715 } 2716 2717 static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev) 2718 { 2719 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2720 case IP_VERSION(9, 4, 3): 2721 case IP_VERSION(9, 4, 4): 2722 case IP_VERSION(9, 5, 0): 2723 aqua_vanjaram_init_soc_config(adev); 2724 break; 2725 case IP_VERSION(12, 1, 0): 2726 soc_v1_0_init_soc_config(adev); 2727 break; 2728 default: 2729 break; 2730 } 2731 } 2732 2733 static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev) 2734 { 2735 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) { 2736 case IP_VERSION(6, 1, 0): 2737 case IP_VERSION(6, 1, 1): 2738 case IP_VERSION(6, 1, 3): 2739 amdgpu_device_ip_block_add(adev, &vpe_v6_1_ip_block); 2740 break; 2741 case IP_VERSION(2, 0, 0): 2742 amdgpu_device_ip_block_add(adev, &vpe_v2_0_ip_block); 2743 break; 2744 default: 2745 break; 2746 } 2747 2748 return 0; 2749 } 2750 2751 static int amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device *adev) 2752 { 2753 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) { 2754 case IP_VERSION(4, 0, 5): 2755 case IP_VERSION(4, 0, 6): 2756 if (amdgpu_umsch_mm & 0x1) { 2757 amdgpu_device_ip_block_add(adev, &umsch_mm_v4_0_ip_block); 2758 adev->enable_umsch_mm = true; 2759 } 2760 break; 2761 default: 2762 break; 2763 } 2764 2765 return 0; 2766 } 2767 2768 static int amdgpu_discovery_set_isp_ip_blocks(struct amdgpu_device *adev) 2769 { 2770 #if defined(CONFIG_DRM_AMD_ISP) 2771 switch (amdgpu_ip_version(adev, ISP_HWIP, 0)) { 2772 case IP_VERSION(4, 1, 0): 2773 amdgpu_device_ip_block_add(adev, &isp_v4_1_0_ip_block); 2774 break; 2775 case IP_VERSION(4, 1, 1): 2776 amdgpu_device_ip_block_add(adev, &isp_v4_1_1_ip_block); 2777 break; 2778 default: 2779 break; 2780 } 2781 #endif 2782 2783 return 0; 2784 } 2785 2786 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 2787 { 2788 int r; 2789 2790 switch (adev->asic_type) { 2791 case CHIP_VEGA10: 2792 /* This is not fatal. We only need the discovery 2793 * binary for sysfs. We don't need it for a 2794 * functional system. 2795 */ 2796 amdgpu_discovery_init(adev); 2797 vega10_reg_base_init(adev); 2798 adev->sdma.num_instances = 2; 2799 adev->sdma.sdma_mask = 3; 2800 adev->gmc.num_umc = 4; 2801 adev->gfx.xcc_mask = 1; 2802 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2803 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2804 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 2805 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 2806 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 2807 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 2808 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2809 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 2810 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 2811 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2812 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2813 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2814 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 2815 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 2816 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2817 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2818 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 2819 break; 2820 case CHIP_VEGA12: 2821 /* This is not fatal. We only need the discovery 2822 * binary for sysfs. We don't need it for a 2823 * functional system. 2824 */ 2825 amdgpu_discovery_init(adev); 2826 vega10_reg_base_init(adev); 2827 adev->sdma.num_instances = 2; 2828 adev->sdma.sdma_mask = 3; 2829 adev->gmc.num_umc = 4; 2830 adev->gfx.xcc_mask = 1; 2831 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2832 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2833 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 2834 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 2835 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 2836 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 2837 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 2838 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 2839 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 2840 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2841 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2842 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2843 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 2844 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 2845 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2846 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2847 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 2848 break; 2849 case CHIP_RAVEN: 2850 /* This is not fatal. We only need the discovery 2851 * binary for sysfs. We don't need it for a 2852 * functional system. 2853 */ 2854 amdgpu_discovery_init(adev); 2855 vega10_reg_base_init(adev); 2856 adev->sdma.num_instances = 1; 2857 adev->sdma.sdma_mask = 1; 2858 adev->vcn.num_vcn_inst = 1; 2859 adev->gmc.num_umc = 2; 2860 adev->gfx.xcc_mask = 1; 2861 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 2862 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2863 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2864 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 2865 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 2866 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 2867 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 2868 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 2869 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 2870 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 2871 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 2872 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 2873 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 2874 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 2875 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 2876 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 2877 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 2878 } else { 2879 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2880 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2881 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 2882 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 2883 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 2884 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2885 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 2886 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 2887 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 2888 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 2889 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 2890 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 2891 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 2892 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 2893 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 2894 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 2895 } 2896 break; 2897 case CHIP_VEGA20: 2898 /* This is not fatal. We only need the discovery 2899 * binary for sysfs. We don't need it for a 2900 * functional system. 2901 */ 2902 amdgpu_discovery_init(adev); 2903 vega20_reg_base_init(adev); 2904 adev->sdma.num_instances = 2; 2905 adev->sdma.sdma_mask = 3; 2906 adev->gmc.num_umc = 8; 2907 adev->gfx.xcc_mask = 1; 2908 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2909 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2910 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 2911 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 2912 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 2913 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 2914 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 2915 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 2916 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 2917 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 2918 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2919 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 2920 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 2921 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 2922 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 2923 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 2924 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 2925 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 2926 break; 2927 case CHIP_ARCTURUS: 2928 /* This is not fatal. We only need the discovery 2929 * binary for sysfs. We don't need it for a 2930 * functional system. 2931 */ 2932 amdgpu_discovery_init(adev); 2933 arct_reg_base_init(adev); 2934 adev->sdma.num_instances = 8; 2935 adev->sdma.sdma_mask = 0xff; 2936 adev->vcn.num_vcn_inst = 2; 2937 adev->gmc.num_umc = 8; 2938 adev->gfx.xcc_mask = 1; 2939 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2940 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2941 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 2942 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 2943 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 2944 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 2945 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 2946 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 2947 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 2948 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 2949 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 2950 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 2951 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 2952 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 2953 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 2954 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 2955 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2956 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 2957 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 2958 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 2959 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 2960 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 2961 break; 2962 case CHIP_ALDEBARAN: 2963 /* This is not fatal. We only need the discovery 2964 * binary for sysfs. We don't need it for a 2965 * functional system. 2966 */ 2967 amdgpu_discovery_init(adev); 2968 aldebaran_reg_base_init(adev); 2969 adev->sdma.num_instances = 5; 2970 adev->sdma.sdma_mask = 0x1f; 2971 adev->vcn.num_vcn_inst = 2; 2972 adev->gmc.num_umc = 4; 2973 adev->gfx.xcc_mask = 1; 2974 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2975 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2976 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 2977 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 2978 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 2979 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 2980 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 2981 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 2982 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 2983 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 2984 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 2985 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 2986 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 2987 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 2988 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 2989 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 2990 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 2991 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 2992 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 2993 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 2994 break; 2995 case CHIP_CYAN_SKILLFISH: 2996 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 2997 r = amdgpu_discovery_reg_base_init(adev); 2998 if (r) 2999 return -EINVAL; 3000 3001 amdgpu_discovery_harvest_ip(adev); 3002 amdgpu_discovery_get_gfx_info(adev); 3003 amdgpu_discovery_get_mall_info(adev); 3004 amdgpu_discovery_get_vcn_info(adev); 3005 } else { 3006 cyan_skillfish_reg_base_init(adev); 3007 adev->sdma.num_instances = 2; 3008 adev->sdma.sdma_mask = 3; 3009 adev->gfx.xcc_mask = 1; 3010 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(2, 0, 3); 3011 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(2, 0, 3); 3012 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(5, 0, 1); 3013 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(5, 0, 1); 3014 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(5, 0, 1); 3015 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(5, 0, 1); 3016 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 5, 0); 3017 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(2, 1, 1); 3018 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(8, 1, 1); 3019 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 8); 3020 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 8); 3021 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 1); 3022 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 8); 3023 adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 1, 3); 3024 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 0, 3); 3025 } 3026 break; 3027 default: 3028 r = amdgpu_discovery_reg_base_init(adev); 3029 if (r) { 3030 drm_err(&adev->ddev, "discovery failed: %d\n", r); 3031 return r; 3032 } 3033 3034 amdgpu_discovery_harvest_ip(adev); 3035 amdgpu_discovery_get_gfx_info(adev); 3036 amdgpu_discovery_get_mall_info(adev); 3037 amdgpu_discovery_get_vcn_info(adev); 3038 break; 3039 } 3040 3041 amdgpu_discovery_init_soc_config(adev); 3042 amdgpu_discovery_sysfs_init(adev); 3043 3044 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3045 case IP_VERSION(9, 0, 1): 3046 case IP_VERSION(9, 2, 1): 3047 case IP_VERSION(9, 4, 0): 3048 case IP_VERSION(9, 4, 1): 3049 case IP_VERSION(9, 4, 2): 3050 case IP_VERSION(9, 4, 3): 3051 case IP_VERSION(9, 4, 4): 3052 case IP_VERSION(9, 5, 0): 3053 adev->family = AMDGPU_FAMILY_AI; 3054 break; 3055 case IP_VERSION(9, 1, 0): 3056 case IP_VERSION(9, 2, 2): 3057 case IP_VERSION(9, 3, 0): 3058 adev->family = AMDGPU_FAMILY_RV; 3059 break; 3060 case IP_VERSION(10, 1, 10): 3061 case IP_VERSION(10, 1, 1): 3062 case IP_VERSION(10, 1, 2): 3063 case IP_VERSION(10, 1, 3): 3064 case IP_VERSION(10, 1, 4): 3065 case IP_VERSION(10, 3, 0): 3066 case IP_VERSION(10, 3, 2): 3067 case IP_VERSION(10, 3, 4): 3068 case IP_VERSION(10, 3, 5): 3069 adev->family = AMDGPU_FAMILY_NV; 3070 break; 3071 case IP_VERSION(10, 3, 1): 3072 adev->family = AMDGPU_FAMILY_VGH; 3073 adev->apu_flags |= AMD_APU_IS_VANGOGH; 3074 break; 3075 case IP_VERSION(10, 3, 3): 3076 adev->family = AMDGPU_FAMILY_YC; 3077 break; 3078 case IP_VERSION(10, 3, 6): 3079 adev->family = AMDGPU_FAMILY_GC_10_3_6; 3080 break; 3081 case IP_VERSION(10, 3, 7): 3082 adev->family = AMDGPU_FAMILY_GC_10_3_7; 3083 break; 3084 case IP_VERSION(11, 0, 0): 3085 case IP_VERSION(11, 0, 2): 3086 case IP_VERSION(11, 0, 3): 3087 adev->family = AMDGPU_FAMILY_GC_11_0_0; 3088 break; 3089 case IP_VERSION(11, 0, 1): 3090 case IP_VERSION(11, 0, 4): 3091 adev->family = AMDGPU_FAMILY_GC_11_0_1; 3092 break; 3093 case IP_VERSION(11, 5, 0): 3094 case IP_VERSION(11, 5, 1): 3095 case IP_VERSION(11, 5, 2): 3096 case IP_VERSION(11, 5, 3): 3097 case IP_VERSION(11, 5, 4): 3098 adev->family = AMDGPU_FAMILY_GC_11_5_0; 3099 break; 3100 case IP_VERSION(12, 0, 0): 3101 case IP_VERSION(12, 0, 1): 3102 case IP_VERSION(12, 1, 0): 3103 adev->family = AMDGPU_FAMILY_GC_12_0_0; 3104 break; 3105 default: 3106 return -EINVAL; 3107 } 3108 3109 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3110 case IP_VERSION(9, 1, 0): 3111 case IP_VERSION(9, 2, 2): 3112 case IP_VERSION(9, 3, 0): 3113 case IP_VERSION(10, 1, 3): 3114 case IP_VERSION(10, 1, 4): 3115 case IP_VERSION(10, 3, 1): 3116 case IP_VERSION(10, 3, 3): 3117 case IP_VERSION(10, 3, 6): 3118 case IP_VERSION(10, 3, 7): 3119 case IP_VERSION(11, 0, 1): 3120 case IP_VERSION(11, 0, 4): 3121 case IP_VERSION(11, 5, 0): 3122 case IP_VERSION(11, 5, 1): 3123 case IP_VERSION(11, 5, 2): 3124 case IP_VERSION(11, 5, 3): 3125 case IP_VERSION(11, 5, 4): 3126 adev->flags |= AMD_IS_APU; 3127 break; 3128 default: 3129 break; 3130 } 3131 3132 /* set NBIO version */ 3133 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 3134 case IP_VERSION(6, 1, 0): 3135 case IP_VERSION(6, 2, 0): 3136 adev->nbio.funcs = &nbio_v6_1_funcs; 3137 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 3138 break; 3139 case IP_VERSION(7, 0, 0): 3140 case IP_VERSION(7, 0, 1): 3141 case IP_VERSION(2, 5, 0): 3142 adev->nbio.funcs = &nbio_v7_0_funcs; 3143 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 3144 break; 3145 case IP_VERSION(7, 4, 0): 3146 case IP_VERSION(7, 4, 1): 3147 case IP_VERSION(7, 4, 4): 3148 adev->nbio.funcs = &nbio_v7_4_funcs; 3149 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 3150 break; 3151 case IP_VERSION(7, 9, 0): 3152 case IP_VERSION(7, 9, 1): 3153 adev->nbio.funcs = &nbio_v7_9_funcs; 3154 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg; 3155 break; 3156 case IP_VERSION(7, 11, 0): 3157 case IP_VERSION(7, 11, 1): 3158 case IP_VERSION(7, 11, 2): 3159 case IP_VERSION(7, 11, 3): 3160 adev->nbio.funcs = &nbio_v7_11_funcs; 3161 adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg; 3162 break; 3163 case IP_VERSION(7, 2, 0): 3164 case IP_VERSION(7, 2, 1): 3165 case IP_VERSION(7, 3, 0): 3166 case IP_VERSION(7, 5, 0): 3167 case IP_VERSION(7, 5, 1): 3168 adev->nbio.funcs = &nbio_v7_2_funcs; 3169 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 3170 break; 3171 case IP_VERSION(2, 1, 1): 3172 case IP_VERSION(2, 3, 0): 3173 case IP_VERSION(2, 3, 1): 3174 case IP_VERSION(2, 3, 2): 3175 case IP_VERSION(3, 3, 0): 3176 case IP_VERSION(3, 3, 1): 3177 case IP_VERSION(3, 3, 2): 3178 case IP_VERSION(3, 3, 3): 3179 adev->nbio.funcs = &nbio_v2_3_funcs; 3180 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 3181 break; 3182 case IP_VERSION(4, 3, 0): 3183 case IP_VERSION(4, 3, 1): 3184 if (amdgpu_sriov_vf(adev)) 3185 adev->nbio.funcs = &nbio_v4_3_sriov_funcs; 3186 else 3187 adev->nbio.funcs = &nbio_v4_3_funcs; 3188 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg; 3189 break; 3190 case IP_VERSION(7, 7, 0): 3191 case IP_VERSION(7, 7, 1): 3192 adev->nbio.funcs = &nbio_v7_7_funcs; 3193 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg; 3194 break; 3195 case IP_VERSION(6, 3, 1): 3196 case IP_VERSION(7, 11, 4): 3197 adev->nbio.funcs = &nbif_v6_3_1_funcs; 3198 adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg; 3199 break; 3200 case IP_VERSION(6, 3, 2): 3201 adev->nbio.funcs = &nbio_v6_3_2_funcs; 3202 break; 3203 default: 3204 break; 3205 } 3206 3207 switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) { 3208 case IP_VERSION(4, 0, 0): 3209 case IP_VERSION(4, 0, 1): 3210 case IP_VERSION(4, 1, 0): 3211 case IP_VERSION(4, 1, 1): 3212 case IP_VERSION(4, 1, 2): 3213 case IP_VERSION(4, 2, 0): 3214 case IP_VERSION(4, 2, 1): 3215 case IP_VERSION(4, 4, 0): 3216 case IP_VERSION(4, 4, 2): 3217 case IP_VERSION(4, 4, 5): 3218 adev->hdp.funcs = &hdp_v4_0_funcs; 3219 break; 3220 case IP_VERSION(5, 0, 0): 3221 case IP_VERSION(5, 0, 1): 3222 case IP_VERSION(5, 0, 2): 3223 case IP_VERSION(5, 0, 3): 3224 case IP_VERSION(5, 0, 4): 3225 case IP_VERSION(5, 2, 0): 3226 adev->hdp.funcs = &hdp_v5_0_funcs; 3227 break; 3228 case IP_VERSION(5, 2, 1): 3229 adev->hdp.funcs = &hdp_v5_2_funcs; 3230 break; 3231 case IP_VERSION(6, 0, 0): 3232 case IP_VERSION(6, 0, 1): 3233 case IP_VERSION(6, 1, 0): 3234 case IP_VERSION(6, 1, 1): 3235 adev->hdp.funcs = &hdp_v6_0_funcs; 3236 break; 3237 case IP_VERSION(7, 0, 0): 3238 adev->hdp.funcs = &hdp_v7_0_funcs; 3239 break; 3240 default: 3241 break; 3242 } 3243 3244 switch (amdgpu_ip_version(adev, DF_HWIP, 0)) { 3245 case IP_VERSION(3, 6, 0): 3246 case IP_VERSION(3, 6, 1): 3247 case IP_VERSION(3, 6, 2): 3248 adev->df.funcs = &df_v3_6_funcs; 3249 break; 3250 case IP_VERSION(2, 1, 0): 3251 case IP_VERSION(2, 1, 1): 3252 case IP_VERSION(2, 5, 0): 3253 case IP_VERSION(3, 5, 1): 3254 case IP_VERSION(3, 5, 2): 3255 adev->df.funcs = &df_v1_7_funcs; 3256 break; 3257 case IP_VERSION(4, 3, 0): 3258 adev->df.funcs = &df_v4_3_funcs; 3259 break; 3260 case IP_VERSION(4, 6, 2): 3261 adev->df.funcs = &df_v4_6_2_funcs; 3262 break; 3263 case IP_VERSION(4, 15, 0): 3264 case IP_VERSION(4, 15, 1): 3265 adev->df.funcs = &df_v4_15_funcs; 3266 break; 3267 default: 3268 break; 3269 } 3270 3271 switch (amdgpu_ip_version(adev, SMUIO_HWIP, 0)) { 3272 case IP_VERSION(9, 0, 0): 3273 case IP_VERSION(9, 0, 1): 3274 case IP_VERSION(10, 0, 0): 3275 case IP_VERSION(10, 0, 1): 3276 case IP_VERSION(10, 0, 2): 3277 adev->smuio.funcs = &smuio_v9_0_funcs; 3278 break; 3279 case IP_VERSION(11, 0, 0): 3280 case IP_VERSION(11, 0, 2): 3281 case IP_VERSION(11, 0, 3): 3282 case IP_VERSION(11, 0, 4): 3283 case IP_VERSION(11, 0, 7): 3284 case IP_VERSION(11, 0, 8): 3285 adev->smuio.funcs = &smuio_v11_0_funcs; 3286 break; 3287 case IP_VERSION(11, 0, 6): 3288 case IP_VERSION(11, 0, 10): 3289 case IP_VERSION(11, 0, 11): 3290 case IP_VERSION(11, 5, 0): 3291 case IP_VERSION(11, 5, 2): 3292 case IP_VERSION(13, 0, 1): 3293 case IP_VERSION(13, 0, 9): 3294 case IP_VERSION(13, 0, 10): 3295 adev->smuio.funcs = &smuio_v11_0_6_funcs; 3296 break; 3297 case IP_VERSION(13, 0, 2): 3298 adev->smuio.funcs = &smuio_v13_0_funcs; 3299 break; 3300 case IP_VERSION(13, 0, 3): 3301 case IP_VERSION(13, 0, 11): 3302 adev->smuio.funcs = &smuio_v13_0_3_funcs; 3303 if (adev->smuio.funcs->get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) { 3304 adev->flags |= AMD_IS_APU; 3305 } 3306 break; 3307 case IP_VERSION(13, 0, 6): 3308 case IP_VERSION(13, 0, 8): 3309 case IP_VERSION(14, 0, 0): 3310 case IP_VERSION(14, 0, 1): 3311 adev->smuio.funcs = &smuio_v13_0_6_funcs; 3312 break; 3313 case IP_VERSION(14, 0, 2): 3314 adev->smuio.funcs = &smuio_v14_0_2_funcs; 3315 break; 3316 case IP_VERSION(15, 0, 0): 3317 adev->smuio.funcs = &smuio_v15_0_0_funcs; 3318 break; 3319 case IP_VERSION(15, 0, 8): 3320 adev->smuio.funcs = &smuio_v15_0_8_funcs; 3321 break; 3322 default: 3323 break; 3324 } 3325 3326 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { 3327 case IP_VERSION(6, 0, 0): 3328 case IP_VERSION(6, 0, 1): 3329 case IP_VERSION(6, 0, 2): 3330 case IP_VERSION(6, 0, 3): 3331 adev->lsdma.funcs = &lsdma_v6_0_funcs; 3332 break; 3333 case IP_VERSION(7, 0, 0): 3334 case IP_VERSION(7, 0, 1): 3335 adev->lsdma.funcs = &lsdma_v7_0_funcs; 3336 break; 3337 case IP_VERSION(7, 1, 0): 3338 adev->lsdma.funcs = &lsdma_v7_1_funcs; 3339 break; 3340 default: 3341 break; 3342 } 3343 3344 r = amdgpu_discovery_set_common_ip_blocks(adev); 3345 if (r) 3346 return r; 3347 3348 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 3349 if (r) 3350 return r; 3351 3352 /* For SR-IOV, PSP needs to be initialized before IH */ 3353 if (amdgpu_sriov_vf(adev)) { 3354 r = amdgpu_discovery_set_psp_ip_blocks(adev); 3355 if (r) 3356 return r; 3357 r = amdgpu_discovery_set_ih_ip_blocks(adev); 3358 if (r) 3359 return r; 3360 } else { 3361 r = amdgpu_discovery_set_ih_ip_blocks(adev); 3362 if (r) 3363 return r; 3364 3365 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3366 r = amdgpu_discovery_set_psp_ip_blocks(adev); 3367 if (r) 3368 return r; 3369 } 3370 } 3371 3372 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3373 r = amdgpu_discovery_set_smu_ip_blocks(adev); 3374 if (r) 3375 return r; 3376 } 3377 3378 r = amdgpu_discovery_set_display_ip_blocks(adev); 3379 if (r) 3380 return r; 3381 3382 r = amdgpu_discovery_set_gc_ip_blocks(adev); 3383 if (r) 3384 return r; 3385 3386 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 3387 if (r) 3388 return r; 3389 3390 r = amdgpu_discovery_set_ras_ip_blocks(adev); 3391 if (r) 3392 return r; 3393 3394 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 3395 !amdgpu_sriov_vf(adev) && 3396 amdgpu_dpm == 1) || 3397 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && 3398 amdgpu_dpm == 1)) { 3399 r = amdgpu_discovery_set_smu_ip_blocks(adev); 3400 if (r) 3401 return r; 3402 } 3403 3404 r = amdgpu_discovery_set_mm_ip_blocks(adev); 3405 if (r) 3406 return r; 3407 3408 r = amdgpu_discovery_set_mes_ip_blocks(adev); 3409 if (r) 3410 return r; 3411 3412 r = amdgpu_discovery_set_vpe_ip_blocks(adev); 3413 if (r) 3414 return r; 3415 3416 r = amdgpu_discovery_set_umsch_mm_ip_blocks(adev); 3417 if (r) 3418 return r; 3419 3420 r = amdgpu_discovery_set_isp_ip_blocks(adev); 3421 if (r) 3422 return r; 3423 return 0; 3424 } 3425 3426 int amdgpu_discovery_get_gc_major_minor_version(struct amdgpu_device *adev, 3427 uint16_t *major, uint16_t *minor) 3428 { 3429 uint8_t *discovery_bin = adev->discovery.bin; 3430 struct table_info *info; 3431 union gc_info *gc_info; 3432 u16 offset; 3433 3434 if (!discovery_bin) 3435 return -EINVAL; 3436 if (amdgpu_discovery_get_table_info(adev, &info, GC)) 3437 return -EINVAL; 3438 3439 offset = le16_to_cpu(info->offset); 3440 if (!offset) 3441 return -EINVAL; 3442 3443 gc_info = (union gc_info *)(discovery_bin + offset); 3444 3445 if (major) 3446 *major = le16_to_cpu(gc_info->v1.header.version_major); 3447 if (minor) 3448 *minor = le16_to_cpu(gc_info->v1.header.version_minor); 3449 return 0; 3450 } 3451