1 /* 2 * Copyright 2018-2024 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_discovery.h" 28 #include "soc15_hw_ip.h" 29 #include "discovery.h" 30 #include "amdgpu_ras.h" 31 32 #include "soc15.h" 33 #include "gfx_v9_0.h" 34 #include "gfx_v9_4_3.h" 35 #include "gmc_v9_0.h" 36 #include "df_v1_7.h" 37 #include "df_v3_6.h" 38 #include "df_v4_3.h" 39 #include "df_v4_6_2.h" 40 #include "df_v4_15.h" 41 #include "nbio_v6_1.h" 42 #include "nbio_v7_0.h" 43 #include "nbio_v7_4.h" 44 #include "nbio_v7_9.h" 45 #include "nbio_v7_11.h" 46 #include "hdp_v4_0.h" 47 #include "vega10_ih.h" 48 #include "vega20_ih.h" 49 #include "sdma_v4_0.h" 50 #include "sdma_v4_4_2.h" 51 #include "uvd_v7_0.h" 52 #include "vce_v4_0.h" 53 #include "vcn_v1_0.h" 54 #include "vcn_v2_5.h" 55 #include "jpeg_v2_5.h" 56 #include "smuio_v9_0.h" 57 #include "gmc_v10_0.h" 58 #include "gmc_v11_0.h" 59 #include "gmc_v12_0.h" 60 #include "gfxhub_v2_0.h" 61 #include "mmhub_v2_0.h" 62 #include "nbio_v2_3.h" 63 #include "nbio_v4_3.h" 64 #include "nbio_v7_2.h" 65 #include "nbio_v7_7.h" 66 #include "nbif_v6_3_1.h" 67 #include "hdp_v5_0.h" 68 #include "hdp_v5_2.h" 69 #include "hdp_v6_0.h" 70 #include "hdp_v7_0.h" 71 #include "nv.h" 72 #include "soc21.h" 73 #include "soc24.h" 74 #include "navi10_ih.h" 75 #include "ih_v6_0.h" 76 #include "ih_v6_1.h" 77 #include "ih_v7_0.h" 78 #include "gfx_v10_0.h" 79 #include "gfx_v11_0.h" 80 #include "gfx_v12_0.h" 81 #include "sdma_v5_0.h" 82 #include "sdma_v5_2.h" 83 #include "sdma_v6_0.h" 84 #include "sdma_v7_0.h" 85 #include "lsdma_v6_0.h" 86 #include "lsdma_v7_0.h" 87 #include "vcn_v2_0.h" 88 #include "jpeg_v2_0.h" 89 #include "vcn_v3_0.h" 90 #include "jpeg_v3_0.h" 91 #include "vcn_v4_0.h" 92 #include "jpeg_v4_0.h" 93 #include "vcn_v4_0_3.h" 94 #include "jpeg_v4_0_3.h" 95 #include "vcn_v4_0_5.h" 96 #include "jpeg_v4_0_5.h" 97 #include "amdgpu_vkms.h" 98 #include "mes_v11_0.h" 99 #include "mes_v12_0.h" 100 #include "smuio_v11_0.h" 101 #include "smuio_v11_0_6.h" 102 #include "smuio_v13_0.h" 103 #include "smuio_v13_0_3.h" 104 #include "smuio_v13_0_6.h" 105 #include "smuio_v14_0_2.h" 106 #include "vcn_v5_0_0.h" 107 #include "vcn_v5_0_1.h" 108 #include "jpeg_v5_0_0.h" 109 #include "jpeg_v5_0_1.h" 110 111 #include "amdgpu_vpe.h" 112 #if defined(CONFIG_DRM_AMD_ISP) 113 #include "amdgpu_isp.h" 114 #endif 115 116 MODULE_FIRMWARE("amdgpu/ip_discovery.bin"); 117 MODULE_FIRMWARE("amdgpu/vega10_ip_discovery.bin"); 118 MODULE_FIRMWARE("amdgpu/vega12_ip_discovery.bin"); 119 MODULE_FIRMWARE("amdgpu/vega20_ip_discovery.bin"); 120 MODULE_FIRMWARE("amdgpu/raven_ip_discovery.bin"); 121 MODULE_FIRMWARE("amdgpu/raven2_ip_discovery.bin"); 122 MODULE_FIRMWARE("amdgpu/picasso_ip_discovery.bin"); 123 MODULE_FIRMWARE("amdgpu/arcturus_ip_discovery.bin"); 124 MODULE_FIRMWARE("amdgpu/aldebaran_ip_discovery.bin"); 125 126 #define mmIP_DISCOVERY_VERSION 0x16A00 127 #define mmRCC_CONFIG_MEMSIZE 0xde3 128 #define mmMP0_SMN_C2PMSG_33 0x16061 129 #define mmMM_INDEX 0x0 130 #define mmMM_INDEX_HI 0x6 131 #define mmMM_DATA 0x1 132 133 static const char *hw_id_names[HW_ID_MAX] = { 134 [MP1_HWID] = "MP1", 135 [MP2_HWID] = "MP2", 136 [THM_HWID] = "THM", 137 [SMUIO_HWID] = "SMUIO", 138 [FUSE_HWID] = "FUSE", 139 [CLKA_HWID] = "CLKA", 140 [PWR_HWID] = "PWR", 141 [GC_HWID] = "GC", 142 [UVD_HWID] = "UVD", 143 [AUDIO_AZ_HWID] = "AUDIO_AZ", 144 [ACP_HWID] = "ACP", 145 [DCI_HWID] = "DCI", 146 [DMU_HWID] = "DMU", 147 [DCO_HWID] = "DCO", 148 [DIO_HWID] = "DIO", 149 [XDMA_HWID] = "XDMA", 150 [DCEAZ_HWID] = "DCEAZ", 151 [DAZ_HWID] = "DAZ", 152 [SDPMUX_HWID] = "SDPMUX", 153 [NTB_HWID] = "NTB", 154 [IOHC_HWID] = "IOHC", 155 [L2IMU_HWID] = "L2IMU", 156 [VCE_HWID] = "VCE", 157 [MMHUB_HWID] = "MMHUB", 158 [ATHUB_HWID] = "ATHUB", 159 [DBGU_NBIO_HWID] = "DBGU_NBIO", 160 [DFX_HWID] = "DFX", 161 [DBGU0_HWID] = "DBGU0", 162 [DBGU1_HWID] = "DBGU1", 163 [OSSSYS_HWID] = "OSSSYS", 164 [HDP_HWID] = "HDP", 165 [SDMA0_HWID] = "SDMA0", 166 [SDMA1_HWID] = "SDMA1", 167 [SDMA2_HWID] = "SDMA2", 168 [SDMA3_HWID] = "SDMA3", 169 [LSDMA_HWID] = "LSDMA", 170 [ISP_HWID] = "ISP", 171 [DBGU_IO_HWID] = "DBGU_IO", 172 [DF_HWID] = "DF", 173 [CLKB_HWID] = "CLKB", 174 [FCH_HWID] = "FCH", 175 [DFX_DAP_HWID] = "DFX_DAP", 176 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 177 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 178 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 179 [L1IMU3_HWID] = "L1IMU3", 180 [L1IMU4_HWID] = "L1IMU4", 181 [L1IMU5_HWID] = "L1IMU5", 182 [L1IMU6_HWID] = "L1IMU6", 183 [L1IMU7_HWID] = "L1IMU7", 184 [L1IMU8_HWID] = "L1IMU8", 185 [L1IMU9_HWID] = "L1IMU9", 186 [L1IMU10_HWID] = "L1IMU10", 187 [L1IMU11_HWID] = "L1IMU11", 188 [L1IMU12_HWID] = "L1IMU12", 189 [L1IMU13_HWID] = "L1IMU13", 190 [L1IMU14_HWID] = "L1IMU14", 191 [L1IMU15_HWID] = "L1IMU15", 192 [WAFLC_HWID] = "WAFLC", 193 [FCH_USB_PD_HWID] = "FCH_USB_PD", 194 [PCIE_HWID] = "PCIE", 195 [PCS_HWID] = "PCS", 196 [DDCL_HWID] = "DDCL", 197 [SST_HWID] = "SST", 198 [IOAGR_HWID] = "IOAGR", 199 [NBIF_HWID] = "NBIF", 200 [IOAPIC_HWID] = "IOAPIC", 201 [SYSTEMHUB_HWID] = "SYSTEMHUB", 202 [NTBCCP_HWID] = "NTBCCP", 203 [UMC_HWID] = "UMC", 204 [SATA_HWID] = "SATA", 205 [USB_HWID] = "USB", 206 [CCXSEC_HWID] = "CCXSEC", 207 [XGMI_HWID] = "XGMI", 208 [XGBE_HWID] = "XGBE", 209 [MP0_HWID] = "MP0", 210 [VPE_HWID] = "VPE", 211 }; 212 213 static int hw_id_map[MAX_HWIP] = { 214 [GC_HWIP] = GC_HWID, 215 [HDP_HWIP] = HDP_HWID, 216 [SDMA0_HWIP] = SDMA0_HWID, 217 [SDMA1_HWIP] = SDMA1_HWID, 218 [SDMA2_HWIP] = SDMA2_HWID, 219 [SDMA3_HWIP] = SDMA3_HWID, 220 [LSDMA_HWIP] = LSDMA_HWID, 221 [MMHUB_HWIP] = MMHUB_HWID, 222 [ATHUB_HWIP] = ATHUB_HWID, 223 [NBIO_HWIP] = NBIF_HWID, 224 [MP0_HWIP] = MP0_HWID, 225 [MP1_HWIP] = MP1_HWID, 226 [UVD_HWIP] = UVD_HWID, 227 [VCE_HWIP] = VCE_HWID, 228 [DF_HWIP] = DF_HWID, 229 [DCE_HWIP] = DMU_HWID, 230 [OSSSYS_HWIP] = OSSSYS_HWID, 231 [SMUIO_HWIP] = SMUIO_HWID, 232 [PWR_HWIP] = PWR_HWID, 233 [NBIF_HWIP] = NBIF_HWID, 234 [THM_HWIP] = THM_HWID, 235 [CLK_HWIP] = CLKA_HWID, 236 [UMC_HWIP] = UMC_HWID, 237 [XGMI_HWIP] = XGMI_HWID, 238 [DCI_HWIP] = DCI_HWID, 239 [PCIE_HWIP] = PCIE_HWID, 240 [VPE_HWIP] = VPE_HWID, 241 [ISP_HWIP] = ISP_HWID, 242 }; 243 244 static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary) 245 { 246 u64 tmr_offset, tmr_size, pos; 247 void *discv_regn; 248 int ret; 249 250 ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size); 251 if (ret) 252 return ret; 253 254 pos = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET; 255 256 /* This region is read-only and reserved from system use */ 257 discv_regn = memremap(pos, adev->mman.discovery_tmr_size, MEMREMAP_WC); 258 if (discv_regn) { 259 memcpy(binary, discv_regn, adev->mman.discovery_tmr_size); 260 memunmap(discv_regn); 261 return 0; 262 } 263 264 return -ENOENT; 265 } 266 267 #define IP_DISCOVERY_V2 2 268 #define IP_DISCOVERY_V4 4 269 270 static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, 271 uint8_t *binary) 272 { 273 bool sz_valid = true; 274 uint64_t vram_size; 275 int i, ret = 0; 276 u32 msg; 277 278 if (!amdgpu_sriov_vf(adev)) { 279 /* It can take up to a second for IFWI init to complete on some dGPUs, 280 * but generally it should be in the 60-100ms range. Normally this starts 281 * as soon as the device gets power so by the time the OS loads this has long 282 * completed. However, when a card is hotplugged via e.g., USB4, we need to 283 * wait for this to complete. Once the C2PMSG is updated, we can 284 * continue. 285 */ 286 287 for (i = 0; i < 1000; i++) { 288 msg = RREG32(mmMP0_SMN_C2PMSG_33); 289 if (msg & 0x80000000) 290 break; 291 msleep(1); 292 } 293 } 294 295 vram_size = RREG32(mmRCC_CONFIG_MEMSIZE); 296 if (!vram_size || vram_size == U32_MAX) 297 sz_valid = false; 298 else 299 vram_size <<= 20; 300 301 if (sz_valid) { 302 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; 303 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, 304 adev->mman.discovery_tmr_size, false); 305 } else { 306 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); 307 } 308 309 if (ret) 310 dev_err(adev->dev, 311 "failed to read discovery info from memory, vram size read: %llx", 312 vram_size); 313 314 return ret; 315 } 316 317 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, 318 uint8_t *binary, 319 const char *fw_name) 320 { 321 const struct firmware *fw; 322 int r; 323 324 r = request_firmware(&fw, fw_name, adev->dev); 325 if (r) { 326 dev_err(adev->dev, "can't load firmware \"%s\"\n", 327 fw_name); 328 return r; 329 } 330 331 memcpy((u8 *)binary, (u8 *)fw->data, fw->size); 332 release_firmware(fw); 333 334 return 0; 335 } 336 337 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 338 { 339 uint16_t checksum = 0; 340 int i; 341 342 for (i = 0; i < size; i++) 343 checksum += data[i]; 344 345 return checksum; 346 } 347 348 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size, 349 uint16_t expected) 350 { 351 return !!(amdgpu_discovery_calculate_checksum(data, size) == expected); 352 } 353 354 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 355 { 356 struct binary_header *bhdr; 357 bhdr = (struct binary_header *)binary; 358 359 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 360 } 361 362 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) 363 { 364 /* 365 * So far, apply this quirk only on those Navy Flounder boards which 366 * have a bad harvest table of VCN config. 367 */ 368 if ((amdgpu_ip_version(adev, UVD_HWIP, 1) == IP_VERSION(3, 0, 1)) && 369 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 2))) { 370 switch (adev->pdev->revision) { 371 case 0xC1: 372 case 0xC2: 373 case 0xC3: 374 case 0xC5: 375 case 0xC7: 376 case 0xCF: 377 case 0xDF: 378 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 379 adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1; 380 break; 381 default: 382 break; 383 } 384 } 385 } 386 387 static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev, 388 struct binary_header *bhdr) 389 { 390 struct table_info *info; 391 uint16_t checksum; 392 uint16_t offset; 393 394 info = &bhdr->table_list[NPS_INFO]; 395 offset = le16_to_cpu(info->offset); 396 checksum = le16_to_cpu(info->checksum); 397 398 struct nps_info_header *nhdr = 399 (struct nps_info_header *)(adev->mman.discovery_bin + offset); 400 401 if (le32_to_cpu(nhdr->table_id) != NPS_INFO_TABLE_ID) { 402 dev_dbg(adev->dev, "invalid ip discovery nps info table id\n"); 403 return -EINVAL; 404 } 405 406 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 407 le32_to_cpu(nhdr->size_bytes), 408 checksum)) { 409 dev_dbg(adev->dev, "invalid nps info data table checksum\n"); 410 return -EINVAL; 411 } 412 413 return 0; 414 } 415 416 static const char *amdgpu_discovery_get_fw_name(struct amdgpu_device *adev) 417 { 418 if (amdgpu_discovery == 2) 419 return "amdgpu/ip_discovery.bin"; 420 421 switch (adev->asic_type) { 422 case CHIP_VEGA10: 423 return "amdgpu/vega10_ip_discovery.bin"; 424 case CHIP_VEGA12: 425 return "amdgpu/vega12_ip_discovery.bin"; 426 case CHIP_RAVEN: 427 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 428 return "amdgpu/raven2_ip_discovery.bin"; 429 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 430 return "amdgpu/picasso_ip_discovery.bin"; 431 else 432 return "amdgpu/raven_ip_discovery.bin"; 433 case CHIP_VEGA20: 434 return "amdgpu/vega20_ip_discovery.bin"; 435 case CHIP_ARCTURUS: 436 return "amdgpu/arcturus_ip_discovery.bin"; 437 case CHIP_ALDEBARAN: 438 return "amdgpu/aldebaran_ip_discovery.bin"; 439 default: 440 return NULL; 441 } 442 } 443 444 static int amdgpu_discovery_init(struct amdgpu_device *adev) 445 { 446 struct table_info *info; 447 struct binary_header *bhdr; 448 const char *fw_name; 449 uint16_t offset; 450 uint16_t size; 451 uint16_t checksum; 452 int r; 453 454 adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE; 455 adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL); 456 if (!adev->mman.discovery_bin) 457 return -ENOMEM; 458 459 /* Read from file if it is the preferred option */ 460 fw_name = amdgpu_discovery_get_fw_name(adev); 461 if (fw_name != NULL) { 462 dev_info(adev->dev, "use ip discovery information from file"); 463 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin, fw_name); 464 465 if (r) { 466 dev_err(adev->dev, "failed to read ip discovery binary from file\n"); 467 r = -EINVAL; 468 goto out; 469 } 470 471 } else { 472 r = amdgpu_discovery_read_binary_from_mem( 473 adev, adev->mman.discovery_bin); 474 if (r) 475 goto out; 476 } 477 478 /* check the ip discovery binary signature */ 479 if (!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) { 480 dev_err(adev->dev, 481 "get invalid ip discovery binary signature\n"); 482 r = -EINVAL; 483 goto out; 484 } 485 486 bhdr = (struct binary_header *)adev->mman.discovery_bin; 487 488 offset = offsetof(struct binary_header, binary_checksum) + 489 sizeof(bhdr->binary_checksum); 490 size = le16_to_cpu(bhdr->binary_size) - offset; 491 checksum = le16_to_cpu(bhdr->binary_checksum); 492 493 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 494 size, checksum)) { 495 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 496 r = -EINVAL; 497 goto out; 498 } 499 500 info = &bhdr->table_list[IP_DISCOVERY]; 501 offset = le16_to_cpu(info->offset); 502 checksum = le16_to_cpu(info->checksum); 503 504 if (offset) { 505 struct ip_discovery_header *ihdr = 506 (struct ip_discovery_header *)(adev->mman.discovery_bin + offset); 507 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { 508 dev_err(adev->dev, "invalid ip discovery data table signature\n"); 509 r = -EINVAL; 510 goto out; 511 } 512 513 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 514 le16_to_cpu(ihdr->size), checksum)) { 515 dev_err(adev->dev, "invalid ip discovery data table checksum\n"); 516 r = -EINVAL; 517 goto out; 518 } 519 } 520 521 info = &bhdr->table_list[GC]; 522 offset = le16_to_cpu(info->offset); 523 checksum = le16_to_cpu(info->checksum); 524 525 if (offset) { 526 struct gpu_info_header *ghdr = 527 (struct gpu_info_header *)(adev->mman.discovery_bin + offset); 528 529 if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) { 530 dev_err(adev->dev, "invalid ip discovery gc table id\n"); 531 r = -EINVAL; 532 goto out; 533 } 534 535 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 536 le32_to_cpu(ghdr->size), checksum)) { 537 dev_err(adev->dev, "invalid gc data table checksum\n"); 538 r = -EINVAL; 539 goto out; 540 } 541 } 542 543 info = &bhdr->table_list[HARVEST_INFO]; 544 offset = le16_to_cpu(info->offset); 545 checksum = le16_to_cpu(info->checksum); 546 547 if (offset) { 548 struct harvest_info_header *hhdr = 549 (struct harvest_info_header *)(adev->mman.discovery_bin + offset); 550 551 if (le32_to_cpu(hhdr->signature) != HARVEST_TABLE_SIGNATURE) { 552 dev_err(adev->dev, "invalid ip discovery harvest table signature\n"); 553 r = -EINVAL; 554 goto out; 555 } 556 557 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 558 sizeof(struct harvest_table), checksum)) { 559 dev_err(adev->dev, "invalid harvest data table checksum\n"); 560 r = -EINVAL; 561 goto out; 562 } 563 } 564 565 info = &bhdr->table_list[VCN_INFO]; 566 offset = le16_to_cpu(info->offset); 567 checksum = le16_to_cpu(info->checksum); 568 569 if (offset) { 570 struct vcn_info_header *vhdr = 571 (struct vcn_info_header *)(adev->mman.discovery_bin + offset); 572 573 if (le32_to_cpu(vhdr->table_id) != VCN_INFO_TABLE_ID) { 574 dev_err(adev->dev, "invalid ip discovery vcn table id\n"); 575 r = -EINVAL; 576 goto out; 577 } 578 579 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 580 le32_to_cpu(vhdr->size_bytes), checksum)) { 581 dev_err(adev->dev, "invalid vcn data table checksum\n"); 582 r = -EINVAL; 583 goto out; 584 } 585 } 586 587 info = &bhdr->table_list[MALL_INFO]; 588 offset = le16_to_cpu(info->offset); 589 checksum = le16_to_cpu(info->checksum); 590 591 if (0 && offset) { 592 struct mall_info_header *mhdr = 593 (struct mall_info_header *)(adev->mman.discovery_bin + offset); 594 595 if (le32_to_cpu(mhdr->table_id) != MALL_INFO_TABLE_ID) { 596 dev_err(adev->dev, "invalid ip discovery mall table id\n"); 597 r = -EINVAL; 598 goto out; 599 } 600 601 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 602 le32_to_cpu(mhdr->size_bytes), checksum)) { 603 dev_err(adev->dev, "invalid mall data table checksum\n"); 604 r = -EINVAL; 605 goto out; 606 } 607 } 608 609 return 0; 610 611 out: 612 kfree(adev->mman.discovery_bin); 613 adev->mman.discovery_bin = NULL; 614 if ((amdgpu_discovery != 2) && 615 (RREG32(mmIP_DISCOVERY_VERSION) == 4)) 616 amdgpu_ras_query_boot_status(adev, 4); 617 return r; 618 } 619 620 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev); 621 622 void amdgpu_discovery_fini(struct amdgpu_device *adev) 623 { 624 amdgpu_discovery_sysfs_fini(adev); 625 kfree(adev->mman.discovery_bin); 626 adev->mman.discovery_bin = NULL; 627 } 628 629 static int amdgpu_discovery_validate_ip(struct amdgpu_device *adev, 630 uint8_t instance, uint16_t hw_id) 631 { 632 if (instance >= HWIP_MAX_INSTANCE) { 633 dev_err(adev->dev, 634 "Unexpected instance_number (%d) from ip discovery blob\n", 635 instance); 636 return -EINVAL; 637 } 638 if (hw_id >= HW_ID_MAX) { 639 dev_err(adev->dev, 640 "Unexpected hw_id (%d) from ip discovery blob\n", 641 hw_id); 642 return -EINVAL; 643 } 644 645 return 0; 646 } 647 648 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev, 649 uint32_t *vcn_harvest_count) 650 { 651 struct binary_header *bhdr; 652 struct ip_discovery_header *ihdr; 653 struct die_header *dhdr; 654 struct ip *ip; 655 uint16_t die_offset, ip_offset, num_dies, num_ips; 656 uint16_t hw_id; 657 uint8_t inst; 658 int i, j; 659 660 bhdr = (struct binary_header *)adev->mman.discovery_bin; 661 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 662 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 663 num_dies = le16_to_cpu(ihdr->num_dies); 664 665 /* scan harvest bit of all IP data structures */ 666 for (i = 0; i < num_dies; i++) { 667 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 668 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 669 num_ips = le16_to_cpu(dhdr->num_ips); 670 ip_offset = die_offset + sizeof(*dhdr); 671 672 for (j = 0; j < num_ips; j++) { 673 ip = (struct ip *)(adev->mman.discovery_bin + 674 ip_offset); 675 inst = ip->number_instance; 676 hw_id = le16_to_cpu(ip->hw_id); 677 if (amdgpu_discovery_validate_ip(adev, inst, hw_id)) 678 goto next_ip; 679 680 if (ip->harvest == 1) { 681 switch (hw_id) { 682 case VCN_HWID: 683 (*vcn_harvest_count)++; 684 if (inst == 0) { 685 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 686 adev->vcn.inst_mask &= 687 ~AMDGPU_VCN_HARVEST_VCN0; 688 adev->jpeg.inst_mask &= 689 ~AMDGPU_VCN_HARVEST_VCN0; 690 } else { 691 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 692 adev->vcn.inst_mask &= 693 ~AMDGPU_VCN_HARVEST_VCN1; 694 adev->jpeg.inst_mask &= 695 ~AMDGPU_VCN_HARVEST_VCN1; 696 } 697 break; 698 case DMU_HWID: 699 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 700 break; 701 default: 702 break; 703 } 704 } 705 next_ip: 706 ip_offset += struct_size(ip, base_address, 707 ip->num_base_address); 708 } 709 } 710 } 711 712 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, 713 uint32_t *vcn_harvest_count, 714 uint32_t *umc_harvest_count) 715 { 716 struct binary_header *bhdr; 717 struct harvest_table *harvest_info; 718 u16 offset; 719 int i; 720 uint32_t umc_harvest_config = 0; 721 722 bhdr = (struct binary_header *)adev->mman.discovery_bin; 723 offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset); 724 725 if (!offset) { 726 dev_err(adev->dev, "invalid harvest table offset\n"); 727 return; 728 } 729 730 harvest_info = (struct harvest_table *)(adev->mman.discovery_bin + offset); 731 732 for (i = 0; i < 32; i++) { 733 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) 734 break; 735 736 switch (le16_to_cpu(harvest_info->list[i].hw_id)) { 737 case VCN_HWID: 738 (*vcn_harvest_count)++; 739 adev->vcn.harvest_config |= 740 (1 << harvest_info->list[i].number_instance); 741 adev->jpeg.harvest_config |= 742 (1 << harvest_info->list[i].number_instance); 743 744 adev->vcn.inst_mask &= 745 ~(1U << harvest_info->list[i].number_instance); 746 adev->jpeg.inst_mask &= 747 ~(1U << harvest_info->list[i].number_instance); 748 break; 749 case DMU_HWID: 750 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 751 break; 752 case UMC_HWID: 753 umc_harvest_config |= 754 1 << (le16_to_cpu(harvest_info->list[i].number_instance)); 755 (*umc_harvest_count)++; 756 break; 757 case GC_HWID: 758 adev->gfx.xcc_mask &= 759 ~(1U << harvest_info->list[i].number_instance); 760 break; 761 case SDMA0_HWID: 762 adev->sdma.sdma_mask &= 763 ~(1U << harvest_info->list[i].number_instance); 764 break; 765 #if defined(CONFIG_DRM_AMD_ISP) 766 case ISP_HWID: 767 adev->isp.harvest_config |= 768 ~(1U << harvest_info->list[i].number_instance); 769 break; 770 #endif 771 default: 772 break; 773 } 774 } 775 776 adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) & 777 ~umc_harvest_config; 778 } 779 780 /* ================================================== */ 781 782 struct ip_hw_instance { 783 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */ 784 785 int hw_id; 786 u8 num_instance; 787 u8 major, minor, revision; 788 u8 harvest; 789 790 int num_base_addresses; 791 u32 base_addr[] __counted_by(num_base_addresses); 792 }; 793 794 struct ip_hw_id { 795 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */ 796 int hw_id; 797 }; 798 799 struct ip_die_entry { 800 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */ 801 u16 num_ips; 802 }; 803 804 /* -------------------------------------------------- */ 805 806 struct ip_hw_instance_attr { 807 struct attribute attr; 808 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf); 809 }; 810 811 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf) 812 { 813 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id); 814 } 815 816 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf) 817 { 818 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance); 819 } 820 821 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf) 822 { 823 return sysfs_emit(buf, "%d\n", ip_hw_instance->major); 824 } 825 826 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf) 827 { 828 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor); 829 } 830 831 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf) 832 { 833 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision); 834 } 835 836 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf) 837 { 838 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest); 839 } 840 841 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf) 842 { 843 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses); 844 } 845 846 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) 847 { 848 ssize_t res, at; 849 int ii; 850 851 for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 852 /* Here we satisfy the condition that, at + size <= PAGE_SIZE. 853 */ 854 if (at + 12 > PAGE_SIZE) 855 break; 856 res = sysfs_emit_at(buf, at, "0x%08X\n", 857 ip_hw_instance->base_addr[ii]); 858 if (res <= 0) 859 break; 860 at += res; 861 } 862 863 return res < 0 ? res : at; 864 } 865 866 static struct ip_hw_instance_attr ip_hw_attr[] = { 867 __ATTR_RO(hw_id), 868 __ATTR_RO(num_instance), 869 __ATTR_RO(major), 870 __ATTR_RO(minor), 871 __ATTR_RO(revision), 872 __ATTR_RO(harvest), 873 __ATTR_RO(num_base_addresses), 874 __ATTR_RO(base_addr), 875 }; 876 877 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; 878 ATTRIBUTE_GROUPS(ip_hw_instance); 879 880 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) 881 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) 882 883 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj, 884 struct attribute *attr, 885 char *buf) 886 { 887 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 888 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr); 889 890 if (!ip_hw_attr->show) 891 return -EIO; 892 893 return ip_hw_attr->show(ip_hw_instance, buf); 894 } 895 896 static const struct sysfs_ops ip_hw_instance_sysfs_ops = { 897 .show = ip_hw_instance_attr_show, 898 }; 899 900 static void ip_hw_instance_release(struct kobject *kobj) 901 { 902 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 903 904 kfree(ip_hw_instance); 905 } 906 907 static const struct kobj_type ip_hw_instance_ktype = { 908 .release = ip_hw_instance_release, 909 .sysfs_ops = &ip_hw_instance_sysfs_ops, 910 .default_groups = ip_hw_instance_groups, 911 }; 912 913 /* -------------------------------------------------- */ 914 915 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset) 916 917 static void ip_hw_id_release(struct kobject *kobj) 918 { 919 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj); 920 921 if (!list_empty(&ip_hw_id->hw_id_kset.list)) 922 DRM_ERROR("ip_hw_id->hw_id_kset is not empty"); 923 kfree(ip_hw_id); 924 } 925 926 static const struct kobj_type ip_hw_id_ktype = { 927 .release = ip_hw_id_release, 928 .sysfs_ops = &kobj_sysfs_ops, 929 }; 930 931 /* -------------------------------------------------- */ 932 933 static void die_kobj_release(struct kobject *kobj); 934 static void ip_disc_release(struct kobject *kobj); 935 936 struct ip_die_entry_attribute { 937 struct attribute attr; 938 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf); 939 }; 940 941 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr) 942 943 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf) 944 { 945 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips); 946 } 947 948 /* If there are more ip_die_entry attrs, other than the number of IPs, 949 * we can make this intro an array of attrs, and then initialize 950 * ip_die_entry_attrs in a loop. 951 */ 952 static struct ip_die_entry_attribute num_ips_attr = 953 __ATTR_RO(num_ips); 954 955 static struct attribute *ip_die_entry_attrs[] = { 956 &num_ips_attr.attr, 957 NULL, 958 }; 959 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ 960 961 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) 962 963 static ssize_t ip_die_entry_attr_show(struct kobject *kobj, 964 struct attribute *attr, 965 char *buf) 966 { 967 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr); 968 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 969 970 if (!ip_die_entry_attr->show) 971 return -EIO; 972 973 return ip_die_entry_attr->show(ip_die_entry, buf); 974 } 975 976 static void ip_die_entry_release(struct kobject *kobj) 977 { 978 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 979 980 if (!list_empty(&ip_die_entry->ip_kset.list)) 981 DRM_ERROR("ip_die_entry->ip_kset is not empty"); 982 kfree(ip_die_entry); 983 } 984 985 static const struct sysfs_ops ip_die_entry_sysfs_ops = { 986 .show = ip_die_entry_attr_show, 987 }; 988 989 static const struct kobj_type ip_die_entry_ktype = { 990 .release = ip_die_entry_release, 991 .sysfs_ops = &ip_die_entry_sysfs_ops, 992 .default_groups = ip_die_entry_groups, 993 }; 994 995 static const struct kobj_type die_kobj_ktype = { 996 .release = die_kobj_release, 997 .sysfs_ops = &kobj_sysfs_ops, 998 }; 999 1000 static const struct kobj_type ip_discovery_ktype = { 1001 .release = ip_disc_release, 1002 .sysfs_ops = &kobj_sysfs_ops, 1003 }; 1004 1005 struct ip_discovery_top { 1006 struct kobject kobj; /* ip_discovery/ */ 1007 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */ 1008 struct amdgpu_device *adev; 1009 }; 1010 1011 static void die_kobj_release(struct kobject *kobj) 1012 { 1013 struct ip_discovery_top *ip_top = container_of(to_kset(kobj), 1014 struct ip_discovery_top, 1015 die_kset); 1016 if (!list_empty(&ip_top->die_kset.list)) 1017 DRM_ERROR("ip_top->die_kset is not empty"); 1018 } 1019 1020 static void ip_disc_release(struct kobject *kobj) 1021 { 1022 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top, 1023 kobj); 1024 struct amdgpu_device *adev = ip_top->adev; 1025 1026 adev->ip_top = NULL; 1027 kfree(ip_top); 1028 } 1029 1030 static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev, 1031 uint16_t hw_id, uint8_t inst) 1032 { 1033 uint8_t harvest = 0; 1034 1035 /* Until a uniform way is figured, get mask based on hwid */ 1036 switch (hw_id) { 1037 case VCN_HWID: 1038 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0; 1039 break; 1040 case DMU_HWID: 1041 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK) 1042 harvest = 0x1; 1043 break; 1044 case UMC_HWID: 1045 /* TODO: It needs another parsing; for now, ignore.*/ 1046 break; 1047 case GC_HWID: 1048 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; 1049 break; 1050 case SDMA0_HWID: 1051 harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0; 1052 break; 1053 default: 1054 break; 1055 } 1056 1057 return harvest; 1058 } 1059 1060 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, 1061 struct ip_die_entry *ip_die_entry, 1062 const size_t _ip_offset, const int num_ips, 1063 bool reg_base_64) 1064 { 1065 int ii, jj, kk, res; 1066 uint16_t hw_id; 1067 uint8_t inst; 1068 1069 DRM_DEBUG("num_ips:%d", num_ips); 1070 1071 /* Find all IPs of a given HW ID, and add their instance to 1072 * #die/#hw_id/#instance/<attributes> 1073 */ 1074 for (ii = 0; ii < HW_ID_MAX; ii++) { 1075 struct ip_hw_id *ip_hw_id = NULL; 1076 size_t ip_offset = _ip_offset; 1077 1078 for (jj = 0; jj < num_ips; jj++) { 1079 struct ip_v4 *ip; 1080 struct ip_hw_instance *ip_hw_instance; 1081 1082 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset); 1083 inst = ip->instance_number; 1084 hw_id = le16_to_cpu(ip->hw_id); 1085 if (amdgpu_discovery_validate_ip(adev, inst, hw_id) || 1086 hw_id != ii) 1087 goto next_ip; 1088 1089 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset); 1090 1091 /* We have a hw_id match; register the hw 1092 * block if not yet registered. 1093 */ 1094 if (!ip_hw_id) { 1095 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL); 1096 if (!ip_hw_id) 1097 return -ENOMEM; 1098 ip_hw_id->hw_id = ii; 1099 1100 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii); 1101 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset; 1102 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype; 1103 res = kset_register(&ip_hw_id->hw_id_kset); 1104 if (res) { 1105 DRM_ERROR("Couldn't register ip_hw_id kset"); 1106 kfree(ip_hw_id); 1107 return res; 1108 } 1109 if (hw_id_names[ii]) { 1110 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj, 1111 &ip_hw_id->hw_id_kset.kobj, 1112 hw_id_names[ii]); 1113 if (res) { 1114 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n", 1115 hw_id_names[ii], 1116 kobject_name(&ip_die_entry->ip_kset.kobj)); 1117 } 1118 } 1119 } 1120 1121 /* Now register its instance. 1122 */ 1123 ip_hw_instance = kzalloc(struct_size(ip_hw_instance, 1124 base_addr, 1125 ip->num_base_address), 1126 GFP_KERNEL); 1127 if (!ip_hw_instance) { 1128 DRM_ERROR("no memory for ip_hw_instance"); 1129 return -ENOMEM; 1130 } 1131 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */ 1132 ip_hw_instance->num_instance = ip->instance_number; 1133 ip_hw_instance->major = ip->major; 1134 ip_hw_instance->minor = ip->minor; 1135 ip_hw_instance->revision = ip->revision; 1136 ip_hw_instance->harvest = 1137 amdgpu_discovery_get_harvest_info( 1138 adev, ip_hw_instance->hw_id, 1139 ip_hw_instance->num_instance); 1140 ip_hw_instance->num_base_addresses = ip->num_base_address; 1141 1142 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) { 1143 if (reg_base_64) 1144 ip_hw_instance->base_addr[kk] = 1145 lower_32_bits(le64_to_cpu(ip->base_address_64[kk])) & 0x3FFFFFFF; 1146 else 1147 ip_hw_instance->base_addr[kk] = ip->base_address[kk]; 1148 } 1149 1150 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); 1151 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; 1152 res = kobject_add(&ip_hw_instance->kobj, NULL, 1153 "%d", ip_hw_instance->num_instance); 1154 next_ip: 1155 if (reg_base_64) 1156 ip_offset += struct_size(ip, base_address_64, 1157 ip->num_base_address); 1158 else 1159 ip_offset += struct_size(ip, base_address, 1160 ip->num_base_address); 1161 } 1162 } 1163 1164 return 0; 1165 } 1166 1167 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) 1168 { 1169 struct binary_header *bhdr; 1170 struct ip_discovery_header *ihdr; 1171 struct die_header *dhdr; 1172 struct kset *die_kset = &adev->ip_top->die_kset; 1173 u16 num_dies, die_offset, num_ips; 1174 size_t ip_offset; 1175 int ii, res; 1176 1177 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1178 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1179 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1180 num_dies = le16_to_cpu(ihdr->num_dies); 1181 1182 DRM_DEBUG("number of dies: %d\n", num_dies); 1183 1184 for (ii = 0; ii < num_dies; ii++) { 1185 struct ip_die_entry *ip_die_entry; 1186 1187 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); 1188 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 1189 num_ips = le16_to_cpu(dhdr->num_ips); 1190 ip_offset = die_offset + sizeof(*dhdr); 1191 1192 /* Add the die to the kset. 1193 * 1194 * dhdr->die_id == ii, which was checked in 1195 * amdgpu_discovery_reg_base_init(). 1196 */ 1197 1198 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL); 1199 if (!ip_die_entry) 1200 return -ENOMEM; 1201 1202 ip_die_entry->num_ips = num_ips; 1203 1204 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id)); 1205 ip_die_entry->ip_kset.kobj.kset = die_kset; 1206 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype; 1207 res = kset_register(&ip_die_entry->ip_kset); 1208 if (res) { 1209 DRM_ERROR("Couldn't register ip_die_entry kset"); 1210 kfree(ip_die_entry); 1211 return res; 1212 } 1213 1214 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips, !!ihdr->base_addr_64_bit); 1215 } 1216 1217 return 0; 1218 } 1219 1220 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) 1221 { 1222 struct kset *die_kset; 1223 int res, ii; 1224 1225 if (!adev->mman.discovery_bin) 1226 return -EINVAL; 1227 1228 adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL); 1229 if (!adev->ip_top) 1230 return -ENOMEM; 1231 1232 adev->ip_top->adev = adev; 1233 1234 res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype, 1235 &adev->dev->kobj, "ip_discovery"); 1236 if (res) { 1237 DRM_ERROR("Couldn't init and add ip_discovery/"); 1238 goto Err; 1239 } 1240 1241 die_kset = &adev->ip_top->die_kset; 1242 kobject_set_name(&die_kset->kobj, "%s", "die"); 1243 die_kset->kobj.parent = &adev->ip_top->kobj; 1244 die_kset->kobj.ktype = &die_kobj_ktype; 1245 res = kset_register(&adev->ip_top->die_kset); 1246 if (res) { 1247 DRM_ERROR("Couldn't register die_kset"); 1248 goto Err; 1249 } 1250 1251 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++) 1252 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr; 1253 ip_hw_instance_attrs[ii] = NULL; 1254 1255 res = amdgpu_discovery_sysfs_recurse(adev); 1256 1257 return res; 1258 Err: 1259 kobject_put(&adev->ip_top->kobj); 1260 return res; 1261 } 1262 1263 /* -------------------------------------------------- */ 1264 1265 #define list_to_kobj(el) container_of(el, struct kobject, entry) 1266 1267 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id) 1268 { 1269 struct list_head *el, *tmp; 1270 struct kset *hw_id_kset; 1271 1272 hw_id_kset = &ip_hw_id->hw_id_kset; 1273 spin_lock(&hw_id_kset->list_lock); 1274 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) { 1275 list_del_init(el); 1276 spin_unlock(&hw_id_kset->list_lock); 1277 /* kobject is embedded in ip_hw_instance */ 1278 kobject_put(list_to_kobj(el)); 1279 spin_lock(&hw_id_kset->list_lock); 1280 } 1281 spin_unlock(&hw_id_kset->list_lock); 1282 kobject_put(&ip_hw_id->hw_id_kset.kobj); 1283 } 1284 1285 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry) 1286 { 1287 struct list_head *el, *tmp; 1288 struct kset *ip_kset; 1289 1290 ip_kset = &ip_die_entry->ip_kset; 1291 spin_lock(&ip_kset->list_lock); 1292 list_for_each_prev_safe(el, tmp, &ip_kset->list) { 1293 list_del_init(el); 1294 spin_unlock(&ip_kset->list_lock); 1295 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el))); 1296 spin_lock(&ip_kset->list_lock); 1297 } 1298 spin_unlock(&ip_kset->list_lock); 1299 kobject_put(&ip_die_entry->ip_kset.kobj); 1300 } 1301 1302 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) 1303 { 1304 struct list_head *el, *tmp; 1305 struct kset *die_kset; 1306 1307 die_kset = &adev->ip_top->die_kset; 1308 spin_lock(&die_kset->list_lock); 1309 list_for_each_prev_safe(el, tmp, &die_kset->list) { 1310 list_del_init(el); 1311 spin_unlock(&die_kset->list_lock); 1312 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 1313 spin_lock(&die_kset->list_lock); 1314 } 1315 spin_unlock(&die_kset->list_lock); 1316 kobject_put(&adev->ip_top->die_kset.kobj); 1317 kobject_put(&adev->ip_top->kobj); 1318 } 1319 1320 /* ================================================== */ 1321 1322 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 1323 { 1324 uint8_t num_base_address, subrev, variant; 1325 struct binary_header *bhdr; 1326 struct ip_discovery_header *ihdr; 1327 struct die_header *dhdr; 1328 struct ip_v4 *ip; 1329 uint16_t die_offset; 1330 uint16_t ip_offset; 1331 uint16_t num_dies; 1332 uint32_t wafl_ver; 1333 uint16_t num_ips; 1334 uint16_t hw_id; 1335 uint8_t inst; 1336 int hw_ip; 1337 int i, j, k; 1338 int r; 1339 1340 r = amdgpu_discovery_init(adev); 1341 if (r) { 1342 DRM_ERROR("amdgpu_discovery_init failed\n"); 1343 return r; 1344 } 1345 1346 wafl_ver = 0; 1347 adev->gfx.xcc_mask = 0; 1348 adev->sdma.sdma_mask = 0; 1349 adev->vcn.inst_mask = 0; 1350 adev->jpeg.inst_mask = 0; 1351 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1352 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1353 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1354 num_dies = le16_to_cpu(ihdr->num_dies); 1355 1356 DRM_DEBUG("number of dies: %d\n", num_dies); 1357 1358 for (i = 0; i < num_dies; i++) { 1359 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1360 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 1361 num_ips = le16_to_cpu(dhdr->num_ips); 1362 ip_offset = die_offset + sizeof(*dhdr); 1363 1364 if (le16_to_cpu(dhdr->die_id) != i) { 1365 DRM_ERROR("invalid die id %d, expected %d\n", 1366 le16_to_cpu(dhdr->die_id), i); 1367 return -EINVAL; 1368 } 1369 1370 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 1371 le16_to_cpu(dhdr->die_id), num_ips); 1372 1373 for (j = 0; j < num_ips; j++) { 1374 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset); 1375 1376 inst = ip->instance_number; 1377 hw_id = le16_to_cpu(ip->hw_id); 1378 if (amdgpu_discovery_validate_ip(adev, inst, hw_id)) 1379 goto next_ip; 1380 1381 num_base_address = ip->num_base_address; 1382 1383 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 1384 hw_id_names[le16_to_cpu(ip->hw_id)], 1385 le16_to_cpu(ip->hw_id), 1386 ip->instance_number, 1387 ip->major, ip->minor, 1388 ip->revision); 1389 1390 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 1391 /* Bit [5:0]: original revision value 1392 * Bit [7:6]: en/decode capability: 1393 * 0b00 : VCN function normally 1394 * 0b10 : encode is disabled 1395 * 0b01 : decode is disabled 1396 */ 1397 if (adev->vcn.num_vcn_inst < 1398 AMDGPU_MAX_VCN_INSTANCES) { 1399 adev->vcn.inst[adev->vcn.num_vcn_inst].vcn_config = 1400 ip->revision & 0xc0; 1401 adev->vcn.num_vcn_inst++; 1402 adev->vcn.inst_mask |= 1403 (1U << ip->instance_number); 1404 adev->jpeg.inst_mask |= 1405 (1U << ip->instance_number); 1406 } else { 1407 dev_err(adev->dev, "Too many VCN instances: %d vs %d\n", 1408 adev->vcn.num_vcn_inst + 1, 1409 AMDGPU_MAX_VCN_INSTANCES); 1410 } 1411 ip->revision &= ~0xc0; 1412 } 1413 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 1414 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 1415 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 1416 le16_to_cpu(ip->hw_id) == SDMA3_HWID) { 1417 if (adev->sdma.num_instances < 1418 AMDGPU_MAX_SDMA_INSTANCES) { 1419 adev->sdma.num_instances++; 1420 adev->sdma.sdma_mask |= 1421 (1U << ip->instance_number); 1422 } else { 1423 dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n", 1424 adev->sdma.num_instances + 1, 1425 AMDGPU_MAX_SDMA_INSTANCES); 1426 } 1427 } 1428 1429 if (le16_to_cpu(ip->hw_id) == VPE_HWID) { 1430 if (adev->vpe.num_instances < AMDGPU_MAX_VPE_INSTANCES) 1431 adev->vpe.num_instances++; 1432 else 1433 dev_err(adev->dev, "Too many VPE instances: %d vs %d\n", 1434 adev->vpe.num_instances + 1, 1435 AMDGPU_MAX_VPE_INSTANCES); 1436 } 1437 1438 if (le16_to_cpu(ip->hw_id) == UMC_HWID) { 1439 adev->gmc.num_umc++; 1440 adev->umc.node_inst_num++; 1441 } 1442 1443 if (le16_to_cpu(ip->hw_id) == GC_HWID) 1444 adev->gfx.xcc_mask |= 1445 (1U << ip->instance_number); 1446 1447 if (!wafl_ver && le16_to_cpu(ip->hw_id) == WAFLC_HWID) 1448 wafl_ver = IP_VERSION_FULL(ip->major, ip->minor, 1449 ip->revision, 0, 0); 1450 1451 for (k = 0; k < num_base_address; k++) { 1452 /* 1453 * convert the endianness of base addresses in place, 1454 * so that we don't need to convert them when accessing adev->reg_offset. 1455 */ 1456 if (ihdr->base_addr_64_bit) 1457 /* Truncate the 64bit base address from ip discovery 1458 * and only store lower 32bit ip base in reg_offset[]. 1459 * Bits > 32 follows ASIC specific format, thus just 1460 * discard them and handle it within specific ASIC. 1461 * By this way reg_offset[] and related helpers can 1462 * stay unchanged. 1463 * The base address is in dwords, thus clear the 1464 * highest 2 bits to store. 1465 */ 1466 ip->base_address[k] = 1467 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF; 1468 else 1469 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 1470 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 1471 } 1472 1473 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 1474 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) && 1475 hw_id_map[hw_ip] != 0) { 1476 DRM_DEBUG("set register base offset for %s\n", 1477 hw_id_names[le16_to_cpu(ip->hw_id)]); 1478 adev->reg_offset[hw_ip][ip->instance_number] = 1479 ip->base_address; 1480 /* Instance support is somewhat inconsistent. 1481 * SDMA is a good example. Sienna cichlid has 4 total 1482 * SDMA instances, each enumerated separately (HWIDs 1483 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 1484 * but they are enumerated as multiple instances of the 1485 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 1486 * example. On most chips there are multiple instances 1487 * with the same HWID. 1488 */ 1489 1490 if (ihdr->version < 3) { 1491 subrev = 0; 1492 variant = 0; 1493 } else { 1494 subrev = ip->sub_revision; 1495 variant = ip->variant; 1496 } 1497 1498 adev->ip_versions[hw_ip] 1499 [ip->instance_number] = 1500 IP_VERSION_FULL(ip->major, 1501 ip->minor, 1502 ip->revision, 1503 variant, 1504 subrev); 1505 } 1506 } 1507 1508 next_ip: 1509 if (ihdr->base_addr_64_bit) 1510 ip_offset += struct_size(ip, base_address_64, ip->num_base_address); 1511 else 1512 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1513 } 1514 } 1515 1516 if (wafl_ver && !adev->ip_versions[XGMI_HWIP][0]) 1517 adev->ip_versions[XGMI_HWIP][0] = wafl_ver; 1518 1519 return 0; 1520 } 1521 1522 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 1523 { 1524 struct ip_discovery_header *ihdr; 1525 struct binary_header *bhdr; 1526 int vcn_harvest_count = 0; 1527 int umc_harvest_count = 0; 1528 uint16_t offset, ihdr_ver; 1529 1530 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1531 offset = le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset); 1532 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1533 offset); 1534 ihdr_ver = le16_to_cpu(ihdr->version); 1535 /* 1536 * Harvest table does not fit Navi1x and legacy GPUs, 1537 * so read harvest bit per IP data structure to set 1538 * harvest configuration. 1539 */ 1540 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 2, 0) && 1541 ihdr_ver <= 2) { 1542 if ((adev->pdev->device == 0x731E && 1543 (adev->pdev->revision == 0xC6 || 1544 adev->pdev->revision == 0xC7)) || 1545 (adev->pdev->device == 0x7340 && 1546 adev->pdev->revision == 0xC9) || 1547 (adev->pdev->device == 0x7360 && 1548 adev->pdev->revision == 0xC7)) 1549 amdgpu_discovery_read_harvest_bit_per_ip(adev, 1550 &vcn_harvest_count); 1551 } else { 1552 amdgpu_discovery_read_from_harvest_table(adev, 1553 &vcn_harvest_count, 1554 &umc_harvest_count); 1555 } 1556 1557 amdgpu_discovery_harvest_config_quirk(adev); 1558 1559 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 1560 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 1561 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 1562 } 1563 1564 if (umc_harvest_count < adev->gmc.num_umc) { 1565 adev->gmc.num_umc -= umc_harvest_count; 1566 } 1567 } 1568 1569 union gc_info { 1570 struct gc_info_v1_0 v1; 1571 struct gc_info_v1_1 v1_1; 1572 struct gc_info_v1_2 v1_2; 1573 struct gc_info_v1_3 v1_3; 1574 struct gc_info_v2_0 v2; 1575 struct gc_info_v2_1 v2_1; 1576 }; 1577 1578 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 1579 { 1580 struct binary_header *bhdr; 1581 union gc_info *gc_info; 1582 u16 offset; 1583 1584 if (!adev->mman.discovery_bin) { 1585 DRM_ERROR("ip discovery uninitialized\n"); 1586 return -EINVAL; 1587 } 1588 1589 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1590 offset = le16_to_cpu(bhdr->table_list[GC].offset); 1591 1592 if (!offset) 1593 return 0; 1594 1595 gc_info = (union gc_info *)(adev->mman.discovery_bin + offset); 1596 1597 switch (le16_to_cpu(gc_info->v1.header.version_major)) { 1598 case 1: 1599 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); 1600 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 1601 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); 1602 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1603 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); 1604 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); 1605 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); 1606 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); 1607 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); 1608 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); 1609 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); 1610 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); 1611 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); 1612 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); 1613 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); 1614 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / 1615 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1616 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); 1617 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 1) { 1618 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa); 1619 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface); 1620 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps); 1621 } 1622 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 2) { 1623 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg); 1624 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size); 1625 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp); 1626 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc); 1627 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc); 1628 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa); 1629 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance); 1630 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu); 1631 } 1632 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 3) { 1633 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v1_3.gc_tcp_size_per_cu); 1634 adev->gfx.config.gc_tcp_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcp_cache_line_size); 1635 adev->gfx.config.gc_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_size_per_sqc); 1636 adev->gfx.config.gc_instruction_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_line_size); 1637 adev->gfx.config.gc_scalar_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_size_per_sqc); 1638 adev->gfx.config.gc_scalar_data_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_line_size); 1639 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v1_3.gc_tcc_size); 1640 adev->gfx.config.gc_tcc_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcc_cache_line_size); 1641 } 1642 break; 1643 case 2: 1644 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); 1645 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); 1646 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1647 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); 1648 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); 1649 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); 1650 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); 1651 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); 1652 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); 1653 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); 1654 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); 1655 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); 1656 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); 1657 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); 1658 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / 1659 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1660 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); 1661 if (le16_to_cpu(gc_info->v2.header.version_minor) == 1) { 1662 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh); 1663 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu); 1664 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XCD */ 1665 adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc); 1666 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_cache_size_per_sqc); 1667 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_size_per_sqc); 1668 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */ 1669 } 1670 break; 1671 default: 1672 dev_err(adev->dev, 1673 "Unhandled GC info table %d.%d\n", 1674 le16_to_cpu(gc_info->v1.header.version_major), 1675 le16_to_cpu(gc_info->v1.header.version_minor)); 1676 return -EINVAL; 1677 } 1678 return 0; 1679 } 1680 1681 union mall_info { 1682 struct mall_info_v1_0 v1; 1683 struct mall_info_v2_0 v2; 1684 }; 1685 1686 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) 1687 { 1688 struct binary_header *bhdr; 1689 union mall_info *mall_info; 1690 u32 u, mall_size_per_umc, m_s_present, half_use; 1691 u64 mall_size; 1692 u16 offset; 1693 1694 if (!adev->mman.discovery_bin) { 1695 DRM_ERROR("ip discovery uninitialized\n"); 1696 return -EINVAL; 1697 } 1698 1699 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1700 offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset); 1701 1702 if (!offset) 1703 return 0; 1704 1705 mall_info = (union mall_info *)(adev->mman.discovery_bin + offset); 1706 1707 switch (le16_to_cpu(mall_info->v1.header.version_major)) { 1708 case 1: 1709 mall_size = 0; 1710 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m); 1711 m_s_present = le32_to_cpu(mall_info->v1.m_s_present); 1712 half_use = le32_to_cpu(mall_info->v1.m_half_use); 1713 for (u = 0; u < adev->gmc.num_umc; u++) { 1714 if (m_s_present & (1 << u)) 1715 mall_size += mall_size_per_umc * 2; 1716 else if (half_use & (1 << u)) 1717 mall_size += mall_size_per_umc / 2; 1718 else 1719 mall_size += mall_size_per_umc; 1720 } 1721 adev->gmc.mall_size = mall_size; 1722 adev->gmc.m_half_use = half_use; 1723 break; 1724 case 2: 1725 mall_size_per_umc = le32_to_cpu(mall_info->v2.mall_size_per_umc); 1726 adev->gmc.mall_size = (uint64_t)mall_size_per_umc * adev->gmc.num_umc; 1727 break; 1728 default: 1729 dev_err(adev->dev, 1730 "Unhandled MALL info table %d.%d\n", 1731 le16_to_cpu(mall_info->v1.header.version_major), 1732 le16_to_cpu(mall_info->v1.header.version_minor)); 1733 return -EINVAL; 1734 } 1735 return 0; 1736 } 1737 1738 union vcn_info { 1739 struct vcn_info_v1_0 v1; 1740 }; 1741 1742 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) 1743 { 1744 struct binary_header *bhdr; 1745 union vcn_info *vcn_info; 1746 u16 offset; 1747 int v; 1748 1749 if (!adev->mman.discovery_bin) { 1750 DRM_ERROR("ip discovery uninitialized\n"); 1751 return -EINVAL; 1752 } 1753 1754 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1755 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES 1756 * but that may change in the future with new GPUs so keep this 1757 * check for defensive purposes. 1758 */ 1759 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { 1760 dev_err(adev->dev, "invalid vcn instances\n"); 1761 return -EINVAL; 1762 } 1763 1764 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1765 offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset); 1766 1767 if (!offset) 1768 return 0; 1769 1770 vcn_info = (union vcn_info *)(adev->mman.discovery_bin + offset); 1771 1772 switch (le16_to_cpu(vcn_info->v1.header.version_major)) { 1773 case 1: 1774 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1775 * so this won't overflow. 1776 */ 1777 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { 1778 adev->vcn.inst[v].vcn_codec_disable_mask = 1779 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits); 1780 } 1781 break; 1782 default: 1783 dev_err(adev->dev, 1784 "Unhandled VCN info table %d.%d\n", 1785 le16_to_cpu(vcn_info->v1.header.version_major), 1786 le16_to_cpu(vcn_info->v1.header.version_minor)); 1787 return -EINVAL; 1788 } 1789 return 0; 1790 } 1791 1792 union nps_info { 1793 struct nps_info_v1_0 v1; 1794 }; 1795 1796 static int amdgpu_discovery_refresh_nps_info(struct amdgpu_device *adev, 1797 union nps_info *nps_data) 1798 { 1799 uint64_t vram_size, pos, offset; 1800 struct nps_info_header *nhdr; 1801 struct binary_header bhdr; 1802 uint16_t checksum; 1803 1804 vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 1805 pos = vram_size - DISCOVERY_TMR_OFFSET; 1806 amdgpu_device_vram_access(adev, pos, &bhdr, sizeof(bhdr), false); 1807 1808 offset = le16_to_cpu(bhdr.table_list[NPS_INFO].offset); 1809 checksum = le16_to_cpu(bhdr.table_list[NPS_INFO].checksum); 1810 1811 amdgpu_device_vram_access(adev, (pos + offset), nps_data, 1812 sizeof(*nps_data), false); 1813 1814 nhdr = (struct nps_info_header *)(nps_data); 1815 if (!amdgpu_discovery_verify_checksum((uint8_t *)nps_data, 1816 le32_to_cpu(nhdr->size_bytes), 1817 checksum)) { 1818 dev_err(adev->dev, "nps data refresh, checksum mismatch\n"); 1819 return -EINVAL; 1820 } 1821 1822 return 0; 1823 } 1824 1825 int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, 1826 uint32_t *nps_type, 1827 struct amdgpu_gmc_memrange **ranges, 1828 int *range_cnt, bool refresh) 1829 { 1830 struct amdgpu_gmc_memrange *mem_ranges; 1831 struct binary_header *bhdr; 1832 union nps_info *nps_info; 1833 union nps_info nps_data; 1834 u16 offset; 1835 int i, r; 1836 1837 if (!nps_type || !range_cnt || !ranges) 1838 return -EINVAL; 1839 1840 if (refresh) { 1841 r = amdgpu_discovery_refresh_nps_info(adev, &nps_data); 1842 if (r) 1843 return r; 1844 nps_info = &nps_data; 1845 } else { 1846 if (!adev->mman.discovery_bin) { 1847 dev_err(adev->dev, 1848 "fetch mem range failed, ip discovery uninitialized\n"); 1849 return -EINVAL; 1850 } 1851 1852 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1853 offset = le16_to_cpu(bhdr->table_list[NPS_INFO].offset); 1854 1855 if (!offset) 1856 return -ENOENT; 1857 1858 /* If verification fails, return as if NPS table doesn't exist */ 1859 if (amdgpu_discovery_verify_npsinfo(adev, bhdr)) 1860 return -ENOENT; 1861 1862 nps_info = 1863 (union nps_info *)(adev->mman.discovery_bin + offset); 1864 } 1865 1866 switch (le16_to_cpu(nps_info->v1.header.version_major)) { 1867 case 1: 1868 mem_ranges = kvcalloc(nps_info->v1.count, 1869 sizeof(*mem_ranges), 1870 GFP_KERNEL); 1871 if (!mem_ranges) 1872 return -ENOMEM; 1873 *nps_type = nps_info->v1.nps_type; 1874 *range_cnt = nps_info->v1.count; 1875 for (i = 0; i < *range_cnt; i++) { 1876 mem_ranges[i].base_address = 1877 nps_info->v1.instance_info[i].base_address; 1878 mem_ranges[i].limit_address = 1879 nps_info->v1.instance_info[i].limit_address; 1880 mem_ranges[i].nid_mask = -1; 1881 mem_ranges[i].flags = 0; 1882 } 1883 *ranges = mem_ranges; 1884 break; 1885 default: 1886 dev_err(adev->dev, "Unhandled NPS info table %d.%d\n", 1887 le16_to_cpu(nps_info->v1.header.version_major), 1888 le16_to_cpu(nps_info->v1.header.version_minor)); 1889 return -EINVAL; 1890 } 1891 1892 return 0; 1893 } 1894 1895 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 1896 { 1897 /* what IP to use for this? */ 1898 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1899 case IP_VERSION(9, 0, 1): 1900 case IP_VERSION(9, 1, 0): 1901 case IP_VERSION(9, 2, 1): 1902 case IP_VERSION(9, 2, 2): 1903 case IP_VERSION(9, 3, 0): 1904 case IP_VERSION(9, 4, 0): 1905 case IP_VERSION(9, 4, 1): 1906 case IP_VERSION(9, 4, 2): 1907 case IP_VERSION(9, 4, 3): 1908 case IP_VERSION(9, 4, 4): 1909 case IP_VERSION(9, 5, 0): 1910 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 1911 break; 1912 case IP_VERSION(10, 1, 10): 1913 case IP_VERSION(10, 1, 1): 1914 case IP_VERSION(10, 1, 2): 1915 case IP_VERSION(10, 1, 3): 1916 case IP_VERSION(10, 1, 4): 1917 case IP_VERSION(10, 3, 0): 1918 case IP_VERSION(10, 3, 1): 1919 case IP_VERSION(10, 3, 2): 1920 case IP_VERSION(10, 3, 3): 1921 case IP_VERSION(10, 3, 4): 1922 case IP_VERSION(10, 3, 5): 1923 case IP_VERSION(10, 3, 6): 1924 case IP_VERSION(10, 3, 7): 1925 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 1926 break; 1927 case IP_VERSION(11, 0, 0): 1928 case IP_VERSION(11, 0, 1): 1929 case IP_VERSION(11, 0, 2): 1930 case IP_VERSION(11, 0, 3): 1931 case IP_VERSION(11, 0, 4): 1932 case IP_VERSION(11, 5, 0): 1933 case IP_VERSION(11, 5, 1): 1934 case IP_VERSION(11, 5, 2): 1935 case IP_VERSION(11, 5, 3): 1936 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); 1937 break; 1938 case IP_VERSION(12, 0, 0): 1939 case IP_VERSION(12, 0, 1): 1940 amdgpu_device_ip_block_add(adev, &soc24_common_ip_block); 1941 break; 1942 default: 1943 dev_err(adev->dev, 1944 "Failed to add common ip block(GC_HWIP:0x%x)\n", 1945 amdgpu_ip_version(adev, GC_HWIP, 0)); 1946 return -EINVAL; 1947 } 1948 return 0; 1949 } 1950 1951 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 1952 { 1953 /* use GC or MMHUB IP version */ 1954 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1955 case IP_VERSION(9, 0, 1): 1956 case IP_VERSION(9, 1, 0): 1957 case IP_VERSION(9, 2, 1): 1958 case IP_VERSION(9, 2, 2): 1959 case IP_VERSION(9, 3, 0): 1960 case IP_VERSION(9, 4, 0): 1961 case IP_VERSION(9, 4, 1): 1962 case IP_VERSION(9, 4, 2): 1963 case IP_VERSION(9, 4, 3): 1964 case IP_VERSION(9, 4, 4): 1965 case IP_VERSION(9, 5, 0): 1966 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 1967 break; 1968 case IP_VERSION(10, 1, 10): 1969 case IP_VERSION(10, 1, 1): 1970 case IP_VERSION(10, 1, 2): 1971 case IP_VERSION(10, 1, 3): 1972 case IP_VERSION(10, 1, 4): 1973 case IP_VERSION(10, 3, 0): 1974 case IP_VERSION(10, 3, 1): 1975 case IP_VERSION(10, 3, 2): 1976 case IP_VERSION(10, 3, 3): 1977 case IP_VERSION(10, 3, 4): 1978 case IP_VERSION(10, 3, 5): 1979 case IP_VERSION(10, 3, 6): 1980 case IP_VERSION(10, 3, 7): 1981 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 1982 break; 1983 case IP_VERSION(11, 0, 0): 1984 case IP_VERSION(11, 0, 1): 1985 case IP_VERSION(11, 0, 2): 1986 case IP_VERSION(11, 0, 3): 1987 case IP_VERSION(11, 0, 4): 1988 case IP_VERSION(11, 5, 0): 1989 case IP_VERSION(11, 5, 1): 1990 case IP_VERSION(11, 5, 2): 1991 case IP_VERSION(11, 5, 3): 1992 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block); 1993 break; 1994 case IP_VERSION(12, 0, 0): 1995 case IP_VERSION(12, 0, 1): 1996 amdgpu_device_ip_block_add(adev, &gmc_v12_0_ip_block); 1997 break; 1998 default: 1999 dev_err(adev->dev, "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 2000 amdgpu_ip_version(adev, GC_HWIP, 0)); 2001 return -EINVAL; 2002 } 2003 return 0; 2004 } 2005 2006 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 2007 { 2008 switch (amdgpu_ip_version(adev, OSSSYS_HWIP, 0)) { 2009 case IP_VERSION(4, 0, 0): 2010 case IP_VERSION(4, 0, 1): 2011 case IP_VERSION(4, 1, 0): 2012 case IP_VERSION(4, 1, 1): 2013 case IP_VERSION(4, 3, 0): 2014 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 2015 break; 2016 case IP_VERSION(4, 2, 0): 2017 case IP_VERSION(4, 2, 1): 2018 case IP_VERSION(4, 4, 0): 2019 case IP_VERSION(4, 4, 2): 2020 case IP_VERSION(4, 4, 5): 2021 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 2022 break; 2023 case IP_VERSION(5, 0, 0): 2024 case IP_VERSION(5, 0, 1): 2025 case IP_VERSION(5, 0, 2): 2026 case IP_VERSION(5, 0, 3): 2027 case IP_VERSION(5, 2, 0): 2028 case IP_VERSION(5, 2, 1): 2029 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 2030 break; 2031 case IP_VERSION(6, 0, 0): 2032 case IP_VERSION(6, 0, 1): 2033 case IP_VERSION(6, 0, 2): 2034 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block); 2035 break; 2036 case IP_VERSION(6, 1, 0): 2037 amdgpu_device_ip_block_add(adev, &ih_v6_1_ip_block); 2038 break; 2039 case IP_VERSION(7, 0, 0): 2040 amdgpu_device_ip_block_add(adev, &ih_v7_0_ip_block); 2041 break; 2042 default: 2043 dev_err(adev->dev, 2044 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 2045 amdgpu_ip_version(adev, OSSSYS_HWIP, 0)); 2046 return -EINVAL; 2047 } 2048 return 0; 2049 } 2050 2051 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 2052 { 2053 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 2054 case IP_VERSION(9, 0, 0): 2055 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 2056 break; 2057 case IP_VERSION(10, 0, 0): 2058 case IP_VERSION(10, 0, 1): 2059 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 2060 break; 2061 case IP_VERSION(11, 0, 0): 2062 case IP_VERSION(11, 0, 2): 2063 case IP_VERSION(11, 0, 4): 2064 case IP_VERSION(11, 0, 5): 2065 case IP_VERSION(11, 0, 9): 2066 case IP_VERSION(11, 0, 7): 2067 case IP_VERSION(11, 0, 11): 2068 case IP_VERSION(11, 0, 12): 2069 case IP_VERSION(11, 0, 13): 2070 case IP_VERSION(11, 5, 0): 2071 case IP_VERSION(11, 5, 2): 2072 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 2073 break; 2074 case IP_VERSION(11, 0, 8): 2075 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 2076 break; 2077 case IP_VERSION(11, 0, 3): 2078 case IP_VERSION(12, 0, 1): 2079 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 2080 break; 2081 case IP_VERSION(13, 0, 0): 2082 case IP_VERSION(13, 0, 1): 2083 case IP_VERSION(13, 0, 2): 2084 case IP_VERSION(13, 0, 3): 2085 case IP_VERSION(13, 0, 5): 2086 case IP_VERSION(13, 0, 6): 2087 case IP_VERSION(13, 0, 7): 2088 case IP_VERSION(13, 0, 8): 2089 case IP_VERSION(13, 0, 10): 2090 case IP_VERSION(13, 0, 11): 2091 case IP_VERSION(13, 0, 12): 2092 case IP_VERSION(13, 0, 14): 2093 case IP_VERSION(14, 0, 0): 2094 case IP_VERSION(14, 0, 1): 2095 case IP_VERSION(14, 0, 4): 2096 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 2097 break; 2098 case IP_VERSION(13, 0, 4): 2099 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block); 2100 break; 2101 case IP_VERSION(14, 0, 2): 2102 case IP_VERSION(14, 0, 3): 2103 case IP_VERSION(14, 0, 5): 2104 amdgpu_device_ip_block_add(adev, &psp_v14_0_ip_block); 2105 break; 2106 default: 2107 dev_err(adev->dev, 2108 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 2109 amdgpu_ip_version(adev, MP0_HWIP, 0)); 2110 return -EINVAL; 2111 } 2112 return 0; 2113 } 2114 2115 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 2116 { 2117 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2118 case IP_VERSION(9, 0, 0): 2119 case IP_VERSION(10, 0, 0): 2120 case IP_VERSION(10, 0, 1): 2121 case IP_VERSION(11, 0, 2): 2122 if (adev->asic_type == CHIP_ARCTURUS) 2123 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2124 else 2125 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 2126 break; 2127 case IP_VERSION(11, 0, 0): 2128 case IP_VERSION(11, 0, 5): 2129 case IP_VERSION(11, 0, 9): 2130 case IP_VERSION(11, 0, 7): 2131 case IP_VERSION(11, 0, 8): 2132 case IP_VERSION(11, 0, 11): 2133 case IP_VERSION(11, 0, 12): 2134 case IP_VERSION(11, 0, 13): 2135 case IP_VERSION(11, 5, 0): 2136 case IP_VERSION(11, 5, 2): 2137 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2138 break; 2139 case IP_VERSION(12, 0, 0): 2140 case IP_VERSION(12, 0, 1): 2141 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 2142 break; 2143 case IP_VERSION(13, 0, 0): 2144 case IP_VERSION(13, 0, 1): 2145 case IP_VERSION(13, 0, 2): 2146 case IP_VERSION(13, 0, 3): 2147 case IP_VERSION(13, 0, 4): 2148 case IP_VERSION(13, 0, 5): 2149 case IP_VERSION(13, 0, 6): 2150 case IP_VERSION(13, 0, 7): 2151 case IP_VERSION(13, 0, 8): 2152 case IP_VERSION(13, 0, 10): 2153 case IP_VERSION(13, 0, 11): 2154 case IP_VERSION(13, 0, 14): 2155 case IP_VERSION(13, 0, 12): 2156 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 2157 break; 2158 case IP_VERSION(14, 0, 0): 2159 case IP_VERSION(14, 0, 1): 2160 case IP_VERSION(14, 0, 2): 2161 case IP_VERSION(14, 0, 3): 2162 case IP_VERSION(14, 0, 4): 2163 case IP_VERSION(14, 0, 5): 2164 amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block); 2165 break; 2166 default: 2167 dev_err(adev->dev, 2168 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 2169 amdgpu_ip_version(adev, MP1_HWIP, 0)); 2170 return -EINVAL; 2171 } 2172 return 0; 2173 } 2174 2175 #if defined(CONFIG_DRM_AMD_DC) 2176 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev) 2177 { 2178 amdgpu_device_set_sriov_virtual_display(adev); 2179 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2180 } 2181 #endif 2182 2183 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 2184 { 2185 if (adev->enable_virtual_display) { 2186 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2187 return 0; 2188 } 2189 2190 if (!amdgpu_device_has_dc_support(adev)) 2191 return 0; 2192 2193 #if defined(CONFIG_DRM_AMD_DC) 2194 if (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2195 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2196 case IP_VERSION(1, 0, 0): 2197 case IP_VERSION(1, 0, 1): 2198 case IP_VERSION(2, 0, 2): 2199 case IP_VERSION(2, 0, 0): 2200 case IP_VERSION(2, 0, 3): 2201 case IP_VERSION(2, 1, 0): 2202 case IP_VERSION(3, 0, 0): 2203 case IP_VERSION(3, 0, 2): 2204 case IP_VERSION(3, 0, 3): 2205 case IP_VERSION(3, 0, 1): 2206 case IP_VERSION(3, 1, 2): 2207 case IP_VERSION(3, 1, 3): 2208 case IP_VERSION(3, 1, 4): 2209 case IP_VERSION(3, 1, 5): 2210 case IP_VERSION(3, 1, 6): 2211 case IP_VERSION(3, 2, 0): 2212 case IP_VERSION(3, 2, 1): 2213 case IP_VERSION(3, 5, 0): 2214 case IP_VERSION(3, 5, 1): 2215 case IP_VERSION(3, 6, 0): 2216 case IP_VERSION(4, 1, 0): 2217 /* TODO: Fix IP version. DC code expects version 4.0.1 */ 2218 if (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(4, 1, 0)) 2219 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(4, 0, 1); 2220 2221 if (amdgpu_sriov_vf(adev)) 2222 amdgpu_discovery_set_sriov_display(adev); 2223 else 2224 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2225 break; 2226 default: 2227 dev_err(adev->dev, 2228 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 2229 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2230 return -EINVAL; 2231 } 2232 } else if (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2233 switch (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2234 case IP_VERSION(12, 0, 0): 2235 case IP_VERSION(12, 0, 1): 2236 case IP_VERSION(12, 1, 0): 2237 if (amdgpu_sriov_vf(adev)) 2238 amdgpu_discovery_set_sriov_display(adev); 2239 else 2240 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2241 break; 2242 default: 2243 dev_err(adev->dev, 2244 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 2245 amdgpu_ip_version(adev, DCI_HWIP, 0)); 2246 return -EINVAL; 2247 } 2248 } 2249 #endif 2250 return 0; 2251 } 2252 2253 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 2254 { 2255 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2256 case IP_VERSION(9, 0, 1): 2257 case IP_VERSION(9, 1, 0): 2258 case IP_VERSION(9, 2, 1): 2259 case IP_VERSION(9, 2, 2): 2260 case IP_VERSION(9, 3, 0): 2261 case IP_VERSION(9, 4, 0): 2262 case IP_VERSION(9, 4, 1): 2263 case IP_VERSION(9, 4, 2): 2264 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 2265 break; 2266 case IP_VERSION(9, 4, 3): 2267 case IP_VERSION(9, 4, 4): 2268 case IP_VERSION(9, 5, 0): 2269 amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block); 2270 break; 2271 case IP_VERSION(10, 1, 10): 2272 case IP_VERSION(10, 1, 2): 2273 case IP_VERSION(10, 1, 1): 2274 case IP_VERSION(10, 1, 3): 2275 case IP_VERSION(10, 1, 4): 2276 case IP_VERSION(10, 3, 0): 2277 case IP_VERSION(10, 3, 2): 2278 case IP_VERSION(10, 3, 1): 2279 case IP_VERSION(10, 3, 4): 2280 case IP_VERSION(10, 3, 5): 2281 case IP_VERSION(10, 3, 6): 2282 case IP_VERSION(10, 3, 3): 2283 case IP_VERSION(10, 3, 7): 2284 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 2285 break; 2286 case IP_VERSION(11, 0, 0): 2287 case IP_VERSION(11, 0, 1): 2288 case IP_VERSION(11, 0, 2): 2289 case IP_VERSION(11, 0, 3): 2290 case IP_VERSION(11, 0, 4): 2291 case IP_VERSION(11, 5, 0): 2292 case IP_VERSION(11, 5, 1): 2293 case IP_VERSION(11, 5, 2): 2294 case IP_VERSION(11, 5, 3): 2295 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); 2296 break; 2297 case IP_VERSION(12, 0, 0): 2298 case IP_VERSION(12, 0, 1): 2299 amdgpu_device_ip_block_add(adev, &gfx_v12_0_ip_block); 2300 break; 2301 default: 2302 dev_err(adev->dev, "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 2303 amdgpu_ip_version(adev, GC_HWIP, 0)); 2304 return -EINVAL; 2305 } 2306 return 0; 2307 } 2308 2309 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 2310 { 2311 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 2312 case IP_VERSION(4, 0, 0): 2313 case IP_VERSION(4, 0, 1): 2314 case IP_VERSION(4, 1, 0): 2315 case IP_VERSION(4, 1, 1): 2316 case IP_VERSION(4, 1, 2): 2317 case IP_VERSION(4, 2, 0): 2318 case IP_VERSION(4, 2, 2): 2319 case IP_VERSION(4, 4, 0): 2320 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 2321 break; 2322 case IP_VERSION(4, 4, 2): 2323 case IP_VERSION(4, 4, 5): 2324 case IP_VERSION(4, 4, 4): 2325 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block); 2326 break; 2327 case IP_VERSION(5, 0, 0): 2328 case IP_VERSION(5, 0, 1): 2329 case IP_VERSION(5, 0, 2): 2330 case IP_VERSION(5, 0, 5): 2331 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 2332 break; 2333 case IP_VERSION(5, 2, 0): 2334 case IP_VERSION(5, 2, 2): 2335 case IP_VERSION(5, 2, 4): 2336 case IP_VERSION(5, 2, 5): 2337 case IP_VERSION(5, 2, 6): 2338 case IP_VERSION(5, 2, 3): 2339 case IP_VERSION(5, 2, 1): 2340 case IP_VERSION(5, 2, 7): 2341 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 2342 break; 2343 case IP_VERSION(6, 0, 0): 2344 case IP_VERSION(6, 0, 1): 2345 case IP_VERSION(6, 0, 2): 2346 case IP_VERSION(6, 0, 3): 2347 case IP_VERSION(6, 1, 0): 2348 case IP_VERSION(6, 1, 1): 2349 case IP_VERSION(6, 1, 2): 2350 case IP_VERSION(6, 1, 3): 2351 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block); 2352 break; 2353 case IP_VERSION(7, 0, 0): 2354 case IP_VERSION(7, 0, 1): 2355 amdgpu_device_ip_block_add(adev, &sdma_v7_0_ip_block); 2356 break; 2357 default: 2358 dev_err(adev->dev, 2359 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 2360 amdgpu_ip_version(adev, SDMA0_HWIP, 0)); 2361 return -EINVAL; 2362 } 2363 return 0; 2364 } 2365 2366 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 2367 { 2368 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2369 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2370 case IP_VERSION(7, 0, 0): 2371 case IP_VERSION(7, 2, 0): 2372 /* UVD is not supported on vega20 SR-IOV */ 2373 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2374 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 2375 break; 2376 default: 2377 dev_err(adev->dev, 2378 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 2379 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2380 return -EINVAL; 2381 } 2382 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2383 case IP_VERSION(4, 0, 0): 2384 case IP_VERSION(4, 1, 0): 2385 /* VCE is not supported on vega20 SR-IOV */ 2386 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2387 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 2388 break; 2389 default: 2390 dev_err(adev->dev, 2391 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 2392 amdgpu_ip_version(adev, VCE_HWIP, 0)); 2393 return -EINVAL; 2394 } 2395 } else { 2396 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2397 case IP_VERSION(1, 0, 0): 2398 case IP_VERSION(1, 0, 1): 2399 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 2400 break; 2401 case IP_VERSION(2, 0, 0): 2402 case IP_VERSION(2, 0, 2): 2403 case IP_VERSION(2, 2, 0): 2404 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 2405 if (!amdgpu_sriov_vf(adev)) 2406 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 2407 break; 2408 case IP_VERSION(2, 0, 3): 2409 break; 2410 case IP_VERSION(2, 5, 0): 2411 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 2412 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 2413 break; 2414 case IP_VERSION(2, 6, 0): 2415 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 2416 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 2417 break; 2418 case IP_VERSION(3, 0, 0): 2419 case IP_VERSION(3, 0, 16): 2420 case IP_VERSION(3, 1, 1): 2421 case IP_VERSION(3, 1, 2): 2422 case IP_VERSION(3, 0, 2): 2423 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2424 if (!amdgpu_sriov_vf(adev)) 2425 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 2426 break; 2427 case IP_VERSION(3, 0, 33): 2428 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2429 break; 2430 case IP_VERSION(4, 0, 0): 2431 case IP_VERSION(4, 0, 2): 2432 case IP_VERSION(4, 0, 4): 2433 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block); 2434 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block); 2435 break; 2436 case IP_VERSION(4, 0, 3): 2437 amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block); 2438 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block); 2439 break; 2440 case IP_VERSION(4, 0, 5): 2441 case IP_VERSION(4, 0, 6): 2442 amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block); 2443 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block); 2444 break; 2445 case IP_VERSION(5, 0, 0): 2446 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block); 2447 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block); 2448 break; 2449 case IP_VERSION(5, 0, 1): 2450 amdgpu_device_ip_block_add(adev, &vcn_v5_0_1_ip_block); 2451 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_1_ip_block); 2452 break; 2453 default: 2454 dev_err(adev->dev, 2455 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 2456 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2457 return -EINVAL; 2458 } 2459 } 2460 return 0; 2461 } 2462 2463 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 2464 { 2465 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2466 case IP_VERSION(11, 0, 0): 2467 case IP_VERSION(11, 0, 1): 2468 case IP_VERSION(11, 0, 2): 2469 case IP_VERSION(11, 0, 3): 2470 case IP_VERSION(11, 0, 4): 2471 case IP_VERSION(11, 5, 0): 2472 case IP_VERSION(11, 5, 1): 2473 case IP_VERSION(11, 5, 2): 2474 case IP_VERSION(11, 5, 3): 2475 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block); 2476 adev->enable_mes = true; 2477 adev->enable_mes_kiq = true; 2478 break; 2479 case IP_VERSION(12, 0, 0): 2480 case IP_VERSION(12, 0, 1): 2481 amdgpu_device_ip_block_add(adev, &mes_v12_0_ip_block); 2482 adev->enable_mes = true; 2483 adev->enable_mes_kiq = true; 2484 if (amdgpu_uni_mes) 2485 adev->enable_uni_mes = true; 2486 break; 2487 default: 2488 break; 2489 } 2490 return 0; 2491 } 2492 2493 static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev) 2494 { 2495 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2496 case IP_VERSION(9, 4, 3): 2497 case IP_VERSION(9, 4, 4): 2498 case IP_VERSION(9, 5, 0): 2499 aqua_vanjaram_init_soc_config(adev); 2500 break; 2501 default: 2502 break; 2503 } 2504 } 2505 2506 static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev) 2507 { 2508 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) { 2509 case IP_VERSION(6, 1, 0): 2510 case IP_VERSION(6, 1, 1): 2511 case IP_VERSION(6, 1, 3): 2512 amdgpu_device_ip_block_add(adev, &vpe_v6_1_ip_block); 2513 break; 2514 default: 2515 break; 2516 } 2517 2518 return 0; 2519 } 2520 2521 static int amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device *adev) 2522 { 2523 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) { 2524 case IP_VERSION(4, 0, 5): 2525 case IP_VERSION(4, 0, 6): 2526 if (amdgpu_umsch_mm & 0x1) { 2527 amdgpu_device_ip_block_add(adev, &umsch_mm_v4_0_ip_block); 2528 adev->enable_umsch_mm = true; 2529 } 2530 break; 2531 default: 2532 break; 2533 } 2534 2535 return 0; 2536 } 2537 2538 static int amdgpu_discovery_set_isp_ip_blocks(struct amdgpu_device *adev) 2539 { 2540 #if defined(CONFIG_DRM_AMD_ISP) 2541 switch (amdgpu_ip_version(adev, ISP_HWIP, 0)) { 2542 case IP_VERSION(4, 1, 0): 2543 amdgpu_device_ip_block_add(adev, &isp_v4_1_0_ip_block); 2544 break; 2545 case IP_VERSION(4, 1, 1): 2546 amdgpu_device_ip_block_add(adev, &isp_v4_1_1_ip_block); 2547 break; 2548 default: 2549 break; 2550 } 2551 #endif 2552 2553 return 0; 2554 } 2555 2556 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 2557 { 2558 int r; 2559 2560 switch (adev->asic_type) { 2561 case CHIP_VEGA10: 2562 case CHIP_VEGA12: 2563 case CHIP_RAVEN: 2564 case CHIP_VEGA20: 2565 case CHIP_ARCTURUS: 2566 case CHIP_ALDEBARAN: 2567 /* this is not fatal. We have a fallback below 2568 * if the new firmwares are not present. some of 2569 * this will be overridden below to keep things 2570 * consistent with the current behavior. 2571 */ 2572 r = amdgpu_discovery_reg_base_init(adev); 2573 if (!r) { 2574 amdgpu_discovery_harvest_ip(adev); 2575 amdgpu_discovery_get_gfx_info(adev); 2576 amdgpu_discovery_get_mall_info(adev); 2577 amdgpu_discovery_get_vcn_info(adev); 2578 } 2579 break; 2580 default: 2581 r = amdgpu_discovery_reg_base_init(adev); 2582 if (r) 2583 return -EINVAL; 2584 2585 amdgpu_discovery_harvest_ip(adev); 2586 amdgpu_discovery_get_gfx_info(adev); 2587 amdgpu_discovery_get_mall_info(adev); 2588 amdgpu_discovery_get_vcn_info(adev); 2589 break; 2590 } 2591 2592 switch (adev->asic_type) { 2593 case CHIP_VEGA10: 2594 vega10_reg_base_init(adev); 2595 adev->sdma.num_instances = 2; 2596 adev->gmc.num_umc = 4; 2597 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2598 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2599 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 2600 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 2601 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 2602 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 2603 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2604 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 2605 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 2606 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2607 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2608 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2609 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 2610 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 2611 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2612 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2613 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 2614 break; 2615 case CHIP_VEGA12: 2616 vega10_reg_base_init(adev); 2617 adev->sdma.num_instances = 2; 2618 adev->gmc.num_umc = 4; 2619 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2620 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2621 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 2622 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 2623 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 2624 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 2625 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 2626 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 2627 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 2628 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2629 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2630 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2631 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 2632 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 2633 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2634 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2635 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 2636 break; 2637 case CHIP_RAVEN: 2638 vega10_reg_base_init(adev); 2639 adev->sdma.num_instances = 1; 2640 adev->vcn.num_vcn_inst = 1; 2641 adev->gmc.num_umc = 2; 2642 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 2643 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2644 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2645 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 2646 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 2647 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 2648 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 2649 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 2650 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 2651 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 2652 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 2653 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 2654 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 2655 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 2656 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 2657 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 2658 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 2659 } else { 2660 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2661 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2662 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 2663 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 2664 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 2665 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2666 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 2667 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 2668 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 2669 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 2670 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 2671 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 2672 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 2673 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 2674 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 2675 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 2676 } 2677 break; 2678 case CHIP_VEGA20: 2679 vega20_reg_base_init(adev); 2680 adev->sdma.num_instances = 2; 2681 adev->gmc.num_umc = 8; 2682 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2683 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2684 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 2685 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 2686 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 2687 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 2688 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 2689 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 2690 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 2691 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 2692 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2693 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 2694 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 2695 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 2696 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 2697 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 2698 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 2699 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 2700 break; 2701 case CHIP_ARCTURUS: 2702 arct_reg_base_init(adev); 2703 adev->sdma.num_instances = 8; 2704 adev->vcn.num_vcn_inst = 2; 2705 adev->gmc.num_umc = 8; 2706 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2707 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2708 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 2709 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 2710 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 2711 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 2712 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 2713 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 2714 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 2715 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 2716 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 2717 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 2718 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 2719 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 2720 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 2721 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 2722 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2723 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 2724 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 2725 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 2726 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 2727 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 2728 break; 2729 case CHIP_ALDEBARAN: 2730 aldebaran_reg_base_init(adev); 2731 adev->sdma.num_instances = 5; 2732 adev->vcn.num_vcn_inst = 2; 2733 adev->gmc.num_umc = 4; 2734 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2735 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2736 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 2737 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 2738 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 2739 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 2740 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 2741 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 2742 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 2743 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 2744 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 2745 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 2746 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 2747 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 2748 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 2749 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 2750 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 2751 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 2752 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 2753 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 2754 break; 2755 default: 2756 break; 2757 } 2758 2759 amdgpu_discovery_init_soc_config(adev); 2760 amdgpu_discovery_sysfs_init(adev); 2761 2762 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2763 case IP_VERSION(9, 0, 1): 2764 case IP_VERSION(9, 2, 1): 2765 case IP_VERSION(9, 4, 0): 2766 case IP_VERSION(9, 4, 1): 2767 case IP_VERSION(9, 4, 2): 2768 case IP_VERSION(9, 4, 3): 2769 case IP_VERSION(9, 4, 4): 2770 case IP_VERSION(9, 5, 0): 2771 adev->family = AMDGPU_FAMILY_AI; 2772 break; 2773 case IP_VERSION(9, 1, 0): 2774 case IP_VERSION(9, 2, 2): 2775 case IP_VERSION(9, 3, 0): 2776 adev->family = AMDGPU_FAMILY_RV; 2777 break; 2778 case IP_VERSION(10, 1, 10): 2779 case IP_VERSION(10, 1, 1): 2780 case IP_VERSION(10, 1, 2): 2781 case IP_VERSION(10, 1, 3): 2782 case IP_VERSION(10, 1, 4): 2783 case IP_VERSION(10, 3, 0): 2784 case IP_VERSION(10, 3, 2): 2785 case IP_VERSION(10, 3, 4): 2786 case IP_VERSION(10, 3, 5): 2787 adev->family = AMDGPU_FAMILY_NV; 2788 break; 2789 case IP_VERSION(10, 3, 1): 2790 adev->family = AMDGPU_FAMILY_VGH; 2791 adev->apu_flags |= AMD_APU_IS_VANGOGH; 2792 break; 2793 case IP_VERSION(10, 3, 3): 2794 adev->family = AMDGPU_FAMILY_YC; 2795 break; 2796 case IP_VERSION(10, 3, 6): 2797 adev->family = AMDGPU_FAMILY_GC_10_3_6; 2798 break; 2799 case IP_VERSION(10, 3, 7): 2800 adev->family = AMDGPU_FAMILY_GC_10_3_7; 2801 break; 2802 case IP_VERSION(11, 0, 0): 2803 case IP_VERSION(11, 0, 2): 2804 case IP_VERSION(11, 0, 3): 2805 adev->family = AMDGPU_FAMILY_GC_11_0_0; 2806 break; 2807 case IP_VERSION(11, 0, 1): 2808 case IP_VERSION(11, 0, 4): 2809 adev->family = AMDGPU_FAMILY_GC_11_0_1; 2810 break; 2811 case IP_VERSION(11, 5, 0): 2812 case IP_VERSION(11, 5, 1): 2813 case IP_VERSION(11, 5, 2): 2814 case IP_VERSION(11, 5, 3): 2815 adev->family = AMDGPU_FAMILY_GC_11_5_0; 2816 break; 2817 case IP_VERSION(12, 0, 0): 2818 case IP_VERSION(12, 0, 1): 2819 adev->family = AMDGPU_FAMILY_GC_12_0_0; 2820 break; 2821 default: 2822 return -EINVAL; 2823 } 2824 2825 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2826 case IP_VERSION(9, 1, 0): 2827 case IP_VERSION(9, 2, 2): 2828 case IP_VERSION(9, 3, 0): 2829 case IP_VERSION(10, 1, 3): 2830 case IP_VERSION(10, 1, 4): 2831 case IP_VERSION(10, 3, 1): 2832 case IP_VERSION(10, 3, 3): 2833 case IP_VERSION(10, 3, 6): 2834 case IP_VERSION(10, 3, 7): 2835 case IP_VERSION(11, 0, 1): 2836 case IP_VERSION(11, 0, 4): 2837 case IP_VERSION(11, 5, 0): 2838 case IP_VERSION(11, 5, 1): 2839 case IP_VERSION(11, 5, 2): 2840 case IP_VERSION(11, 5, 3): 2841 adev->flags |= AMD_IS_APU; 2842 break; 2843 default: 2844 break; 2845 } 2846 2847 /* set NBIO version */ 2848 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 2849 case IP_VERSION(6, 1, 0): 2850 case IP_VERSION(6, 2, 0): 2851 adev->nbio.funcs = &nbio_v6_1_funcs; 2852 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 2853 break; 2854 case IP_VERSION(7, 0, 0): 2855 case IP_VERSION(7, 0, 1): 2856 case IP_VERSION(2, 5, 0): 2857 adev->nbio.funcs = &nbio_v7_0_funcs; 2858 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 2859 break; 2860 case IP_VERSION(7, 4, 0): 2861 case IP_VERSION(7, 4, 1): 2862 case IP_VERSION(7, 4, 4): 2863 adev->nbio.funcs = &nbio_v7_4_funcs; 2864 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 2865 break; 2866 case IP_VERSION(7, 9, 0): 2867 case IP_VERSION(7, 9, 1): 2868 adev->nbio.funcs = &nbio_v7_9_funcs; 2869 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg; 2870 break; 2871 case IP_VERSION(7, 11, 0): 2872 case IP_VERSION(7, 11, 1): 2873 case IP_VERSION(7, 11, 2): 2874 case IP_VERSION(7, 11, 3): 2875 adev->nbio.funcs = &nbio_v7_11_funcs; 2876 adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg; 2877 break; 2878 case IP_VERSION(7, 2, 0): 2879 case IP_VERSION(7, 2, 1): 2880 case IP_VERSION(7, 3, 0): 2881 case IP_VERSION(7, 5, 0): 2882 case IP_VERSION(7, 5, 1): 2883 adev->nbio.funcs = &nbio_v7_2_funcs; 2884 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 2885 break; 2886 case IP_VERSION(2, 1, 1): 2887 case IP_VERSION(2, 3, 0): 2888 case IP_VERSION(2, 3, 1): 2889 case IP_VERSION(2, 3, 2): 2890 case IP_VERSION(3, 3, 0): 2891 case IP_VERSION(3, 3, 1): 2892 case IP_VERSION(3, 3, 2): 2893 case IP_VERSION(3, 3, 3): 2894 adev->nbio.funcs = &nbio_v2_3_funcs; 2895 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 2896 break; 2897 case IP_VERSION(4, 3, 0): 2898 case IP_VERSION(4, 3, 1): 2899 if (amdgpu_sriov_vf(adev)) 2900 adev->nbio.funcs = &nbio_v4_3_sriov_funcs; 2901 else 2902 adev->nbio.funcs = &nbio_v4_3_funcs; 2903 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg; 2904 break; 2905 case IP_VERSION(7, 7, 0): 2906 case IP_VERSION(7, 7, 1): 2907 adev->nbio.funcs = &nbio_v7_7_funcs; 2908 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg; 2909 break; 2910 case IP_VERSION(6, 3, 1): 2911 adev->nbio.funcs = &nbif_v6_3_1_funcs; 2912 adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg; 2913 break; 2914 default: 2915 break; 2916 } 2917 2918 switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) { 2919 case IP_VERSION(4, 0, 0): 2920 case IP_VERSION(4, 0, 1): 2921 case IP_VERSION(4, 1, 0): 2922 case IP_VERSION(4, 1, 1): 2923 case IP_VERSION(4, 1, 2): 2924 case IP_VERSION(4, 2, 0): 2925 case IP_VERSION(4, 2, 1): 2926 case IP_VERSION(4, 4, 0): 2927 case IP_VERSION(4, 4, 2): 2928 case IP_VERSION(4, 4, 5): 2929 adev->hdp.funcs = &hdp_v4_0_funcs; 2930 break; 2931 case IP_VERSION(5, 0, 0): 2932 case IP_VERSION(5, 0, 1): 2933 case IP_VERSION(5, 0, 2): 2934 case IP_VERSION(5, 0, 3): 2935 case IP_VERSION(5, 0, 4): 2936 case IP_VERSION(5, 2, 0): 2937 adev->hdp.funcs = &hdp_v5_0_funcs; 2938 break; 2939 case IP_VERSION(5, 2, 1): 2940 adev->hdp.funcs = &hdp_v5_2_funcs; 2941 break; 2942 case IP_VERSION(6, 0, 0): 2943 case IP_VERSION(6, 0, 1): 2944 case IP_VERSION(6, 1, 0): 2945 adev->hdp.funcs = &hdp_v6_0_funcs; 2946 break; 2947 case IP_VERSION(7, 0, 0): 2948 adev->hdp.funcs = &hdp_v7_0_funcs; 2949 break; 2950 default: 2951 break; 2952 } 2953 2954 switch (amdgpu_ip_version(adev, DF_HWIP, 0)) { 2955 case IP_VERSION(3, 6, 0): 2956 case IP_VERSION(3, 6, 1): 2957 case IP_VERSION(3, 6, 2): 2958 adev->df.funcs = &df_v3_6_funcs; 2959 break; 2960 case IP_VERSION(2, 1, 0): 2961 case IP_VERSION(2, 1, 1): 2962 case IP_VERSION(2, 5, 0): 2963 case IP_VERSION(3, 5, 1): 2964 case IP_VERSION(3, 5, 2): 2965 adev->df.funcs = &df_v1_7_funcs; 2966 break; 2967 case IP_VERSION(4, 3, 0): 2968 adev->df.funcs = &df_v4_3_funcs; 2969 break; 2970 case IP_VERSION(4, 6, 2): 2971 adev->df.funcs = &df_v4_6_2_funcs; 2972 break; 2973 case IP_VERSION(4, 15, 0): 2974 case IP_VERSION(4, 15, 1): 2975 adev->df.funcs = &df_v4_15_funcs; 2976 break; 2977 default: 2978 break; 2979 } 2980 2981 switch (amdgpu_ip_version(adev, SMUIO_HWIP, 0)) { 2982 case IP_VERSION(9, 0, 0): 2983 case IP_VERSION(9, 0, 1): 2984 case IP_VERSION(10, 0, 0): 2985 case IP_VERSION(10, 0, 1): 2986 case IP_VERSION(10, 0, 2): 2987 adev->smuio.funcs = &smuio_v9_0_funcs; 2988 break; 2989 case IP_VERSION(11, 0, 0): 2990 case IP_VERSION(11, 0, 2): 2991 case IP_VERSION(11, 0, 3): 2992 case IP_VERSION(11, 0, 4): 2993 case IP_VERSION(11, 0, 7): 2994 case IP_VERSION(11, 0, 8): 2995 adev->smuio.funcs = &smuio_v11_0_funcs; 2996 break; 2997 case IP_VERSION(11, 0, 6): 2998 case IP_VERSION(11, 0, 10): 2999 case IP_VERSION(11, 0, 11): 3000 case IP_VERSION(11, 5, 0): 3001 case IP_VERSION(11, 5, 2): 3002 case IP_VERSION(13, 0, 1): 3003 case IP_VERSION(13, 0, 9): 3004 case IP_VERSION(13, 0, 10): 3005 adev->smuio.funcs = &smuio_v11_0_6_funcs; 3006 break; 3007 case IP_VERSION(13, 0, 2): 3008 adev->smuio.funcs = &smuio_v13_0_funcs; 3009 break; 3010 case IP_VERSION(13, 0, 3): 3011 case IP_VERSION(13, 0, 11): 3012 adev->smuio.funcs = &smuio_v13_0_3_funcs; 3013 if (adev->smuio.funcs->get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) { 3014 adev->flags |= AMD_IS_APU; 3015 } 3016 break; 3017 case IP_VERSION(13, 0, 6): 3018 case IP_VERSION(13, 0, 8): 3019 case IP_VERSION(14, 0, 0): 3020 case IP_VERSION(14, 0, 1): 3021 adev->smuio.funcs = &smuio_v13_0_6_funcs; 3022 break; 3023 case IP_VERSION(14, 0, 2): 3024 adev->smuio.funcs = &smuio_v14_0_2_funcs; 3025 break; 3026 default: 3027 break; 3028 } 3029 3030 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { 3031 case IP_VERSION(6, 0, 0): 3032 case IP_VERSION(6, 0, 1): 3033 case IP_VERSION(6, 0, 2): 3034 case IP_VERSION(6, 0, 3): 3035 adev->lsdma.funcs = &lsdma_v6_0_funcs; 3036 break; 3037 case IP_VERSION(7, 0, 0): 3038 case IP_VERSION(7, 0, 1): 3039 adev->lsdma.funcs = &lsdma_v7_0_funcs; 3040 break; 3041 default: 3042 break; 3043 } 3044 3045 r = amdgpu_discovery_set_common_ip_blocks(adev); 3046 if (r) 3047 return r; 3048 3049 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 3050 if (r) 3051 return r; 3052 3053 /* For SR-IOV, PSP needs to be initialized before IH */ 3054 if (amdgpu_sriov_vf(adev)) { 3055 r = amdgpu_discovery_set_psp_ip_blocks(adev); 3056 if (r) 3057 return r; 3058 r = amdgpu_discovery_set_ih_ip_blocks(adev); 3059 if (r) 3060 return r; 3061 } else { 3062 r = amdgpu_discovery_set_ih_ip_blocks(adev); 3063 if (r) 3064 return r; 3065 3066 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3067 r = amdgpu_discovery_set_psp_ip_blocks(adev); 3068 if (r) 3069 return r; 3070 } 3071 } 3072 3073 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3074 r = amdgpu_discovery_set_smu_ip_blocks(adev); 3075 if (r) 3076 return r; 3077 } 3078 3079 r = amdgpu_discovery_set_display_ip_blocks(adev); 3080 if (r) 3081 return r; 3082 3083 r = amdgpu_discovery_set_gc_ip_blocks(adev); 3084 if (r) 3085 return r; 3086 3087 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 3088 if (r) 3089 return r; 3090 3091 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 3092 !amdgpu_sriov_vf(adev)) || 3093 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 3094 r = amdgpu_discovery_set_smu_ip_blocks(adev); 3095 if (r) 3096 return r; 3097 } 3098 3099 r = amdgpu_discovery_set_mm_ip_blocks(adev); 3100 if (r) 3101 return r; 3102 3103 r = amdgpu_discovery_set_mes_ip_blocks(adev); 3104 if (r) 3105 return r; 3106 3107 r = amdgpu_discovery_set_vpe_ip_blocks(adev); 3108 if (r) 3109 return r; 3110 3111 r = amdgpu_discovery_set_umsch_mm_ip_blocks(adev); 3112 if (r) 3113 return r; 3114 3115 r = amdgpu_discovery_set_isp_ip_blocks(adev); 3116 if (r) 3117 return r; 3118 return 0; 3119 } 3120 3121