1 /* 2 * Copyright 2018-2024 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_discovery.h" 28 #include "soc15_hw_ip.h" 29 #include "discovery.h" 30 #include "amdgpu_ras.h" 31 32 #include "soc15.h" 33 #include "gfx_v9_0.h" 34 #include "gfx_v9_4_3.h" 35 #include "gmc_v9_0.h" 36 #include "df_v1_7.h" 37 #include "df_v3_6.h" 38 #include "df_v4_3.h" 39 #include "df_v4_6_2.h" 40 #include "df_v4_15.h" 41 #include "nbio_v6_1.h" 42 #include "nbio_v7_0.h" 43 #include "nbio_v7_4.h" 44 #include "nbio_v7_9.h" 45 #include "nbio_v7_11.h" 46 #include "hdp_v4_0.h" 47 #include "vega10_ih.h" 48 #include "vega20_ih.h" 49 #include "sdma_v4_0.h" 50 #include "sdma_v4_4_2.h" 51 #include "uvd_v7_0.h" 52 #include "vce_v4_0.h" 53 #include "vcn_v1_0.h" 54 #include "vcn_v2_5.h" 55 #include "jpeg_v2_5.h" 56 #include "smuio_v9_0.h" 57 #include "gmc_v10_0.h" 58 #include "gmc_v11_0.h" 59 #include "gmc_v12_0.h" 60 #include "gfxhub_v2_0.h" 61 #include "mmhub_v2_0.h" 62 #include "nbio_v2_3.h" 63 #include "nbio_v4_3.h" 64 #include "nbio_v7_2.h" 65 #include "nbio_v7_7.h" 66 #include "nbif_v6_3_1.h" 67 #include "hdp_v5_0.h" 68 #include "hdp_v5_2.h" 69 #include "hdp_v6_0.h" 70 #include "hdp_v7_0.h" 71 #include "nv.h" 72 #include "soc21.h" 73 #include "soc24.h" 74 #include "navi10_ih.h" 75 #include "ih_v6_0.h" 76 #include "ih_v6_1.h" 77 #include "ih_v7_0.h" 78 #include "gfx_v10_0.h" 79 #include "gfx_v11_0.h" 80 #include "gfx_v12_0.h" 81 #include "sdma_v5_0.h" 82 #include "sdma_v5_2.h" 83 #include "sdma_v6_0.h" 84 #include "sdma_v7_0.h" 85 #include "lsdma_v6_0.h" 86 #include "lsdma_v7_0.h" 87 #include "vcn_v2_0.h" 88 #include "jpeg_v2_0.h" 89 #include "vcn_v3_0.h" 90 #include "jpeg_v3_0.h" 91 #include "vcn_v4_0.h" 92 #include "jpeg_v4_0.h" 93 #include "vcn_v4_0_3.h" 94 #include "jpeg_v4_0_3.h" 95 #include "vcn_v4_0_5.h" 96 #include "jpeg_v4_0_5.h" 97 #include "amdgpu_vkms.h" 98 #include "mes_v11_0.h" 99 #include "mes_v12_0.h" 100 #include "smuio_v11_0.h" 101 #include "smuio_v11_0_6.h" 102 #include "smuio_v13_0.h" 103 #include "smuio_v13_0_3.h" 104 #include "smuio_v13_0_6.h" 105 #include "smuio_v14_0_2.h" 106 #include "vcn_v5_0_0.h" 107 #include "vcn_v5_0_1.h" 108 #include "jpeg_v5_0_0.h" 109 #include "jpeg_v5_0_1.h" 110 111 #include "amdgpu_vpe.h" 112 #if defined(CONFIG_DRM_AMD_ISP) 113 #include "amdgpu_isp.h" 114 #endif 115 116 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin" 117 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY); 118 119 #define mmIP_DISCOVERY_VERSION 0x16A00 120 #define mmRCC_CONFIG_MEMSIZE 0xde3 121 #define mmMP0_SMN_C2PMSG_33 0x16061 122 #define mmMM_INDEX 0x0 123 #define mmMM_INDEX_HI 0x6 124 #define mmMM_DATA 0x1 125 126 static const char *hw_id_names[HW_ID_MAX] = { 127 [MP1_HWID] = "MP1", 128 [MP2_HWID] = "MP2", 129 [THM_HWID] = "THM", 130 [SMUIO_HWID] = "SMUIO", 131 [FUSE_HWID] = "FUSE", 132 [CLKA_HWID] = "CLKA", 133 [PWR_HWID] = "PWR", 134 [GC_HWID] = "GC", 135 [UVD_HWID] = "UVD", 136 [AUDIO_AZ_HWID] = "AUDIO_AZ", 137 [ACP_HWID] = "ACP", 138 [DCI_HWID] = "DCI", 139 [DMU_HWID] = "DMU", 140 [DCO_HWID] = "DCO", 141 [DIO_HWID] = "DIO", 142 [XDMA_HWID] = "XDMA", 143 [DCEAZ_HWID] = "DCEAZ", 144 [DAZ_HWID] = "DAZ", 145 [SDPMUX_HWID] = "SDPMUX", 146 [NTB_HWID] = "NTB", 147 [IOHC_HWID] = "IOHC", 148 [L2IMU_HWID] = "L2IMU", 149 [VCE_HWID] = "VCE", 150 [MMHUB_HWID] = "MMHUB", 151 [ATHUB_HWID] = "ATHUB", 152 [DBGU_NBIO_HWID] = "DBGU_NBIO", 153 [DFX_HWID] = "DFX", 154 [DBGU0_HWID] = "DBGU0", 155 [DBGU1_HWID] = "DBGU1", 156 [OSSSYS_HWID] = "OSSSYS", 157 [HDP_HWID] = "HDP", 158 [SDMA0_HWID] = "SDMA0", 159 [SDMA1_HWID] = "SDMA1", 160 [SDMA2_HWID] = "SDMA2", 161 [SDMA3_HWID] = "SDMA3", 162 [LSDMA_HWID] = "LSDMA", 163 [ISP_HWID] = "ISP", 164 [DBGU_IO_HWID] = "DBGU_IO", 165 [DF_HWID] = "DF", 166 [CLKB_HWID] = "CLKB", 167 [FCH_HWID] = "FCH", 168 [DFX_DAP_HWID] = "DFX_DAP", 169 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 170 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 171 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 172 [L1IMU3_HWID] = "L1IMU3", 173 [L1IMU4_HWID] = "L1IMU4", 174 [L1IMU5_HWID] = "L1IMU5", 175 [L1IMU6_HWID] = "L1IMU6", 176 [L1IMU7_HWID] = "L1IMU7", 177 [L1IMU8_HWID] = "L1IMU8", 178 [L1IMU9_HWID] = "L1IMU9", 179 [L1IMU10_HWID] = "L1IMU10", 180 [L1IMU11_HWID] = "L1IMU11", 181 [L1IMU12_HWID] = "L1IMU12", 182 [L1IMU13_HWID] = "L1IMU13", 183 [L1IMU14_HWID] = "L1IMU14", 184 [L1IMU15_HWID] = "L1IMU15", 185 [WAFLC_HWID] = "WAFLC", 186 [FCH_USB_PD_HWID] = "FCH_USB_PD", 187 [PCIE_HWID] = "PCIE", 188 [PCS_HWID] = "PCS", 189 [DDCL_HWID] = "DDCL", 190 [SST_HWID] = "SST", 191 [IOAGR_HWID] = "IOAGR", 192 [NBIF_HWID] = "NBIF", 193 [IOAPIC_HWID] = "IOAPIC", 194 [SYSTEMHUB_HWID] = "SYSTEMHUB", 195 [NTBCCP_HWID] = "NTBCCP", 196 [UMC_HWID] = "UMC", 197 [SATA_HWID] = "SATA", 198 [USB_HWID] = "USB", 199 [CCXSEC_HWID] = "CCXSEC", 200 [XGMI_HWID] = "XGMI", 201 [XGBE_HWID] = "XGBE", 202 [MP0_HWID] = "MP0", 203 [VPE_HWID] = "VPE", 204 }; 205 206 static int hw_id_map[MAX_HWIP] = { 207 [GC_HWIP] = GC_HWID, 208 [HDP_HWIP] = HDP_HWID, 209 [SDMA0_HWIP] = SDMA0_HWID, 210 [SDMA1_HWIP] = SDMA1_HWID, 211 [SDMA2_HWIP] = SDMA2_HWID, 212 [SDMA3_HWIP] = SDMA3_HWID, 213 [LSDMA_HWIP] = LSDMA_HWID, 214 [MMHUB_HWIP] = MMHUB_HWID, 215 [ATHUB_HWIP] = ATHUB_HWID, 216 [NBIO_HWIP] = NBIF_HWID, 217 [MP0_HWIP] = MP0_HWID, 218 [MP1_HWIP] = MP1_HWID, 219 [UVD_HWIP] = UVD_HWID, 220 [VCE_HWIP] = VCE_HWID, 221 [DF_HWIP] = DF_HWID, 222 [DCE_HWIP] = DMU_HWID, 223 [OSSSYS_HWIP] = OSSSYS_HWID, 224 [SMUIO_HWIP] = SMUIO_HWID, 225 [PWR_HWIP] = PWR_HWID, 226 [NBIF_HWIP] = NBIF_HWID, 227 [THM_HWIP] = THM_HWID, 228 [CLK_HWIP] = CLKA_HWID, 229 [UMC_HWIP] = UMC_HWID, 230 [XGMI_HWIP] = XGMI_HWID, 231 [DCI_HWIP] = DCI_HWID, 232 [PCIE_HWIP] = PCIE_HWID, 233 [VPE_HWIP] = VPE_HWID, 234 [ISP_HWIP] = ISP_HWID, 235 }; 236 237 static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary) 238 { 239 u64 tmr_offset, tmr_size, pos; 240 void *discv_regn; 241 int ret; 242 243 ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size); 244 if (ret) 245 return ret; 246 247 pos = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET; 248 249 /* This region is read-only and reserved from system use */ 250 discv_regn = memremap(pos, adev->mman.discovery_tmr_size, MEMREMAP_WC); 251 if (discv_regn) { 252 memcpy(binary, discv_regn, adev->mman.discovery_tmr_size); 253 memunmap(discv_regn); 254 return 0; 255 } 256 257 return -ENOENT; 258 } 259 260 #define IP_DISCOVERY_V2 2 261 #define IP_DISCOVERY_V4 4 262 263 static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, 264 uint8_t *binary) 265 { 266 uint64_t vram_size; 267 u32 msg; 268 int i, ret = 0; 269 270 if (!amdgpu_sriov_vf(adev)) { 271 /* It can take up to a second for IFWI init to complete on some dGPUs, 272 * but generally it should be in the 60-100ms range. Normally this starts 273 * as soon as the device gets power so by the time the OS loads this has long 274 * completed. However, when a card is hotplugged via e.g., USB4, we need to 275 * wait for this to complete. Once the C2PMSG is updated, we can 276 * continue. 277 */ 278 279 for (i = 0; i < 1000; i++) { 280 msg = RREG32(mmMP0_SMN_C2PMSG_33); 281 if (msg & 0x80000000) 282 break; 283 msleep(1); 284 } 285 } 286 287 vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 288 289 if (vram_size) { 290 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; 291 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, 292 adev->mman.discovery_tmr_size, false); 293 } else { 294 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); 295 } 296 297 return ret; 298 } 299 300 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary) 301 { 302 const struct firmware *fw; 303 const char *fw_name; 304 int r; 305 306 switch (amdgpu_discovery) { 307 case 2: 308 fw_name = FIRMWARE_IP_DISCOVERY; 309 break; 310 default: 311 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n"); 312 return -EINVAL; 313 } 314 315 r = request_firmware(&fw, fw_name, adev->dev); 316 if (r) { 317 dev_err(adev->dev, "can't load firmware \"%s\"\n", 318 fw_name); 319 return r; 320 } 321 322 memcpy((u8 *)binary, (u8 *)fw->data, fw->size); 323 release_firmware(fw); 324 325 return 0; 326 } 327 328 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 329 { 330 uint16_t checksum = 0; 331 int i; 332 333 for (i = 0; i < size; i++) 334 checksum += data[i]; 335 336 return checksum; 337 } 338 339 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size, 340 uint16_t expected) 341 { 342 return !!(amdgpu_discovery_calculate_checksum(data, size) == expected); 343 } 344 345 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 346 { 347 struct binary_header *bhdr; 348 bhdr = (struct binary_header *)binary; 349 350 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 351 } 352 353 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) 354 { 355 /* 356 * So far, apply this quirk only on those Navy Flounder boards which 357 * have a bad harvest table of VCN config. 358 */ 359 if ((amdgpu_ip_version(adev, UVD_HWIP, 1) == IP_VERSION(3, 0, 1)) && 360 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 2))) { 361 switch (adev->pdev->revision) { 362 case 0xC1: 363 case 0xC2: 364 case 0xC3: 365 case 0xC5: 366 case 0xC7: 367 case 0xCF: 368 case 0xDF: 369 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 370 adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1; 371 break; 372 default: 373 break; 374 } 375 } 376 } 377 378 static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev, 379 struct binary_header *bhdr) 380 { 381 struct table_info *info; 382 uint16_t checksum; 383 uint16_t offset; 384 385 info = &bhdr->table_list[NPS_INFO]; 386 offset = le16_to_cpu(info->offset); 387 checksum = le16_to_cpu(info->checksum); 388 389 struct nps_info_header *nhdr = 390 (struct nps_info_header *)(adev->mman.discovery_bin + offset); 391 392 if (le32_to_cpu(nhdr->table_id) != NPS_INFO_TABLE_ID) { 393 dev_dbg(adev->dev, "invalid ip discovery nps info table id\n"); 394 return -EINVAL; 395 } 396 397 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 398 le32_to_cpu(nhdr->size_bytes), 399 checksum)) { 400 dev_dbg(adev->dev, "invalid nps info data table checksum\n"); 401 return -EINVAL; 402 } 403 404 return 0; 405 } 406 407 static int amdgpu_discovery_init(struct amdgpu_device *adev) 408 { 409 struct table_info *info; 410 struct binary_header *bhdr; 411 uint16_t offset; 412 uint16_t size; 413 uint16_t checksum; 414 int r; 415 416 adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE; 417 adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL); 418 if (!adev->mman.discovery_bin) 419 return -ENOMEM; 420 421 /* Read from file if it is the preferred option */ 422 if (amdgpu_discovery == 2) { 423 dev_info(adev->dev, "use ip discovery information from file"); 424 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin); 425 426 if (r) { 427 dev_err(adev->dev, "failed to read ip discovery binary from file\n"); 428 r = -EINVAL; 429 goto out; 430 } 431 432 } else { 433 r = amdgpu_discovery_read_binary_from_mem( 434 adev, adev->mman.discovery_bin); 435 if (r) 436 goto out; 437 } 438 439 /* check the ip discovery binary signature */ 440 if (!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) { 441 dev_err(adev->dev, 442 "get invalid ip discovery binary signature\n"); 443 r = -EINVAL; 444 goto out; 445 } 446 447 bhdr = (struct binary_header *)adev->mman.discovery_bin; 448 449 offset = offsetof(struct binary_header, binary_checksum) + 450 sizeof(bhdr->binary_checksum); 451 size = le16_to_cpu(bhdr->binary_size) - offset; 452 checksum = le16_to_cpu(bhdr->binary_checksum); 453 454 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 455 size, checksum)) { 456 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 457 r = -EINVAL; 458 goto out; 459 } 460 461 info = &bhdr->table_list[IP_DISCOVERY]; 462 offset = le16_to_cpu(info->offset); 463 checksum = le16_to_cpu(info->checksum); 464 465 if (offset) { 466 struct ip_discovery_header *ihdr = 467 (struct ip_discovery_header *)(adev->mman.discovery_bin + offset); 468 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { 469 dev_err(adev->dev, "invalid ip discovery data table signature\n"); 470 r = -EINVAL; 471 goto out; 472 } 473 474 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 475 le16_to_cpu(ihdr->size), checksum)) { 476 dev_err(adev->dev, "invalid ip discovery data table checksum\n"); 477 r = -EINVAL; 478 goto out; 479 } 480 } 481 482 info = &bhdr->table_list[GC]; 483 offset = le16_to_cpu(info->offset); 484 checksum = le16_to_cpu(info->checksum); 485 486 if (offset) { 487 struct gpu_info_header *ghdr = 488 (struct gpu_info_header *)(adev->mman.discovery_bin + offset); 489 490 if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) { 491 dev_err(adev->dev, "invalid ip discovery gc table id\n"); 492 r = -EINVAL; 493 goto out; 494 } 495 496 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 497 le32_to_cpu(ghdr->size), checksum)) { 498 dev_err(adev->dev, "invalid gc data table checksum\n"); 499 r = -EINVAL; 500 goto out; 501 } 502 } 503 504 info = &bhdr->table_list[HARVEST_INFO]; 505 offset = le16_to_cpu(info->offset); 506 checksum = le16_to_cpu(info->checksum); 507 508 if (offset) { 509 struct harvest_info_header *hhdr = 510 (struct harvest_info_header *)(adev->mman.discovery_bin + offset); 511 512 if (le32_to_cpu(hhdr->signature) != HARVEST_TABLE_SIGNATURE) { 513 dev_err(adev->dev, "invalid ip discovery harvest table signature\n"); 514 r = -EINVAL; 515 goto out; 516 } 517 518 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 519 sizeof(struct harvest_table), checksum)) { 520 dev_err(adev->dev, "invalid harvest data table checksum\n"); 521 r = -EINVAL; 522 goto out; 523 } 524 } 525 526 info = &bhdr->table_list[VCN_INFO]; 527 offset = le16_to_cpu(info->offset); 528 checksum = le16_to_cpu(info->checksum); 529 530 if (offset) { 531 struct vcn_info_header *vhdr = 532 (struct vcn_info_header *)(adev->mman.discovery_bin + offset); 533 534 if (le32_to_cpu(vhdr->table_id) != VCN_INFO_TABLE_ID) { 535 dev_err(adev->dev, "invalid ip discovery vcn table id\n"); 536 r = -EINVAL; 537 goto out; 538 } 539 540 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 541 le32_to_cpu(vhdr->size_bytes), checksum)) { 542 dev_err(adev->dev, "invalid vcn data table checksum\n"); 543 r = -EINVAL; 544 goto out; 545 } 546 } 547 548 info = &bhdr->table_list[MALL_INFO]; 549 offset = le16_to_cpu(info->offset); 550 checksum = le16_to_cpu(info->checksum); 551 552 if (0 && offset) { 553 struct mall_info_header *mhdr = 554 (struct mall_info_header *)(adev->mman.discovery_bin + offset); 555 556 if (le32_to_cpu(mhdr->table_id) != MALL_INFO_TABLE_ID) { 557 dev_err(adev->dev, "invalid ip discovery mall table id\n"); 558 r = -EINVAL; 559 goto out; 560 } 561 562 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, 563 le32_to_cpu(mhdr->size_bytes), checksum)) { 564 dev_err(adev->dev, "invalid mall data table checksum\n"); 565 r = -EINVAL; 566 goto out; 567 } 568 } 569 570 return 0; 571 572 out: 573 kfree(adev->mman.discovery_bin); 574 adev->mman.discovery_bin = NULL; 575 if ((amdgpu_discovery != 2) && 576 (RREG32(mmIP_DISCOVERY_VERSION) == 4)) 577 amdgpu_ras_query_boot_status(adev, 4); 578 return r; 579 } 580 581 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev); 582 583 void amdgpu_discovery_fini(struct amdgpu_device *adev) 584 { 585 amdgpu_discovery_sysfs_fini(adev); 586 kfree(adev->mman.discovery_bin); 587 adev->mman.discovery_bin = NULL; 588 } 589 590 static int amdgpu_discovery_validate_ip(struct amdgpu_device *adev, 591 uint8_t instance, uint16_t hw_id) 592 { 593 if (instance >= HWIP_MAX_INSTANCE) { 594 dev_err(adev->dev, 595 "Unexpected instance_number (%d) from ip discovery blob\n", 596 instance); 597 return -EINVAL; 598 } 599 if (hw_id >= HW_ID_MAX) { 600 dev_err(adev->dev, 601 "Unexpected hw_id (%d) from ip discovery blob\n", 602 hw_id); 603 return -EINVAL; 604 } 605 606 return 0; 607 } 608 609 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev, 610 uint32_t *vcn_harvest_count) 611 { 612 struct binary_header *bhdr; 613 struct ip_discovery_header *ihdr; 614 struct die_header *dhdr; 615 struct ip *ip; 616 uint16_t die_offset, ip_offset, num_dies, num_ips; 617 uint16_t hw_id; 618 uint8_t inst; 619 int i, j; 620 621 bhdr = (struct binary_header *)adev->mman.discovery_bin; 622 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 623 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 624 num_dies = le16_to_cpu(ihdr->num_dies); 625 626 /* scan harvest bit of all IP data structures */ 627 for (i = 0; i < num_dies; i++) { 628 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 629 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 630 num_ips = le16_to_cpu(dhdr->num_ips); 631 ip_offset = die_offset + sizeof(*dhdr); 632 633 for (j = 0; j < num_ips; j++) { 634 ip = (struct ip *)(adev->mman.discovery_bin + 635 ip_offset); 636 inst = ip->number_instance; 637 hw_id = le16_to_cpu(ip->hw_id); 638 if (amdgpu_discovery_validate_ip(adev, inst, hw_id)) 639 goto next_ip; 640 641 if (ip->harvest == 1) { 642 switch (hw_id) { 643 case VCN_HWID: 644 (*vcn_harvest_count)++; 645 if (inst == 0) { 646 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 647 adev->vcn.inst_mask &= 648 ~AMDGPU_VCN_HARVEST_VCN0; 649 adev->jpeg.inst_mask &= 650 ~AMDGPU_VCN_HARVEST_VCN0; 651 } else { 652 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 653 adev->vcn.inst_mask &= 654 ~AMDGPU_VCN_HARVEST_VCN1; 655 adev->jpeg.inst_mask &= 656 ~AMDGPU_VCN_HARVEST_VCN1; 657 } 658 break; 659 case DMU_HWID: 660 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 661 break; 662 default: 663 break; 664 } 665 } 666 next_ip: 667 ip_offset += struct_size(ip, base_address, 668 ip->num_base_address); 669 } 670 } 671 } 672 673 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, 674 uint32_t *vcn_harvest_count, 675 uint32_t *umc_harvest_count) 676 { 677 struct binary_header *bhdr; 678 struct harvest_table *harvest_info; 679 u16 offset; 680 int i; 681 uint32_t umc_harvest_config = 0; 682 683 bhdr = (struct binary_header *)adev->mman.discovery_bin; 684 offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset); 685 686 if (!offset) { 687 dev_err(adev->dev, "invalid harvest table offset\n"); 688 return; 689 } 690 691 harvest_info = (struct harvest_table *)(adev->mman.discovery_bin + offset); 692 693 for (i = 0; i < 32; i++) { 694 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) 695 break; 696 697 switch (le16_to_cpu(harvest_info->list[i].hw_id)) { 698 case VCN_HWID: 699 (*vcn_harvest_count)++; 700 adev->vcn.harvest_config |= 701 (1 << harvest_info->list[i].number_instance); 702 adev->jpeg.harvest_config |= 703 (1 << harvest_info->list[i].number_instance); 704 705 adev->vcn.inst_mask &= 706 ~(1U << harvest_info->list[i].number_instance); 707 adev->jpeg.inst_mask &= 708 ~(1U << harvest_info->list[i].number_instance); 709 break; 710 case DMU_HWID: 711 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 712 break; 713 case UMC_HWID: 714 umc_harvest_config |= 715 1 << (le16_to_cpu(harvest_info->list[i].number_instance)); 716 (*umc_harvest_count)++; 717 break; 718 case GC_HWID: 719 adev->gfx.xcc_mask &= 720 ~(1U << harvest_info->list[i].number_instance); 721 break; 722 case SDMA0_HWID: 723 adev->sdma.sdma_mask &= 724 ~(1U << harvest_info->list[i].number_instance); 725 break; 726 #if defined(CONFIG_DRM_AMD_ISP) 727 case ISP_HWID: 728 adev->isp.harvest_config |= 729 ~(1U << harvest_info->list[i].number_instance); 730 break; 731 #endif 732 default: 733 break; 734 } 735 } 736 737 adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) & 738 ~umc_harvest_config; 739 } 740 741 /* ================================================== */ 742 743 struct ip_hw_instance { 744 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */ 745 746 int hw_id; 747 u8 num_instance; 748 u8 major, minor, revision; 749 u8 harvest; 750 751 int num_base_addresses; 752 u32 base_addr[] __counted_by(num_base_addresses); 753 }; 754 755 struct ip_hw_id { 756 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */ 757 int hw_id; 758 }; 759 760 struct ip_die_entry { 761 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */ 762 u16 num_ips; 763 }; 764 765 /* -------------------------------------------------- */ 766 767 struct ip_hw_instance_attr { 768 struct attribute attr; 769 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf); 770 }; 771 772 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf) 773 { 774 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id); 775 } 776 777 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf) 778 { 779 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance); 780 } 781 782 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf) 783 { 784 return sysfs_emit(buf, "%d\n", ip_hw_instance->major); 785 } 786 787 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf) 788 { 789 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor); 790 } 791 792 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf) 793 { 794 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision); 795 } 796 797 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf) 798 { 799 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest); 800 } 801 802 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf) 803 { 804 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses); 805 } 806 807 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) 808 { 809 ssize_t res, at; 810 int ii; 811 812 for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 813 /* Here we satisfy the condition that, at + size <= PAGE_SIZE. 814 */ 815 if (at + 12 > PAGE_SIZE) 816 break; 817 res = sysfs_emit_at(buf, at, "0x%08X\n", 818 ip_hw_instance->base_addr[ii]); 819 if (res <= 0) 820 break; 821 at += res; 822 } 823 824 return res < 0 ? res : at; 825 } 826 827 static struct ip_hw_instance_attr ip_hw_attr[] = { 828 __ATTR_RO(hw_id), 829 __ATTR_RO(num_instance), 830 __ATTR_RO(major), 831 __ATTR_RO(minor), 832 __ATTR_RO(revision), 833 __ATTR_RO(harvest), 834 __ATTR_RO(num_base_addresses), 835 __ATTR_RO(base_addr), 836 }; 837 838 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; 839 ATTRIBUTE_GROUPS(ip_hw_instance); 840 841 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) 842 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) 843 844 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj, 845 struct attribute *attr, 846 char *buf) 847 { 848 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 849 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr); 850 851 if (!ip_hw_attr->show) 852 return -EIO; 853 854 return ip_hw_attr->show(ip_hw_instance, buf); 855 } 856 857 static const struct sysfs_ops ip_hw_instance_sysfs_ops = { 858 .show = ip_hw_instance_attr_show, 859 }; 860 861 static void ip_hw_instance_release(struct kobject *kobj) 862 { 863 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 864 865 kfree(ip_hw_instance); 866 } 867 868 static const struct kobj_type ip_hw_instance_ktype = { 869 .release = ip_hw_instance_release, 870 .sysfs_ops = &ip_hw_instance_sysfs_ops, 871 .default_groups = ip_hw_instance_groups, 872 }; 873 874 /* -------------------------------------------------- */ 875 876 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset) 877 878 static void ip_hw_id_release(struct kobject *kobj) 879 { 880 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj); 881 882 if (!list_empty(&ip_hw_id->hw_id_kset.list)) 883 DRM_ERROR("ip_hw_id->hw_id_kset is not empty"); 884 kfree(ip_hw_id); 885 } 886 887 static const struct kobj_type ip_hw_id_ktype = { 888 .release = ip_hw_id_release, 889 .sysfs_ops = &kobj_sysfs_ops, 890 }; 891 892 /* -------------------------------------------------- */ 893 894 static void die_kobj_release(struct kobject *kobj); 895 static void ip_disc_release(struct kobject *kobj); 896 897 struct ip_die_entry_attribute { 898 struct attribute attr; 899 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf); 900 }; 901 902 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr) 903 904 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf) 905 { 906 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips); 907 } 908 909 /* If there are more ip_die_entry attrs, other than the number of IPs, 910 * we can make this intro an array of attrs, and then initialize 911 * ip_die_entry_attrs in a loop. 912 */ 913 static struct ip_die_entry_attribute num_ips_attr = 914 __ATTR_RO(num_ips); 915 916 static struct attribute *ip_die_entry_attrs[] = { 917 &num_ips_attr.attr, 918 NULL, 919 }; 920 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ 921 922 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) 923 924 static ssize_t ip_die_entry_attr_show(struct kobject *kobj, 925 struct attribute *attr, 926 char *buf) 927 { 928 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr); 929 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 930 931 if (!ip_die_entry_attr->show) 932 return -EIO; 933 934 return ip_die_entry_attr->show(ip_die_entry, buf); 935 } 936 937 static void ip_die_entry_release(struct kobject *kobj) 938 { 939 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 940 941 if (!list_empty(&ip_die_entry->ip_kset.list)) 942 DRM_ERROR("ip_die_entry->ip_kset is not empty"); 943 kfree(ip_die_entry); 944 } 945 946 static const struct sysfs_ops ip_die_entry_sysfs_ops = { 947 .show = ip_die_entry_attr_show, 948 }; 949 950 static const struct kobj_type ip_die_entry_ktype = { 951 .release = ip_die_entry_release, 952 .sysfs_ops = &ip_die_entry_sysfs_ops, 953 .default_groups = ip_die_entry_groups, 954 }; 955 956 static const struct kobj_type die_kobj_ktype = { 957 .release = die_kobj_release, 958 .sysfs_ops = &kobj_sysfs_ops, 959 }; 960 961 static const struct kobj_type ip_discovery_ktype = { 962 .release = ip_disc_release, 963 .sysfs_ops = &kobj_sysfs_ops, 964 }; 965 966 struct ip_discovery_top { 967 struct kobject kobj; /* ip_discovery/ */ 968 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */ 969 struct amdgpu_device *adev; 970 }; 971 972 static void die_kobj_release(struct kobject *kobj) 973 { 974 struct ip_discovery_top *ip_top = container_of(to_kset(kobj), 975 struct ip_discovery_top, 976 die_kset); 977 if (!list_empty(&ip_top->die_kset.list)) 978 DRM_ERROR("ip_top->die_kset is not empty"); 979 } 980 981 static void ip_disc_release(struct kobject *kobj) 982 { 983 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top, 984 kobj); 985 struct amdgpu_device *adev = ip_top->adev; 986 987 adev->ip_top = NULL; 988 kfree(ip_top); 989 } 990 991 static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev, 992 uint16_t hw_id, uint8_t inst) 993 { 994 uint8_t harvest = 0; 995 996 /* Until a uniform way is figured, get mask based on hwid */ 997 switch (hw_id) { 998 case VCN_HWID: 999 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0; 1000 break; 1001 case DMU_HWID: 1002 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK) 1003 harvest = 0x1; 1004 break; 1005 case UMC_HWID: 1006 /* TODO: It needs another parsing; for now, ignore.*/ 1007 break; 1008 case GC_HWID: 1009 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; 1010 break; 1011 case SDMA0_HWID: 1012 harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0; 1013 break; 1014 default: 1015 break; 1016 } 1017 1018 return harvest; 1019 } 1020 1021 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, 1022 struct ip_die_entry *ip_die_entry, 1023 const size_t _ip_offset, const int num_ips, 1024 bool reg_base_64) 1025 { 1026 int ii, jj, kk, res; 1027 uint16_t hw_id; 1028 uint8_t inst; 1029 1030 DRM_DEBUG("num_ips:%d", num_ips); 1031 1032 /* Find all IPs of a given HW ID, and add their instance to 1033 * #die/#hw_id/#instance/<attributes> 1034 */ 1035 for (ii = 0; ii < HW_ID_MAX; ii++) { 1036 struct ip_hw_id *ip_hw_id = NULL; 1037 size_t ip_offset = _ip_offset; 1038 1039 for (jj = 0; jj < num_ips; jj++) { 1040 struct ip_v4 *ip; 1041 struct ip_hw_instance *ip_hw_instance; 1042 1043 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset); 1044 inst = ip->instance_number; 1045 hw_id = le16_to_cpu(ip->hw_id); 1046 if (amdgpu_discovery_validate_ip(adev, inst, hw_id) || 1047 hw_id != ii) 1048 goto next_ip; 1049 1050 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset); 1051 1052 /* We have a hw_id match; register the hw 1053 * block if not yet registered. 1054 */ 1055 if (!ip_hw_id) { 1056 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL); 1057 if (!ip_hw_id) 1058 return -ENOMEM; 1059 ip_hw_id->hw_id = ii; 1060 1061 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii); 1062 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset; 1063 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype; 1064 res = kset_register(&ip_hw_id->hw_id_kset); 1065 if (res) { 1066 DRM_ERROR("Couldn't register ip_hw_id kset"); 1067 kfree(ip_hw_id); 1068 return res; 1069 } 1070 if (hw_id_names[ii]) { 1071 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj, 1072 &ip_hw_id->hw_id_kset.kobj, 1073 hw_id_names[ii]); 1074 if (res) { 1075 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n", 1076 hw_id_names[ii], 1077 kobject_name(&ip_die_entry->ip_kset.kobj)); 1078 } 1079 } 1080 } 1081 1082 /* Now register its instance. 1083 */ 1084 ip_hw_instance = kzalloc(struct_size(ip_hw_instance, 1085 base_addr, 1086 ip->num_base_address), 1087 GFP_KERNEL); 1088 if (!ip_hw_instance) { 1089 DRM_ERROR("no memory for ip_hw_instance"); 1090 return -ENOMEM; 1091 } 1092 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */ 1093 ip_hw_instance->num_instance = ip->instance_number; 1094 ip_hw_instance->major = ip->major; 1095 ip_hw_instance->minor = ip->minor; 1096 ip_hw_instance->revision = ip->revision; 1097 ip_hw_instance->harvest = 1098 amdgpu_discovery_get_harvest_info( 1099 adev, ip_hw_instance->hw_id, 1100 ip_hw_instance->num_instance); 1101 ip_hw_instance->num_base_addresses = ip->num_base_address; 1102 1103 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) { 1104 if (reg_base_64) 1105 ip_hw_instance->base_addr[kk] = 1106 lower_32_bits(le64_to_cpu(ip->base_address_64[kk])) & 0x3FFFFFFF; 1107 else 1108 ip_hw_instance->base_addr[kk] = ip->base_address[kk]; 1109 } 1110 1111 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); 1112 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; 1113 res = kobject_add(&ip_hw_instance->kobj, NULL, 1114 "%d", ip_hw_instance->num_instance); 1115 next_ip: 1116 if (reg_base_64) 1117 ip_offset += struct_size(ip, base_address_64, 1118 ip->num_base_address); 1119 else 1120 ip_offset += struct_size(ip, base_address, 1121 ip->num_base_address); 1122 } 1123 } 1124 1125 return 0; 1126 } 1127 1128 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) 1129 { 1130 struct binary_header *bhdr; 1131 struct ip_discovery_header *ihdr; 1132 struct die_header *dhdr; 1133 struct kset *die_kset = &adev->ip_top->die_kset; 1134 u16 num_dies, die_offset, num_ips; 1135 size_t ip_offset; 1136 int ii, res; 1137 1138 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1139 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1140 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1141 num_dies = le16_to_cpu(ihdr->num_dies); 1142 1143 DRM_DEBUG("number of dies: %d\n", num_dies); 1144 1145 for (ii = 0; ii < num_dies; ii++) { 1146 struct ip_die_entry *ip_die_entry; 1147 1148 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); 1149 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 1150 num_ips = le16_to_cpu(dhdr->num_ips); 1151 ip_offset = die_offset + sizeof(*dhdr); 1152 1153 /* Add the die to the kset. 1154 * 1155 * dhdr->die_id == ii, which was checked in 1156 * amdgpu_discovery_reg_base_init(). 1157 */ 1158 1159 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL); 1160 if (!ip_die_entry) 1161 return -ENOMEM; 1162 1163 ip_die_entry->num_ips = num_ips; 1164 1165 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id)); 1166 ip_die_entry->ip_kset.kobj.kset = die_kset; 1167 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype; 1168 res = kset_register(&ip_die_entry->ip_kset); 1169 if (res) { 1170 DRM_ERROR("Couldn't register ip_die_entry kset"); 1171 kfree(ip_die_entry); 1172 return res; 1173 } 1174 1175 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips, !!ihdr->base_addr_64_bit); 1176 } 1177 1178 return 0; 1179 } 1180 1181 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) 1182 { 1183 struct kset *die_kset; 1184 int res, ii; 1185 1186 if (!adev->mman.discovery_bin) 1187 return -EINVAL; 1188 1189 adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL); 1190 if (!adev->ip_top) 1191 return -ENOMEM; 1192 1193 adev->ip_top->adev = adev; 1194 1195 res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype, 1196 &adev->dev->kobj, "ip_discovery"); 1197 if (res) { 1198 DRM_ERROR("Couldn't init and add ip_discovery/"); 1199 goto Err; 1200 } 1201 1202 die_kset = &adev->ip_top->die_kset; 1203 kobject_set_name(&die_kset->kobj, "%s", "die"); 1204 die_kset->kobj.parent = &adev->ip_top->kobj; 1205 die_kset->kobj.ktype = &die_kobj_ktype; 1206 res = kset_register(&adev->ip_top->die_kset); 1207 if (res) { 1208 DRM_ERROR("Couldn't register die_kset"); 1209 goto Err; 1210 } 1211 1212 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++) 1213 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr; 1214 ip_hw_instance_attrs[ii] = NULL; 1215 1216 res = amdgpu_discovery_sysfs_recurse(adev); 1217 1218 return res; 1219 Err: 1220 kobject_put(&adev->ip_top->kobj); 1221 return res; 1222 } 1223 1224 /* -------------------------------------------------- */ 1225 1226 #define list_to_kobj(el) container_of(el, struct kobject, entry) 1227 1228 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id) 1229 { 1230 struct list_head *el, *tmp; 1231 struct kset *hw_id_kset; 1232 1233 hw_id_kset = &ip_hw_id->hw_id_kset; 1234 spin_lock(&hw_id_kset->list_lock); 1235 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) { 1236 list_del_init(el); 1237 spin_unlock(&hw_id_kset->list_lock); 1238 /* kobject is embedded in ip_hw_instance */ 1239 kobject_put(list_to_kobj(el)); 1240 spin_lock(&hw_id_kset->list_lock); 1241 } 1242 spin_unlock(&hw_id_kset->list_lock); 1243 kobject_put(&ip_hw_id->hw_id_kset.kobj); 1244 } 1245 1246 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry) 1247 { 1248 struct list_head *el, *tmp; 1249 struct kset *ip_kset; 1250 1251 ip_kset = &ip_die_entry->ip_kset; 1252 spin_lock(&ip_kset->list_lock); 1253 list_for_each_prev_safe(el, tmp, &ip_kset->list) { 1254 list_del_init(el); 1255 spin_unlock(&ip_kset->list_lock); 1256 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el))); 1257 spin_lock(&ip_kset->list_lock); 1258 } 1259 spin_unlock(&ip_kset->list_lock); 1260 kobject_put(&ip_die_entry->ip_kset.kobj); 1261 } 1262 1263 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) 1264 { 1265 struct list_head *el, *tmp; 1266 struct kset *die_kset; 1267 1268 die_kset = &adev->ip_top->die_kset; 1269 spin_lock(&die_kset->list_lock); 1270 list_for_each_prev_safe(el, tmp, &die_kset->list) { 1271 list_del_init(el); 1272 spin_unlock(&die_kset->list_lock); 1273 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 1274 spin_lock(&die_kset->list_lock); 1275 } 1276 spin_unlock(&die_kset->list_lock); 1277 kobject_put(&adev->ip_top->die_kset.kobj); 1278 kobject_put(&adev->ip_top->kobj); 1279 } 1280 1281 /* ================================================== */ 1282 1283 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 1284 { 1285 uint8_t num_base_address, subrev, variant; 1286 struct binary_header *bhdr; 1287 struct ip_discovery_header *ihdr; 1288 struct die_header *dhdr; 1289 struct ip_v4 *ip; 1290 uint16_t die_offset; 1291 uint16_t ip_offset; 1292 uint16_t num_dies; 1293 uint16_t num_ips; 1294 uint16_t hw_id; 1295 uint8_t inst; 1296 int hw_ip; 1297 int i, j, k; 1298 int r; 1299 1300 r = amdgpu_discovery_init(adev); 1301 if (r) { 1302 DRM_ERROR("amdgpu_discovery_init failed\n"); 1303 return r; 1304 } 1305 1306 adev->gfx.xcc_mask = 0; 1307 adev->sdma.sdma_mask = 0; 1308 adev->vcn.inst_mask = 0; 1309 adev->jpeg.inst_mask = 0; 1310 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1311 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1312 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1313 num_dies = le16_to_cpu(ihdr->num_dies); 1314 1315 DRM_DEBUG("number of dies: %d\n", num_dies); 1316 1317 for (i = 0; i < num_dies; i++) { 1318 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1319 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); 1320 num_ips = le16_to_cpu(dhdr->num_ips); 1321 ip_offset = die_offset + sizeof(*dhdr); 1322 1323 if (le16_to_cpu(dhdr->die_id) != i) { 1324 DRM_ERROR("invalid die id %d, expected %d\n", 1325 le16_to_cpu(dhdr->die_id), i); 1326 return -EINVAL; 1327 } 1328 1329 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 1330 le16_to_cpu(dhdr->die_id), num_ips); 1331 1332 for (j = 0; j < num_ips; j++) { 1333 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset); 1334 1335 inst = ip->instance_number; 1336 hw_id = le16_to_cpu(ip->hw_id); 1337 if (amdgpu_discovery_validate_ip(adev, inst, hw_id)) 1338 goto next_ip; 1339 1340 num_base_address = ip->num_base_address; 1341 1342 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 1343 hw_id_names[le16_to_cpu(ip->hw_id)], 1344 le16_to_cpu(ip->hw_id), 1345 ip->instance_number, 1346 ip->major, ip->minor, 1347 ip->revision); 1348 1349 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 1350 /* Bit [5:0]: original revision value 1351 * Bit [7:6]: en/decode capability: 1352 * 0b00 : VCN function normally 1353 * 0b10 : encode is disabled 1354 * 0b01 : decode is disabled 1355 */ 1356 if (adev->vcn.num_vcn_inst < 1357 AMDGPU_MAX_VCN_INSTANCES) { 1358 adev->vcn.inst[adev->vcn.num_vcn_inst].vcn_config = 1359 ip->revision & 0xc0; 1360 adev->vcn.num_vcn_inst++; 1361 adev->vcn.inst_mask |= 1362 (1U << ip->instance_number); 1363 adev->jpeg.inst_mask |= 1364 (1U << ip->instance_number); 1365 } else { 1366 dev_err(adev->dev, "Too many VCN instances: %d vs %d\n", 1367 adev->vcn.num_vcn_inst + 1, 1368 AMDGPU_MAX_VCN_INSTANCES); 1369 } 1370 ip->revision &= ~0xc0; 1371 } 1372 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 1373 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 1374 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 1375 le16_to_cpu(ip->hw_id) == SDMA3_HWID) { 1376 if (adev->sdma.num_instances < 1377 AMDGPU_MAX_SDMA_INSTANCES) { 1378 adev->sdma.num_instances++; 1379 adev->sdma.sdma_mask |= 1380 (1U << ip->instance_number); 1381 } else { 1382 dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n", 1383 adev->sdma.num_instances + 1, 1384 AMDGPU_MAX_SDMA_INSTANCES); 1385 } 1386 } 1387 1388 if (le16_to_cpu(ip->hw_id) == VPE_HWID) { 1389 if (adev->vpe.num_instances < AMDGPU_MAX_VPE_INSTANCES) 1390 adev->vpe.num_instances++; 1391 else 1392 dev_err(adev->dev, "Too many VPE instances: %d vs %d\n", 1393 adev->vpe.num_instances + 1, 1394 AMDGPU_MAX_VPE_INSTANCES); 1395 } 1396 1397 if (le16_to_cpu(ip->hw_id) == UMC_HWID) { 1398 adev->gmc.num_umc++; 1399 adev->umc.node_inst_num++; 1400 } 1401 1402 if (le16_to_cpu(ip->hw_id) == GC_HWID) 1403 adev->gfx.xcc_mask |= 1404 (1U << ip->instance_number); 1405 1406 for (k = 0; k < num_base_address; k++) { 1407 /* 1408 * convert the endianness of base addresses in place, 1409 * so that we don't need to convert them when accessing adev->reg_offset. 1410 */ 1411 if (ihdr->base_addr_64_bit) 1412 /* Truncate the 64bit base address from ip discovery 1413 * and only store lower 32bit ip base in reg_offset[]. 1414 * Bits > 32 follows ASIC specific format, thus just 1415 * discard them and handle it within specific ASIC. 1416 * By this way reg_offset[] and related helpers can 1417 * stay unchanged. 1418 * The base address is in dwords, thus clear the 1419 * highest 2 bits to store. 1420 */ 1421 ip->base_address[k] = 1422 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF; 1423 else 1424 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 1425 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 1426 } 1427 1428 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 1429 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) && 1430 hw_id_map[hw_ip] != 0) { 1431 DRM_DEBUG("set register base offset for %s\n", 1432 hw_id_names[le16_to_cpu(ip->hw_id)]); 1433 adev->reg_offset[hw_ip][ip->instance_number] = 1434 ip->base_address; 1435 /* Instance support is somewhat inconsistent. 1436 * SDMA is a good example. Sienna cichlid has 4 total 1437 * SDMA instances, each enumerated separately (HWIDs 1438 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 1439 * but they are enumerated as multiple instances of the 1440 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 1441 * example. On most chips there are multiple instances 1442 * with the same HWID. 1443 */ 1444 1445 if (ihdr->version < 3) { 1446 subrev = 0; 1447 variant = 0; 1448 } else { 1449 subrev = ip->sub_revision; 1450 variant = ip->variant; 1451 } 1452 1453 adev->ip_versions[hw_ip] 1454 [ip->instance_number] = 1455 IP_VERSION_FULL(ip->major, 1456 ip->minor, 1457 ip->revision, 1458 variant, 1459 subrev); 1460 } 1461 } 1462 1463 next_ip: 1464 if (ihdr->base_addr_64_bit) 1465 ip_offset += struct_size(ip, base_address_64, ip->num_base_address); 1466 else 1467 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1468 } 1469 } 1470 1471 return 0; 1472 } 1473 1474 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 1475 { 1476 struct ip_discovery_header *ihdr; 1477 struct binary_header *bhdr; 1478 int vcn_harvest_count = 0; 1479 int umc_harvest_count = 0; 1480 uint16_t offset, ihdr_ver; 1481 1482 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1483 offset = le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset); 1484 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + 1485 offset); 1486 ihdr_ver = le16_to_cpu(ihdr->version); 1487 /* 1488 * Harvest table does not fit Navi1x and legacy GPUs, 1489 * so read harvest bit per IP data structure to set 1490 * harvest configuration. 1491 */ 1492 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 2, 0) && 1493 ihdr_ver <= 2) { 1494 if ((adev->pdev->device == 0x731E && 1495 (adev->pdev->revision == 0xC6 || 1496 adev->pdev->revision == 0xC7)) || 1497 (adev->pdev->device == 0x7340 && 1498 adev->pdev->revision == 0xC9) || 1499 (adev->pdev->device == 0x7360 && 1500 adev->pdev->revision == 0xC7)) 1501 amdgpu_discovery_read_harvest_bit_per_ip(adev, 1502 &vcn_harvest_count); 1503 } else { 1504 amdgpu_discovery_read_from_harvest_table(adev, 1505 &vcn_harvest_count, 1506 &umc_harvest_count); 1507 } 1508 1509 amdgpu_discovery_harvest_config_quirk(adev); 1510 1511 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 1512 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 1513 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 1514 } 1515 1516 if (umc_harvest_count < adev->gmc.num_umc) { 1517 adev->gmc.num_umc -= umc_harvest_count; 1518 } 1519 } 1520 1521 union gc_info { 1522 struct gc_info_v1_0 v1; 1523 struct gc_info_v1_1 v1_1; 1524 struct gc_info_v1_2 v1_2; 1525 struct gc_info_v1_3 v1_3; 1526 struct gc_info_v2_0 v2; 1527 struct gc_info_v2_1 v2_1; 1528 }; 1529 1530 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 1531 { 1532 struct binary_header *bhdr; 1533 union gc_info *gc_info; 1534 u16 offset; 1535 1536 if (!adev->mman.discovery_bin) { 1537 DRM_ERROR("ip discovery uninitialized\n"); 1538 return -EINVAL; 1539 } 1540 1541 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1542 offset = le16_to_cpu(bhdr->table_list[GC].offset); 1543 1544 if (!offset) 1545 return 0; 1546 1547 gc_info = (union gc_info *)(adev->mman.discovery_bin + offset); 1548 1549 switch (le16_to_cpu(gc_info->v1.header.version_major)) { 1550 case 1: 1551 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); 1552 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 1553 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); 1554 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1555 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); 1556 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); 1557 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); 1558 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); 1559 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); 1560 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); 1561 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); 1562 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); 1563 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); 1564 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); 1565 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); 1566 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / 1567 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1568 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); 1569 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 1) { 1570 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa); 1571 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface); 1572 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps); 1573 } 1574 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 2) { 1575 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg); 1576 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size); 1577 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp); 1578 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc); 1579 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc); 1580 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa); 1581 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance); 1582 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu); 1583 } 1584 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 3) { 1585 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v1_3.gc_tcp_size_per_cu); 1586 adev->gfx.config.gc_tcp_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcp_cache_line_size); 1587 adev->gfx.config.gc_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_size_per_sqc); 1588 adev->gfx.config.gc_instruction_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_line_size); 1589 adev->gfx.config.gc_scalar_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_size_per_sqc); 1590 adev->gfx.config.gc_scalar_data_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_line_size); 1591 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v1_3.gc_tcc_size); 1592 adev->gfx.config.gc_tcc_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcc_cache_line_size); 1593 } 1594 break; 1595 case 2: 1596 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); 1597 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); 1598 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1599 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); 1600 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); 1601 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); 1602 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); 1603 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); 1604 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); 1605 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); 1606 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); 1607 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); 1608 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); 1609 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); 1610 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / 1611 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1612 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); 1613 if (le16_to_cpu(gc_info->v2.header.version_minor) == 1) { 1614 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh); 1615 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu); 1616 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XCD */ 1617 adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc); 1618 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_cache_size_per_sqc); 1619 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_size_per_sqc); 1620 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */ 1621 } 1622 break; 1623 default: 1624 dev_err(adev->dev, 1625 "Unhandled GC info table %d.%d\n", 1626 le16_to_cpu(gc_info->v1.header.version_major), 1627 le16_to_cpu(gc_info->v1.header.version_minor)); 1628 return -EINVAL; 1629 } 1630 return 0; 1631 } 1632 1633 union mall_info { 1634 struct mall_info_v1_0 v1; 1635 struct mall_info_v2_0 v2; 1636 }; 1637 1638 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) 1639 { 1640 struct binary_header *bhdr; 1641 union mall_info *mall_info; 1642 u32 u, mall_size_per_umc, m_s_present, half_use; 1643 u64 mall_size; 1644 u16 offset; 1645 1646 if (!adev->mman.discovery_bin) { 1647 DRM_ERROR("ip discovery uninitialized\n"); 1648 return -EINVAL; 1649 } 1650 1651 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1652 offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset); 1653 1654 if (!offset) 1655 return 0; 1656 1657 mall_info = (union mall_info *)(adev->mman.discovery_bin + offset); 1658 1659 switch (le16_to_cpu(mall_info->v1.header.version_major)) { 1660 case 1: 1661 mall_size = 0; 1662 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m); 1663 m_s_present = le32_to_cpu(mall_info->v1.m_s_present); 1664 half_use = le32_to_cpu(mall_info->v1.m_half_use); 1665 for (u = 0; u < adev->gmc.num_umc; u++) { 1666 if (m_s_present & (1 << u)) 1667 mall_size += mall_size_per_umc * 2; 1668 else if (half_use & (1 << u)) 1669 mall_size += mall_size_per_umc / 2; 1670 else 1671 mall_size += mall_size_per_umc; 1672 } 1673 adev->gmc.mall_size = mall_size; 1674 adev->gmc.m_half_use = half_use; 1675 break; 1676 case 2: 1677 mall_size_per_umc = le32_to_cpu(mall_info->v2.mall_size_per_umc); 1678 adev->gmc.mall_size = (uint64_t)mall_size_per_umc * adev->gmc.num_umc; 1679 break; 1680 default: 1681 dev_err(adev->dev, 1682 "Unhandled MALL info table %d.%d\n", 1683 le16_to_cpu(mall_info->v1.header.version_major), 1684 le16_to_cpu(mall_info->v1.header.version_minor)); 1685 return -EINVAL; 1686 } 1687 return 0; 1688 } 1689 1690 union vcn_info { 1691 struct vcn_info_v1_0 v1; 1692 }; 1693 1694 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) 1695 { 1696 struct binary_header *bhdr; 1697 union vcn_info *vcn_info; 1698 u16 offset; 1699 int v; 1700 1701 if (!adev->mman.discovery_bin) { 1702 DRM_ERROR("ip discovery uninitialized\n"); 1703 return -EINVAL; 1704 } 1705 1706 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1707 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES 1708 * but that may change in the future with new GPUs so keep this 1709 * check for defensive purposes. 1710 */ 1711 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { 1712 dev_err(adev->dev, "invalid vcn instances\n"); 1713 return -EINVAL; 1714 } 1715 1716 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1717 offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset); 1718 1719 if (!offset) 1720 return 0; 1721 1722 vcn_info = (union vcn_info *)(adev->mman.discovery_bin + offset); 1723 1724 switch (le16_to_cpu(vcn_info->v1.header.version_major)) { 1725 case 1: 1726 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1727 * so this won't overflow. 1728 */ 1729 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { 1730 adev->vcn.inst[v].vcn_codec_disable_mask = 1731 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits); 1732 } 1733 break; 1734 default: 1735 dev_err(adev->dev, 1736 "Unhandled VCN info table %d.%d\n", 1737 le16_to_cpu(vcn_info->v1.header.version_major), 1738 le16_to_cpu(vcn_info->v1.header.version_minor)); 1739 return -EINVAL; 1740 } 1741 return 0; 1742 } 1743 1744 union nps_info { 1745 struct nps_info_v1_0 v1; 1746 }; 1747 1748 static int amdgpu_discovery_refresh_nps_info(struct amdgpu_device *adev, 1749 union nps_info *nps_data) 1750 { 1751 uint64_t vram_size, pos, offset; 1752 struct nps_info_header *nhdr; 1753 struct binary_header bhdr; 1754 uint16_t checksum; 1755 1756 vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 1757 pos = vram_size - DISCOVERY_TMR_OFFSET; 1758 amdgpu_device_vram_access(adev, pos, &bhdr, sizeof(bhdr), false); 1759 1760 offset = le16_to_cpu(bhdr.table_list[NPS_INFO].offset); 1761 checksum = le16_to_cpu(bhdr.table_list[NPS_INFO].checksum); 1762 1763 amdgpu_device_vram_access(adev, (pos + offset), nps_data, 1764 sizeof(*nps_data), false); 1765 1766 nhdr = (struct nps_info_header *)(nps_data); 1767 if (!amdgpu_discovery_verify_checksum((uint8_t *)nps_data, 1768 le32_to_cpu(nhdr->size_bytes), 1769 checksum)) { 1770 dev_err(adev->dev, "nps data refresh, checksum mismatch\n"); 1771 return -EINVAL; 1772 } 1773 1774 return 0; 1775 } 1776 1777 int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, 1778 uint32_t *nps_type, 1779 struct amdgpu_gmc_memrange **ranges, 1780 int *range_cnt, bool refresh) 1781 { 1782 struct amdgpu_gmc_memrange *mem_ranges; 1783 struct binary_header *bhdr; 1784 union nps_info *nps_info; 1785 union nps_info nps_data; 1786 u16 offset; 1787 int i, r; 1788 1789 if (!nps_type || !range_cnt || !ranges) 1790 return -EINVAL; 1791 1792 if (refresh) { 1793 r = amdgpu_discovery_refresh_nps_info(adev, &nps_data); 1794 if (r) 1795 return r; 1796 nps_info = &nps_data; 1797 } else { 1798 if (!adev->mman.discovery_bin) { 1799 dev_err(adev->dev, 1800 "fetch mem range failed, ip discovery uninitialized\n"); 1801 return -EINVAL; 1802 } 1803 1804 bhdr = (struct binary_header *)adev->mman.discovery_bin; 1805 offset = le16_to_cpu(bhdr->table_list[NPS_INFO].offset); 1806 1807 if (!offset) 1808 return -ENOENT; 1809 1810 /* If verification fails, return as if NPS table doesn't exist */ 1811 if (amdgpu_discovery_verify_npsinfo(adev, bhdr)) 1812 return -ENOENT; 1813 1814 nps_info = 1815 (union nps_info *)(adev->mman.discovery_bin + offset); 1816 } 1817 1818 switch (le16_to_cpu(nps_info->v1.header.version_major)) { 1819 case 1: 1820 mem_ranges = kvcalloc(nps_info->v1.count, 1821 sizeof(*mem_ranges), 1822 GFP_KERNEL); 1823 if (!mem_ranges) 1824 return -ENOMEM; 1825 *nps_type = nps_info->v1.nps_type; 1826 *range_cnt = nps_info->v1.count; 1827 for (i = 0; i < *range_cnt; i++) { 1828 mem_ranges[i].base_address = 1829 nps_info->v1.instance_info[i].base_address; 1830 mem_ranges[i].limit_address = 1831 nps_info->v1.instance_info[i].limit_address; 1832 mem_ranges[i].nid_mask = -1; 1833 mem_ranges[i].flags = 0; 1834 } 1835 *ranges = mem_ranges; 1836 break; 1837 default: 1838 dev_err(adev->dev, "Unhandled NPS info table %d.%d\n", 1839 le16_to_cpu(nps_info->v1.header.version_major), 1840 le16_to_cpu(nps_info->v1.header.version_minor)); 1841 return -EINVAL; 1842 } 1843 1844 return 0; 1845 } 1846 1847 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 1848 { 1849 /* what IP to use for this? */ 1850 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1851 case IP_VERSION(9, 0, 1): 1852 case IP_VERSION(9, 1, 0): 1853 case IP_VERSION(9, 2, 1): 1854 case IP_VERSION(9, 2, 2): 1855 case IP_VERSION(9, 3, 0): 1856 case IP_VERSION(9, 4, 0): 1857 case IP_VERSION(9, 4, 1): 1858 case IP_VERSION(9, 4, 2): 1859 case IP_VERSION(9, 4, 3): 1860 case IP_VERSION(9, 4, 4): 1861 case IP_VERSION(9, 5, 0): 1862 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 1863 break; 1864 case IP_VERSION(10, 1, 10): 1865 case IP_VERSION(10, 1, 1): 1866 case IP_VERSION(10, 1, 2): 1867 case IP_VERSION(10, 1, 3): 1868 case IP_VERSION(10, 1, 4): 1869 case IP_VERSION(10, 3, 0): 1870 case IP_VERSION(10, 3, 1): 1871 case IP_VERSION(10, 3, 2): 1872 case IP_VERSION(10, 3, 3): 1873 case IP_VERSION(10, 3, 4): 1874 case IP_VERSION(10, 3, 5): 1875 case IP_VERSION(10, 3, 6): 1876 case IP_VERSION(10, 3, 7): 1877 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 1878 break; 1879 case IP_VERSION(11, 0, 0): 1880 case IP_VERSION(11, 0, 1): 1881 case IP_VERSION(11, 0, 2): 1882 case IP_VERSION(11, 0, 3): 1883 case IP_VERSION(11, 0, 4): 1884 case IP_VERSION(11, 5, 0): 1885 case IP_VERSION(11, 5, 1): 1886 case IP_VERSION(11, 5, 2): 1887 case IP_VERSION(11, 5, 3): 1888 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); 1889 break; 1890 case IP_VERSION(12, 0, 0): 1891 case IP_VERSION(12, 0, 1): 1892 amdgpu_device_ip_block_add(adev, &soc24_common_ip_block); 1893 break; 1894 default: 1895 dev_err(adev->dev, 1896 "Failed to add common ip block(GC_HWIP:0x%x)\n", 1897 amdgpu_ip_version(adev, GC_HWIP, 0)); 1898 return -EINVAL; 1899 } 1900 return 0; 1901 } 1902 1903 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 1904 { 1905 /* use GC or MMHUB IP version */ 1906 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1907 case IP_VERSION(9, 0, 1): 1908 case IP_VERSION(9, 1, 0): 1909 case IP_VERSION(9, 2, 1): 1910 case IP_VERSION(9, 2, 2): 1911 case IP_VERSION(9, 3, 0): 1912 case IP_VERSION(9, 4, 0): 1913 case IP_VERSION(9, 4, 1): 1914 case IP_VERSION(9, 4, 2): 1915 case IP_VERSION(9, 4, 3): 1916 case IP_VERSION(9, 4, 4): 1917 case IP_VERSION(9, 5, 0): 1918 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 1919 break; 1920 case IP_VERSION(10, 1, 10): 1921 case IP_VERSION(10, 1, 1): 1922 case IP_VERSION(10, 1, 2): 1923 case IP_VERSION(10, 1, 3): 1924 case IP_VERSION(10, 1, 4): 1925 case IP_VERSION(10, 3, 0): 1926 case IP_VERSION(10, 3, 1): 1927 case IP_VERSION(10, 3, 2): 1928 case IP_VERSION(10, 3, 3): 1929 case IP_VERSION(10, 3, 4): 1930 case IP_VERSION(10, 3, 5): 1931 case IP_VERSION(10, 3, 6): 1932 case IP_VERSION(10, 3, 7): 1933 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 1934 break; 1935 case IP_VERSION(11, 0, 0): 1936 case IP_VERSION(11, 0, 1): 1937 case IP_VERSION(11, 0, 2): 1938 case IP_VERSION(11, 0, 3): 1939 case IP_VERSION(11, 0, 4): 1940 case IP_VERSION(11, 5, 0): 1941 case IP_VERSION(11, 5, 1): 1942 case IP_VERSION(11, 5, 2): 1943 case IP_VERSION(11, 5, 3): 1944 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block); 1945 break; 1946 case IP_VERSION(12, 0, 0): 1947 case IP_VERSION(12, 0, 1): 1948 amdgpu_device_ip_block_add(adev, &gmc_v12_0_ip_block); 1949 break; 1950 default: 1951 dev_err(adev->dev, "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 1952 amdgpu_ip_version(adev, GC_HWIP, 0)); 1953 return -EINVAL; 1954 } 1955 return 0; 1956 } 1957 1958 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 1959 { 1960 switch (amdgpu_ip_version(adev, OSSSYS_HWIP, 0)) { 1961 case IP_VERSION(4, 0, 0): 1962 case IP_VERSION(4, 0, 1): 1963 case IP_VERSION(4, 1, 0): 1964 case IP_VERSION(4, 1, 1): 1965 case IP_VERSION(4, 3, 0): 1966 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 1967 break; 1968 case IP_VERSION(4, 2, 0): 1969 case IP_VERSION(4, 2, 1): 1970 case IP_VERSION(4, 4, 0): 1971 case IP_VERSION(4, 4, 2): 1972 case IP_VERSION(4, 4, 5): 1973 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 1974 break; 1975 case IP_VERSION(5, 0, 0): 1976 case IP_VERSION(5, 0, 1): 1977 case IP_VERSION(5, 0, 2): 1978 case IP_VERSION(5, 0, 3): 1979 case IP_VERSION(5, 2, 0): 1980 case IP_VERSION(5, 2, 1): 1981 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 1982 break; 1983 case IP_VERSION(6, 0, 0): 1984 case IP_VERSION(6, 0, 1): 1985 case IP_VERSION(6, 0, 2): 1986 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block); 1987 break; 1988 case IP_VERSION(6, 1, 0): 1989 amdgpu_device_ip_block_add(adev, &ih_v6_1_ip_block); 1990 break; 1991 case IP_VERSION(7, 0, 0): 1992 amdgpu_device_ip_block_add(adev, &ih_v7_0_ip_block); 1993 break; 1994 default: 1995 dev_err(adev->dev, 1996 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 1997 amdgpu_ip_version(adev, OSSSYS_HWIP, 0)); 1998 return -EINVAL; 1999 } 2000 return 0; 2001 } 2002 2003 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 2004 { 2005 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 2006 case IP_VERSION(9, 0, 0): 2007 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 2008 break; 2009 case IP_VERSION(10, 0, 0): 2010 case IP_VERSION(10, 0, 1): 2011 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 2012 break; 2013 case IP_VERSION(11, 0, 0): 2014 case IP_VERSION(11, 0, 2): 2015 case IP_VERSION(11, 0, 4): 2016 case IP_VERSION(11, 0, 5): 2017 case IP_VERSION(11, 0, 9): 2018 case IP_VERSION(11, 0, 7): 2019 case IP_VERSION(11, 0, 11): 2020 case IP_VERSION(11, 0, 12): 2021 case IP_VERSION(11, 0, 13): 2022 case IP_VERSION(11, 5, 0): 2023 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 2024 break; 2025 case IP_VERSION(11, 0, 8): 2026 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 2027 break; 2028 case IP_VERSION(11, 0, 3): 2029 case IP_VERSION(12, 0, 1): 2030 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 2031 break; 2032 case IP_VERSION(13, 0, 0): 2033 case IP_VERSION(13, 0, 1): 2034 case IP_VERSION(13, 0, 2): 2035 case IP_VERSION(13, 0, 3): 2036 case IP_VERSION(13, 0, 5): 2037 case IP_VERSION(13, 0, 6): 2038 case IP_VERSION(13, 0, 7): 2039 case IP_VERSION(13, 0, 8): 2040 case IP_VERSION(13, 0, 10): 2041 case IP_VERSION(13, 0, 11): 2042 case IP_VERSION(13, 0, 12): 2043 case IP_VERSION(13, 0, 14): 2044 case IP_VERSION(14, 0, 0): 2045 case IP_VERSION(14, 0, 1): 2046 case IP_VERSION(14, 0, 4): 2047 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 2048 break; 2049 case IP_VERSION(13, 0, 4): 2050 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block); 2051 break; 2052 case IP_VERSION(14, 0, 2): 2053 case IP_VERSION(14, 0, 3): 2054 case IP_VERSION(14, 0, 5): 2055 amdgpu_device_ip_block_add(adev, &psp_v14_0_ip_block); 2056 break; 2057 default: 2058 dev_err(adev->dev, 2059 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 2060 amdgpu_ip_version(adev, MP0_HWIP, 0)); 2061 return -EINVAL; 2062 } 2063 return 0; 2064 } 2065 2066 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 2067 { 2068 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2069 case IP_VERSION(9, 0, 0): 2070 case IP_VERSION(10, 0, 0): 2071 case IP_VERSION(10, 0, 1): 2072 case IP_VERSION(11, 0, 2): 2073 if (adev->asic_type == CHIP_ARCTURUS) 2074 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2075 else 2076 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 2077 break; 2078 case IP_VERSION(11, 0, 0): 2079 case IP_VERSION(11, 0, 5): 2080 case IP_VERSION(11, 0, 9): 2081 case IP_VERSION(11, 0, 7): 2082 case IP_VERSION(11, 0, 8): 2083 case IP_VERSION(11, 0, 11): 2084 case IP_VERSION(11, 0, 12): 2085 case IP_VERSION(11, 0, 13): 2086 case IP_VERSION(11, 5, 0): 2087 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2088 break; 2089 case IP_VERSION(12, 0, 0): 2090 case IP_VERSION(12, 0, 1): 2091 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 2092 break; 2093 case IP_VERSION(13, 0, 0): 2094 case IP_VERSION(13, 0, 1): 2095 case IP_VERSION(13, 0, 2): 2096 case IP_VERSION(13, 0, 3): 2097 case IP_VERSION(13, 0, 4): 2098 case IP_VERSION(13, 0, 5): 2099 case IP_VERSION(13, 0, 6): 2100 case IP_VERSION(13, 0, 7): 2101 case IP_VERSION(13, 0, 8): 2102 case IP_VERSION(13, 0, 10): 2103 case IP_VERSION(13, 0, 11): 2104 case IP_VERSION(13, 0, 14): 2105 case IP_VERSION(13, 0, 12): 2106 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 2107 break; 2108 case IP_VERSION(14, 0, 0): 2109 case IP_VERSION(14, 0, 1): 2110 case IP_VERSION(14, 0, 2): 2111 case IP_VERSION(14, 0, 3): 2112 case IP_VERSION(14, 0, 4): 2113 case IP_VERSION(14, 0, 5): 2114 amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block); 2115 break; 2116 default: 2117 dev_err(adev->dev, 2118 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 2119 amdgpu_ip_version(adev, MP1_HWIP, 0)); 2120 return -EINVAL; 2121 } 2122 return 0; 2123 } 2124 2125 #if defined(CONFIG_DRM_AMD_DC) 2126 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev) 2127 { 2128 amdgpu_device_set_sriov_virtual_display(adev); 2129 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2130 } 2131 #endif 2132 2133 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 2134 { 2135 if (adev->enable_virtual_display) { 2136 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2137 return 0; 2138 } 2139 2140 if (!amdgpu_device_has_dc_support(adev)) 2141 return 0; 2142 2143 #if defined(CONFIG_DRM_AMD_DC) 2144 if (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2145 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2146 case IP_VERSION(1, 0, 0): 2147 case IP_VERSION(1, 0, 1): 2148 case IP_VERSION(2, 0, 2): 2149 case IP_VERSION(2, 0, 0): 2150 case IP_VERSION(2, 0, 3): 2151 case IP_VERSION(2, 1, 0): 2152 case IP_VERSION(3, 0, 0): 2153 case IP_VERSION(3, 0, 2): 2154 case IP_VERSION(3, 0, 3): 2155 case IP_VERSION(3, 0, 1): 2156 case IP_VERSION(3, 1, 2): 2157 case IP_VERSION(3, 1, 3): 2158 case IP_VERSION(3, 1, 4): 2159 case IP_VERSION(3, 1, 5): 2160 case IP_VERSION(3, 1, 6): 2161 case IP_VERSION(3, 2, 0): 2162 case IP_VERSION(3, 2, 1): 2163 case IP_VERSION(3, 5, 0): 2164 case IP_VERSION(3, 5, 1): 2165 case IP_VERSION(4, 1, 0): 2166 /* TODO: Fix IP version. DC code expects version 4.0.1 */ 2167 if (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(4, 1, 0)) 2168 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(4, 0, 1); 2169 2170 if (amdgpu_sriov_vf(adev)) 2171 amdgpu_discovery_set_sriov_display(adev); 2172 else 2173 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2174 break; 2175 default: 2176 dev_err(adev->dev, 2177 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 2178 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2179 return -EINVAL; 2180 } 2181 } else if (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2182 switch (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2183 case IP_VERSION(12, 0, 0): 2184 case IP_VERSION(12, 0, 1): 2185 case IP_VERSION(12, 1, 0): 2186 if (amdgpu_sriov_vf(adev)) 2187 amdgpu_discovery_set_sriov_display(adev); 2188 else 2189 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2190 break; 2191 default: 2192 dev_err(adev->dev, 2193 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 2194 amdgpu_ip_version(adev, DCI_HWIP, 0)); 2195 return -EINVAL; 2196 } 2197 } 2198 #endif 2199 return 0; 2200 } 2201 2202 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 2203 { 2204 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2205 case IP_VERSION(9, 0, 1): 2206 case IP_VERSION(9, 1, 0): 2207 case IP_VERSION(9, 2, 1): 2208 case IP_VERSION(9, 2, 2): 2209 case IP_VERSION(9, 3, 0): 2210 case IP_VERSION(9, 4, 0): 2211 case IP_VERSION(9, 4, 1): 2212 case IP_VERSION(9, 4, 2): 2213 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 2214 break; 2215 case IP_VERSION(9, 4, 3): 2216 case IP_VERSION(9, 4, 4): 2217 case IP_VERSION(9, 5, 0): 2218 amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block); 2219 break; 2220 case IP_VERSION(10, 1, 10): 2221 case IP_VERSION(10, 1, 2): 2222 case IP_VERSION(10, 1, 1): 2223 case IP_VERSION(10, 1, 3): 2224 case IP_VERSION(10, 1, 4): 2225 case IP_VERSION(10, 3, 0): 2226 case IP_VERSION(10, 3, 2): 2227 case IP_VERSION(10, 3, 1): 2228 case IP_VERSION(10, 3, 4): 2229 case IP_VERSION(10, 3, 5): 2230 case IP_VERSION(10, 3, 6): 2231 case IP_VERSION(10, 3, 3): 2232 case IP_VERSION(10, 3, 7): 2233 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 2234 break; 2235 case IP_VERSION(11, 0, 0): 2236 case IP_VERSION(11, 0, 1): 2237 case IP_VERSION(11, 0, 2): 2238 case IP_VERSION(11, 0, 3): 2239 case IP_VERSION(11, 0, 4): 2240 case IP_VERSION(11, 5, 0): 2241 case IP_VERSION(11, 5, 1): 2242 case IP_VERSION(11, 5, 2): 2243 case IP_VERSION(11, 5, 3): 2244 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); 2245 break; 2246 case IP_VERSION(12, 0, 0): 2247 case IP_VERSION(12, 0, 1): 2248 amdgpu_device_ip_block_add(adev, &gfx_v12_0_ip_block); 2249 break; 2250 default: 2251 dev_err(adev->dev, "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 2252 amdgpu_ip_version(adev, GC_HWIP, 0)); 2253 return -EINVAL; 2254 } 2255 return 0; 2256 } 2257 2258 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 2259 { 2260 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 2261 case IP_VERSION(4, 0, 0): 2262 case IP_VERSION(4, 0, 1): 2263 case IP_VERSION(4, 1, 0): 2264 case IP_VERSION(4, 1, 1): 2265 case IP_VERSION(4, 1, 2): 2266 case IP_VERSION(4, 2, 0): 2267 case IP_VERSION(4, 2, 2): 2268 case IP_VERSION(4, 4, 0): 2269 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 2270 break; 2271 case IP_VERSION(4, 4, 2): 2272 case IP_VERSION(4, 4, 5): 2273 case IP_VERSION(4, 4, 4): 2274 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block); 2275 break; 2276 case IP_VERSION(5, 0, 0): 2277 case IP_VERSION(5, 0, 1): 2278 case IP_VERSION(5, 0, 2): 2279 case IP_VERSION(5, 0, 5): 2280 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 2281 break; 2282 case IP_VERSION(5, 2, 0): 2283 case IP_VERSION(5, 2, 2): 2284 case IP_VERSION(5, 2, 4): 2285 case IP_VERSION(5, 2, 5): 2286 case IP_VERSION(5, 2, 6): 2287 case IP_VERSION(5, 2, 3): 2288 case IP_VERSION(5, 2, 1): 2289 case IP_VERSION(5, 2, 7): 2290 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 2291 break; 2292 case IP_VERSION(6, 0, 0): 2293 case IP_VERSION(6, 0, 1): 2294 case IP_VERSION(6, 0, 2): 2295 case IP_VERSION(6, 0, 3): 2296 case IP_VERSION(6, 1, 0): 2297 case IP_VERSION(6, 1, 1): 2298 case IP_VERSION(6, 1, 2): 2299 case IP_VERSION(6, 1, 3): 2300 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block); 2301 break; 2302 case IP_VERSION(7, 0, 0): 2303 case IP_VERSION(7, 0, 1): 2304 amdgpu_device_ip_block_add(adev, &sdma_v7_0_ip_block); 2305 break; 2306 default: 2307 dev_err(adev->dev, 2308 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 2309 amdgpu_ip_version(adev, SDMA0_HWIP, 0)); 2310 return -EINVAL; 2311 } 2312 return 0; 2313 } 2314 2315 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 2316 { 2317 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2318 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2319 case IP_VERSION(7, 0, 0): 2320 case IP_VERSION(7, 2, 0): 2321 /* UVD is not supported on vega20 SR-IOV */ 2322 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2323 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 2324 break; 2325 default: 2326 dev_err(adev->dev, 2327 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 2328 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2329 return -EINVAL; 2330 } 2331 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2332 case IP_VERSION(4, 0, 0): 2333 case IP_VERSION(4, 1, 0): 2334 /* VCE is not supported on vega20 SR-IOV */ 2335 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2336 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 2337 break; 2338 default: 2339 dev_err(adev->dev, 2340 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 2341 amdgpu_ip_version(adev, VCE_HWIP, 0)); 2342 return -EINVAL; 2343 } 2344 } else { 2345 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2346 case IP_VERSION(1, 0, 0): 2347 case IP_VERSION(1, 0, 1): 2348 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 2349 break; 2350 case IP_VERSION(2, 0, 0): 2351 case IP_VERSION(2, 0, 2): 2352 case IP_VERSION(2, 2, 0): 2353 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 2354 if (!amdgpu_sriov_vf(adev)) 2355 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 2356 break; 2357 case IP_VERSION(2, 0, 3): 2358 break; 2359 case IP_VERSION(2, 5, 0): 2360 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 2361 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 2362 break; 2363 case IP_VERSION(2, 6, 0): 2364 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 2365 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 2366 break; 2367 case IP_VERSION(3, 0, 0): 2368 case IP_VERSION(3, 0, 16): 2369 case IP_VERSION(3, 1, 1): 2370 case IP_VERSION(3, 1, 2): 2371 case IP_VERSION(3, 0, 2): 2372 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2373 if (!amdgpu_sriov_vf(adev)) 2374 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 2375 break; 2376 case IP_VERSION(3, 0, 33): 2377 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2378 break; 2379 case IP_VERSION(4, 0, 0): 2380 case IP_VERSION(4, 0, 2): 2381 case IP_VERSION(4, 0, 4): 2382 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block); 2383 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block); 2384 break; 2385 case IP_VERSION(4, 0, 3): 2386 amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block); 2387 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block); 2388 break; 2389 case IP_VERSION(4, 0, 5): 2390 case IP_VERSION(4, 0, 6): 2391 amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block); 2392 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block); 2393 break; 2394 case IP_VERSION(5, 0, 0): 2395 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block); 2396 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block); 2397 break; 2398 case IP_VERSION(5, 0, 1): 2399 amdgpu_device_ip_block_add(adev, &vcn_v5_0_1_ip_block); 2400 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_1_ip_block); 2401 break; 2402 default: 2403 dev_err(adev->dev, 2404 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 2405 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2406 return -EINVAL; 2407 } 2408 } 2409 return 0; 2410 } 2411 2412 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 2413 { 2414 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2415 case IP_VERSION(11, 0, 0): 2416 case IP_VERSION(11, 0, 1): 2417 case IP_VERSION(11, 0, 2): 2418 case IP_VERSION(11, 0, 3): 2419 case IP_VERSION(11, 0, 4): 2420 case IP_VERSION(11, 5, 0): 2421 case IP_VERSION(11, 5, 1): 2422 case IP_VERSION(11, 5, 2): 2423 case IP_VERSION(11, 5, 3): 2424 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block); 2425 adev->enable_mes = true; 2426 adev->enable_mes_kiq = true; 2427 break; 2428 case IP_VERSION(12, 0, 0): 2429 case IP_VERSION(12, 0, 1): 2430 amdgpu_device_ip_block_add(adev, &mes_v12_0_ip_block); 2431 adev->enable_mes = true; 2432 adev->enable_mes_kiq = true; 2433 if (amdgpu_uni_mes) 2434 adev->enable_uni_mes = true; 2435 break; 2436 default: 2437 break; 2438 } 2439 return 0; 2440 } 2441 2442 static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev) 2443 { 2444 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2445 case IP_VERSION(9, 4, 3): 2446 case IP_VERSION(9, 4, 4): 2447 case IP_VERSION(9, 5, 0): 2448 aqua_vanjaram_init_soc_config(adev); 2449 break; 2450 default: 2451 break; 2452 } 2453 } 2454 2455 static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev) 2456 { 2457 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) { 2458 case IP_VERSION(6, 1, 0): 2459 case IP_VERSION(6, 1, 1): 2460 case IP_VERSION(6, 1, 3): 2461 amdgpu_device_ip_block_add(adev, &vpe_v6_1_ip_block); 2462 break; 2463 default: 2464 break; 2465 } 2466 2467 return 0; 2468 } 2469 2470 static int amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device *adev) 2471 { 2472 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) { 2473 case IP_VERSION(4, 0, 5): 2474 case IP_VERSION(4, 0, 6): 2475 if (amdgpu_umsch_mm & 0x1) { 2476 amdgpu_device_ip_block_add(adev, &umsch_mm_v4_0_ip_block); 2477 adev->enable_umsch_mm = true; 2478 } 2479 break; 2480 default: 2481 break; 2482 } 2483 2484 return 0; 2485 } 2486 2487 static int amdgpu_discovery_set_isp_ip_blocks(struct amdgpu_device *adev) 2488 { 2489 #if defined(CONFIG_DRM_AMD_ISP) 2490 switch (amdgpu_ip_version(adev, ISP_HWIP, 0)) { 2491 case IP_VERSION(4, 1, 0): 2492 amdgpu_device_ip_block_add(adev, &isp_v4_1_0_ip_block); 2493 break; 2494 case IP_VERSION(4, 1, 1): 2495 amdgpu_device_ip_block_add(adev, &isp_v4_1_1_ip_block); 2496 break; 2497 default: 2498 break; 2499 } 2500 #endif 2501 2502 return 0; 2503 } 2504 2505 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 2506 { 2507 int r; 2508 2509 switch (adev->asic_type) { 2510 case CHIP_VEGA10: 2511 vega10_reg_base_init(adev); 2512 adev->sdma.num_instances = 2; 2513 adev->gmc.num_umc = 4; 2514 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2515 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2516 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 2517 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 2518 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 2519 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 2520 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2521 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 2522 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 2523 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2524 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2525 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2526 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 2527 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 2528 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2529 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2530 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 2531 break; 2532 case CHIP_VEGA12: 2533 vega10_reg_base_init(adev); 2534 adev->sdma.num_instances = 2; 2535 adev->gmc.num_umc = 4; 2536 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2537 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2538 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 2539 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 2540 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 2541 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 2542 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 2543 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 2544 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 2545 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2546 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2547 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2548 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 2549 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 2550 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2551 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2552 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 2553 break; 2554 case CHIP_RAVEN: 2555 vega10_reg_base_init(adev); 2556 adev->sdma.num_instances = 1; 2557 adev->vcn.num_vcn_inst = 1; 2558 adev->gmc.num_umc = 2; 2559 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 2560 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2561 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2562 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 2563 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 2564 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 2565 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 2566 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 2567 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 2568 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 2569 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 2570 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 2571 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 2572 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 2573 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 2574 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 2575 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 2576 } else { 2577 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2578 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2579 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 2580 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 2581 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 2582 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2583 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 2584 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 2585 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 2586 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 2587 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 2588 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 2589 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 2590 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 2591 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 2592 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 2593 } 2594 break; 2595 case CHIP_VEGA20: 2596 vega20_reg_base_init(adev); 2597 adev->sdma.num_instances = 2; 2598 adev->gmc.num_umc = 8; 2599 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2600 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2601 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 2602 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 2603 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 2604 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 2605 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 2606 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 2607 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 2608 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 2609 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2610 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 2611 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 2612 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 2613 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 2614 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 2615 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 2616 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 2617 break; 2618 case CHIP_ARCTURUS: 2619 arct_reg_base_init(adev); 2620 adev->sdma.num_instances = 8; 2621 adev->vcn.num_vcn_inst = 2; 2622 adev->gmc.num_umc = 8; 2623 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2624 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2625 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 2626 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 2627 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 2628 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 2629 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 2630 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 2631 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 2632 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 2633 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 2634 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 2635 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 2636 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 2637 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 2638 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 2639 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2640 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 2641 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 2642 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 2643 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 2644 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 2645 break; 2646 case CHIP_ALDEBARAN: 2647 aldebaran_reg_base_init(adev); 2648 adev->sdma.num_instances = 5; 2649 adev->vcn.num_vcn_inst = 2; 2650 adev->gmc.num_umc = 4; 2651 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2652 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2653 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 2654 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 2655 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 2656 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 2657 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 2658 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 2659 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 2660 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 2661 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 2662 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 2663 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 2664 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 2665 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 2666 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 2667 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 2668 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 2669 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 2670 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 2671 break; 2672 default: 2673 r = amdgpu_discovery_reg_base_init(adev); 2674 if (r) 2675 return -EINVAL; 2676 2677 amdgpu_discovery_harvest_ip(adev); 2678 amdgpu_discovery_get_gfx_info(adev); 2679 amdgpu_discovery_get_mall_info(adev); 2680 amdgpu_discovery_get_vcn_info(adev); 2681 break; 2682 } 2683 2684 amdgpu_discovery_init_soc_config(adev); 2685 amdgpu_discovery_sysfs_init(adev); 2686 2687 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2688 case IP_VERSION(9, 0, 1): 2689 case IP_VERSION(9, 2, 1): 2690 case IP_VERSION(9, 4, 0): 2691 case IP_VERSION(9, 4, 1): 2692 case IP_VERSION(9, 4, 2): 2693 case IP_VERSION(9, 4, 3): 2694 case IP_VERSION(9, 4, 4): 2695 case IP_VERSION(9, 5, 0): 2696 adev->family = AMDGPU_FAMILY_AI; 2697 break; 2698 case IP_VERSION(9, 1, 0): 2699 case IP_VERSION(9, 2, 2): 2700 case IP_VERSION(9, 3, 0): 2701 adev->family = AMDGPU_FAMILY_RV; 2702 break; 2703 case IP_VERSION(10, 1, 10): 2704 case IP_VERSION(10, 1, 1): 2705 case IP_VERSION(10, 1, 2): 2706 case IP_VERSION(10, 1, 3): 2707 case IP_VERSION(10, 1, 4): 2708 case IP_VERSION(10, 3, 0): 2709 case IP_VERSION(10, 3, 2): 2710 case IP_VERSION(10, 3, 4): 2711 case IP_VERSION(10, 3, 5): 2712 adev->family = AMDGPU_FAMILY_NV; 2713 break; 2714 case IP_VERSION(10, 3, 1): 2715 adev->family = AMDGPU_FAMILY_VGH; 2716 adev->apu_flags |= AMD_APU_IS_VANGOGH; 2717 break; 2718 case IP_VERSION(10, 3, 3): 2719 adev->family = AMDGPU_FAMILY_YC; 2720 break; 2721 case IP_VERSION(10, 3, 6): 2722 adev->family = AMDGPU_FAMILY_GC_10_3_6; 2723 break; 2724 case IP_VERSION(10, 3, 7): 2725 adev->family = AMDGPU_FAMILY_GC_10_3_7; 2726 break; 2727 case IP_VERSION(11, 0, 0): 2728 case IP_VERSION(11, 0, 2): 2729 case IP_VERSION(11, 0, 3): 2730 adev->family = AMDGPU_FAMILY_GC_11_0_0; 2731 break; 2732 case IP_VERSION(11, 0, 1): 2733 case IP_VERSION(11, 0, 4): 2734 adev->family = AMDGPU_FAMILY_GC_11_0_1; 2735 break; 2736 case IP_VERSION(11, 5, 0): 2737 case IP_VERSION(11, 5, 1): 2738 case IP_VERSION(11, 5, 2): 2739 case IP_VERSION(11, 5, 3): 2740 adev->family = AMDGPU_FAMILY_GC_11_5_0; 2741 break; 2742 case IP_VERSION(12, 0, 0): 2743 case IP_VERSION(12, 0, 1): 2744 adev->family = AMDGPU_FAMILY_GC_12_0_0; 2745 break; 2746 default: 2747 return -EINVAL; 2748 } 2749 2750 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2751 case IP_VERSION(9, 1, 0): 2752 case IP_VERSION(9, 2, 2): 2753 case IP_VERSION(9, 3, 0): 2754 case IP_VERSION(10, 1, 3): 2755 case IP_VERSION(10, 1, 4): 2756 case IP_VERSION(10, 3, 1): 2757 case IP_VERSION(10, 3, 3): 2758 case IP_VERSION(10, 3, 6): 2759 case IP_VERSION(10, 3, 7): 2760 case IP_VERSION(11, 0, 1): 2761 case IP_VERSION(11, 0, 4): 2762 case IP_VERSION(11, 5, 0): 2763 case IP_VERSION(11, 5, 1): 2764 case IP_VERSION(11, 5, 2): 2765 case IP_VERSION(11, 5, 3): 2766 adev->flags |= AMD_IS_APU; 2767 break; 2768 default: 2769 break; 2770 } 2771 2772 if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(4, 8, 0)) 2773 adev->gmc.xgmi.supported = true; 2774 2775 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2776 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) 2777 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 4, 0); 2778 2779 /* set NBIO version */ 2780 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 2781 case IP_VERSION(6, 1, 0): 2782 case IP_VERSION(6, 2, 0): 2783 adev->nbio.funcs = &nbio_v6_1_funcs; 2784 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 2785 break; 2786 case IP_VERSION(7, 0, 0): 2787 case IP_VERSION(7, 0, 1): 2788 case IP_VERSION(2, 5, 0): 2789 adev->nbio.funcs = &nbio_v7_0_funcs; 2790 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 2791 break; 2792 case IP_VERSION(7, 4, 0): 2793 case IP_VERSION(7, 4, 1): 2794 case IP_VERSION(7, 4, 4): 2795 adev->nbio.funcs = &nbio_v7_4_funcs; 2796 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 2797 break; 2798 case IP_VERSION(7, 9, 0): 2799 case IP_VERSION(7, 9, 1): 2800 adev->nbio.funcs = &nbio_v7_9_funcs; 2801 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg; 2802 break; 2803 case IP_VERSION(7, 11, 0): 2804 case IP_VERSION(7, 11, 1): 2805 case IP_VERSION(7, 11, 2): 2806 case IP_VERSION(7, 11, 3): 2807 adev->nbio.funcs = &nbio_v7_11_funcs; 2808 adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg; 2809 break; 2810 case IP_VERSION(7, 2, 0): 2811 case IP_VERSION(7, 2, 1): 2812 case IP_VERSION(7, 3, 0): 2813 case IP_VERSION(7, 5, 0): 2814 case IP_VERSION(7, 5, 1): 2815 adev->nbio.funcs = &nbio_v7_2_funcs; 2816 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 2817 break; 2818 case IP_VERSION(2, 1, 1): 2819 case IP_VERSION(2, 3, 0): 2820 case IP_VERSION(2, 3, 1): 2821 case IP_VERSION(2, 3, 2): 2822 case IP_VERSION(3, 3, 0): 2823 case IP_VERSION(3, 3, 1): 2824 case IP_VERSION(3, 3, 2): 2825 case IP_VERSION(3, 3, 3): 2826 adev->nbio.funcs = &nbio_v2_3_funcs; 2827 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 2828 break; 2829 case IP_VERSION(4, 3, 0): 2830 case IP_VERSION(4, 3, 1): 2831 if (amdgpu_sriov_vf(adev)) 2832 adev->nbio.funcs = &nbio_v4_3_sriov_funcs; 2833 else 2834 adev->nbio.funcs = &nbio_v4_3_funcs; 2835 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg; 2836 break; 2837 case IP_VERSION(7, 7, 0): 2838 case IP_VERSION(7, 7, 1): 2839 adev->nbio.funcs = &nbio_v7_7_funcs; 2840 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg; 2841 break; 2842 case IP_VERSION(6, 3, 1): 2843 adev->nbio.funcs = &nbif_v6_3_1_funcs; 2844 adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg; 2845 break; 2846 default: 2847 break; 2848 } 2849 2850 switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) { 2851 case IP_VERSION(4, 0, 0): 2852 case IP_VERSION(4, 0, 1): 2853 case IP_VERSION(4, 1, 0): 2854 case IP_VERSION(4, 1, 1): 2855 case IP_VERSION(4, 1, 2): 2856 case IP_VERSION(4, 2, 0): 2857 case IP_VERSION(4, 2, 1): 2858 case IP_VERSION(4, 4, 0): 2859 case IP_VERSION(4, 4, 2): 2860 case IP_VERSION(4, 4, 5): 2861 adev->hdp.funcs = &hdp_v4_0_funcs; 2862 break; 2863 case IP_VERSION(5, 0, 0): 2864 case IP_VERSION(5, 0, 1): 2865 case IP_VERSION(5, 0, 2): 2866 case IP_VERSION(5, 0, 3): 2867 case IP_VERSION(5, 0, 4): 2868 case IP_VERSION(5, 2, 0): 2869 adev->hdp.funcs = &hdp_v5_0_funcs; 2870 break; 2871 case IP_VERSION(5, 2, 1): 2872 adev->hdp.funcs = &hdp_v5_2_funcs; 2873 break; 2874 case IP_VERSION(6, 0, 0): 2875 case IP_VERSION(6, 0, 1): 2876 case IP_VERSION(6, 1, 0): 2877 adev->hdp.funcs = &hdp_v6_0_funcs; 2878 break; 2879 case IP_VERSION(7, 0, 0): 2880 adev->hdp.funcs = &hdp_v7_0_funcs; 2881 break; 2882 default: 2883 break; 2884 } 2885 2886 switch (amdgpu_ip_version(adev, DF_HWIP, 0)) { 2887 case IP_VERSION(3, 6, 0): 2888 case IP_VERSION(3, 6, 1): 2889 case IP_VERSION(3, 6, 2): 2890 adev->df.funcs = &df_v3_6_funcs; 2891 break; 2892 case IP_VERSION(2, 1, 0): 2893 case IP_VERSION(2, 1, 1): 2894 case IP_VERSION(2, 5, 0): 2895 case IP_VERSION(3, 5, 1): 2896 case IP_VERSION(3, 5, 2): 2897 adev->df.funcs = &df_v1_7_funcs; 2898 break; 2899 case IP_VERSION(4, 3, 0): 2900 adev->df.funcs = &df_v4_3_funcs; 2901 break; 2902 case IP_VERSION(4, 6, 2): 2903 adev->df.funcs = &df_v4_6_2_funcs; 2904 break; 2905 case IP_VERSION(4, 15, 0): 2906 case IP_VERSION(4, 15, 1): 2907 adev->df.funcs = &df_v4_15_funcs; 2908 break; 2909 default: 2910 break; 2911 } 2912 2913 switch (amdgpu_ip_version(adev, SMUIO_HWIP, 0)) { 2914 case IP_VERSION(9, 0, 0): 2915 case IP_VERSION(9, 0, 1): 2916 case IP_VERSION(10, 0, 0): 2917 case IP_VERSION(10, 0, 1): 2918 case IP_VERSION(10, 0, 2): 2919 adev->smuio.funcs = &smuio_v9_0_funcs; 2920 break; 2921 case IP_VERSION(11, 0, 0): 2922 case IP_VERSION(11, 0, 2): 2923 case IP_VERSION(11, 0, 3): 2924 case IP_VERSION(11, 0, 4): 2925 case IP_VERSION(11, 0, 7): 2926 case IP_VERSION(11, 0, 8): 2927 adev->smuio.funcs = &smuio_v11_0_funcs; 2928 break; 2929 case IP_VERSION(11, 0, 6): 2930 case IP_VERSION(11, 0, 10): 2931 case IP_VERSION(11, 0, 11): 2932 case IP_VERSION(11, 5, 0): 2933 case IP_VERSION(13, 0, 1): 2934 case IP_VERSION(13, 0, 9): 2935 case IP_VERSION(13, 0, 10): 2936 adev->smuio.funcs = &smuio_v11_0_6_funcs; 2937 break; 2938 case IP_VERSION(13, 0, 2): 2939 adev->smuio.funcs = &smuio_v13_0_funcs; 2940 break; 2941 case IP_VERSION(13, 0, 3): 2942 case IP_VERSION(13, 0, 11): 2943 adev->smuio.funcs = &smuio_v13_0_3_funcs; 2944 if (adev->smuio.funcs->get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) { 2945 adev->flags |= AMD_IS_APU; 2946 } 2947 break; 2948 case IP_VERSION(13, 0, 6): 2949 case IP_VERSION(13, 0, 8): 2950 case IP_VERSION(14, 0, 0): 2951 case IP_VERSION(14, 0, 1): 2952 adev->smuio.funcs = &smuio_v13_0_6_funcs; 2953 break; 2954 case IP_VERSION(14, 0, 2): 2955 adev->smuio.funcs = &smuio_v14_0_2_funcs; 2956 break; 2957 default: 2958 break; 2959 } 2960 2961 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { 2962 case IP_VERSION(6, 0, 0): 2963 case IP_VERSION(6, 0, 1): 2964 case IP_VERSION(6, 0, 2): 2965 case IP_VERSION(6, 0, 3): 2966 adev->lsdma.funcs = &lsdma_v6_0_funcs; 2967 break; 2968 case IP_VERSION(7, 0, 0): 2969 case IP_VERSION(7, 0, 1): 2970 adev->lsdma.funcs = &lsdma_v7_0_funcs; 2971 break; 2972 default: 2973 break; 2974 } 2975 2976 r = amdgpu_discovery_set_common_ip_blocks(adev); 2977 if (r) 2978 return r; 2979 2980 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 2981 if (r) 2982 return r; 2983 2984 /* For SR-IOV, PSP needs to be initialized before IH */ 2985 if (amdgpu_sriov_vf(adev)) { 2986 r = amdgpu_discovery_set_psp_ip_blocks(adev); 2987 if (r) 2988 return r; 2989 r = amdgpu_discovery_set_ih_ip_blocks(adev); 2990 if (r) 2991 return r; 2992 } else { 2993 r = amdgpu_discovery_set_ih_ip_blocks(adev); 2994 if (r) 2995 return r; 2996 2997 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2998 r = amdgpu_discovery_set_psp_ip_blocks(adev); 2999 if (r) 3000 return r; 3001 } 3002 } 3003 3004 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3005 r = amdgpu_discovery_set_smu_ip_blocks(adev); 3006 if (r) 3007 return r; 3008 } 3009 3010 r = amdgpu_discovery_set_display_ip_blocks(adev); 3011 if (r) 3012 return r; 3013 3014 r = amdgpu_discovery_set_gc_ip_blocks(adev); 3015 if (r) 3016 return r; 3017 3018 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 3019 if (r) 3020 return r; 3021 3022 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 3023 !amdgpu_sriov_vf(adev)) || 3024 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { 3025 r = amdgpu_discovery_set_smu_ip_blocks(adev); 3026 if (r) 3027 return r; 3028 } 3029 3030 r = amdgpu_discovery_set_mm_ip_blocks(adev); 3031 if (r) 3032 return r; 3033 3034 r = amdgpu_discovery_set_mes_ip_blocks(adev); 3035 if (r) 3036 return r; 3037 3038 r = amdgpu_discovery_set_vpe_ip_blocks(adev); 3039 if (r) 3040 return r; 3041 3042 r = amdgpu_discovery_set_umsch_mm_ip_blocks(adev); 3043 if (r) 3044 return r; 3045 3046 r = amdgpu_discovery_set_isp_ip_blocks(adev); 3047 if (r) 3048 return r; 3049 return 0; 3050 } 3051 3052