1 /* 2 * Copyright 2018-2024 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_discovery.h" 28 #include "soc15_hw_ip.h" 29 #include "discovery.h" 30 #include "amdgpu_ras.h" 31 32 #include "soc15.h" 33 #include "gfx_v9_0.h" 34 #include "gfx_v9_4_3.h" 35 #include "gmc_v9_0.h" 36 #include "df_v1_7.h" 37 #include "df_v3_6.h" 38 #include "df_v4_3.h" 39 #include "df_v4_6_2.h" 40 #include "df_v4_15.h" 41 #include "nbio_v6_1.h" 42 #include "nbio_v7_0.h" 43 #include "nbio_v7_4.h" 44 #include "nbio_v7_9.h" 45 #include "nbio_v7_11.h" 46 #include "hdp_v4_0.h" 47 #include "vega10_ih.h" 48 #include "vega20_ih.h" 49 #include "sdma_v4_0.h" 50 #include "sdma_v4_4_2.h" 51 #include "uvd_v7_0.h" 52 #include "vce_v4_0.h" 53 #include "vcn_v1_0.h" 54 #include "vcn_v2_5.h" 55 #include "jpeg_v2_5.h" 56 #include "smuio_v9_0.h" 57 #include "gmc_v10_0.h" 58 #include "gmc_v11_0.h" 59 #include "gmc_v12_0.h" 60 #include "gfxhub_v2_0.h" 61 #include "mmhub_v2_0.h" 62 #include "nbio_v2_3.h" 63 #include "nbio_v4_3.h" 64 #include "nbio_v7_2.h" 65 #include "nbio_v7_7.h" 66 #include "nbif_v6_3_1.h" 67 #include "hdp_v5_0.h" 68 #include "hdp_v5_2.h" 69 #include "hdp_v6_0.h" 70 #include "hdp_v7_0.h" 71 #include "nv.h" 72 #include "soc21.h" 73 #include "soc24.h" 74 #include "soc_v1_0.h" 75 #include "navi10_ih.h" 76 #include "ih_v6_0.h" 77 #include "ih_v6_1.h" 78 #include "ih_v7_0.h" 79 #include "gfx_v10_0.h" 80 #include "gfx_v11_0.h" 81 #include "gfx_v12_0.h" 82 #include "gfx_v12_1.h" 83 #include "sdma_v5_0.h" 84 #include "sdma_v5_2.h" 85 #include "sdma_v6_0.h" 86 #include "sdma_v7_0.h" 87 #include "sdma_v7_1.h" 88 #include "lsdma_v6_0.h" 89 #include "lsdma_v7_0.h" 90 #include "lsdma_v7_1.h" 91 #include "vcn_v2_0.h" 92 #include "jpeg_v2_0.h" 93 #include "vcn_v3_0.h" 94 #include "jpeg_v3_0.h" 95 #include "vcn_v4_0.h" 96 #include "jpeg_v4_0.h" 97 #include "vcn_v4_0_3.h" 98 #include "jpeg_v4_0_3.h" 99 #include "vcn_v4_0_5.h" 100 #include "jpeg_v4_0_5.h" 101 #include "amdgpu_vkms.h" 102 #include "mes_v11_0.h" 103 #include "mes_v12_0.h" 104 #include "mes_v12_1.h" 105 #include "smuio_v11_0.h" 106 #include "smuio_v11_0_6.h" 107 #include "smuio_v13_0.h" 108 #include "smuio_v13_0_3.h" 109 #include "smuio_v13_0_6.h" 110 #include "smuio_v14_0_2.h" 111 #include "smuio_v15_0_0.h" 112 #include "smuio_v15_0_8.h" 113 #include "vcn_v5_0_0.h" 114 #include "vcn_v5_0_1.h" 115 #include "jpeg_v5_0_0.h" 116 #include "jpeg_v5_0_1.h" 117 #include "jpeg_v5_3_0.h" 118 119 #include "amdgpu_ras_mgr.h" 120 121 #include "amdgpu_vpe.h" 122 #if defined(CONFIG_DRM_AMD_ISP) 123 #include "amdgpu_isp.h" 124 #endif 125 126 MODULE_FIRMWARE("amdgpu/ip_discovery.bin"); 127 MODULE_FIRMWARE("amdgpu/vega10_ip_discovery.bin"); 128 MODULE_FIRMWARE("amdgpu/vega12_ip_discovery.bin"); 129 MODULE_FIRMWARE("amdgpu/vega20_ip_discovery.bin"); 130 MODULE_FIRMWARE("amdgpu/raven_ip_discovery.bin"); 131 MODULE_FIRMWARE("amdgpu/raven2_ip_discovery.bin"); 132 MODULE_FIRMWARE("amdgpu/picasso_ip_discovery.bin"); 133 MODULE_FIRMWARE("amdgpu/arcturus_ip_discovery.bin"); 134 MODULE_FIRMWARE("amdgpu/aldebaran_ip_discovery.bin"); 135 136 /* Note: These registers are consistent across all the SOCs */ 137 #define mmIP_DISCOVERY_VERSION 0x16A00 138 #define mmRCC_CONFIG_MEMSIZE 0xde3 139 #define mmMP0_SMN_C2PMSG_33 0x16061 140 #define mmMM_INDEX 0x0 141 #define mmMM_INDEX_HI 0x6 142 #define mmMM_DATA 0x1 143 144 #define mmDRIVER_SCRATCH_0 0x94 145 #define mmDRIVER_SCRATCH_1 0x95 146 #define mmDRIVER_SCRATCH_2 0x96 147 148 static const char *hw_id_names[HW_ID_MAX] = { 149 [MP1_HWID] = "MP1", 150 [MP2_HWID] = "MP2", 151 [THM_HWID] = "THM", 152 [SMUIO_HWID] = "SMUIO", 153 [FUSE_HWID] = "FUSE", 154 [CLKA_HWID] = "CLKA", 155 [PWR_HWID] = "PWR", 156 [GC_HWID] = "GC", 157 [UVD_HWID] = "UVD", 158 [AUDIO_AZ_HWID] = "AUDIO_AZ", 159 [ACP_HWID] = "ACP", 160 [DCI_HWID] = "DCI", 161 [DMU_HWID] = "DMU", 162 [DCO_HWID] = "DCO", 163 [DIO_HWID] = "DIO", 164 [XDMA_HWID] = "XDMA", 165 [DCEAZ_HWID] = "DCEAZ", 166 [DAZ_HWID] = "DAZ", 167 [SDPMUX_HWID] = "SDPMUX", 168 [NTB_HWID] = "NTB", 169 [IOHC_HWID] = "IOHC", 170 [L2IMU_HWID] = "L2IMU", 171 [VCE_HWID] = "VCE", 172 [MMHUB_HWID] = "MMHUB", 173 [ATHUB_HWID] = "ATHUB", 174 [DBGU_NBIO_HWID] = "DBGU_NBIO", 175 [DFX_HWID] = "DFX", 176 [DBGU0_HWID] = "DBGU0", 177 [DBGU1_HWID] = "DBGU1", 178 [OSSSYS_HWID] = "OSSSYS", 179 [HDP_HWID] = "HDP", 180 [SDMA0_HWID] = "SDMA0", 181 [SDMA1_HWID] = "SDMA1", 182 [SDMA2_HWID] = "SDMA2", 183 [SDMA3_HWID] = "SDMA3", 184 [LSDMA_HWID] = "LSDMA", 185 [ISP_HWID] = "ISP", 186 [DBGU_IO_HWID] = "DBGU_IO", 187 [DF_HWID] = "DF", 188 [CLKB_HWID] = "CLKB", 189 [FCH_HWID] = "FCH", 190 [DFX_DAP_HWID] = "DFX_DAP", 191 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 192 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 193 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 194 [L1IMU3_HWID] = "L1IMU3", 195 [L1IMU4_HWID] = "L1IMU4", 196 [L1IMU5_HWID] = "L1IMU5", 197 [L1IMU6_HWID] = "L1IMU6", 198 [L1IMU7_HWID] = "L1IMU7", 199 [L1IMU8_HWID] = "L1IMU8", 200 [L1IMU9_HWID] = "L1IMU9", 201 [L1IMU10_HWID] = "L1IMU10", 202 [L1IMU11_HWID] = "L1IMU11", 203 [L1IMU12_HWID] = "L1IMU12", 204 [L1IMU13_HWID] = "L1IMU13", 205 [L1IMU14_HWID] = "L1IMU14", 206 [L1IMU15_HWID] = "L1IMU15", 207 [WAFLC_HWID] = "WAFLC", 208 [FCH_USB_PD_HWID] = "FCH_USB_PD", 209 [PCIE_HWID] = "PCIE", 210 [PCS_HWID] = "PCS", 211 [DDCL_HWID] = "DDCL", 212 [SST_HWID] = "SST", 213 [IOAGR_HWID] = "IOAGR", 214 [NBIF_HWID] = "NBIF", 215 [IOAPIC_HWID] = "IOAPIC", 216 [SYSTEMHUB_HWID] = "SYSTEMHUB", 217 [NTBCCP_HWID] = "NTBCCP", 218 [UMC_HWID] = "UMC", 219 [SATA_HWID] = "SATA", 220 [USB_HWID] = "USB", 221 [CCXSEC_HWID] = "CCXSEC", 222 [XGMI_HWID] = "XGMI", 223 [XGBE_HWID] = "XGBE", 224 [MP0_HWID] = "MP0", 225 [VPE_HWID] = "VPE", 226 [ATU_HWID] = "ATU", 227 [AIGC_HWID] = "AIGC", 228 }; 229 230 static int hw_id_map[MAX_HWIP] = { 231 [GC_HWIP] = GC_HWID, 232 [HDP_HWIP] = HDP_HWID, 233 [SDMA0_HWIP] = SDMA0_HWID, 234 [SDMA1_HWIP] = SDMA1_HWID, 235 [SDMA2_HWIP] = SDMA2_HWID, 236 [SDMA3_HWIP] = SDMA3_HWID, 237 [LSDMA_HWIP] = LSDMA_HWID, 238 [MMHUB_HWIP] = MMHUB_HWID, 239 [ATHUB_HWIP] = ATHUB_HWID, 240 [NBIO_HWIP] = NBIF_HWID, 241 [MP0_HWIP] = MP0_HWID, 242 [MP1_HWIP] = MP1_HWID, 243 [UVD_HWIP] = UVD_HWID, 244 [VCE_HWIP] = VCE_HWID, 245 [DF_HWIP] = DF_HWID, 246 [DCE_HWIP] = DMU_HWID, 247 [OSSSYS_HWIP] = OSSSYS_HWID, 248 [SMUIO_HWIP] = SMUIO_HWID, 249 [PWR_HWIP] = PWR_HWID, 250 [NBIF_HWIP] = NBIF_HWID, 251 [THM_HWIP] = THM_HWID, 252 [CLK_HWIP] = CLKA_HWID, 253 [UMC_HWIP] = UMC_HWID, 254 [XGMI_HWIP] = XGMI_HWID, 255 [DCI_HWIP] = DCI_HWID, 256 [PCIE_HWIP] = PCIE_HWID, 257 [VPE_HWIP] = VPE_HWID, 258 [ISP_HWIP] = ISP_HWID, 259 [ATU_HWIP] = ATU_HWID, 260 }; 261 262 static int amdgpu_discovery_get_tmr_info(struct amdgpu_device *adev, 263 bool *is_tmr_in_sysmem) 264 { 265 u64 vram_size, tmr_offset, tmr_size; 266 u32 msg, tmr_offset_lo, tmr_offset_hi; 267 int i, ret; 268 269 if (!amdgpu_sriov_vf(adev)) { 270 /* It can take up to two second for IFWI init to complete on some dGPUs, 271 * but generally it should be in the 60-100ms range. Normally this starts 272 * as soon as the device gets power so by the time the OS loads this has long 273 * completed. However, when a card is hotplugged via e.g., USB4, we need to 274 * wait for this to complete. Once the C2PMSG is updated, we can 275 * continue. 276 */ 277 278 for (i = 0; i < 2000; i++) { 279 msg = RREG32(mmMP0_SMN_C2PMSG_33); 280 if (msg & 0x80000000) 281 break; 282 msleep(1); 283 } 284 } 285 286 vram_size = RREG32(mmRCC_CONFIG_MEMSIZE); 287 if (vram_size == U32_MAX) 288 return -ENXIO; 289 else if (!vram_size) 290 *is_tmr_in_sysmem = true; 291 else 292 *is_tmr_in_sysmem = false; 293 294 /* init the default tmr size and offset */ 295 adev->discovery.size = DISCOVERY_TMR_SIZE; 296 if (vram_size) 297 adev->discovery.offset = (vram_size << 20) - DISCOVERY_TMR_OFFSET; 298 299 if (amdgpu_sriov_vf(adev)) { 300 if (adev->virt.is_dynamic_crit_regn_enabled) { 301 adev->discovery.offset = 302 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].offset; 303 adev->discovery.size = 304 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].size_kb << 10; 305 if (!adev->discovery.offset || !adev->discovery.size) 306 return -EINVAL; 307 } else { 308 goto out; 309 } 310 } else { 311 tmr_size = RREG32(mmDRIVER_SCRATCH_2); 312 if (tmr_size) { 313 /* It's preferred to transition to PSP mailbox reg interface 314 * for both bare-metal and passthrough if available */ 315 adev->discovery.size = (u32)tmr_size; 316 tmr_offset_lo = RREG32(mmDRIVER_SCRATCH_0); 317 tmr_offset_hi = RREG32(mmDRIVER_SCRATCH_1); 318 adev->discovery.offset = ((u64)le32_to_cpu(tmr_offset_hi) << 32 | 319 le32_to_cpu(tmr_offset_lo)); 320 } else if (!vram_size) { 321 /* fall back to apci approach to query tmr offset if vram_size is 0 */ 322 ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size); 323 if (ret) 324 return ret; 325 adev->discovery.size = (u32)tmr_size; 326 adev->discovery.offset = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET; 327 } 328 } 329 out: 330 adev->discovery.bin = kzalloc(adev->discovery.size, GFP_KERNEL); 331 if (!adev->discovery.bin) 332 return -ENOMEM; 333 adev->discovery.debugfs_blob.data = adev->discovery.bin; 334 adev->discovery.debugfs_blob.size = adev->discovery.size; 335 336 return 0; 337 } 338 339 static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary) 340 { 341 void *discv_regn; 342 343 /* This region is read-only and reserved from system use */ 344 discv_regn = memremap(adev->discovery.offset, adev->discovery.size, MEMREMAP_WC); 345 if (discv_regn) { 346 memcpy(binary, discv_regn, adev->discovery.size); 347 memunmap(discv_regn); 348 return 0; 349 } 350 351 return -ENOENT; 352 } 353 354 #define IP_DISCOVERY_V2 2 355 #define IP_DISCOVERY_V4 4 356 357 static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, 358 uint8_t *binary, 359 bool is_tmr_in_sysmem) 360 { 361 int ret = 0; 362 363 if (!is_tmr_in_sysmem) { 364 if (amdgpu_sriov_vf(adev) && 365 amdgpu_sriov_xgmi_connected_to_cpu(adev)) { 366 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); 367 } else { 368 amdgpu_device_vram_access(adev, adev->discovery.offset, 369 (uint32_t *)binary, 370 adev->discovery.size, false); 371 adev->discovery.reserve_tmr = true; 372 } 373 } else { 374 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); 375 } 376 377 return ret; 378 } 379 380 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, 381 uint8_t *binary, 382 const char *fw_name) 383 { 384 const struct firmware *fw; 385 int r; 386 387 r = firmware_request_nowarn(&fw, fw_name, adev->dev); 388 if (r) { 389 if (amdgpu_discovery == 2) 390 dev_err(adev->dev, "can't load firmware \"%s\"\n", fw_name); 391 else 392 drm_info(&adev->ddev, "Optional firmware \"%s\" was not found\n", fw_name); 393 return r; 394 } 395 396 memcpy((u8 *)binary, (u8 *)fw->data, fw->size); 397 release_firmware(fw); 398 399 return 0; 400 } 401 402 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 403 { 404 uint16_t checksum = 0; 405 int i; 406 407 for (i = 0; i < size; i++) 408 checksum += data[i]; 409 410 return checksum; 411 } 412 413 static inline bool amdgpu_discovery_verify_checksum(struct amdgpu_device *adev, 414 uint8_t *data, uint32_t size, 415 uint16_t expected) 416 { 417 uint16_t calculated; 418 419 calculated = amdgpu_discovery_calculate_checksum(data, size); 420 421 if (calculated != expected) { 422 dev_err(adev->dev, "Discovery checksum failed: calc 0x%04x != exp 0x%04x, size %u.\n", 423 calculated, expected, size); 424 return false; 425 } 426 427 return true; 428 } 429 430 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 431 { 432 struct binary_header *bhdr; 433 bhdr = (struct binary_header *)binary; 434 435 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 436 } 437 438 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) 439 { 440 /* 441 * So far, apply this quirk only on those Navy Flounder boards which 442 * have a bad harvest table of VCN config. 443 */ 444 if ((amdgpu_ip_version(adev, UVD_HWIP, 1) == IP_VERSION(3, 0, 1)) && 445 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 2))) { 446 switch (adev->pdev->revision) { 447 case 0xC1: 448 case 0xC2: 449 case 0xC3: 450 case 0xC5: 451 case 0xC7: 452 case 0xCF: 453 case 0xDF: 454 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 455 adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1; 456 break; 457 default: 458 break; 459 } 460 } 461 } 462 463 static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev, 464 struct table_info *info) 465 { 466 uint8_t *discovery_bin = adev->discovery.bin; 467 uint16_t checksum; 468 uint16_t offset; 469 470 offset = le16_to_cpu(info->offset); 471 checksum = le16_to_cpu(info->checksum); 472 473 struct nps_info_header *nhdr = 474 (struct nps_info_header *)(discovery_bin + offset); 475 476 if (le32_to_cpu(nhdr->table_id) != NPS_INFO_TABLE_ID) { 477 dev_dbg(adev->dev, "invalid ip discovery nps info table id\n"); 478 return -EINVAL; 479 } 480 481 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, 482 le32_to_cpu(nhdr->size_bytes), 483 checksum)) { 484 dev_dbg(adev->dev, "invalid nps info data table checksum\n"); 485 return -EINVAL; 486 } 487 488 return 0; 489 } 490 491 static const char *amdgpu_discovery_get_fw_name(struct amdgpu_device *adev) 492 { 493 if (amdgpu_discovery == 2) { 494 /* Assume there is valid discovery TMR in VRAM even if binary is sideloaded */ 495 adev->discovery.reserve_tmr = true; 496 return "amdgpu/ip_discovery.bin"; 497 } 498 499 switch (adev->asic_type) { 500 case CHIP_VEGA10: 501 return "amdgpu/vega10_ip_discovery.bin"; 502 case CHIP_VEGA12: 503 return "amdgpu/vega12_ip_discovery.bin"; 504 case CHIP_RAVEN: 505 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 506 return "amdgpu/raven2_ip_discovery.bin"; 507 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 508 return "amdgpu/picasso_ip_discovery.bin"; 509 else 510 return "amdgpu/raven_ip_discovery.bin"; 511 case CHIP_VEGA20: 512 return "amdgpu/vega20_ip_discovery.bin"; 513 case CHIP_ARCTURUS: 514 return "amdgpu/arcturus_ip_discovery.bin"; 515 case CHIP_ALDEBARAN: 516 return "amdgpu/aldebaran_ip_discovery.bin"; 517 default: 518 return NULL; 519 } 520 } 521 522 static int amdgpu_discovery_get_table_info(struct amdgpu_device *adev, 523 struct table_info **info, 524 uint16_t table_id) 525 { 526 struct binary_header *bhdr = 527 (struct binary_header *)adev->discovery.bin; 528 struct binary_header_v2 *bhdrv2; 529 530 switch (bhdr->version_major) { 531 case 2: 532 bhdrv2 = (struct binary_header_v2 *)adev->discovery.bin; 533 *info = &bhdrv2->table_list[table_id]; 534 break; 535 case 1: 536 *info = &bhdr->table_list[table_id]; 537 break; 538 default: 539 dev_err(adev->dev, "Invalid ip discovery table version\n"); 540 return -EINVAL; 541 } 542 543 return 0; 544 } 545 546 static int amdgpu_discovery_table_check(struct amdgpu_device *adev, 547 uint8_t *discovery_bin, 548 uint16_t table_id) 549 { 550 int r, act_val, exp_val, table_size; 551 uint16_t offset, checksum; 552 struct table_info *info; 553 bool check_table = true; 554 char *table_name; 555 556 r = amdgpu_discovery_get_table_info(adev, &info, table_id); 557 if (r) 558 return r; 559 offset = le16_to_cpu(info->offset); 560 checksum = le16_to_cpu(info->checksum); 561 562 switch (table_id) { 563 case IP_DISCOVERY: { 564 struct ip_discovery_header *ihdr = 565 (struct ip_discovery_header *)(discovery_bin + offset); 566 act_val = le32_to_cpu(ihdr->signature); 567 exp_val = DISCOVERY_TABLE_SIGNATURE; 568 table_size = le16_to_cpu(ihdr->size); 569 table_name = "data table"; 570 break; 571 } 572 case GC: { 573 struct gpu_info_header *ghdr = 574 (struct gpu_info_header *)(discovery_bin + offset); 575 act_val = le32_to_cpu(ghdr->table_id); 576 exp_val = GC_TABLE_ID; 577 table_size = le16_to_cpu(ghdr->size); 578 table_name = "gc table"; 579 break; 580 } 581 case HARVEST_INFO: { 582 struct harvest_info_header *hhdr = 583 (struct harvest_info_header *)(discovery_bin + offset); 584 act_val = le32_to_cpu(hhdr->signature); 585 exp_val = HARVEST_TABLE_SIGNATURE; 586 table_size = sizeof(struct harvest_table); 587 table_name = "harvest table"; 588 break; 589 } 590 case VCN_INFO: { 591 struct vcn_info_header *vhdr = 592 (struct vcn_info_header *)(discovery_bin + offset); 593 act_val = le32_to_cpu(vhdr->table_id); 594 exp_val = VCN_INFO_TABLE_ID; 595 table_size = le32_to_cpu(vhdr->size_bytes); 596 table_name = "vcn table"; 597 break; 598 } 599 case MALL_INFO: { 600 struct mall_info_header *mhdr = 601 (struct mall_info_header *)(discovery_bin + offset); 602 act_val = le32_to_cpu(mhdr->table_id); 603 exp_val = MALL_INFO_TABLE_ID; 604 table_size = le32_to_cpu(mhdr->size_bytes); 605 table_name = "mall table"; 606 check_table = false; 607 break; 608 } 609 default: 610 dev_err(adev->dev, "invalid ip discovery table id %d specified\n", table_id); 611 check_table = false; 612 break; 613 } 614 615 if (check_table && offset) { 616 if (act_val != exp_val) { 617 dev_err(adev->dev, "invalid ip discovery %s signature\n", table_name); 618 return -EINVAL; 619 } 620 621 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, 622 table_size, checksum)) { 623 dev_err(adev->dev, "invalid ip discovery %s checksum\n", table_name); 624 return -EINVAL; 625 } 626 } 627 628 return 0; 629 } 630 631 static int amdgpu_discovery_init(struct amdgpu_device *adev) 632 { 633 struct binary_header *bhdr; 634 uint8_t *discovery_bin; 635 const char *fw_name; 636 uint16_t offset; 637 uint16_t size; 638 uint16_t checksum; 639 uint16_t table_id; 640 bool is_tmr_in_sysmem; 641 int r; 642 643 r = amdgpu_discovery_get_tmr_info(adev, &is_tmr_in_sysmem); 644 if (r) 645 return r; 646 647 discovery_bin = adev->discovery.bin; 648 /* Read from file if it is the preferred option */ 649 fw_name = amdgpu_discovery_get_fw_name(adev); 650 if (fw_name != NULL) { 651 drm_dbg(&adev->ddev, "use ip discovery information from file"); 652 r = amdgpu_discovery_read_binary_from_file(adev, discovery_bin, 653 fw_name); 654 if (r) 655 goto out; 656 } else { 657 drm_dbg(&adev->ddev, "use ip discovery information from memory"); 658 r = amdgpu_discovery_read_binary_from_mem(adev, discovery_bin, 659 is_tmr_in_sysmem); 660 if (r) 661 goto out; 662 } 663 664 /* check the ip discovery binary signature */ 665 if (!amdgpu_discovery_verify_binary_signature(discovery_bin)) { 666 dev_err(adev->dev, 667 "get invalid ip discovery binary signature\n"); 668 r = -EINVAL; 669 goto out; 670 } 671 672 bhdr = (struct binary_header *)discovery_bin; 673 674 offset = offsetof(struct binary_header, binary_checksum) + 675 sizeof(bhdr->binary_checksum); 676 size = le16_to_cpu(bhdr->binary_size) - offset; 677 checksum = le16_to_cpu(bhdr->binary_checksum); 678 679 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, size, 680 checksum)) { 681 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 682 r = -EINVAL; 683 goto out; 684 } 685 686 for (table_id = 0; table_id <= MALL_INFO; table_id++) { 687 r = amdgpu_discovery_table_check(adev, discovery_bin, table_id); 688 if (r) 689 goto out; 690 } 691 692 return 0; 693 694 out: 695 kfree(adev->discovery.bin); 696 adev->discovery.bin = NULL; 697 if ((amdgpu_discovery != 2) && 698 (RREG32(mmIP_DISCOVERY_VERSION) == 4)) 699 amdgpu_ras_query_boot_status(adev, 4); 700 return r; 701 } 702 703 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev); 704 705 void amdgpu_discovery_fini(struct amdgpu_device *adev) 706 { 707 amdgpu_discovery_sysfs_fini(adev); 708 kfree(adev->discovery.bin); 709 adev->discovery.bin = NULL; 710 } 711 712 static int amdgpu_discovery_validate_ip(struct amdgpu_device *adev, 713 uint8_t instance, uint16_t hw_id) 714 { 715 if (instance >= HWIP_MAX_INSTANCE) { 716 dev_err(adev->dev, 717 "Unexpected instance_number (%d) from ip discovery blob\n", 718 instance); 719 return -EINVAL; 720 } 721 if (hw_id >= HW_ID_MAX) { 722 dev_err(adev->dev, 723 "Unexpected hw_id (%d) from ip discovery blob\n", 724 hw_id); 725 return -EINVAL; 726 } 727 728 return 0; 729 } 730 731 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev, 732 uint32_t *vcn_harvest_count) 733 { 734 uint8_t *discovery_bin = adev->discovery.bin; 735 struct binary_header *bhdr; 736 struct ip_discovery_header *ihdr; 737 struct die_header *dhdr; 738 struct ip *ip; 739 uint16_t die_offset, ip_offset, num_dies, num_ips; 740 uint16_t hw_id; 741 uint8_t inst; 742 int i, j; 743 744 bhdr = (struct binary_header *)discovery_bin; 745 ihdr = (struct ip_discovery_header 746 *)(discovery_bin + 747 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 748 num_dies = le16_to_cpu(ihdr->num_dies); 749 750 /* scan harvest bit of all IP data structures */ 751 for (i = 0; i < num_dies; i++) { 752 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 753 dhdr = (struct die_header *)(discovery_bin + die_offset); 754 num_ips = le16_to_cpu(dhdr->num_ips); 755 ip_offset = die_offset + sizeof(*dhdr); 756 757 for (j = 0; j < num_ips; j++) { 758 ip = (struct ip *)(discovery_bin + ip_offset); 759 inst = ip->number_instance; 760 hw_id = le16_to_cpu(ip->hw_id); 761 if (amdgpu_discovery_validate_ip(adev, inst, hw_id)) 762 goto next_ip; 763 764 if (ip->harvest == 1) { 765 switch (hw_id) { 766 case VCN_HWID: 767 (*vcn_harvest_count)++; 768 if (inst == 0) { 769 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 770 adev->vcn.inst_mask &= 771 ~AMDGPU_VCN_HARVEST_VCN0; 772 adev->jpeg.inst_mask &= 773 ~AMDGPU_VCN_HARVEST_VCN0; 774 } else { 775 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 776 adev->vcn.inst_mask &= 777 ~AMDGPU_VCN_HARVEST_VCN1; 778 adev->jpeg.inst_mask &= 779 ~AMDGPU_VCN_HARVEST_VCN1; 780 } 781 break; 782 case DMU_HWID: 783 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 784 break; 785 default: 786 break; 787 } 788 } 789 next_ip: 790 ip_offset += struct_size(ip, base_address, 791 ip->num_base_address); 792 } 793 } 794 } 795 796 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, 797 uint32_t *vcn_harvest_count, 798 uint32_t *umc_harvest_count) 799 { 800 uint8_t *discovery_bin = adev->discovery.bin; 801 struct table_info *info; 802 struct harvest_table *harvest_info; 803 u16 offset; 804 int i; 805 u64 umc_harvest_config = 0; 806 807 if (amdgpu_discovery_get_table_info(adev, &info, HARVEST_INFO)) 808 return; 809 offset = le16_to_cpu(info->offset); 810 811 if (!offset) { 812 dev_err(adev->dev, "invalid harvest table offset\n"); 813 return; 814 } 815 816 harvest_info = (struct harvest_table *)(discovery_bin + offset); 817 818 for (i = 0; i < 32; i++) { 819 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) 820 break; 821 822 switch (le16_to_cpu(harvest_info->list[i].hw_id)) { 823 case VCN_HWID: 824 (*vcn_harvest_count)++; 825 adev->vcn.harvest_config |= 826 (1 << harvest_info->list[i].number_instance); 827 adev->jpeg.harvest_config |= 828 (1 << harvest_info->list[i].number_instance); 829 830 adev->vcn.inst_mask &= 831 ~(1U << harvest_info->list[i].number_instance); 832 adev->jpeg.inst_mask &= 833 ~(1U << harvest_info->list[i].number_instance); 834 break; 835 case DMU_HWID: 836 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 837 break; 838 case UMC_HWID: 839 umc_harvest_config |= 840 1 << (le16_to_cpu(harvest_info->list[i].number_instance)); 841 (*umc_harvest_count)++; 842 break; 843 case GC_HWID: 844 adev->gfx.xcc_mask &= 845 ~(1U << harvest_info->list[i].number_instance); 846 break; 847 case SDMA0_HWID: 848 adev->sdma.sdma_mask &= 849 ~(1U << harvest_info->list[i].number_instance); 850 break; 851 #if defined(CONFIG_DRM_AMD_ISP) 852 case ISP_HWID: 853 adev->isp.harvest_config |= 854 ~(1U << harvest_info->list[i].number_instance); 855 break; 856 #endif 857 default: 858 break; 859 } 860 } 861 862 adev->umc.active_mask = ((1ULL << adev->umc.node_inst_num) - 1ULL) & 863 ~umc_harvest_config; 864 } 865 866 /* ================================================== */ 867 868 struct ip_hw_instance { 869 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */ 870 871 int hw_id; 872 u8 num_instance; 873 u8 major, minor, revision; 874 u8 harvest; 875 876 int num_base_addresses; 877 u32 base_addr[] __counted_by(num_base_addresses); 878 }; 879 880 struct ip_hw_id { 881 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */ 882 int hw_id; 883 }; 884 885 struct ip_die_entry { 886 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */ 887 u16 num_ips; 888 }; 889 890 /* -------------------------------------------------- */ 891 892 struct ip_hw_instance_attr { 893 struct attribute attr; 894 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf); 895 }; 896 897 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf) 898 { 899 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id); 900 } 901 902 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf) 903 { 904 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance); 905 } 906 907 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf) 908 { 909 return sysfs_emit(buf, "%d\n", ip_hw_instance->major); 910 } 911 912 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf) 913 { 914 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor); 915 } 916 917 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf) 918 { 919 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision); 920 } 921 922 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf) 923 { 924 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest); 925 } 926 927 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf) 928 { 929 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses); 930 } 931 932 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) 933 { 934 ssize_t at; 935 int ii; 936 937 for (at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 938 /* Here we satisfy the condition that, at + size <= PAGE_SIZE. 939 */ 940 if (at + 12 > PAGE_SIZE) 941 break; 942 at += sysfs_emit_at(buf, at, "0x%08X\n", 943 ip_hw_instance->base_addr[ii]); 944 } 945 946 return at; 947 } 948 949 static struct ip_hw_instance_attr ip_hw_attr[] = { 950 __ATTR_RO(hw_id), 951 __ATTR_RO(num_instance), 952 __ATTR_RO(major), 953 __ATTR_RO(minor), 954 __ATTR_RO(revision), 955 __ATTR_RO(harvest), 956 __ATTR_RO(num_base_addresses), 957 __ATTR_RO(base_addr), 958 }; 959 960 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; 961 ATTRIBUTE_GROUPS(ip_hw_instance); 962 963 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) 964 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) 965 966 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj, 967 struct attribute *attr, 968 char *buf) 969 { 970 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 971 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr); 972 973 if (!ip_hw_attr->show) 974 return -EIO; 975 976 return ip_hw_attr->show(ip_hw_instance, buf); 977 } 978 979 static const struct sysfs_ops ip_hw_instance_sysfs_ops = { 980 .show = ip_hw_instance_attr_show, 981 }; 982 983 static void ip_hw_instance_release(struct kobject *kobj) 984 { 985 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 986 987 kfree(ip_hw_instance); 988 } 989 990 static const struct kobj_type ip_hw_instance_ktype = { 991 .release = ip_hw_instance_release, 992 .sysfs_ops = &ip_hw_instance_sysfs_ops, 993 .default_groups = ip_hw_instance_groups, 994 }; 995 996 /* -------------------------------------------------- */ 997 998 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset) 999 1000 static void ip_hw_id_release(struct kobject *kobj) 1001 { 1002 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj); 1003 1004 if (!list_empty(&ip_hw_id->hw_id_kset.list)) 1005 DRM_ERROR("ip_hw_id->hw_id_kset is not empty"); 1006 kfree(ip_hw_id); 1007 } 1008 1009 static const struct kobj_type ip_hw_id_ktype = { 1010 .release = ip_hw_id_release, 1011 .sysfs_ops = &kobj_sysfs_ops, 1012 }; 1013 1014 /* -------------------------------------------------- */ 1015 1016 static void die_kobj_release(struct kobject *kobj); 1017 static void ip_disc_release(struct kobject *kobj); 1018 1019 struct ip_die_entry_attribute { 1020 struct attribute attr; 1021 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf); 1022 }; 1023 1024 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr) 1025 1026 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf) 1027 { 1028 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips); 1029 } 1030 1031 /* If there are more ip_die_entry attrs, other than the number of IPs, 1032 * we can make this intro an array of attrs, and then initialize 1033 * ip_die_entry_attrs in a loop. 1034 */ 1035 static struct ip_die_entry_attribute num_ips_attr = 1036 __ATTR_RO(num_ips); 1037 1038 static struct attribute *ip_die_entry_attrs[] = { 1039 &num_ips_attr.attr, 1040 NULL, 1041 }; 1042 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ 1043 1044 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) 1045 1046 static ssize_t ip_die_entry_attr_show(struct kobject *kobj, 1047 struct attribute *attr, 1048 char *buf) 1049 { 1050 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr); 1051 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 1052 1053 if (!ip_die_entry_attr->show) 1054 return -EIO; 1055 1056 return ip_die_entry_attr->show(ip_die_entry, buf); 1057 } 1058 1059 static void ip_die_entry_release(struct kobject *kobj) 1060 { 1061 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 1062 1063 if (!list_empty(&ip_die_entry->ip_kset.list)) 1064 DRM_ERROR("ip_die_entry->ip_kset is not empty"); 1065 kfree(ip_die_entry); 1066 } 1067 1068 static const struct sysfs_ops ip_die_entry_sysfs_ops = { 1069 .show = ip_die_entry_attr_show, 1070 }; 1071 1072 static const struct kobj_type ip_die_entry_ktype = { 1073 .release = ip_die_entry_release, 1074 .sysfs_ops = &ip_die_entry_sysfs_ops, 1075 .default_groups = ip_die_entry_groups, 1076 }; 1077 1078 static const struct kobj_type die_kobj_ktype = { 1079 .release = die_kobj_release, 1080 .sysfs_ops = &kobj_sysfs_ops, 1081 }; 1082 1083 static const struct kobj_type ip_discovery_ktype = { 1084 .release = ip_disc_release, 1085 .sysfs_ops = &kobj_sysfs_ops, 1086 }; 1087 1088 struct ip_discovery_top { 1089 struct kobject kobj; /* ip_discovery/ */ 1090 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */ 1091 struct amdgpu_device *adev; 1092 }; 1093 1094 static void die_kobj_release(struct kobject *kobj) 1095 { 1096 struct ip_discovery_top *ip_top = container_of(to_kset(kobj), 1097 struct ip_discovery_top, 1098 die_kset); 1099 if (!list_empty(&ip_top->die_kset.list)) 1100 DRM_ERROR("ip_top->die_kset is not empty"); 1101 } 1102 1103 static void ip_disc_release(struct kobject *kobj) 1104 { 1105 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top, 1106 kobj); 1107 struct amdgpu_device *adev = ip_top->adev; 1108 1109 kfree(ip_top); 1110 adev->discovery.ip_top = NULL; 1111 } 1112 1113 static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev, 1114 uint16_t hw_id, uint8_t inst) 1115 { 1116 uint8_t harvest = 0; 1117 1118 /* Until a uniform way is figured, get mask based on hwid */ 1119 switch (hw_id) { 1120 case VCN_HWID: 1121 /* VCN vs UVD+VCE */ 1122 if (!amdgpu_ip_version(adev, VCE_HWIP, 0)) 1123 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0; 1124 break; 1125 case DMU_HWID: 1126 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK) 1127 harvest = 0x1; 1128 break; 1129 case UMC_HWID: 1130 /* TODO: It needs another parsing; for now, ignore.*/ 1131 break; 1132 case GC_HWID: 1133 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; 1134 break; 1135 case SDMA0_HWID: 1136 harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0; 1137 break; 1138 default: 1139 break; 1140 } 1141 1142 return harvest; 1143 } 1144 1145 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, 1146 struct ip_die_entry *ip_die_entry, 1147 const size_t _ip_offset, const int num_ips, 1148 bool reg_base_64) 1149 { 1150 uint8_t *discovery_bin = adev->discovery.bin; 1151 int ii, jj, kk, res; 1152 uint16_t hw_id; 1153 uint8_t inst; 1154 1155 DRM_DEBUG("num_ips:%d", num_ips); 1156 1157 /* Find all IPs of a given HW ID, and add their instance to 1158 * #die/#hw_id/#instance/<attributes> 1159 */ 1160 for (ii = 0; ii < HW_ID_MAX; ii++) { 1161 struct ip_hw_id *ip_hw_id = NULL; 1162 size_t ip_offset = _ip_offset; 1163 1164 for (jj = 0; jj < num_ips; jj++) { 1165 struct ip_v4 *ip; 1166 struct ip_hw_instance *ip_hw_instance; 1167 1168 ip = (struct ip_v4 *)(discovery_bin + ip_offset); 1169 inst = ip->instance_number; 1170 hw_id = le16_to_cpu(ip->hw_id); 1171 if (amdgpu_discovery_validate_ip(adev, inst, hw_id) || 1172 hw_id != ii) 1173 goto next_ip; 1174 1175 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset); 1176 1177 /* We have a hw_id match; register the hw 1178 * block if not yet registered. 1179 */ 1180 if (!ip_hw_id) { 1181 ip_hw_id = kzalloc_obj(*ip_hw_id); 1182 if (!ip_hw_id) 1183 return -ENOMEM; 1184 ip_hw_id->hw_id = ii; 1185 1186 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii); 1187 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset; 1188 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype; 1189 res = kset_register(&ip_hw_id->hw_id_kset); 1190 if (res) { 1191 DRM_ERROR("Couldn't register ip_hw_id kset"); 1192 kfree(ip_hw_id); 1193 return res; 1194 } 1195 if (hw_id_names[ii]) { 1196 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj, 1197 &ip_hw_id->hw_id_kset.kobj, 1198 hw_id_names[ii]); 1199 if (res) { 1200 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n", 1201 hw_id_names[ii], 1202 kobject_name(&ip_die_entry->ip_kset.kobj)); 1203 } 1204 } 1205 } 1206 1207 /* Now register its instance. 1208 */ 1209 ip_hw_instance = kzalloc_flex(*ip_hw_instance, 1210 base_addr, 1211 ip->num_base_address); 1212 if (!ip_hw_instance) { 1213 DRM_ERROR("no memory for ip_hw_instance"); 1214 return -ENOMEM; 1215 } 1216 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */ 1217 ip_hw_instance->num_instance = ip->instance_number; 1218 ip_hw_instance->major = ip->major; 1219 ip_hw_instance->minor = ip->minor; 1220 ip_hw_instance->revision = ip->revision; 1221 ip_hw_instance->harvest = 1222 amdgpu_discovery_get_harvest_info( 1223 adev, ip_hw_instance->hw_id, 1224 ip_hw_instance->num_instance); 1225 ip_hw_instance->num_base_addresses = ip->num_base_address; 1226 1227 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) 1228 ip_hw_instance->base_addr[kk] = ip->base_address[kk]; 1229 1230 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); 1231 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; 1232 res = kobject_add(&ip_hw_instance->kobj, NULL, 1233 "%d", ip_hw_instance->num_instance); 1234 next_ip: 1235 if (reg_base_64) 1236 ip_offset += struct_size(ip, base_address_64, 1237 ip->num_base_address); 1238 else 1239 ip_offset += struct_size(ip, base_address, 1240 ip->num_base_address); 1241 } 1242 } 1243 1244 return 0; 1245 } 1246 1247 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) 1248 { 1249 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1250 uint8_t *discovery_bin = adev->discovery.bin; 1251 struct table_info *info; 1252 struct ip_discovery_header *ihdr; 1253 struct die_header *dhdr; 1254 struct kset *die_kset = &ip_top->die_kset; 1255 u16 num_dies, die_offset, num_ips; 1256 size_t ip_offset; 1257 int ii, res; 1258 1259 res = amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY); 1260 if (res) 1261 return res; 1262 ihdr = (struct ip_discovery_header 1263 *)(discovery_bin + 1264 le16_to_cpu(info->offset)); 1265 num_dies = le16_to_cpu(ihdr->num_dies); 1266 1267 DRM_DEBUG("number of dies: %d\n", num_dies); 1268 1269 for (ii = 0; ii < num_dies; ii++) { 1270 struct ip_die_entry *ip_die_entry; 1271 1272 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); 1273 dhdr = (struct die_header *)(discovery_bin + die_offset); 1274 num_ips = le16_to_cpu(dhdr->num_ips); 1275 ip_offset = die_offset + sizeof(*dhdr); 1276 1277 /* Add the die to the kset. 1278 * 1279 * dhdr->die_id == ii, which was checked in 1280 * amdgpu_discovery_reg_base_init(). 1281 */ 1282 1283 ip_die_entry = kzalloc_obj(*ip_die_entry); 1284 if (!ip_die_entry) 1285 return -ENOMEM; 1286 1287 ip_die_entry->num_ips = num_ips; 1288 1289 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id)); 1290 ip_die_entry->ip_kset.kobj.kset = die_kset; 1291 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype; 1292 res = kset_register(&ip_die_entry->ip_kset); 1293 if (res) { 1294 DRM_ERROR("Couldn't register ip_die_entry kset"); 1295 kfree(ip_die_entry); 1296 return res; 1297 } 1298 1299 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips, !!ihdr->base_addr_64_bit); 1300 } 1301 1302 return 0; 1303 } 1304 1305 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) 1306 { 1307 uint8_t *discovery_bin = adev->discovery.bin; 1308 struct ip_discovery_top *ip_top; 1309 struct kset *die_kset; 1310 int res, ii; 1311 1312 if (!discovery_bin) 1313 return -EINVAL; 1314 1315 ip_top = kzalloc_obj(*ip_top); 1316 if (!ip_top) 1317 return -ENOMEM; 1318 1319 ip_top->adev = adev; 1320 adev->discovery.ip_top = ip_top; 1321 res = kobject_init_and_add(&ip_top->kobj, &ip_discovery_ktype, 1322 &adev->dev->kobj, "ip_discovery"); 1323 if (res) { 1324 DRM_ERROR("Couldn't init and add ip_discovery/"); 1325 goto Err; 1326 } 1327 1328 die_kset = &ip_top->die_kset; 1329 kobject_set_name(&die_kset->kobj, "%s", "die"); 1330 die_kset->kobj.parent = &ip_top->kobj; 1331 die_kset->kobj.ktype = &die_kobj_ktype; 1332 res = kset_register(&ip_top->die_kset); 1333 if (res) { 1334 DRM_ERROR("Couldn't register die_kset"); 1335 goto Err; 1336 } 1337 1338 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++) 1339 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr; 1340 ip_hw_instance_attrs[ii] = NULL; 1341 1342 res = amdgpu_discovery_sysfs_recurse(adev); 1343 1344 return res; 1345 Err: 1346 kobject_put(&ip_top->kobj); 1347 return res; 1348 } 1349 1350 /* -------------------------------------------------- */ 1351 1352 #define list_to_kobj(el) container_of(el, struct kobject, entry) 1353 1354 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id) 1355 { 1356 struct list_head *el, *tmp; 1357 struct kset *hw_id_kset; 1358 1359 hw_id_kset = &ip_hw_id->hw_id_kset; 1360 spin_lock(&hw_id_kset->list_lock); 1361 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) { 1362 list_del_init(el); 1363 spin_unlock(&hw_id_kset->list_lock); 1364 /* kobject is embedded in ip_hw_instance */ 1365 kobject_put(list_to_kobj(el)); 1366 spin_lock(&hw_id_kset->list_lock); 1367 } 1368 spin_unlock(&hw_id_kset->list_lock); 1369 kobject_put(&ip_hw_id->hw_id_kset.kobj); 1370 } 1371 1372 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry) 1373 { 1374 struct list_head *el, *tmp; 1375 struct kset *ip_kset; 1376 1377 ip_kset = &ip_die_entry->ip_kset; 1378 spin_lock(&ip_kset->list_lock); 1379 list_for_each_prev_safe(el, tmp, &ip_kset->list) { 1380 list_del_init(el); 1381 spin_unlock(&ip_kset->list_lock); 1382 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el))); 1383 spin_lock(&ip_kset->list_lock); 1384 } 1385 spin_unlock(&ip_kset->list_lock); 1386 kobject_put(&ip_die_entry->ip_kset.kobj); 1387 } 1388 1389 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) 1390 { 1391 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1392 struct list_head *el, *tmp; 1393 struct kset *die_kset; 1394 1395 die_kset = &ip_top->die_kset; 1396 spin_lock(&die_kset->list_lock); 1397 list_for_each_prev_safe(el, tmp, &die_kset->list) { 1398 list_del_init(el); 1399 spin_unlock(&die_kset->list_lock); 1400 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 1401 spin_lock(&die_kset->list_lock); 1402 } 1403 spin_unlock(&die_kset->list_lock); 1404 kobject_put(&ip_top->die_kset.kobj); 1405 kobject_put(&ip_top->kobj); 1406 } 1407 1408 /* devcoredump support */ 1409 void amdgpu_discovery_dump(struct amdgpu_device *adev, struct drm_printer *p) 1410 { 1411 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1412 struct ip_die_entry *ip_die_entry; 1413 struct list_head *el_die, *el_hw_id, *el_hw_inst; 1414 struct ip_hw_id *hw_id; 1415 struct kset *die_kset; 1416 struct ip_hw_instance *ip_inst; 1417 int i = 0, j; 1418 1419 die_kset = &ip_top->die_kset; 1420 1421 drm_printf(p, "\nHW IP Discovery\n"); 1422 spin_lock(&die_kset->list_lock); 1423 list_for_each(el_die, &die_kset->list) { 1424 drm_printf(p, "die %d\n", i++); 1425 ip_die_entry = to_ip_die_entry(list_to_kobj(el_die)); 1426 1427 list_for_each(el_hw_id, &ip_die_entry->ip_kset.list) { 1428 hw_id = to_ip_hw_id(list_to_kobj(el_hw_id)); 1429 drm_printf(p, "hw_id %d %s\n", hw_id->hw_id, hw_id_names[hw_id->hw_id]); 1430 1431 list_for_each(el_hw_inst, &hw_id->hw_id_kset.list) { 1432 ip_inst = to_ip_hw_instance(list_to_kobj(el_hw_inst)); 1433 drm_printf(p, "\tinstance %d\n", ip_inst->num_instance); 1434 drm_printf(p, "\tmajor %d\n", ip_inst->major); 1435 drm_printf(p, "\tminor %d\n", ip_inst->minor); 1436 drm_printf(p, "\trevision %d\n", ip_inst->revision); 1437 drm_printf(p, "\tharvest 0x%01X\n", ip_inst->harvest); 1438 drm_printf(p, "\tnum_base_addresses %d\n", 1439 ip_inst->num_base_addresses); 1440 for (j = 0; j < ip_inst->num_base_addresses; j++) 1441 drm_printf(p, "\tbase_addr[%d] 0x%08X\n", 1442 j, ip_inst->base_addr[j]); 1443 } 1444 } 1445 } 1446 spin_unlock(&die_kset->list_lock); 1447 } 1448 1449 1450 /* ================================================== */ 1451 1452 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 1453 { 1454 uint8_t num_base_address, subrev, variant; 1455 struct table_info *info; 1456 struct ip_discovery_header *ihdr; 1457 struct die_header *dhdr; 1458 uint8_t *discovery_bin; 1459 struct ip_v4 *ip; 1460 uint16_t die_offset; 1461 uint16_t ip_offset; 1462 uint16_t num_dies; 1463 uint32_t wafl_ver; 1464 uint16_t num_ips; 1465 uint16_t hw_id; 1466 uint8_t inst; 1467 int hw_ip; 1468 int i, j, k; 1469 int r; 1470 1471 r = amdgpu_discovery_init(adev); 1472 if (r) 1473 return r; 1474 discovery_bin = adev->discovery.bin; 1475 wafl_ver = 0; 1476 adev->gfx.xcc_mask = 0; 1477 adev->sdma.sdma_mask = 0; 1478 adev->vcn.inst_mask = 0; 1479 adev->jpeg.inst_mask = 0; 1480 r = amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY); 1481 if (r) 1482 return r; 1483 ihdr = (struct ip_discovery_header 1484 *)(discovery_bin + 1485 le16_to_cpu(info->offset)); 1486 num_dies = le16_to_cpu(ihdr->num_dies); 1487 1488 DRM_DEBUG("number of dies: %d\n", num_dies); 1489 1490 for (i = 0; i < num_dies; i++) { 1491 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1492 dhdr = (struct die_header *)(discovery_bin + die_offset); 1493 num_ips = le16_to_cpu(dhdr->num_ips); 1494 ip_offset = die_offset + sizeof(*dhdr); 1495 1496 if (le16_to_cpu(dhdr->die_id) != i) { 1497 DRM_ERROR("invalid die id %d, expected %d\n", 1498 le16_to_cpu(dhdr->die_id), i); 1499 return -EINVAL; 1500 } 1501 1502 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 1503 le16_to_cpu(dhdr->die_id), num_ips); 1504 1505 for (j = 0; j < num_ips; j++) { 1506 ip = (struct ip_v4 *)(discovery_bin + ip_offset); 1507 1508 inst = ip->instance_number; 1509 hw_id = le16_to_cpu(ip->hw_id); 1510 if (amdgpu_discovery_validate_ip(adev, inst, hw_id)) 1511 goto next_ip; 1512 1513 num_base_address = ip->num_base_address; 1514 1515 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 1516 hw_id_names[le16_to_cpu(ip->hw_id)], 1517 le16_to_cpu(ip->hw_id), 1518 ip->instance_number, 1519 ip->major, ip->minor, 1520 ip->revision); 1521 1522 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 1523 /* Bit [5:0]: original revision value 1524 * Bit [7:6]: en/decode capability: 1525 * 0b00 : VCN function normally 1526 * 0b10 : encode is disabled 1527 * 0b01 : decode is disabled 1528 */ 1529 if (adev->vcn.num_vcn_inst < 1530 AMDGPU_MAX_VCN_INSTANCES) { 1531 adev->vcn.inst[adev->vcn.num_vcn_inst].vcn_config = 1532 ip->revision & 0xc0; 1533 adev->vcn.num_vcn_inst++; 1534 adev->vcn.inst_mask |= 1535 (1U << ip->instance_number); 1536 adev->jpeg.inst_mask |= 1537 (1U << ip->instance_number); 1538 } else { 1539 dev_err(adev->dev, "Too many VCN instances: %d vs %d\n", 1540 adev->vcn.num_vcn_inst + 1, 1541 AMDGPU_MAX_VCN_INSTANCES); 1542 } 1543 ip->revision &= ~0xc0; 1544 } 1545 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 1546 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 1547 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 1548 le16_to_cpu(ip->hw_id) == SDMA3_HWID) { 1549 if (adev->sdma.num_instances < 1550 AMDGPU_MAX_SDMA_INSTANCES) { 1551 adev->sdma.num_instances++; 1552 adev->sdma.sdma_mask |= 1553 (1U << ip->instance_number); 1554 } else { 1555 dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n", 1556 adev->sdma.num_instances + 1, 1557 AMDGPU_MAX_SDMA_INSTANCES); 1558 } 1559 } 1560 1561 if (le16_to_cpu(ip->hw_id) == VPE_HWID) { 1562 if (adev->vpe.num_instances < AMDGPU_MAX_VPE_INSTANCES) 1563 adev->vpe.num_instances++; 1564 else 1565 dev_err(adev->dev, "Too many VPE instances: %d vs %d\n", 1566 adev->vpe.num_instances + 1, 1567 AMDGPU_MAX_VPE_INSTANCES); 1568 } 1569 1570 if (le16_to_cpu(ip->hw_id) == UMC_HWID) { 1571 adev->gmc.num_umc++; 1572 adev->umc.node_inst_num++; 1573 } 1574 1575 if (le16_to_cpu(ip->hw_id) == GC_HWID) 1576 adev->gfx.xcc_mask |= 1577 (1U << ip->instance_number); 1578 1579 if (!wafl_ver && le16_to_cpu(ip->hw_id) == WAFLC_HWID) 1580 wafl_ver = IP_VERSION_FULL(ip->major, ip->minor, 1581 ip->revision, 0, 0); 1582 1583 for (k = 0; k < num_base_address; k++) { 1584 /* 1585 * convert the endianness of base addresses in place, 1586 * so that we don't need to convert them when accessing adev->reg_offset. 1587 */ 1588 if (ihdr->base_addr_64_bit) 1589 /* Truncate the 64bit base address from ip discovery 1590 * and only store lower 32bit ip base in reg_offset[]. 1591 * Bits > 32 follows ASIC specific format, thus just 1592 * discard them and handle it within specific ASIC. 1593 * By this way reg_offset[] and related helpers can 1594 * stay unchanged. 1595 * The base address is in dwords, thus clear the 1596 * highest 2 bits to store. 1597 */ 1598 ip->base_address[k] = 1599 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF; 1600 else 1601 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 1602 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 1603 } 1604 1605 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 1606 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) && 1607 hw_id_map[hw_ip] != 0) { 1608 DRM_DEBUG("set register base offset for %s\n", 1609 hw_id_names[le16_to_cpu(ip->hw_id)]); 1610 adev->reg_offset[hw_ip][ip->instance_number] = 1611 ip->base_address; 1612 /* Instance support is somewhat inconsistent. 1613 * SDMA is a good example. Sienna cichlid has 4 total 1614 * SDMA instances, each enumerated separately (HWIDs 1615 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 1616 * but they are enumerated as multiple instances of the 1617 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 1618 * example. On most chips there are multiple instances 1619 * with the same HWID. 1620 */ 1621 1622 if (ihdr->version < 3) { 1623 subrev = 0; 1624 variant = 0; 1625 } else { 1626 subrev = ip->sub_revision; 1627 variant = ip->variant; 1628 } 1629 1630 adev->ip_versions[hw_ip] 1631 [ip->instance_number] = 1632 IP_VERSION_FULL(ip->major, 1633 ip->minor, 1634 ip->revision, 1635 variant, 1636 subrev); 1637 } 1638 } 1639 1640 next_ip: 1641 if (ihdr->base_addr_64_bit) 1642 ip_offset += struct_size(ip, base_address_64, ip->num_base_address); 1643 else 1644 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1645 } 1646 } 1647 1648 if (wafl_ver && !adev->ip_versions[XGMI_HWIP][0]) 1649 adev->ip_versions[XGMI_HWIP][0] = wafl_ver; 1650 1651 return 0; 1652 } 1653 1654 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 1655 { 1656 uint8_t *discovery_bin = adev->discovery.bin; 1657 struct ip_discovery_header *ihdr; 1658 struct table_info *info; 1659 int vcn_harvest_count = 0; 1660 int umc_harvest_count = 0; 1661 uint16_t ihdr_ver; 1662 1663 if (amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY)) 1664 return; 1665 ihdr = (struct ip_discovery_header *)(discovery_bin + 1666 le16_to_cpu(info->offset)); 1667 ihdr_ver = le16_to_cpu(ihdr->version); 1668 /* 1669 * Harvest table does not fit Navi1x and legacy GPUs, 1670 * so read harvest bit per IP data structure to set 1671 * harvest configuration. 1672 */ 1673 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 2, 0) && 1674 ihdr_ver <= 2) { 1675 if ((adev->pdev->device == 0x731E && 1676 (adev->pdev->revision == 0xC6 || 1677 adev->pdev->revision == 0xC7)) || 1678 (adev->pdev->device == 0x7340 && 1679 adev->pdev->revision == 0xC9) || 1680 (adev->pdev->device == 0x7360 && 1681 adev->pdev->revision == 0xC7)) 1682 amdgpu_discovery_read_harvest_bit_per_ip(adev, 1683 &vcn_harvest_count); 1684 } else { 1685 amdgpu_discovery_read_from_harvest_table(adev, 1686 &vcn_harvest_count, 1687 &umc_harvest_count); 1688 } 1689 1690 amdgpu_discovery_harvest_config_quirk(adev); 1691 1692 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 1693 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 1694 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 1695 } 1696 1697 if (umc_harvest_count < adev->gmc.num_umc) { 1698 adev->gmc.num_umc -= umc_harvest_count; 1699 } 1700 } 1701 1702 union gc_info { 1703 struct gc_info_v1_0 v1; 1704 struct gc_info_v1_1 v1_1; 1705 struct gc_info_v1_2 v1_2; 1706 struct gc_info_v1_3 v1_3; 1707 struct gc_info_v2_0 v2; 1708 struct gc_info_v2_1 v2_1; 1709 }; 1710 1711 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 1712 { 1713 uint8_t *discovery_bin = adev->discovery.bin; 1714 struct table_info *info; 1715 union gc_info *gc_info; 1716 u16 offset; 1717 1718 if (!discovery_bin) { 1719 DRM_ERROR("ip discovery uninitialized\n"); 1720 return -EINVAL; 1721 } 1722 1723 if (amdgpu_discovery_get_table_info(adev, &info, GC)) 1724 return -EINVAL; 1725 offset = le16_to_cpu(info->offset); 1726 1727 if (!offset) 1728 return 0; 1729 1730 gc_info = (union gc_info *)(discovery_bin + offset); 1731 1732 switch (le16_to_cpu(gc_info->v1.header.version_major)) { 1733 case 1: 1734 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); 1735 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 1736 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); 1737 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1738 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); 1739 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); 1740 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); 1741 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); 1742 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); 1743 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); 1744 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); 1745 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); 1746 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); 1747 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); 1748 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); 1749 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / 1750 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1751 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); 1752 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 1) { 1753 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa); 1754 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface); 1755 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps); 1756 } 1757 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 2) { 1758 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg); 1759 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size); 1760 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp); 1761 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc); 1762 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc); 1763 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa); 1764 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance); 1765 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu); 1766 } 1767 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 3) { 1768 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v1_3.gc_tcp_size_per_cu); 1769 adev->gfx.config.gc_tcp_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcp_cache_line_size); 1770 adev->gfx.config.gc_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_size_per_sqc); 1771 adev->gfx.config.gc_instruction_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_line_size); 1772 adev->gfx.config.gc_scalar_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_size_per_sqc); 1773 adev->gfx.config.gc_scalar_data_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_line_size); 1774 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v1_3.gc_tcc_size); 1775 adev->gfx.config.gc_tcc_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcc_cache_line_size); 1776 } 1777 break; 1778 case 2: 1779 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); 1780 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); 1781 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1782 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); 1783 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); 1784 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); 1785 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); 1786 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); 1787 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); 1788 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); 1789 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); 1790 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); 1791 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); 1792 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); 1793 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / 1794 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1795 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); 1796 if (le16_to_cpu(gc_info->v2.header.version_minor) == 1) { 1797 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh); 1798 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu); 1799 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XCD */ 1800 adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc); 1801 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_cache_size_per_sqc); 1802 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_size_per_sqc); 1803 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */ 1804 } 1805 break; 1806 default: 1807 dev_err(adev->dev, 1808 "Unhandled GC info table %d.%d\n", 1809 le16_to_cpu(gc_info->v1.header.version_major), 1810 le16_to_cpu(gc_info->v1.header.version_minor)); 1811 return -EINVAL; 1812 } 1813 return 0; 1814 } 1815 1816 union mall_info { 1817 struct mall_info_v1_0 v1; 1818 struct mall_info_v2_0 v2; 1819 }; 1820 1821 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) 1822 { 1823 uint8_t *discovery_bin = adev->discovery.bin; 1824 struct table_info *info; 1825 union mall_info *mall_info; 1826 u32 u, mall_size_per_umc, m_s_present, half_use; 1827 u64 mall_size; 1828 u16 offset; 1829 1830 if (!discovery_bin) { 1831 DRM_ERROR("ip discovery uninitialized\n"); 1832 return -EINVAL; 1833 } 1834 1835 if (amdgpu_discovery_get_table_info(adev, &info, MALL_INFO)) 1836 return -EINVAL; 1837 offset = le16_to_cpu(info->offset); 1838 1839 if (!offset) 1840 return 0; 1841 1842 mall_info = (union mall_info *)(discovery_bin + offset); 1843 1844 switch (le16_to_cpu(mall_info->v1.header.version_major)) { 1845 case 1: 1846 mall_size = 0; 1847 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m); 1848 m_s_present = le32_to_cpu(mall_info->v1.m_s_present); 1849 half_use = le32_to_cpu(mall_info->v1.m_half_use); 1850 for (u = 0; u < adev->gmc.num_umc; u++) { 1851 if (m_s_present & (1 << u)) 1852 mall_size += mall_size_per_umc * 2; 1853 else if (half_use & (1 << u)) 1854 mall_size += mall_size_per_umc / 2; 1855 else 1856 mall_size += mall_size_per_umc; 1857 } 1858 adev->gmc.mall_size = mall_size; 1859 adev->gmc.m_half_use = half_use; 1860 break; 1861 case 2: 1862 mall_size_per_umc = le32_to_cpu(mall_info->v2.mall_size_per_umc); 1863 adev->gmc.mall_size = (uint64_t)mall_size_per_umc * adev->gmc.num_umc; 1864 break; 1865 default: 1866 dev_err(adev->dev, 1867 "Unhandled MALL info table %d.%d\n", 1868 le16_to_cpu(mall_info->v1.header.version_major), 1869 le16_to_cpu(mall_info->v1.header.version_minor)); 1870 return -EINVAL; 1871 } 1872 return 0; 1873 } 1874 1875 union vcn_info { 1876 struct vcn_info_v1_0 v1; 1877 }; 1878 1879 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) 1880 { 1881 uint8_t *discovery_bin = adev->discovery.bin; 1882 struct table_info *info; 1883 union vcn_info *vcn_info; 1884 u16 offset; 1885 int v; 1886 1887 if (!discovery_bin) { 1888 DRM_ERROR("ip discovery uninitialized\n"); 1889 return -EINVAL; 1890 } 1891 1892 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1893 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES 1894 * but that may change in the future with new GPUs so keep this 1895 * check for defensive purposes. 1896 */ 1897 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { 1898 dev_err(adev->dev, "invalid vcn instances\n"); 1899 return -EINVAL; 1900 } 1901 1902 if (amdgpu_discovery_get_table_info(adev, &info, VCN_INFO)) 1903 return -EINVAL; 1904 offset = le16_to_cpu(info->offset); 1905 1906 if (!offset) 1907 return 0; 1908 1909 vcn_info = (union vcn_info *)(discovery_bin + offset); 1910 1911 switch (le16_to_cpu(vcn_info->v1.header.version_major)) { 1912 case 1: 1913 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1914 * so this won't overflow. 1915 */ 1916 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { 1917 adev->vcn.inst[v].vcn_codec_disable_mask = 1918 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits); 1919 } 1920 break; 1921 default: 1922 dev_err(adev->dev, 1923 "Unhandled VCN info table %d.%d\n", 1924 le16_to_cpu(vcn_info->v1.header.version_major), 1925 le16_to_cpu(vcn_info->v1.header.version_minor)); 1926 return -EINVAL; 1927 } 1928 return 0; 1929 } 1930 1931 union nps_info { 1932 struct nps_info_v1_0 v1; 1933 }; 1934 1935 static int amdgpu_discovery_refresh_nps_info(struct amdgpu_device *adev, 1936 union nps_info *nps_data) 1937 { 1938 uint64_t vram_size, pos, offset; 1939 struct nps_info_header *nhdr; 1940 struct binary_header bhdr; 1941 struct binary_header_v2 bhdrv2; 1942 uint16_t checksum; 1943 1944 vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 1945 pos = vram_size - DISCOVERY_TMR_OFFSET; 1946 amdgpu_device_vram_access(adev, pos, &bhdr, sizeof(bhdr), false); 1947 1948 switch (bhdr.version_major) { 1949 case 2: 1950 amdgpu_device_vram_access(adev, pos, &bhdrv2, sizeof(bhdrv2), false); 1951 offset = le16_to_cpu(bhdrv2.table_list[NPS_INFO].offset); 1952 checksum = le16_to_cpu(bhdrv2.table_list[NPS_INFO].checksum); 1953 break; 1954 case 1: 1955 offset = le16_to_cpu(bhdr.table_list[NPS_INFO].offset); 1956 checksum = le16_to_cpu(bhdr.table_list[NPS_INFO].checksum); 1957 break; 1958 default: 1959 return -EINVAL; 1960 } 1961 1962 amdgpu_device_vram_access(adev, (pos + offset), nps_data, 1963 sizeof(*nps_data), false); 1964 1965 nhdr = (struct nps_info_header *)(nps_data); 1966 if (!amdgpu_discovery_verify_checksum(adev, (uint8_t *)nps_data, 1967 le32_to_cpu(nhdr->size_bytes), 1968 checksum)) { 1969 dev_err(adev->dev, "nps data refresh, checksum mismatch\n"); 1970 return -EINVAL; 1971 } 1972 1973 return 0; 1974 } 1975 1976 int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, 1977 uint32_t *nps_type, 1978 struct amdgpu_gmc_memrange **ranges, 1979 int *range_cnt, bool refresh) 1980 { 1981 uint8_t *discovery_bin = adev->discovery.bin; 1982 struct amdgpu_gmc_memrange *mem_ranges; 1983 struct table_info *info; 1984 union nps_info *nps_info; 1985 union nps_info nps_data; 1986 u16 offset; 1987 int i, r; 1988 1989 if (!nps_type || !range_cnt || !ranges) 1990 return -EINVAL; 1991 1992 if (refresh) { 1993 r = amdgpu_discovery_refresh_nps_info(adev, &nps_data); 1994 if (r) 1995 return r; 1996 nps_info = &nps_data; 1997 } else { 1998 if (!discovery_bin) { 1999 dev_err(adev->dev, 2000 "fetch mem range failed, ip discovery uninitialized\n"); 2001 return -EINVAL; 2002 } 2003 2004 if (amdgpu_discovery_get_table_info(adev, &info, NPS_INFO)) 2005 return -EINVAL; 2006 offset = le16_to_cpu(info->offset); 2007 2008 if (!offset) 2009 return -ENOENT; 2010 2011 /* If verification fails, return as if NPS table doesn't exist */ 2012 if (amdgpu_discovery_verify_npsinfo(adev, info)) 2013 return -ENOENT; 2014 2015 nps_info = (union nps_info *)(discovery_bin + offset); 2016 } 2017 2018 switch (le16_to_cpu(nps_info->v1.header.version_major)) { 2019 case 1: 2020 mem_ranges = kvzalloc_objs(*mem_ranges, nps_info->v1.count); 2021 if (!mem_ranges) 2022 return -ENOMEM; 2023 *nps_type = nps_info->v1.nps_type; 2024 *range_cnt = nps_info->v1.count; 2025 for (i = 0; i < *range_cnt; i++) { 2026 mem_ranges[i].base_address = 2027 nps_info->v1.instance_info[i].base_address; 2028 mem_ranges[i].limit_address = 2029 nps_info->v1.instance_info[i].limit_address; 2030 mem_ranges[i].nid_mask = -1; 2031 mem_ranges[i].flags = 0; 2032 } 2033 *ranges = mem_ranges; 2034 break; 2035 default: 2036 dev_err(adev->dev, "Unhandled NPS info table %d.%d\n", 2037 le16_to_cpu(nps_info->v1.header.version_major), 2038 le16_to_cpu(nps_info->v1.header.version_minor)); 2039 return -EINVAL; 2040 } 2041 2042 return 0; 2043 } 2044 2045 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 2046 { 2047 /* what IP to use for this? */ 2048 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2049 case IP_VERSION(9, 0, 1): 2050 case IP_VERSION(9, 1, 0): 2051 case IP_VERSION(9, 2, 1): 2052 case IP_VERSION(9, 2, 2): 2053 case IP_VERSION(9, 3, 0): 2054 case IP_VERSION(9, 4, 0): 2055 case IP_VERSION(9, 4, 1): 2056 case IP_VERSION(9, 4, 2): 2057 case IP_VERSION(9, 4, 3): 2058 case IP_VERSION(9, 4, 4): 2059 case IP_VERSION(9, 5, 0): 2060 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 2061 break; 2062 case IP_VERSION(10, 1, 10): 2063 case IP_VERSION(10, 1, 1): 2064 case IP_VERSION(10, 1, 2): 2065 case IP_VERSION(10, 1, 3): 2066 case IP_VERSION(10, 1, 4): 2067 case IP_VERSION(10, 3, 0): 2068 case IP_VERSION(10, 3, 1): 2069 case IP_VERSION(10, 3, 2): 2070 case IP_VERSION(10, 3, 3): 2071 case IP_VERSION(10, 3, 4): 2072 case IP_VERSION(10, 3, 5): 2073 case IP_VERSION(10, 3, 6): 2074 case IP_VERSION(10, 3, 7): 2075 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 2076 break; 2077 case IP_VERSION(11, 0, 0): 2078 case IP_VERSION(11, 0, 1): 2079 case IP_VERSION(11, 0, 2): 2080 case IP_VERSION(11, 0, 3): 2081 case IP_VERSION(11, 0, 4): 2082 case IP_VERSION(11, 5, 0): 2083 case IP_VERSION(11, 5, 1): 2084 case IP_VERSION(11, 5, 2): 2085 case IP_VERSION(11, 5, 3): 2086 case IP_VERSION(11, 5, 4): 2087 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); 2088 break; 2089 case IP_VERSION(12, 0, 0): 2090 case IP_VERSION(12, 0, 1): 2091 amdgpu_device_ip_block_add(adev, &soc24_common_ip_block); 2092 break; 2093 case IP_VERSION(12, 1, 0): 2094 amdgpu_device_ip_block_add(adev, &soc_v1_0_common_ip_block); 2095 break; 2096 default: 2097 dev_err(adev->dev, 2098 "Failed to add common ip block(GC_HWIP:0x%x)\n", 2099 amdgpu_ip_version(adev, GC_HWIP, 0)); 2100 return -EINVAL; 2101 } 2102 return 0; 2103 } 2104 2105 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 2106 { 2107 /* use GC or MMHUB IP version */ 2108 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2109 case IP_VERSION(9, 0, 1): 2110 case IP_VERSION(9, 1, 0): 2111 case IP_VERSION(9, 2, 1): 2112 case IP_VERSION(9, 2, 2): 2113 case IP_VERSION(9, 3, 0): 2114 case IP_VERSION(9, 4, 0): 2115 case IP_VERSION(9, 4, 1): 2116 case IP_VERSION(9, 4, 2): 2117 case IP_VERSION(9, 4, 3): 2118 case IP_VERSION(9, 4, 4): 2119 case IP_VERSION(9, 5, 0): 2120 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 2121 break; 2122 case IP_VERSION(10, 1, 10): 2123 case IP_VERSION(10, 1, 1): 2124 case IP_VERSION(10, 1, 2): 2125 case IP_VERSION(10, 1, 3): 2126 case IP_VERSION(10, 1, 4): 2127 case IP_VERSION(10, 3, 0): 2128 case IP_VERSION(10, 3, 1): 2129 case IP_VERSION(10, 3, 2): 2130 case IP_VERSION(10, 3, 3): 2131 case IP_VERSION(10, 3, 4): 2132 case IP_VERSION(10, 3, 5): 2133 case IP_VERSION(10, 3, 6): 2134 case IP_VERSION(10, 3, 7): 2135 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 2136 break; 2137 case IP_VERSION(11, 0, 0): 2138 case IP_VERSION(11, 0, 1): 2139 case IP_VERSION(11, 0, 2): 2140 case IP_VERSION(11, 0, 3): 2141 case IP_VERSION(11, 0, 4): 2142 case IP_VERSION(11, 5, 0): 2143 case IP_VERSION(11, 5, 1): 2144 case IP_VERSION(11, 5, 2): 2145 case IP_VERSION(11, 5, 3): 2146 case IP_VERSION(11, 5, 4): 2147 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block); 2148 break; 2149 case IP_VERSION(12, 0, 0): 2150 case IP_VERSION(12, 0, 1): 2151 case IP_VERSION(12, 1, 0): 2152 amdgpu_device_ip_block_add(adev, &gmc_v12_0_ip_block); 2153 break; 2154 default: 2155 dev_err(adev->dev, "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 2156 amdgpu_ip_version(adev, GC_HWIP, 0)); 2157 return -EINVAL; 2158 } 2159 return 0; 2160 } 2161 2162 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 2163 { 2164 switch (amdgpu_ip_version(adev, OSSSYS_HWIP, 0)) { 2165 case IP_VERSION(4, 0, 0): 2166 case IP_VERSION(4, 0, 1): 2167 case IP_VERSION(4, 1, 0): 2168 case IP_VERSION(4, 1, 1): 2169 case IP_VERSION(4, 3, 0): 2170 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 2171 break; 2172 case IP_VERSION(4, 2, 0): 2173 case IP_VERSION(4, 2, 1): 2174 case IP_VERSION(4, 4, 0): 2175 case IP_VERSION(4, 4, 2): 2176 case IP_VERSION(4, 4, 5): 2177 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 2178 break; 2179 case IP_VERSION(5, 0, 0): 2180 case IP_VERSION(5, 0, 1): 2181 case IP_VERSION(5, 0, 2): 2182 case IP_VERSION(5, 0, 3): 2183 case IP_VERSION(5, 2, 0): 2184 case IP_VERSION(5, 2, 1): 2185 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 2186 break; 2187 case IP_VERSION(6, 0, 0): 2188 case IP_VERSION(6, 0, 1): 2189 case IP_VERSION(6, 0, 2): 2190 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block); 2191 break; 2192 case IP_VERSION(6, 1, 0): 2193 case IP_VERSION(6, 1, 1): 2194 amdgpu_device_ip_block_add(adev, &ih_v6_1_ip_block); 2195 break; 2196 case IP_VERSION(7, 0, 0): 2197 case IP_VERSION(7, 1, 0): 2198 amdgpu_device_ip_block_add(adev, &ih_v7_0_ip_block); 2199 break; 2200 default: 2201 dev_err(adev->dev, 2202 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 2203 amdgpu_ip_version(adev, OSSSYS_HWIP, 0)); 2204 return -EINVAL; 2205 } 2206 return 0; 2207 } 2208 2209 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 2210 { 2211 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 2212 case IP_VERSION(9, 0, 0): 2213 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 2214 break; 2215 case IP_VERSION(10, 0, 0): 2216 case IP_VERSION(10, 0, 1): 2217 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 2218 break; 2219 case IP_VERSION(11, 0, 0): 2220 case IP_VERSION(11, 0, 2): 2221 case IP_VERSION(11, 0, 4): 2222 case IP_VERSION(11, 0, 5): 2223 case IP_VERSION(11, 0, 9): 2224 case IP_VERSION(11, 0, 7): 2225 case IP_VERSION(11, 0, 11): 2226 case IP_VERSION(11, 0, 12): 2227 case IP_VERSION(11, 0, 13): 2228 case IP_VERSION(11, 5, 0): 2229 case IP_VERSION(11, 5, 2): 2230 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 2231 break; 2232 case IP_VERSION(11, 0, 8): 2233 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 2234 break; 2235 case IP_VERSION(11, 0, 3): 2236 case IP_VERSION(12, 0, 1): 2237 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 2238 break; 2239 case IP_VERSION(13, 0, 0): 2240 case IP_VERSION(13, 0, 1): 2241 case IP_VERSION(13, 0, 2): 2242 case IP_VERSION(13, 0, 3): 2243 case IP_VERSION(13, 0, 5): 2244 case IP_VERSION(13, 0, 6): 2245 case IP_VERSION(13, 0, 7): 2246 case IP_VERSION(13, 0, 8): 2247 case IP_VERSION(13, 0, 10): 2248 case IP_VERSION(13, 0, 11): 2249 case IP_VERSION(13, 0, 12): 2250 case IP_VERSION(13, 0, 14): 2251 case IP_VERSION(13, 0, 15): 2252 case IP_VERSION(14, 0, 0): 2253 case IP_VERSION(14, 0, 1): 2254 case IP_VERSION(14, 0, 4): 2255 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 2256 break; 2257 case IP_VERSION(13, 0, 4): 2258 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block); 2259 break; 2260 case IP_VERSION(14, 0, 2): 2261 case IP_VERSION(14, 0, 3): 2262 case IP_VERSION(14, 0, 5): 2263 amdgpu_device_ip_block_add(adev, &psp_v14_0_ip_block); 2264 break; 2265 case IP_VERSION(15, 0, 0): 2266 amdgpu_device_ip_block_add(adev, &psp_v15_0_ip_block); 2267 break; 2268 case IP_VERSION(15, 0, 8): 2269 amdgpu_device_ip_block_add(adev, &psp_v15_0_8_ip_block); 2270 break; 2271 default: 2272 dev_err(adev->dev, 2273 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 2274 amdgpu_ip_version(adev, MP0_HWIP, 0)); 2275 return -EINVAL; 2276 } 2277 return 0; 2278 } 2279 2280 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 2281 { 2282 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2283 case IP_VERSION(9, 0, 0): 2284 case IP_VERSION(10, 0, 0): 2285 case IP_VERSION(10, 0, 1): 2286 case IP_VERSION(11, 0, 2): 2287 if (adev->asic_type == CHIP_ARCTURUS) 2288 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2289 else 2290 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 2291 break; 2292 case IP_VERSION(11, 0, 0): 2293 case IP_VERSION(11, 0, 5): 2294 case IP_VERSION(11, 0, 9): 2295 case IP_VERSION(11, 0, 7): 2296 case IP_VERSION(11, 0, 11): 2297 case IP_VERSION(11, 0, 12): 2298 case IP_VERSION(11, 0, 13): 2299 case IP_VERSION(11, 5, 0): 2300 case IP_VERSION(11, 5, 2): 2301 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2302 break; 2303 case IP_VERSION(11, 0, 8): 2304 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) 2305 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2306 break; 2307 case IP_VERSION(12, 0, 0): 2308 case IP_VERSION(12, 0, 1): 2309 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 2310 break; 2311 case IP_VERSION(13, 0, 0): 2312 case IP_VERSION(13, 0, 1): 2313 case IP_VERSION(13, 0, 2): 2314 case IP_VERSION(13, 0, 3): 2315 case IP_VERSION(13, 0, 4): 2316 case IP_VERSION(13, 0, 5): 2317 case IP_VERSION(13, 0, 6): 2318 case IP_VERSION(13, 0, 7): 2319 case IP_VERSION(13, 0, 8): 2320 case IP_VERSION(13, 0, 10): 2321 case IP_VERSION(13, 0, 11): 2322 case IP_VERSION(13, 0, 14): 2323 case IP_VERSION(13, 0, 12): 2324 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 2325 break; 2326 case IP_VERSION(14, 0, 0): 2327 case IP_VERSION(14, 0, 1): 2328 case IP_VERSION(14, 0, 2): 2329 case IP_VERSION(14, 0, 3): 2330 case IP_VERSION(14, 0, 4): 2331 case IP_VERSION(14, 0, 5): 2332 amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block); 2333 break; 2334 case IP_VERSION(15, 0, 0): 2335 amdgpu_device_ip_block_add(adev, &smu_v15_0_ip_block); 2336 break; 2337 default: 2338 dev_err(adev->dev, 2339 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 2340 amdgpu_ip_version(adev, MP1_HWIP, 0)); 2341 return -EINVAL; 2342 } 2343 return 0; 2344 } 2345 2346 #if defined(CONFIG_DRM_AMD_DC) 2347 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev) 2348 { 2349 amdgpu_device_set_sriov_virtual_display(adev); 2350 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2351 } 2352 #endif 2353 2354 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 2355 { 2356 if (adev->enable_virtual_display) { 2357 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2358 return 0; 2359 } 2360 2361 if (!amdgpu_device_has_dc_support(adev)) 2362 return 0; 2363 2364 #if defined(CONFIG_DRM_AMD_DC) 2365 if (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2366 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2367 case IP_VERSION(1, 0, 0): 2368 case IP_VERSION(1, 0, 1): 2369 case IP_VERSION(2, 0, 2): 2370 case IP_VERSION(2, 0, 0): 2371 case IP_VERSION(2, 0, 3): 2372 case IP_VERSION(2, 1, 0): 2373 case IP_VERSION(3, 0, 0): 2374 case IP_VERSION(3, 0, 2): 2375 case IP_VERSION(3, 0, 3): 2376 case IP_VERSION(3, 0, 1): 2377 case IP_VERSION(3, 1, 2): 2378 case IP_VERSION(3, 1, 3): 2379 case IP_VERSION(3, 1, 4): 2380 case IP_VERSION(3, 1, 5): 2381 case IP_VERSION(3, 1, 6): 2382 case IP_VERSION(3, 2, 0): 2383 case IP_VERSION(3, 2, 1): 2384 case IP_VERSION(3, 5, 0): 2385 case IP_VERSION(3, 5, 1): 2386 case IP_VERSION(3, 6, 0): 2387 case IP_VERSION(4, 1, 0): 2388 case IP_VERSION(4, 2, 0): 2389 /* TODO: Fix IP version. DC code expects version 4.0.1 */ 2390 if (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(4, 1, 0)) 2391 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(4, 0, 1); 2392 2393 if (amdgpu_sriov_vf(adev)) 2394 amdgpu_discovery_set_sriov_display(adev); 2395 else 2396 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2397 break; 2398 default: 2399 dev_err(adev->dev, 2400 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 2401 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2402 return -EINVAL; 2403 } 2404 } else if (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2405 switch (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2406 case IP_VERSION(12, 0, 0): 2407 case IP_VERSION(12, 0, 1): 2408 case IP_VERSION(12, 1, 0): 2409 if (amdgpu_sriov_vf(adev)) 2410 amdgpu_discovery_set_sriov_display(adev); 2411 else 2412 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2413 break; 2414 default: 2415 dev_err(adev->dev, 2416 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 2417 amdgpu_ip_version(adev, DCI_HWIP, 0)); 2418 return -EINVAL; 2419 } 2420 } 2421 #endif 2422 return 0; 2423 } 2424 2425 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 2426 { 2427 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2428 case IP_VERSION(9, 0, 1): 2429 case IP_VERSION(9, 1, 0): 2430 case IP_VERSION(9, 2, 1): 2431 case IP_VERSION(9, 2, 2): 2432 case IP_VERSION(9, 3, 0): 2433 case IP_VERSION(9, 4, 0): 2434 case IP_VERSION(9, 4, 1): 2435 case IP_VERSION(9, 4, 2): 2436 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 2437 break; 2438 case IP_VERSION(9, 4, 3): 2439 case IP_VERSION(9, 4, 4): 2440 case IP_VERSION(9, 5, 0): 2441 amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block); 2442 break; 2443 case IP_VERSION(10, 1, 10): 2444 case IP_VERSION(10, 1, 2): 2445 case IP_VERSION(10, 1, 1): 2446 case IP_VERSION(10, 1, 3): 2447 case IP_VERSION(10, 1, 4): 2448 case IP_VERSION(10, 3, 0): 2449 case IP_VERSION(10, 3, 2): 2450 case IP_VERSION(10, 3, 1): 2451 case IP_VERSION(10, 3, 4): 2452 case IP_VERSION(10, 3, 5): 2453 case IP_VERSION(10, 3, 6): 2454 case IP_VERSION(10, 3, 3): 2455 case IP_VERSION(10, 3, 7): 2456 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 2457 break; 2458 case IP_VERSION(11, 0, 0): 2459 case IP_VERSION(11, 0, 1): 2460 case IP_VERSION(11, 0, 2): 2461 case IP_VERSION(11, 0, 3): 2462 case IP_VERSION(11, 0, 4): 2463 case IP_VERSION(11, 5, 0): 2464 case IP_VERSION(11, 5, 1): 2465 case IP_VERSION(11, 5, 2): 2466 case IP_VERSION(11, 5, 3): 2467 case IP_VERSION(11, 5, 4): 2468 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); 2469 break; 2470 case IP_VERSION(12, 0, 0): 2471 case IP_VERSION(12, 0, 1): 2472 amdgpu_device_ip_block_add(adev, &gfx_v12_0_ip_block); 2473 break; 2474 case IP_VERSION(12, 1, 0): 2475 amdgpu_device_ip_block_add(adev, &gfx_v12_1_ip_block); 2476 break; 2477 default: 2478 dev_err(adev->dev, "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 2479 amdgpu_ip_version(adev, GC_HWIP, 0)); 2480 return -EINVAL; 2481 } 2482 return 0; 2483 } 2484 2485 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 2486 { 2487 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 2488 case IP_VERSION(4, 0, 0): 2489 case IP_VERSION(4, 0, 1): 2490 case IP_VERSION(4, 1, 0): 2491 case IP_VERSION(4, 1, 1): 2492 case IP_VERSION(4, 1, 2): 2493 case IP_VERSION(4, 2, 0): 2494 case IP_VERSION(4, 2, 2): 2495 case IP_VERSION(4, 4, 0): 2496 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 2497 break; 2498 case IP_VERSION(4, 4, 2): 2499 case IP_VERSION(4, 4, 5): 2500 case IP_VERSION(4, 4, 4): 2501 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block); 2502 break; 2503 case IP_VERSION(5, 0, 0): 2504 case IP_VERSION(5, 0, 1): 2505 case IP_VERSION(5, 0, 2): 2506 case IP_VERSION(5, 0, 5): 2507 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 2508 break; 2509 case IP_VERSION(5, 2, 0): 2510 case IP_VERSION(5, 2, 2): 2511 case IP_VERSION(5, 2, 4): 2512 case IP_VERSION(5, 2, 5): 2513 case IP_VERSION(5, 2, 6): 2514 case IP_VERSION(5, 2, 3): 2515 case IP_VERSION(5, 2, 1): 2516 case IP_VERSION(5, 2, 7): 2517 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 2518 break; 2519 case IP_VERSION(6, 0, 0): 2520 case IP_VERSION(6, 0, 1): 2521 case IP_VERSION(6, 0, 2): 2522 case IP_VERSION(6, 0, 3): 2523 case IP_VERSION(6, 1, 0): 2524 case IP_VERSION(6, 1, 1): 2525 case IP_VERSION(6, 1, 2): 2526 case IP_VERSION(6, 1, 3): 2527 case IP_VERSION(6, 1, 4): 2528 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block); 2529 break; 2530 case IP_VERSION(7, 0, 0): 2531 case IP_VERSION(7, 0, 1): 2532 amdgpu_device_ip_block_add(adev, &sdma_v7_0_ip_block); 2533 break; 2534 case IP_VERSION(7, 1, 0): 2535 amdgpu_device_ip_block_add(adev, &sdma_v7_1_ip_block); 2536 break; 2537 default: 2538 dev_err(adev->dev, 2539 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 2540 amdgpu_ip_version(adev, SDMA0_HWIP, 0)); 2541 return -EINVAL; 2542 } 2543 2544 return 0; 2545 } 2546 2547 static int amdgpu_discovery_set_ras_ip_blocks(struct amdgpu_device *adev) 2548 { 2549 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 2550 case IP_VERSION(13, 0, 6): 2551 case IP_VERSION(13, 0, 12): 2552 case IP_VERSION(13, 0, 14): 2553 amdgpu_device_ip_block_add(adev, &ras_v1_0_ip_block); 2554 break; 2555 default: 2556 break; 2557 } 2558 return 0; 2559 } 2560 2561 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 2562 { 2563 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2564 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2565 case IP_VERSION(7, 0, 0): 2566 case IP_VERSION(7, 2, 0): 2567 /* UVD is not supported on vega20 SR-IOV */ 2568 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2569 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 2570 break; 2571 default: 2572 dev_err(adev->dev, 2573 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 2574 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2575 return -EINVAL; 2576 } 2577 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2578 case IP_VERSION(4, 0, 0): 2579 case IP_VERSION(4, 1, 0): 2580 /* VCE is not supported on vega20 SR-IOV */ 2581 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2582 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 2583 break; 2584 default: 2585 dev_err(adev->dev, 2586 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 2587 amdgpu_ip_version(adev, VCE_HWIP, 0)); 2588 return -EINVAL; 2589 } 2590 } else { 2591 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2592 case IP_VERSION(1, 0, 0): 2593 case IP_VERSION(1, 0, 1): 2594 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 2595 break; 2596 case IP_VERSION(2, 0, 0): 2597 case IP_VERSION(2, 0, 2): 2598 case IP_VERSION(2, 2, 0): 2599 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 2600 if (!amdgpu_sriov_vf(adev)) 2601 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 2602 break; 2603 case IP_VERSION(2, 0, 3): 2604 break; 2605 case IP_VERSION(2, 5, 0): 2606 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 2607 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 2608 break; 2609 case IP_VERSION(2, 6, 0): 2610 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 2611 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 2612 break; 2613 case IP_VERSION(3, 0, 0): 2614 case IP_VERSION(3, 0, 16): 2615 case IP_VERSION(3, 1, 1): 2616 case IP_VERSION(3, 1, 2): 2617 case IP_VERSION(3, 0, 2): 2618 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2619 if (!amdgpu_sriov_vf(adev)) 2620 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 2621 break; 2622 case IP_VERSION(3, 0, 33): 2623 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2624 break; 2625 case IP_VERSION(4, 0, 0): 2626 case IP_VERSION(4, 0, 2): 2627 case IP_VERSION(4, 0, 4): 2628 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block); 2629 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block); 2630 break; 2631 case IP_VERSION(4, 0, 3): 2632 amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block); 2633 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block); 2634 break; 2635 case IP_VERSION(4, 0, 5): 2636 case IP_VERSION(4, 0, 6): 2637 amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block); 2638 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block); 2639 break; 2640 case IP_VERSION(5, 0, 0): 2641 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block); 2642 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block); 2643 break; 2644 case IP_VERSION(5, 3, 0): 2645 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block); 2646 amdgpu_device_ip_block_add(adev, &jpeg_v5_3_0_ip_block); 2647 break; 2648 case IP_VERSION(5, 0, 1): 2649 amdgpu_device_ip_block_add(adev, &vcn_v5_0_1_ip_block); 2650 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_1_ip_block); 2651 break; 2652 default: 2653 dev_err(adev->dev, 2654 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 2655 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2656 return -EINVAL; 2657 } 2658 } 2659 return 0; 2660 } 2661 2662 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 2663 { 2664 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2665 case IP_VERSION(11, 0, 0): 2666 case IP_VERSION(11, 0, 1): 2667 case IP_VERSION(11, 0, 2): 2668 case IP_VERSION(11, 0, 3): 2669 case IP_VERSION(11, 0, 4): 2670 case IP_VERSION(11, 5, 0): 2671 case IP_VERSION(11, 5, 1): 2672 case IP_VERSION(11, 5, 2): 2673 case IP_VERSION(11, 5, 3): 2674 case IP_VERSION(11, 5, 4): 2675 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block); 2676 adev->enable_mes = true; 2677 adev->enable_mes_kiq = true; 2678 break; 2679 case IP_VERSION(12, 0, 0): 2680 case IP_VERSION(12, 0, 1): 2681 amdgpu_device_ip_block_add(adev, &mes_v12_0_ip_block); 2682 adev->enable_mes = true; 2683 adev->enable_mes_kiq = true; 2684 if (amdgpu_uni_mes) 2685 adev->enable_uni_mes = true; 2686 break; 2687 case IP_VERSION(12, 1, 0): 2688 amdgpu_device_ip_block_add(adev, &mes_v12_1_ip_block); 2689 adev->enable_mes = true; 2690 adev->enable_mes_kiq = true; 2691 if (amdgpu_uni_mes) 2692 adev->enable_uni_mes = true; 2693 break; 2694 default: 2695 break; 2696 } 2697 return 0; 2698 } 2699 2700 static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev) 2701 { 2702 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2703 case IP_VERSION(9, 4, 3): 2704 case IP_VERSION(9, 4, 4): 2705 case IP_VERSION(9, 5, 0): 2706 aqua_vanjaram_init_soc_config(adev); 2707 break; 2708 case IP_VERSION(12, 1, 0): 2709 soc_v1_0_init_soc_config(adev); 2710 break; 2711 default: 2712 break; 2713 } 2714 } 2715 2716 static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev) 2717 { 2718 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) { 2719 case IP_VERSION(6, 1, 0): 2720 case IP_VERSION(6, 1, 1): 2721 case IP_VERSION(6, 1, 3): 2722 amdgpu_device_ip_block_add(adev, &vpe_v6_1_ip_block); 2723 break; 2724 default: 2725 break; 2726 } 2727 2728 return 0; 2729 } 2730 2731 static int amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device *adev) 2732 { 2733 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) { 2734 case IP_VERSION(4, 0, 5): 2735 case IP_VERSION(4, 0, 6): 2736 if (amdgpu_umsch_mm & 0x1) { 2737 amdgpu_device_ip_block_add(adev, &umsch_mm_v4_0_ip_block); 2738 adev->enable_umsch_mm = true; 2739 } 2740 break; 2741 default: 2742 break; 2743 } 2744 2745 return 0; 2746 } 2747 2748 static int amdgpu_discovery_set_isp_ip_blocks(struct amdgpu_device *adev) 2749 { 2750 #if defined(CONFIG_DRM_AMD_ISP) 2751 switch (amdgpu_ip_version(adev, ISP_HWIP, 0)) { 2752 case IP_VERSION(4, 1, 0): 2753 amdgpu_device_ip_block_add(adev, &isp_v4_1_0_ip_block); 2754 break; 2755 case IP_VERSION(4, 1, 1): 2756 amdgpu_device_ip_block_add(adev, &isp_v4_1_1_ip_block); 2757 break; 2758 default: 2759 break; 2760 } 2761 #endif 2762 2763 return 0; 2764 } 2765 2766 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 2767 { 2768 int r; 2769 2770 switch (adev->asic_type) { 2771 case CHIP_VEGA10: 2772 /* This is not fatal. We only need the discovery 2773 * binary for sysfs. We don't need it for a 2774 * functional system. 2775 */ 2776 amdgpu_discovery_init(adev); 2777 vega10_reg_base_init(adev); 2778 adev->sdma.num_instances = 2; 2779 adev->sdma.sdma_mask = 3; 2780 adev->gmc.num_umc = 4; 2781 adev->gfx.xcc_mask = 1; 2782 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2783 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2784 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 2785 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 2786 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 2787 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 2788 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2789 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 2790 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 2791 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2792 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2793 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2794 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 2795 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 2796 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2797 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2798 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 2799 break; 2800 case CHIP_VEGA12: 2801 /* This is not fatal. We only need the discovery 2802 * binary for sysfs. We don't need it for a 2803 * functional system. 2804 */ 2805 amdgpu_discovery_init(adev); 2806 vega10_reg_base_init(adev); 2807 adev->sdma.num_instances = 2; 2808 adev->sdma.sdma_mask = 3; 2809 adev->gmc.num_umc = 4; 2810 adev->gfx.xcc_mask = 1; 2811 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2812 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2813 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 2814 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 2815 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 2816 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 2817 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 2818 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 2819 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 2820 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2821 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2822 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2823 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 2824 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 2825 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2826 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2827 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 2828 break; 2829 case CHIP_RAVEN: 2830 /* This is not fatal. We only need the discovery 2831 * binary for sysfs. We don't need it for a 2832 * functional system. 2833 */ 2834 amdgpu_discovery_init(adev); 2835 vega10_reg_base_init(adev); 2836 adev->sdma.num_instances = 1; 2837 adev->sdma.sdma_mask = 1; 2838 adev->vcn.num_vcn_inst = 1; 2839 adev->gmc.num_umc = 2; 2840 adev->gfx.xcc_mask = 1; 2841 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 2842 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2843 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2844 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 2845 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 2846 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 2847 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 2848 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 2849 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 2850 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 2851 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 2852 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 2853 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 2854 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 2855 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 2856 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 2857 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 2858 } else { 2859 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2860 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2861 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 2862 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 2863 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 2864 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2865 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 2866 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 2867 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 2868 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 2869 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 2870 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 2871 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 2872 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 2873 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 2874 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 2875 } 2876 break; 2877 case CHIP_VEGA20: 2878 /* This is not fatal. We only need the discovery 2879 * binary for sysfs. We don't need it for a 2880 * functional system. 2881 */ 2882 amdgpu_discovery_init(adev); 2883 vega20_reg_base_init(adev); 2884 adev->sdma.num_instances = 2; 2885 adev->sdma.sdma_mask = 3; 2886 adev->gmc.num_umc = 8; 2887 adev->gfx.xcc_mask = 1; 2888 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2889 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2890 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 2891 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 2892 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 2893 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 2894 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 2895 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 2896 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 2897 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 2898 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2899 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 2900 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 2901 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 2902 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 2903 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 2904 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 2905 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 2906 break; 2907 case CHIP_ARCTURUS: 2908 /* This is not fatal. We only need the discovery 2909 * binary for sysfs. We don't need it for a 2910 * functional system. 2911 */ 2912 amdgpu_discovery_init(adev); 2913 arct_reg_base_init(adev); 2914 adev->sdma.num_instances = 8; 2915 adev->sdma.sdma_mask = 0xff; 2916 adev->vcn.num_vcn_inst = 2; 2917 adev->gmc.num_umc = 8; 2918 adev->gfx.xcc_mask = 1; 2919 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2920 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2921 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 2922 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 2923 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 2924 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 2925 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 2926 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 2927 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 2928 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 2929 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 2930 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 2931 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 2932 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 2933 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 2934 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 2935 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2936 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 2937 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 2938 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 2939 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 2940 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 2941 break; 2942 case CHIP_ALDEBARAN: 2943 /* This is not fatal. We only need the discovery 2944 * binary for sysfs. We don't need it for a 2945 * functional system. 2946 */ 2947 amdgpu_discovery_init(adev); 2948 aldebaran_reg_base_init(adev); 2949 adev->sdma.num_instances = 5; 2950 adev->sdma.sdma_mask = 0x1f; 2951 adev->vcn.num_vcn_inst = 2; 2952 adev->gmc.num_umc = 4; 2953 adev->gfx.xcc_mask = 1; 2954 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2955 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2956 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 2957 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 2958 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 2959 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 2960 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 2961 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 2962 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 2963 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 2964 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 2965 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 2966 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 2967 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 2968 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 2969 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 2970 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 2971 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 2972 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 2973 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 2974 break; 2975 case CHIP_CYAN_SKILLFISH: 2976 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 2977 r = amdgpu_discovery_reg_base_init(adev); 2978 if (r) 2979 return -EINVAL; 2980 2981 amdgpu_discovery_harvest_ip(adev); 2982 amdgpu_discovery_get_gfx_info(adev); 2983 amdgpu_discovery_get_mall_info(adev); 2984 amdgpu_discovery_get_vcn_info(adev); 2985 } else { 2986 cyan_skillfish_reg_base_init(adev); 2987 adev->sdma.num_instances = 2; 2988 adev->sdma.sdma_mask = 3; 2989 adev->gfx.xcc_mask = 1; 2990 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(2, 0, 3); 2991 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(2, 0, 3); 2992 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(5, 0, 1); 2993 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(5, 0, 1); 2994 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(5, 0, 1); 2995 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(5, 0, 1); 2996 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 5, 0); 2997 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(2, 1, 1); 2998 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(8, 1, 1); 2999 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 8); 3000 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 8); 3001 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 1); 3002 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 8); 3003 adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 1, 3); 3004 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 0, 3); 3005 } 3006 break; 3007 default: 3008 r = amdgpu_discovery_reg_base_init(adev); 3009 if (r) { 3010 drm_err(&adev->ddev, "discovery failed: %d\n", r); 3011 return r; 3012 } 3013 3014 amdgpu_discovery_harvest_ip(adev); 3015 amdgpu_discovery_get_gfx_info(adev); 3016 amdgpu_discovery_get_mall_info(adev); 3017 amdgpu_discovery_get_vcn_info(adev); 3018 break; 3019 } 3020 3021 amdgpu_discovery_init_soc_config(adev); 3022 amdgpu_discovery_sysfs_init(adev); 3023 3024 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3025 case IP_VERSION(9, 0, 1): 3026 case IP_VERSION(9, 2, 1): 3027 case IP_VERSION(9, 4, 0): 3028 case IP_VERSION(9, 4, 1): 3029 case IP_VERSION(9, 4, 2): 3030 case IP_VERSION(9, 4, 3): 3031 case IP_VERSION(9, 4, 4): 3032 case IP_VERSION(9, 5, 0): 3033 adev->family = AMDGPU_FAMILY_AI; 3034 break; 3035 case IP_VERSION(9, 1, 0): 3036 case IP_VERSION(9, 2, 2): 3037 case IP_VERSION(9, 3, 0): 3038 adev->family = AMDGPU_FAMILY_RV; 3039 break; 3040 case IP_VERSION(10, 1, 10): 3041 case IP_VERSION(10, 1, 1): 3042 case IP_VERSION(10, 1, 2): 3043 case IP_VERSION(10, 1, 3): 3044 case IP_VERSION(10, 1, 4): 3045 case IP_VERSION(10, 3, 0): 3046 case IP_VERSION(10, 3, 2): 3047 case IP_VERSION(10, 3, 4): 3048 case IP_VERSION(10, 3, 5): 3049 adev->family = AMDGPU_FAMILY_NV; 3050 break; 3051 case IP_VERSION(10, 3, 1): 3052 adev->family = AMDGPU_FAMILY_VGH; 3053 adev->apu_flags |= AMD_APU_IS_VANGOGH; 3054 break; 3055 case IP_VERSION(10, 3, 3): 3056 adev->family = AMDGPU_FAMILY_YC; 3057 break; 3058 case IP_VERSION(10, 3, 6): 3059 adev->family = AMDGPU_FAMILY_GC_10_3_6; 3060 break; 3061 case IP_VERSION(10, 3, 7): 3062 adev->family = AMDGPU_FAMILY_GC_10_3_7; 3063 break; 3064 case IP_VERSION(11, 0, 0): 3065 case IP_VERSION(11, 0, 2): 3066 case IP_VERSION(11, 0, 3): 3067 adev->family = AMDGPU_FAMILY_GC_11_0_0; 3068 break; 3069 case IP_VERSION(11, 0, 1): 3070 case IP_VERSION(11, 0, 4): 3071 adev->family = AMDGPU_FAMILY_GC_11_0_1; 3072 break; 3073 case IP_VERSION(11, 5, 0): 3074 case IP_VERSION(11, 5, 1): 3075 case IP_VERSION(11, 5, 2): 3076 case IP_VERSION(11, 5, 3): 3077 adev->family = AMDGPU_FAMILY_GC_11_5_0; 3078 break; 3079 case IP_VERSION(11, 5, 4): 3080 adev->family = AMDGPU_FAMILY_GC_11_5_4; 3081 break; 3082 case IP_VERSION(12, 0, 0): 3083 case IP_VERSION(12, 0, 1): 3084 case IP_VERSION(12, 1, 0): 3085 adev->family = AMDGPU_FAMILY_GC_12_0_0; 3086 break; 3087 default: 3088 return -EINVAL; 3089 } 3090 3091 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3092 case IP_VERSION(9, 1, 0): 3093 case IP_VERSION(9, 2, 2): 3094 case IP_VERSION(9, 3, 0): 3095 case IP_VERSION(10, 1, 3): 3096 case IP_VERSION(10, 1, 4): 3097 case IP_VERSION(10, 3, 1): 3098 case IP_VERSION(10, 3, 3): 3099 case IP_VERSION(10, 3, 6): 3100 case IP_VERSION(10, 3, 7): 3101 case IP_VERSION(11, 0, 1): 3102 case IP_VERSION(11, 0, 4): 3103 case IP_VERSION(11, 5, 0): 3104 case IP_VERSION(11, 5, 1): 3105 case IP_VERSION(11, 5, 2): 3106 case IP_VERSION(11, 5, 3): 3107 case IP_VERSION(11, 5, 4): 3108 adev->flags |= AMD_IS_APU; 3109 break; 3110 default: 3111 break; 3112 } 3113 3114 /* set NBIO version */ 3115 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 3116 case IP_VERSION(6, 1, 0): 3117 case IP_VERSION(6, 2, 0): 3118 adev->nbio.funcs = &nbio_v6_1_funcs; 3119 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 3120 break; 3121 case IP_VERSION(7, 0, 0): 3122 case IP_VERSION(7, 0, 1): 3123 case IP_VERSION(2, 5, 0): 3124 adev->nbio.funcs = &nbio_v7_0_funcs; 3125 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 3126 break; 3127 case IP_VERSION(7, 4, 0): 3128 case IP_VERSION(7, 4, 1): 3129 case IP_VERSION(7, 4, 4): 3130 adev->nbio.funcs = &nbio_v7_4_funcs; 3131 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 3132 break; 3133 case IP_VERSION(7, 9, 0): 3134 case IP_VERSION(7, 9, 1): 3135 adev->nbio.funcs = &nbio_v7_9_funcs; 3136 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg; 3137 break; 3138 case IP_VERSION(7, 11, 0): 3139 case IP_VERSION(7, 11, 1): 3140 case IP_VERSION(7, 11, 2): 3141 case IP_VERSION(7, 11, 3): 3142 adev->nbio.funcs = &nbio_v7_11_funcs; 3143 adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg; 3144 break; 3145 case IP_VERSION(7, 2, 0): 3146 case IP_VERSION(7, 2, 1): 3147 case IP_VERSION(7, 3, 0): 3148 case IP_VERSION(7, 5, 0): 3149 case IP_VERSION(7, 5, 1): 3150 adev->nbio.funcs = &nbio_v7_2_funcs; 3151 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 3152 break; 3153 case IP_VERSION(2, 1, 1): 3154 case IP_VERSION(2, 3, 0): 3155 case IP_VERSION(2, 3, 1): 3156 case IP_VERSION(2, 3, 2): 3157 case IP_VERSION(3, 3, 0): 3158 case IP_VERSION(3, 3, 1): 3159 case IP_VERSION(3, 3, 2): 3160 case IP_VERSION(3, 3, 3): 3161 adev->nbio.funcs = &nbio_v2_3_funcs; 3162 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 3163 break; 3164 case IP_VERSION(4, 3, 0): 3165 case IP_VERSION(4, 3, 1): 3166 if (amdgpu_sriov_vf(adev)) 3167 adev->nbio.funcs = &nbio_v4_3_sriov_funcs; 3168 else 3169 adev->nbio.funcs = &nbio_v4_3_funcs; 3170 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg; 3171 break; 3172 case IP_VERSION(7, 7, 0): 3173 case IP_VERSION(7, 7, 1): 3174 adev->nbio.funcs = &nbio_v7_7_funcs; 3175 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg; 3176 break; 3177 case IP_VERSION(6, 3, 1): 3178 case IP_VERSION(7, 11, 4): 3179 adev->nbio.funcs = &nbif_v6_3_1_funcs; 3180 adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg; 3181 break; 3182 default: 3183 break; 3184 } 3185 3186 switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) { 3187 case IP_VERSION(4, 0, 0): 3188 case IP_VERSION(4, 0, 1): 3189 case IP_VERSION(4, 1, 0): 3190 case IP_VERSION(4, 1, 1): 3191 case IP_VERSION(4, 1, 2): 3192 case IP_VERSION(4, 2, 0): 3193 case IP_VERSION(4, 2, 1): 3194 case IP_VERSION(4, 4, 0): 3195 case IP_VERSION(4, 4, 2): 3196 case IP_VERSION(4, 4, 5): 3197 adev->hdp.funcs = &hdp_v4_0_funcs; 3198 break; 3199 case IP_VERSION(5, 0, 0): 3200 case IP_VERSION(5, 0, 1): 3201 case IP_VERSION(5, 0, 2): 3202 case IP_VERSION(5, 0, 3): 3203 case IP_VERSION(5, 0, 4): 3204 case IP_VERSION(5, 2, 0): 3205 adev->hdp.funcs = &hdp_v5_0_funcs; 3206 break; 3207 case IP_VERSION(5, 2, 1): 3208 adev->hdp.funcs = &hdp_v5_2_funcs; 3209 break; 3210 case IP_VERSION(6, 0, 0): 3211 case IP_VERSION(6, 0, 1): 3212 case IP_VERSION(6, 1, 0): 3213 case IP_VERSION(6, 1, 1): 3214 adev->hdp.funcs = &hdp_v6_0_funcs; 3215 break; 3216 case IP_VERSION(7, 0, 0): 3217 adev->hdp.funcs = &hdp_v7_0_funcs; 3218 break; 3219 default: 3220 break; 3221 } 3222 3223 switch (amdgpu_ip_version(adev, DF_HWIP, 0)) { 3224 case IP_VERSION(3, 6, 0): 3225 case IP_VERSION(3, 6, 1): 3226 case IP_VERSION(3, 6, 2): 3227 adev->df.funcs = &df_v3_6_funcs; 3228 break; 3229 case IP_VERSION(2, 1, 0): 3230 case IP_VERSION(2, 1, 1): 3231 case IP_VERSION(2, 5, 0): 3232 case IP_VERSION(3, 5, 1): 3233 case IP_VERSION(3, 5, 2): 3234 adev->df.funcs = &df_v1_7_funcs; 3235 break; 3236 case IP_VERSION(4, 3, 0): 3237 adev->df.funcs = &df_v4_3_funcs; 3238 break; 3239 case IP_VERSION(4, 6, 2): 3240 adev->df.funcs = &df_v4_6_2_funcs; 3241 break; 3242 case IP_VERSION(4, 15, 0): 3243 case IP_VERSION(4, 15, 1): 3244 adev->df.funcs = &df_v4_15_funcs; 3245 break; 3246 default: 3247 break; 3248 } 3249 3250 switch (amdgpu_ip_version(adev, SMUIO_HWIP, 0)) { 3251 case IP_VERSION(9, 0, 0): 3252 case IP_VERSION(9, 0, 1): 3253 case IP_VERSION(10, 0, 0): 3254 case IP_VERSION(10, 0, 1): 3255 case IP_VERSION(10, 0, 2): 3256 adev->smuio.funcs = &smuio_v9_0_funcs; 3257 break; 3258 case IP_VERSION(11, 0, 0): 3259 case IP_VERSION(11, 0, 2): 3260 case IP_VERSION(11, 0, 3): 3261 case IP_VERSION(11, 0, 4): 3262 case IP_VERSION(11, 0, 7): 3263 case IP_VERSION(11, 0, 8): 3264 adev->smuio.funcs = &smuio_v11_0_funcs; 3265 break; 3266 case IP_VERSION(11, 0, 6): 3267 case IP_VERSION(11, 0, 10): 3268 case IP_VERSION(11, 0, 11): 3269 case IP_VERSION(11, 5, 0): 3270 case IP_VERSION(11, 5, 2): 3271 case IP_VERSION(13, 0, 1): 3272 case IP_VERSION(13, 0, 9): 3273 case IP_VERSION(13, 0, 10): 3274 adev->smuio.funcs = &smuio_v11_0_6_funcs; 3275 break; 3276 case IP_VERSION(13, 0, 2): 3277 adev->smuio.funcs = &smuio_v13_0_funcs; 3278 break; 3279 case IP_VERSION(13, 0, 3): 3280 case IP_VERSION(13, 0, 11): 3281 adev->smuio.funcs = &smuio_v13_0_3_funcs; 3282 if (adev->smuio.funcs->get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) { 3283 adev->flags |= AMD_IS_APU; 3284 } 3285 break; 3286 case IP_VERSION(13, 0, 6): 3287 case IP_VERSION(13, 0, 8): 3288 case IP_VERSION(14, 0, 0): 3289 case IP_VERSION(14, 0, 1): 3290 adev->smuio.funcs = &smuio_v13_0_6_funcs; 3291 break; 3292 case IP_VERSION(14, 0, 2): 3293 adev->smuio.funcs = &smuio_v14_0_2_funcs; 3294 break; 3295 case IP_VERSION(15, 0, 0): 3296 adev->smuio.funcs = &smuio_v15_0_0_funcs; 3297 break; 3298 case IP_VERSION(15, 0, 8): 3299 adev->smuio.funcs = &smuio_v15_0_8_funcs; 3300 break; 3301 default: 3302 break; 3303 } 3304 3305 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { 3306 case IP_VERSION(6, 0, 0): 3307 case IP_VERSION(6, 0, 1): 3308 case IP_VERSION(6, 0, 2): 3309 case IP_VERSION(6, 0, 3): 3310 adev->lsdma.funcs = &lsdma_v6_0_funcs; 3311 break; 3312 case IP_VERSION(7, 0, 0): 3313 case IP_VERSION(7, 0, 1): 3314 adev->lsdma.funcs = &lsdma_v7_0_funcs; 3315 break; 3316 case IP_VERSION(7, 1, 0): 3317 adev->lsdma.funcs = &lsdma_v7_1_funcs; 3318 break; 3319 default: 3320 break; 3321 } 3322 3323 r = amdgpu_discovery_set_common_ip_blocks(adev); 3324 if (r) 3325 return r; 3326 3327 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 3328 if (r) 3329 return r; 3330 3331 /* For SR-IOV, PSP needs to be initialized before IH */ 3332 if (amdgpu_sriov_vf(adev)) { 3333 r = amdgpu_discovery_set_psp_ip_blocks(adev); 3334 if (r) 3335 return r; 3336 r = amdgpu_discovery_set_ih_ip_blocks(adev); 3337 if (r) 3338 return r; 3339 } else { 3340 r = amdgpu_discovery_set_ih_ip_blocks(adev); 3341 if (r) 3342 return r; 3343 3344 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3345 r = amdgpu_discovery_set_psp_ip_blocks(adev); 3346 if (r) 3347 return r; 3348 } 3349 } 3350 3351 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3352 r = amdgpu_discovery_set_smu_ip_blocks(adev); 3353 if (r) 3354 return r; 3355 } 3356 3357 r = amdgpu_discovery_set_display_ip_blocks(adev); 3358 if (r) 3359 return r; 3360 3361 r = amdgpu_discovery_set_gc_ip_blocks(adev); 3362 if (r) 3363 return r; 3364 3365 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 3366 if (r) 3367 return r; 3368 3369 r = amdgpu_discovery_set_ras_ip_blocks(adev); 3370 if (r) 3371 return r; 3372 3373 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 3374 !amdgpu_sriov_vf(adev) && 3375 amdgpu_dpm == 1) || 3376 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && 3377 amdgpu_dpm == 1)) { 3378 r = amdgpu_discovery_set_smu_ip_blocks(adev); 3379 if (r) 3380 return r; 3381 } 3382 3383 r = amdgpu_discovery_set_mm_ip_blocks(adev); 3384 if (r) 3385 return r; 3386 3387 r = amdgpu_discovery_set_mes_ip_blocks(adev); 3388 if (r) 3389 return r; 3390 3391 r = amdgpu_discovery_set_vpe_ip_blocks(adev); 3392 if (r) 3393 return r; 3394 3395 r = amdgpu_discovery_set_umsch_mm_ip_blocks(adev); 3396 if (r) 3397 return r; 3398 3399 r = amdgpu_discovery_set_isp_ip_blocks(adev); 3400 if (r) 3401 return r; 3402 return 0; 3403 } 3404 3405