1 /* 2 * Copyright 2018-2024 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_discovery.h" 28 #include "soc15_hw_ip.h" 29 #include "discovery.h" 30 #include "amdgpu_ras.h" 31 32 #include "soc15.h" 33 #include "gfx_v9_0.h" 34 #include "gfx_v9_4_3.h" 35 #include "gmc_v9_0.h" 36 #include "df_v1_7.h" 37 #include "df_v3_6.h" 38 #include "df_v4_3.h" 39 #include "df_v4_6_2.h" 40 #include "df_v4_15.h" 41 #include "nbio_v6_1.h" 42 #include "nbio_v7_0.h" 43 #include "nbio_v7_4.h" 44 #include "nbio_v7_9.h" 45 #include "nbio_v7_11.h" 46 #include "hdp_v4_0.h" 47 #include "vega10_ih.h" 48 #include "vega20_ih.h" 49 #include "sdma_v4_0.h" 50 #include "sdma_v4_4_2.h" 51 #include "uvd_v7_0.h" 52 #include "vce_v4_0.h" 53 #include "vcn_v1_0.h" 54 #include "vcn_v2_5.h" 55 #include "jpeg_v2_5.h" 56 #include "smuio_v9_0.h" 57 #include "gmc_v10_0.h" 58 #include "gmc_v11_0.h" 59 #include "gmc_v12_0.h" 60 #include "gfxhub_v2_0.h" 61 #include "mmhub_v2_0.h" 62 #include "nbio_v2_3.h" 63 #include "nbio_v4_3.h" 64 #include "nbio_v7_2.h" 65 #include "nbio_v7_7.h" 66 #include "nbif_v6_3_1.h" 67 #include "hdp_v5_0.h" 68 #include "hdp_v5_2.h" 69 #include "hdp_v6_0.h" 70 #include "hdp_v7_0.h" 71 #include "nv.h" 72 #include "soc21.h" 73 #include "soc24.h" 74 #include "soc_v1_0.h" 75 #include "navi10_ih.h" 76 #include "ih_v6_0.h" 77 #include "ih_v6_1.h" 78 #include "ih_v7_0.h" 79 #include "gfx_v10_0.h" 80 #include "gfx_v11_0.h" 81 #include "gfx_v12_0.h" 82 #include "gfx_v12_1.h" 83 #include "sdma_v5_0.h" 84 #include "sdma_v5_2.h" 85 #include "sdma_v6_0.h" 86 #include "sdma_v7_0.h" 87 #include "sdma_v7_1.h" 88 #include "lsdma_v6_0.h" 89 #include "lsdma_v7_0.h" 90 #include "lsdma_v7_1.h" 91 #include "vcn_v2_0.h" 92 #include "jpeg_v2_0.h" 93 #include "vcn_v3_0.h" 94 #include "jpeg_v3_0.h" 95 #include "vcn_v4_0.h" 96 #include "jpeg_v4_0.h" 97 #include "vcn_v4_0_3.h" 98 #include "jpeg_v4_0_3.h" 99 #include "vcn_v4_0_5.h" 100 #include "jpeg_v4_0_5.h" 101 #include "amdgpu_vkms.h" 102 #include "mes_v11_0.h" 103 #include "mes_v12_0.h" 104 #include "mes_v12_1.h" 105 #include "smuio_v11_0.h" 106 #include "smuio_v11_0_6.h" 107 #include "smuio_v13_0.h" 108 #include "smuio_v13_0_3.h" 109 #include "smuio_v13_0_6.h" 110 #include "smuio_v14_0_2.h" 111 #include "smuio_v15_0_0.h" 112 #include "smuio_v15_0_8.h" 113 #include "vcn_v5_0_0.h" 114 #include "vcn_v5_0_1.h" 115 #include "jpeg_v5_0_0.h" 116 #include "jpeg_v5_0_1.h" 117 #include "jpeg_v5_3_0.h" 118 119 #include "amdgpu_ras_mgr.h" 120 121 #include "amdgpu_vpe.h" 122 #if defined(CONFIG_DRM_AMD_ISP) 123 #include "amdgpu_isp.h" 124 #endif 125 126 MODULE_FIRMWARE("amdgpu/ip_discovery.bin"); 127 MODULE_FIRMWARE("amdgpu/vega10_ip_discovery.bin"); 128 MODULE_FIRMWARE("amdgpu/vega12_ip_discovery.bin"); 129 MODULE_FIRMWARE("amdgpu/vega20_ip_discovery.bin"); 130 MODULE_FIRMWARE("amdgpu/raven_ip_discovery.bin"); 131 MODULE_FIRMWARE("amdgpu/raven2_ip_discovery.bin"); 132 MODULE_FIRMWARE("amdgpu/picasso_ip_discovery.bin"); 133 MODULE_FIRMWARE("amdgpu/arcturus_ip_discovery.bin"); 134 MODULE_FIRMWARE("amdgpu/aldebaran_ip_discovery.bin"); 135 136 /* Note: These registers are consistent across all the SOCs */ 137 #define mmIP_DISCOVERY_VERSION 0x16A00 138 #define mmRCC_CONFIG_MEMSIZE 0xde3 139 #define mmMP0_SMN_C2PMSG_33 0x16061 140 #define mmMM_INDEX 0x0 141 #define mmMM_INDEX_HI 0x6 142 #define mmMM_DATA 0x1 143 144 #define mmDRIVER_SCRATCH_0 0x94 145 #define mmDRIVER_SCRATCH_1 0x95 146 #define mmDRIVER_SCRATCH_2 0x96 147 148 static const char *hw_id_names[HW_ID_MAX] = { 149 [MP1_HWID] = "MP1", 150 [MP2_HWID] = "MP2", 151 [THM_HWID] = "THM", 152 [SMUIO_HWID] = "SMUIO", 153 [FUSE_HWID] = "FUSE", 154 [CLKA_HWID] = "CLKA", 155 [PWR_HWID] = "PWR", 156 [GC_HWID] = "GC", 157 [UVD_HWID] = "UVD", 158 [AUDIO_AZ_HWID] = "AUDIO_AZ", 159 [ACP_HWID] = "ACP", 160 [DCI_HWID] = "DCI", 161 [DMU_HWID] = "DMU", 162 [DCO_HWID] = "DCO", 163 [DIO_HWID] = "DIO", 164 [XDMA_HWID] = "XDMA", 165 [DCEAZ_HWID] = "DCEAZ", 166 [DAZ_HWID] = "DAZ", 167 [SDPMUX_HWID] = "SDPMUX", 168 [NTB_HWID] = "NTB", 169 [IOHC_HWID] = "IOHC", 170 [L2IMU_HWID] = "L2IMU", 171 [VCE_HWID] = "VCE", 172 [MMHUB_HWID] = "MMHUB", 173 [ATHUB_HWID] = "ATHUB", 174 [DBGU_NBIO_HWID] = "DBGU_NBIO", 175 [DFX_HWID] = "DFX", 176 [DBGU0_HWID] = "DBGU0", 177 [DBGU1_HWID] = "DBGU1", 178 [OSSSYS_HWID] = "OSSSYS", 179 [HDP_HWID] = "HDP", 180 [SDMA0_HWID] = "SDMA0", 181 [SDMA1_HWID] = "SDMA1", 182 [SDMA2_HWID] = "SDMA2", 183 [SDMA3_HWID] = "SDMA3", 184 [LSDMA_HWID] = "LSDMA", 185 [ISP_HWID] = "ISP", 186 [DBGU_IO_HWID] = "DBGU_IO", 187 [DF_HWID] = "DF", 188 [CLKB_HWID] = "CLKB", 189 [FCH_HWID] = "FCH", 190 [DFX_DAP_HWID] = "DFX_DAP", 191 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 192 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 193 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 194 [L1IMU3_HWID] = "L1IMU3", 195 [L1IMU4_HWID] = "L1IMU4", 196 [L1IMU5_HWID] = "L1IMU5", 197 [L1IMU6_HWID] = "L1IMU6", 198 [L1IMU7_HWID] = "L1IMU7", 199 [L1IMU8_HWID] = "L1IMU8", 200 [L1IMU9_HWID] = "L1IMU9", 201 [L1IMU10_HWID] = "L1IMU10", 202 [L1IMU11_HWID] = "L1IMU11", 203 [L1IMU12_HWID] = "L1IMU12", 204 [L1IMU13_HWID] = "L1IMU13", 205 [L1IMU14_HWID] = "L1IMU14", 206 [L1IMU15_HWID] = "L1IMU15", 207 [WAFLC_HWID] = "WAFLC", 208 [FCH_USB_PD_HWID] = "FCH_USB_PD", 209 [PCIE_HWID] = "PCIE", 210 [PCS_HWID] = "PCS", 211 [DDCL_HWID] = "DDCL", 212 [SST_HWID] = "SST", 213 [IOAGR_HWID] = "IOAGR", 214 [NBIF_HWID] = "NBIF", 215 [IOAPIC_HWID] = "IOAPIC", 216 [SYSTEMHUB_HWID] = "SYSTEMHUB", 217 [NTBCCP_HWID] = "NTBCCP", 218 [UMC_HWID] = "UMC", 219 [SATA_HWID] = "SATA", 220 [USB_HWID] = "USB", 221 [CCXSEC_HWID] = "CCXSEC", 222 [XGMI_HWID] = "XGMI", 223 [XGBE_HWID] = "XGBE", 224 [MP0_HWID] = "MP0", 225 [VPE_HWID] = "VPE", 226 [ATU_HWID] = "ATU", 227 [AIGC_HWID] = "AIGC", 228 }; 229 230 static int hw_id_map[MAX_HWIP] = { 231 [GC_HWIP] = GC_HWID, 232 [HDP_HWIP] = HDP_HWID, 233 [SDMA0_HWIP] = SDMA0_HWID, 234 [SDMA1_HWIP] = SDMA1_HWID, 235 [SDMA2_HWIP] = SDMA2_HWID, 236 [SDMA3_HWIP] = SDMA3_HWID, 237 [LSDMA_HWIP] = LSDMA_HWID, 238 [MMHUB_HWIP] = MMHUB_HWID, 239 [ATHUB_HWIP] = ATHUB_HWID, 240 [NBIO_HWIP] = NBIF_HWID, 241 [MP0_HWIP] = MP0_HWID, 242 [MP1_HWIP] = MP1_HWID, 243 [UVD_HWIP] = UVD_HWID, 244 [VCE_HWIP] = VCE_HWID, 245 [DF_HWIP] = DF_HWID, 246 [DCE_HWIP] = DMU_HWID, 247 [OSSSYS_HWIP] = OSSSYS_HWID, 248 [SMUIO_HWIP] = SMUIO_HWID, 249 [PWR_HWIP] = PWR_HWID, 250 [NBIF_HWIP] = NBIF_HWID, 251 [THM_HWIP] = THM_HWID, 252 [CLK_HWIP] = CLKA_HWID, 253 [UMC_HWIP] = UMC_HWID, 254 [XGMI_HWIP] = XGMI_HWID, 255 [DCI_HWIP] = DCI_HWID, 256 [PCIE_HWIP] = PCIE_HWID, 257 [VPE_HWIP] = VPE_HWID, 258 [ISP_HWIP] = ISP_HWID, 259 [ATU_HWIP] = ATU_HWID, 260 }; 261 262 static int amdgpu_discovery_get_tmr_info(struct amdgpu_device *adev, 263 bool *is_tmr_in_sysmem) 264 { 265 u64 vram_size, tmr_offset, tmr_size; 266 u32 msg, tmr_offset_lo, tmr_offset_hi; 267 int i, ret; 268 269 if (!amdgpu_sriov_vf(adev)) { 270 /* It can take up to two second for IFWI init to complete on some dGPUs, 271 * but generally it should be in the 60-100ms range. Normally this starts 272 * as soon as the device gets power so by the time the OS loads this has long 273 * completed. However, when a card is hotplugged via e.g., USB4, we need to 274 * wait for this to complete. Once the C2PMSG is updated, we can 275 * continue. 276 */ 277 278 for (i = 0; i < 2000; i++) { 279 msg = RREG32(mmMP0_SMN_C2PMSG_33); 280 if (msg & 0x80000000) 281 break; 282 msleep(1); 283 } 284 } 285 286 vram_size = RREG32(mmRCC_CONFIG_MEMSIZE); 287 if (vram_size == U32_MAX) 288 return -ENXIO; 289 else if (!vram_size) 290 *is_tmr_in_sysmem = true; 291 else 292 *is_tmr_in_sysmem = false; 293 294 /* init the default tmr size and offset */ 295 adev->discovery.size = DISCOVERY_TMR_SIZE; 296 if (vram_size) 297 adev->discovery.offset = (vram_size << 20) - DISCOVERY_TMR_OFFSET; 298 299 if (amdgpu_sriov_vf(adev) && adev->virt.is_dynamic_crit_regn_enabled) { 300 adev->discovery.offset = 301 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].offset; 302 adev->discovery.size = 303 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].size_kb << 10; 304 if (!adev->discovery.offset || !adev->discovery.size) 305 return -EINVAL; 306 } else { 307 tmr_size = RREG32(mmDRIVER_SCRATCH_2); 308 if (tmr_size) { 309 /* It's preferred to transition to PSP mailbox reg interface 310 * for both bare-metal and passthrough if available */ 311 adev->discovery.size = (u32)tmr_size; 312 tmr_offset_lo = RREG32(mmDRIVER_SCRATCH_0); 313 tmr_offset_hi = RREG32(mmDRIVER_SCRATCH_1); 314 adev->discovery.offset = ((u64)le32_to_cpu(tmr_offset_hi) << 32 | 315 le32_to_cpu(tmr_offset_lo)); 316 } else if (!vram_size) { 317 /* fall back to apci approach to query tmr offset if vram_size is 0 */ 318 ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size); 319 if (ret) 320 return ret; 321 adev->discovery.size = (u32)tmr_size; 322 adev->discovery.offset = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET; 323 } 324 } 325 326 adev->discovery.bin = kzalloc(adev->discovery.size, GFP_KERNEL); 327 if (!adev->discovery.bin) 328 return -ENOMEM; 329 adev->discovery.debugfs_blob.data = adev->discovery.bin; 330 adev->discovery.debugfs_blob.size = adev->discovery.size; 331 332 return 0; 333 } 334 335 static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary) 336 { 337 void *discv_regn; 338 339 /* This region is read-only and reserved from system use */ 340 discv_regn = memremap(adev->discovery.offset, adev->discovery.size, MEMREMAP_WC); 341 if (discv_regn) { 342 memcpy(binary, discv_regn, adev->discovery.size); 343 memunmap(discv_regn); 344 return 0; 345 } 346 347 return -ENOENT; 348 } 349 350 #define IP_DISCOVERY_V2 2 351 #define IP_DISCOVERY_V4 4 352 353 static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, 354 uint8_t *binary, 355 bool is_tmr_in_sysmem) 356 { 357 int ret = 0; 358 359 if (!is_tmr_in_sysmem) { 360 if (amdgpu_sriov_vf(adev) && 361 amdgpu_sriov_xgmi_connected_to_cpu(adev)) { 362 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); 363 } else { 364 amdgpu_device_vram_access(adev, adev->discovery.offset, 365 (uint32_t *)binary, 366 adev->discovery.size, false); 367 adev->discovery.reserve_tmr = true; 368 } 369 } else { 370 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); 371 } 372 373 return ret; 374 } 375 376 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, 377 uint8_t *binary, 378 const char *fw_name) 379 { 380 const struct firmware *fw; 381 int r; 382 383 r = firmware_request_nowarn(&fw, fw_name, adev->dev); 384 if (r) { 385 if (amdgpu_discovery == 2) 386 dev_err(adev->dev, "can't load firmware \"%s\"\n", fw_name); 387 else 388 drm_info(&adev->ddev, "Optional firmware \"%s\" was not found\n", fw_name); 389 return r; 390 } 391 392 memcpy((u8 *)binary, (u8 *)fw->data, fw->size); 393 release_firmware(fw); 394 395 return 0; 396 } 397 398 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 399 { 400 uint16_t checksum = 0; 401 int i; 402 403 for (i = 0; i < size; i++) 404 checksum += data[i]; 405 406 return checksum; 407 } 408 409 static inline bool amdgpu_discovery_verify_checksum(struct amdgpu_device *adev, 410 uint8_t *data, uint32_t size, 411 uint16_t expected) 412 { 413 uint16_t calculated; 414 415 calculated = amdgpu_discovery_calculate_checksum(data, size); 416 417 if (calculated != expected) { 418 dev_err(adev->dev, "Discovery checksum failed: calc 0x%04x != exp 0x%04x, size %u.\n", 419 calculated, expected, size); 420 return false; 421 } 422 423 return true; 424 } 425 426 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 427 { 428 struct binary_header *bhdr; 429 bhdr = (struct binary_header *)binary; 430 431 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 432 } 433 434 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) 435 { 436 /* 437 * So far, apply this quirk only on those Navy Flounder boards which 438 * have a bad harvest table of VCN config. 439 */ 440 if ((amdgpu_ip_version(adev, UVD_HWIP, 1) == IP_VERSION(3, 0, 1)) && 441 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 2))) { 442 switch (adev->pdev->revision) { 443 case 0xC1: 444 case 0xC2: 445 case 0xC3: 446 case 0xC5: 447 case 0xC7: 448 case 0xCF: 449 case 0xDF: 450 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 451 adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1; 452 break; 453 default: 454 break; 455 } 456 } 457 } 458 459 static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev, 460 struct table_info *info) 461 { 462 uint8_t *discovery_bin = adev->discovery.bin; 463 uint16_t checksum; 464 uint16_t offset; 465 466 offset = le16_to_cpu(info->offset); 467 checksum = le16_to_cpu(info->checksum); 468 469 struct nps_info_header *nhdr = 470 (struct nps_info_header *)(discovery_bin + offset); 471 472 if (le32_to_cpu(nhdr->table_id) != NPS_INFO_TABLE_ID) { 473 dev_dbg(adev->dev, "invalid ip discovery nps info table id\n"); 474 return -EINVAL; 475 } 476 477 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, 478 le32_to_cpu(nhdr->size_bytes), 479 checksum)) { 480 dev_dbg(adev->dev, "invalid nps info data table checksum\n"); 481 return -EINVAL; 482 } 483 484 return 0; 485 } 486 487 static const char *amdgpu_discovery_get_fw_name(struct amdgpu_device *adev) 488 { 489 if (amdgpu_discovery == 2) { 490 /* Assume there is valid discovery TMR in VRAM even if binary is sideloaded */ 491 adev->discovery.reserve_tmr = true; 492 return "amdgpu/ip_discovery.bin"; 493 } 494 495 switch (adev->asic_type) { 496 case CHIP_VEGA10: 497 return "amdgpu/vega10_ip_discovery.bin"; 498 case CHIP_VEGA12: 499 return "amdgpu/vega12_ip_discovery.bin"; 500 case CHIP_RAVEN: 501 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 502 return "amdgpu/raven2_ip_discovery.bin"; 503 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 504 return "amdgpu/picasso_ip_discovery.bin"; 505 else 506 return "amdgpu/raven_ip_discovery.bin"; 507 case CHIP_VEGA20: 508 return "amdgpu/vega20_ip_discovery.bin"; 509 case CHIP_ARCTURUS: 510 return "amdgpu/arcturus_ip_discovery.bin"; 511 case CHIP_ALDEBARAN: 512 return "amdgpu/aldebaran_ip_discovery.bin"; 513 default: 514 return NULL; 515 } 516 } 517 518 static int amdgpu_discovery_get_table_info(struct amdgpu_device *adev, 519 struct table_info **info, 520 uint16_t table_id) 521 { 522 struct binary_header *bhdr = 523 (struct binary_header *)adev->discovery.bin; 524 struct binary_header_v2 *bhdrv2; 525 526 switch (bhdr->version_major) { 527 case 2: 528 bhdrv2 = (struct binary_header_v2 *)adev->discovery.bin; 529 *info = &bhdrv2->table_list[table_id]; 530 break; 531 case 1: 532 *info = &bhdr->table_list[table_id]; 533 break; 534 default: 535 dev_err(adev->dev, "Invalid ip discovery table version\n"); 536 return -EINVAL; 537 } 538 539 return 0; 540 } 541 542 static int amdgpu_discovery_table_check(struct amdgpu_device *adev, 543 uint8_t *discovery_bin, 544 uint16_t table_id) 545 { 546 int r, act_val, exp_val, table_size; 547 uint16_t offset, checksum; 548 struct table_info *info; 549 bool check_table = true; 550 char *table_name; 551 552 r = amdgpu_discovery_get_table_info(adev, &info, table_id); 553 if (r) 554 return r; 555 offset = le16_to_cpu(info->offset); 556 checksum = le16_to_cpu(info->checksum); 557 558 switch (table_id) { 559 case IP_DISCOVERY: 560 struct ip_discovery_header *ihdr = 561 (struct ip_discovery_header *)(discovery_bin + offset); 562 act_val = le32_to_cpu(ihdr->signature); 563 exp_val = DISCOVERY_TABLE_SIGNATURE; 564 table_size = le16_to_cpu(ihdr->size); 565 table_name = "data table"; 566 break; 567 case GC: 568 struct gpu_info_header *ghdr = 569 (struct gpu_info_header *)(discovery_bin + offset); 570 act_val = le32_to_cpu(ghdr->table_id); 571 exp_val = GC_TABLE_ID; 572 table_size = le16_to_cpu(ghdr->size); 573 table_name = "gc table"; 574 break; 575 case HARVEST_INFO: 576 struct harvest_info_header *hhdr = 577 (struct harvest_info_header *)(discovery_bin + offset); 578 act_val = le32_to_cpu(hhdr->signature); 579 exp_val = HARVEST_TABLE_SIGNATURE; 580 table_size = sizeof(struct harvest_table); 581 table_name = "harvest table"; 582 break; 583 case VCN_INFO: 584 struct vcn_info_header *vhdr = 585 (struct vcn_info_header *)(discovery_bin + offset); 586 act_val = le32_to_cpu(vhdr->table_id); 587 exp_val = VCN_INFO_TABLE_ID; 588 table_size = le32_to_cpu(vhdr->size_bytes); 589 table_name = "vcn table"; 590 break; 591 case MALL_INFO: 592 struct mall_info_header *mhdr = 593 (struct mall_info_header *)(discovery_bin + offset); 594 act_val = le32_to_cpu(mhdr->table_id); 595 exp_val = MALL_INFO_TABLE_ID; 596 table_size = le32_to_cpu(mhdr->size_bytes); 597 table_name = "mall table"; 598 check_table = false; 599 break; 600 default: 601 dev_err(adev->dev, "invalid ip discovery table id %d specified\n", table_id); 602 check_table = false; 603 break; 604 } 605 606 if (check_table && offset) { 607 if (act_val != exp_val) { 608 dev_err(adev->dev, "invalid ip discovery %s signature\n", table_name); 609 return -EINVAL; 610 } 611 612 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, 613 table_size, checksum)) { 614 dev_err(adev->dev, "invalid ip discovery %s checksum\n", table_name); 615 return -EINVAL; 616 } 617 } 618 619 return 0; 620 } 621 622 static int amdgpu_discovery_init(struct amdgpu_device *adev) 623 { 624 struct binary_header *bhdr; 625 uint8_t *discovery_bin; 626 const char *fw_name; 627 uint16_t offset; 628 uint16_t size; 629 uint16_t checksum; 630 uint16_t table_id; 631 bool is_tmr_in_sysmem; 632 int r; 633 634 r = amdgpu_discovery_get_tmr_info(adev, &is_tmr_in_sysmem); 635 if (r) 636 return r; 637 638 discovery_bin = adev->discovery.bin; 639 /* Read from file if it is the preferred option */ 640 fw_name = amdgpu_discovery_get_fw_name(adev); 641 if (fw_name != NULL) { 642 drm_dbg(&adev->ddev, "use ip discovery information from file"); 643 r = amdgpu_discovery_read_binary_from_file(adev, discovery_bin, 644 fw_name); 645 if (r) 646 goto out; 647 } else { 648 drm_dbg(&adev->ddev, "use ip discovery information from memory"); 649 r = amdgpu_discovery_read_binary_from_mem(adev, discovery_bin, 650 is_tmr_in_sysmem); 651 if (r) 652 goto out; 653 } 654 655 /* check the ip discovery binary signature */ 656 if (!amdgpu_discovery_verify_binary_signature(discovery_bin)) { 657 dev_err(adev->dev, 658 "get invalid ip discovery binary signature\n"); 659 r = -EINVAL; 660 goto out; 661 } 662 663 bhdr = (struct binary_header *)discovery_bin; 664 665 offset = offsetof(struct binary_header, binary_checksum) + 666 sizeof(bhdr->binary_checksum); 667 size = le16_to_cpu(bhdr->binary_size) - offset; 668 checksum = le16_to_cpu(bhdr->binary_checksum); 669 670 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, size, 671 checksum)) { 672 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 673 r = -EINVAL; 674 goto out; 675 } 676 677 for (table_id = 0; table_id <= MALL_INFO; table_id++) { 678 r = amdgpu_discovery_table_check(adev, discovery_bin, table_id); 679 if (r) 680 goto out; 681 } 682 683 return 0; 684 685 out: 686 kfree(adev->discovery.bin); 687 adev->discovery.bin = NULL; 688 if ((amdgpu_discovery != 2) && 689 (RREG32(mmIP_DISCOVERY_VERSION) == 4)) 690 amdgpu_ras_query_boot_status(adev, 4); 691 return r; 692 } 693 694 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev); 695 696 void amdgpu_discovery_fini(struct amdgpu_device *adev) 697 { 698 amdgpu_discovery_sysfs_fini(adev); 699 kfree(adev->discovery.bin); 700 adev->discovery.bin = NULL; 701 } 702 703 static int amdgpu_discovery_validate_ip(struct amdgpu_device *adev, 704 uint8_t instance, uint16_t hw_id) 705 { 706 if (instance >= HWIP_MAX_INSTANCE) { 707 dev_err(adev->dev, 708 "Unexpected instance_number (%d) from ip discovery blob\n", 709 instance); 710 return -EINVAL; 711 } 712 if (hw_id >= HW_ID_MAX) { 713 dev_err(adev->dev, 714 "Unexpected hw_id (%d) from ip discovery blob\n", 715 hw_id); 716 return -EINVAL; 717 } 718 719 return 0; 720 } 721 722 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev, 723 uint32_t *vcn_harvest_count) 724 { 725 uint8_t *discovery_bin = adev->discovery.bin; 726 struct binary_header *bhdr; 727 struct ip_discovery_header *ihdr; 728 struct die_header *dhdr; 729 struct ip *ip; 730 uint16_t die_offset, ip_offset, num_dies, num_ips; 731 uint16_t hw_id; 732 uint8_t inst; 733 int i, j; 734 735 bhdr = (struct binary_header *)discovery_bin; 736 ihdr = (struct ip_discovery_header 737 *)(discovery_bin + 738 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 739 num_dies = le16_to_cpu(ihdr->num_dies); 740 741 /* scan harvest bit of all IP data structures */ 742 for (i = 0; i < num_dies; i++) { 743 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 744 dhdr = (struct die_header *)(discovery_bin + die_offset); 745 num_ips = le16_to_cpu(dhdr->num_ips); 746 ip_offset = die_offset + sizeof(*dhdr); 747 748 for (j = 0; j < num_ips; j++) { 749 ip = (struct ip *)(discovery_bin + ip_offset); 750 inst = ip->number_instance; 751 hw_id = le16_to_cpu(ip->hw_id); 752 if (amdgpu_discovery_validate_ip(adev, inst, hw_id)) 753 goto next_ip; 754 755 if (ip->harvest == 1) { 756 switch (hw_id) { 757 case VCN_HWID: 758 (*vcn_harvest_count)++; 759 if (inst == 0) { 760 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 761 adev->vcn.inst_mask &= 762 ~AMDGPU_VCN_HARVEST_VCN0; 763 adev->jpeg.inst_mask &= 764 ~AMDGPU_VCN_HARVEST_VCN0; 765 } else { 766 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 767 adev->vcn.inst_mask &= 768 ~AMDGPU_VCN_HARVEST_VCN1; 769 adev->jpeg.inst_mask &= 770 ~AMDGPU_VCN_HARVEST_VCN1; 771 } 772 break; 773 case DMU_HWID: 774 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 775 break; 776 default: 777 break; 778 } 779 } 780 next_ip: 781 ip_offset += struct_size(ip, base_address, 782 ip->num_base_address); 783 } 784 } 785 } 786 787 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, 788 uint32_t *vcn_harvest_count, 789 uint32_t *umc_harvest_count) 790 { 791 uint8_t *discovery_bin = adev->discovery.bin; 792 struct table_info *info; 793 struct harvest_table *harvest_info; 794 u16 offset; 795 int i; 796 u64 umc_harvest_config = 0; 797 798 if (amdgpu_discovery_get_table_info(adev, &info, HARVEST_INFO)) 799 return; 800 offset = le16_to_cpu(info->offset); 801 802 if (!offset) { 803 dev_err(adev->dev, "invalid harvest table offset\n"); 804 return; 805 } 806 807 harvest_info = (struct harvest_table *)(discovery_bin + offset); 808 809 for (i = 0; i < 32; i++) { 810 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) 811 break; 812 813 switch (le16_to_cpu(harvest_info->list[i].hw_id)) { 814 case VCN_HWID: 815 (*vcn_harvest_count)++; 816 adev->vcn.harvest_config |= 817 (1 << harvest_info->list[i].number_instance); 818 adev->jpeg.harvest_config |= 819 (1 << harvest_info->list[i].number_instance); 820 821 adev->vcn.inst_mask &= 822 ~(1U << harvest_info->list[i].number_instance); 823 adev->jpeg.inst_mask &= 824 ~(1U << harvest_info->list[i].number_instance); 825 break; 826 case DMU_HWID: 827 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 828 break; 829 case UMC_HWID: 830 umc_harvest_config |= 831 1 << (le16_to_cpu(harvest_info->list[i].number_instance)); 832 (*umc_harvest_count)++; 833 break; 834 case GC_HWID: 835 adev->gfx.xcc_mask &= 836 ~(1U << harvest_info->list[i].number_instance); 837 break; 838 case SDMA0_HWID: 839 adev->sdma.sdma_mask &= 840 ~(1U << harvest_info->list[i].number_instance); 841 break; 842 #if defined(CONFIG_DRM_AMD_ISP) 843 case ISP_HWID: 844 adev->isp.harvest_config |= 845 ~(1U << harvest_info->list[i].number_instance); 846 break; 847 #endif 848 default: 849 break; 850 } 851 } 852 853 adev->umc.active_mask = ((1ULL << adev->umc.node_inst_num) - 1ULL) & 854 ~umc_harvest_config; 855 } 856 857 /* ================================================== */ 858 859 struct ip_hw_instance { 860 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */ 861 862 int hw_id; 863 u8 num_instance; 864 u8 major, minor, revision; 865 u8 harvest; 866 867 int num_base_addresses; 868 u32 base_addr[] __counted_by(num_base_addresses); 869 }; 870 871 struct ip_hw_id { 872 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */ 873 int hw_id; 874 }; 875 876 struct ip_die_entry { 877 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */ 878 u16 num_ips; 879 }; 880 881 /* -------------------------------------------------- */ 882 883 struct ip_hw_instance_attr { 884 struct attribute attr; 885 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf); 886 }; 887 888 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf) 889 { 890 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id); 891 } 892 893 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf) 894 { 895 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance); 896 } 897 898 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf) 899 { 900 return sysfs_emit(buf, "%d\n", ip_hw_instance->major); 901 } 902 903 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf) 904 { 905 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor); 906 } 907 908 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf) 909 { 910 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision); 911 } 912 913 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf) 914 { 915 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest); 916 } 917 918 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf) 919 { 920 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses); 921 } 922 923 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) 924 { 925 ssize_t at; 926 int ii; 927 928 for (at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 929 /* Here we satisfy the condition that, at + size <= PAGE_SIZE. 930 */ 931 if (at + 12 > PAGE_SIZE) 932 break; 933 at += sysfs_emit_at(buf, at, "0x%08X\n", 934 ip_hw_instance->base_addr[ii]); 935 } 936 937 return at; 938 } 939 940 static struct ip_hw_instance_attr ip_hw_attr[] = { 941 __ATTR_RO(hw_id), 942 __ATTR_RO(num_instance), 943 __ATTR_RO(major), 944 __ATTR_RO(minor), 945 __ATTR_RO(revision), 946 __ATTR_RO(harvest), 947 __ATTR_RO(num_base_addresses), 948 __ATTR_RO(base_addr), 949 }; 950 951 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; 952 ATTRIBUTE_GROUPS(ip_hw_instance); 953 954 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) 955 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) 956 957 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj, 958 struct attribute *attr, 959 char *buf) 960 { 961 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 962 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr); 963 964 if (!ip_hw_attr->show) 965 return -EIO; 966 967 return ip_hw_attr->show(ip_hw_instance, buf); 968 } 969 970 static const struct sysfs_ops ip_hw_instance_sysfs_ops = { 971 .show = ip_hw_instance_attr_show, 972 }; 973 974 static void ip_hw_instance_release(struct kobject *kobj) 975 { 976 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 977 978 kfree(ip_hw_instance); 979 } 980 981 static const struct kobj_type ip_hw_instance_ktype = { 982 .release = ip_hw_instance_release, 983 .sysfs_ops = &ip_hw_instance_sysfs_ops, 984 .default_groups = ip_hw_instance_groups, 985 }; 986 987 /* -------------------------------------------------- */ 988 989 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset) 990 991 static void ip_hw_id_release(struct kobject *kobj) 992 { 993 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj); 994 995 if (!list_empty(&ip_hw_id->hw_id_kset.list)) 996 DRM_ERROR("ip_hw_id->hw_id_kset is not empty"); 997 kfree(ip_hw_id); 998 } 999 1000 static const struct kobj_type ip_hw_id_ktype = { 1001 .release = ip_hw_id_release, 1002 .sysfs_ops = &kobj_sysfs_ops, 1003 }; 1004 1005 /* -------------------------------------------------- */ 1006 1007 static void die_kobj_release(struct kobject *kobj); 1008 static void ip_disc_release(struct kobject *kobj); 1009 1010 struct ip_die_entry_attribute { 1011 struct attribute attr; 1012 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf); 1013 }; 1014 1015 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr) 1016 1017 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf) 1018 { 1019 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips); 1020 } 1021 1022 /* If there are more ip_die_entry attrs, other than the number of IPs, 1023 * we can make this intro an array of attrs, and then initialize 1024 * ip_die_entry_attrs in a loop. 1025 */ 1026 static struct ip_die_entry_attribute num_ips_attr = 1027 __ATTR_RO(num_ips); 1028 1029 static struct attribute *ip_die_entry_attrs[] = { 1030 &num_ips_attr.attr, 1031 NULL, 1032 }; 1033 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ 1034 1035 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) 1036 1037 static ssize_t ip_die_entry_attr_show(struct kobject *kobj, 1038 struct attribute *attr, 1039 char *buf) 1040 { 1041 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr); 1042 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 1043 1044 if (!ip_die_entry_attr->show) 1045 return -EIO; 1046 1047 return ip_die_entry_attr->show(ip_die_entry, buf); 1048 } 1049 1050 static void ip_die_entry_release(struct kobject *kobj) 1051 { 1052 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 1053 1054 if (!list_empty(&ip_die_entry->ip_kset.list)) 1055 DRM_ERROR("ip_die_entry->ip_kset is not empty"); 1056 kfree(ip_die_entry); 1057 } 1058 1059 static const struct sysfs_ops ip_die_entry_sysfs_ops = { 1060 .show = ip_die_entry_attr_show, 1061 }; 1062 1063 static const struct kobj_type ip_die_entry_ktype = { 1064 .release = ip_die_entry_release, 1065 .sysfs_ops = &ip_die_entry_sysfs_ops, 1066 .default_groups = ip_die_entry_groups, 1067 }; 1068 1069 static const struct kobj_type die_kobj_ktype = { 1070 .release = die_kobj_release, 1071 .sysfs_ops = &kobj_sysfs_ops, 1072 }; 1073 1074 static const struct kobj_type ip_discovery_ktype = { 1075 .release = ip_disc_release, 1076 .sysfs_ops = &kobj_sysfs_ops, 1077 }; 1078 1079 struct ip_discovery_top { 1080 struct kobject kobj; /* ip_discovery/ */ 1081 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */ 1082 struct amdgpu_device *adev; 1083 }; 1084 1085 static void die_kobj_release(struct kobject *kobj) 1086 { 1087 struct ip_discovery_top *ip_top = container_of(to_kset(kobj), 1088 struct ip_discovery_top, 1089 die_kset); 1090 if (!list_empty(&ip_top->die_kset.list)) 1091 DRM_ERROR("ip_top->die_kset is not empty"); 1092 } 1093 1094 static void ip_disc_release(struct kobject *kobj) 1095 { 1096 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top, 1097 kobj); 1098 struct amdgpu_device *adev = ip_top->adev; 1099 1100 kfree(ip_top); 1101 adev->discovery.ip_top = NULL; 1102 } 1103 1104 static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev, 1105 uint16_t hw_id, uint8_t inst) 1106 { 1107 uint8_t harvest = 0; 1108 1109 /* Until a uniform way is figured, get mask based on hwid */ 1110 switch (hw_id) { 1111 case VCN_HWID: 1112 /* VCN vs UVD+VCE */ 1113 if (!amdgpu_ip_version(adev, VCE_HWIP, 0)) 1114 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0; 1115 break; 1116 case DMU_HWID: 1117 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK) 1118 harvest = 0x1; 1119 break; 1120 case UMC_HWID: 1121 /* TODO: It needs another parsing; for now, ignore.*/ 1122 break; 1123 case GC_HWID: 1124 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; 1125 break; 1126 case SDMA0_HWID: 1127 harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0; 1128 break; 1129 default: 1130 break; 1131 } 1132 1133 return harvest; 1134 } 1135 1136 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, 1137 struct ip_die_entry *ip_die_entry, 1138 const size_t _ip_offset, const int num_ips, 1139 bool reg_base_64) 1140 { 1141 uint8_t *discovery_bin = adev->discovery.bin; 1142 int ii, jj, kk, res; 1143 uint16_t hw_id; 1144 uint8_t inst; 1145 1146 DRM_DEBUG("num_ips:%d", num_ips); 1147 1148 /* Find all IPs of a given HW ID, and add their instance to 1149 * #die/#hw_id/#instance/<attributes> 1150 */ 1151 for (ii = 0; ii < HW_ID_MAX; ii++) { 1152 struct ip_hw_id *ip_hw_id = NULL; 1153 size_t ip_offset = _ip_offset; 1154 1155 for (jj = 0; jj < num_ips; jj++) { 1156 struct ip_v4 *ip; 1157 struct ip_hw_instance *ip_hw_instance; 1158 1159 ip = (struct ip_v4 *)(discovery_bin + ip_offset); 1160 inst = ip->instance_number; 1161 hw_id = le16_to_cpu(ip->hw_id); 1162 if (amdgpu_discovery_validate_ip(adev, inst, hw_id) || 1163 hw_id != ii) 1164 goto next_ip; 1165 1166 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset); 1167 1168 /* We have a hw_id match; register the hw 1169 * block if not yet registered. 1170 */ 1171 if (!ip_hw_id) { 1172 ip_hw_id = kzalloc_obj(*ip_hw_id); 1173 if (!ip_hw_id) 1174 return -ENOMEM; 1175 ip_hw_id->hw_id = ii; 1176 1177 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii); 1178 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset; 1179 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype; 1180 res = kset_register(&ip_hw_id->hw_id_kset); 1181 if (res) { 1182 DRM_ERROR("Couldn't register ip_hw_id kset"); 1183 kfree(ip_hw_id); 1184 return res; 1185 } 1186 if (hw_id_names[ii]) { 1187 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj, 1188 &ip_hw_id->hw_id_kset.kobj, 1189 hw_id_names[ii]); 1190 if (res) { 1191 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n", 1192 hw_id_names[ii], 1193 kobject_name(&ip_die_entry->ip_kset.kobj)); 1194 } 1195 } 1196 } 1197 1198 /* Now register its instance. 1199 */ 1200 ip_hw_instance = kzalloc_flex(*ip_hw_instance, 1201 base_addr, 1202 ip->num_base_address); 1203 if (!ip_hw_instance) { 1204 DRM_ERROR("no memory for ip_hw_instance"); 1205 return -ENOMEM; 1206 } 1207 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */ 1208 ip_hw_instance->num_instance = ip->instance_number; 1209 ip_hw_instance->major = ip->major; 1210 ip_hw_instance->minor = ip->minor; 1211 ip_hw_instance->revision = ip->revision; 1212 ip_hw_instance->harvest = 1213 amdgpu_discovery_get_harvest_info( 1214 adev, ip_hw_instance->hw_id, 1215 ip_hw_instance->num_instance); 1216 ip_hw_instance->num_base_addresses = ip->num_base_address; 1217 1218 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) 1219 ip_hw_instance->base_addr[kk] = ip->base_address[kk]; 1220 1221 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); 1222 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; 1223 res = kobject_add(&ip_hw_instance->kobj, NULL, 1224 "%d", ip_hw_instance->num_instance); 1225 next_ip: 1226 if (reg_base_64) 1227 ip_offset += struct_size(ip, base_address_64, 1228 ip->num_base_address); 1229 else 1230 ip_offset += struct_size(ip, base_address, 1231 ip->num_base_address); 1232 } 1233 } 1234 1235 return 0; 1236 } 1237 1238 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) 1239 { 1240 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1241 uint8_t *discovery_bin = adev->discovery.bin; 1242 struct table_info *info; 1243 struct ip_discovery_header *ihdr; 1244 struct die_header *dhdr; 1245 struct kset *die_kset = &ip_top->die_kset; 1246 u16 num_dies, die_offset, num_ips; 1247 size_t ip_offset; 1248 int ii, res; 1249 1250 res = amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY); 1251 if (res) 1252 return res; 1253 ihdr = (struct ip_discovery_header 1254 *)(discovery_bin + 1255 le16_to_cpu(info->offset)); 1256 num_dies = le16_to_cpu(ihdr->num_dies); 1257 1258 DRM_DEBUG("number of dies: %d\n", num_dies); 1259 1260 for (ii = 0; ii < num_dies; ii++) { 1261 struct ip_die_entry *ip_die_entry; 1262 1263 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); 1264 dhdr = (struct die_header *)(discovery_bin + die_offset); 1265 num_ips = le16_to_cpu(dhdr->num_ips); 1266 ip_offset = die_offset + sizeof(*dhdr); 1267 1268 /* Add the die to the kset. 1269 * 1270 * dhdr->die_id == ii, which was checked in 1271 * amdgpu_discovery_reg_base_init(). 1272 */ 1273 1274 ip_die_entry = kzalloc_obj(*ip_die_entry); 1275 if (!ip_die_entry) 1276 return -ENOMEM; 1277 1278 ip_die_entry->num_ips = num_ips; 1279 1280 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id)); 1281 ip_die_entry->ip_kset.kobj.kset = die_kset; 1282 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype; 1283 res = kset_register(&ip_die_entry->ip_kset); 1284 if (res) { 1285 DRM_ERROR("Couldn't register ip_die_entry kset"); 1286 kfree(ip_die_entry); 1287 return res; 1288 } 1289 1290 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips, !!ihdr->base_addr_64_bit); 1291 } 1292 1293 return 0; 1294 } 1295 1296 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) 1297 { 1298 uint8_t *discovery_bin = adev->discovery.bin; 1299 struct ip_discovery_top *ip_top; 1300 struct kset *die_kset; 1301 int res, ii; 1302 1303 if (!discovery_bin) 1304 return -EINVAL; 1305 1306 ip_top = kzalloc_obj(*ip_top); 1307 if (!ip_top) 1308 return -ENOMEM; 1309 1310 ip_top->adev = adev; 1311 adev->discovery.ip_top = ip_top; 1312 res = kobject_init_and_add(&ip_top->kobj, &ip_discovery_ktype, 1313 &adev->dev->kobj, "ip_discovery"); 1314 if (res) { 1315 DRM_ERROR("Couldn't init and add ip_discovery/"); 1316 goto Err; 1317 } 1318 1319 die_kset = &ip_top->die_kset; 1320 kobject_set_name(&die_kset->kobj, "%s", "die"); 1321 die_kset->kobj.parent = &ip_top->kobj; 1322 die_kset->kobj.ktype = &die_kobj_ktype; 1323 res = kset_register(&ip_top->die_kset); 1324 if (res) { 1325 DRM_ERROR("Couldn't register die_kset"); 1326 goto Err; 1327 } 1328 1329 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++) 1330 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr; 1331 ip_hw_instance_attrs[ii] = NULL; 1332 1333 res = amdgpu_discovery_sysfs_recurse(adev); 1334 1335 return res; 1336 Err: 1337 kobject_put(&ip_top->kobj); 1338 return res; 1339 } 1340 1341 /* -------------------------------------------------- */ 1342 1343 #define list_to_kobj(el) container_of(el, struct kobject, entry) 1344 1345 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id) 1346 { 1347 struct list_head *el, *tmp; 1348 struct kset *hw_id_kset; 1349 1350 hw_id_kset = &ip_hw_id->hw_id_kset; 1351 spin_lock(&hw_id_kset->list_lock); 1352 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) { 1353 list_del_init(el); 1354 spin_unlock(&hw_id_kset->list_lock); 1355 /* kobject is embedded in ip_hw_instance */ 1356 kobject_put(list_to_kobj(el)); 1357 spin_lock(&hw_id_kset->list_lock); 1358 } 1359 spin_unlock(&hw_id_kset->list_lock); 1360 kobject_put(&ip_hw_id->hw_id_kset.kobj); 1361 } 1362 1363 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry) 1364 { 1365 struct list_head *el, *tmp; 1366 struct kset *ip_kset; 1367 1368 ip_kset = &ip_die_entry->ip_kset; 1369 spin_lock(&ip_kset->list_lock); 1370 list_for_each_prev_safe(el, tmp, &ip_kset->list) { 1371 list_del_init(el); 1372 spin_unlock(&ip_kset->list_lock); 1373 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el))); 1374 spin_lock(&ip_kset->list_lock); 1375 } 1376 spin_unlock(&ip_kset->list_lock); 1377 kobject_put(&ip_die_entry->ip_kset.kobj); 1378 } 1379 1380 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) 1381 { 1382 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1383 struct list_head *el, *tmp; 1384 struct kset *die_kset; 1385 1386 die_kset = &ip_top->die_kset; 1387 spin_lock(&die_kset->list_lock); 1388 list_for_each_prev_safe(el, tmp, &die_kset->list) { 1389 list_del_init(el); 1390 spin_unlock(&die_kset->list_lock); 1391 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 1392 spin_lock(&die_kset->list_lock); 1393 } 1394 spin_unlock(&die_kset->list_lock); 1395 kobject_put(&ip_top->die_kset.kobj); 1396 kobject_put(&ip_top->kobj); 1397 } 1398 1399 /* devcoredump support */ 1400 void amdgpu_discovery_dump(struct amdgpu_device *adev, struct drm_printer *p) 1401 { 1402 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1403 struct ip_die_entry *ip_die_entry; 1404 struct list_head *el_die, *el_hw_id, *el_hw_inst; 1405 struct ip_hw_id *hw_id; 1406 struct kset *die_kset; 1407 struct ip_hw_instance *ip_inst; 1408 int i = 0, j; 1409 1410 die_kset = &ip_top->die_kset; 1411 1412 drm_printf(p, "\nHW IP Discovery\n"); 1413 spin_lock(&die_kset->list_lock); 1414 list_for_each(el_die, &die_kset->list) { 1415 drm_printf(p, "die %d\n", i++); 1416 ip_die_entry = to_ip_die_entry(list_to_kobj(el_die)); 1417 1418 list_for_each(el_hw_id, &ip_die_entry->ip_kset.list) { 1419 hw_id = to_ip_hw_id(list_to_kobj(el_hw_id)); 1420 drm_printf(p, "hw_id %d %s\n", hw_id->hw_id, hw_id_names[hw_id->hw_id]); 1421 1422 list_for_each(el_hw_inst, &hw_id->hw_id_kset.list) { 1423 ip_inst = to_ip_hw_instance(list_to_kobj(el_hw_inst)); 1424 drm_printf(p, "\tinstance %d\n", ip_inst->num_instance); 1425 drm_printf(p, "\tmajor %d\n", ip_inst->major); 1426 drm_printf(p, "\tminor %d\n", ip_inst->minor); 1427 drm_printf(p, "\trevision %d\n", ip_inst->revision); 1428 drm_printf(p, "\tharvest 0x%01X\n", ip_inst->harvest); 1429 drm_printf(p, "\tnum_base_addresses %d\n", 1430 ip_inst->num_base_addresses); 1431 for (j = 0; j < ip_inst->num_base_addresses; j++) 1432 drm_printf(p, "\tbase_addr[%d] 0x%08X\n", 1433 j, ip_inst->base_addr[j]); 1434 } 1435 } 1436 } 1437 spin_unlock(&die_kset->list_lock); 1438 } 1439 1440 1441 /* ================================================== */ 1442 1443 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 1444 { 1445 uint8_t num_base_address, subrev, variant; 1446 struct table_info *info; 1447 struct ip_discovery_header *ihdr; 1448 struct die_header *dhdr; 1449 uint8_t *discovery_bin; 1450 struct ip_v4 *ip; 1451 uint16_t die_offset; 1452 uint16_t ip_offset; 1453 uint16_t num_dies; 1454 uint32_t wafl_ver; 1455 uint16_t num_ips; 1456 uint16_t hw_id; 1457 uint8_t inst; 1458 int hw_ip; 1459 int i, j, k; 1460 int r; 1461 1462 r = amdgpu_discovery_init(adev); 1463 if (r) 1464 return r; 1465 discovery_bin = adev->discovery.bin; 1466 wafl_ver = 0; 1467 adev->gfx.xcc_mask = 0; 1468 adev->sdma.sdma_mask = 0; 1469 adev->vcn.inst_mask = 0; 1470 adev->jpeg.inst_mask = 0; 1471 r = amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY); 1472 if (r) 1473 return r; 1474 ihdr = (struct ip_discovery_header 1475 *)(discovery_bin + 1476 le16_to_cpu(info->offset)); 1477 num_dies = le16_to_cpu(ihdr->num_dies); 1478 1479 DRM_DEBUG("number of dies: %d\n", num_dies); 1480 1481 for (i = 0; i < num_dies; i++) { 1482 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1483 dhdr = (struct die_header *)(discovery_bin + die_offset); 1484 num_ips = le16_to_cpu(dhdr->num_ips); 1485 ip_offset = die_offset + sizeof(*dhdr); 1486 1487 if (le16_to_cpu(dhdr->die_id) != i) { 1488 DRM_ERROR("invalid die id %d, expected %d\n", 1489 le16_to_cpu(dhdr->die_id), i); 1490 return -EINVAL; 1491 } 1492 1493 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 1494 le16_to_cpu(dhdr->die_id), num_ips); 1495 1496 for (j = 0; j < num_ips; j++) { 1497 ip = (struct ip_v4 *)(discovery_bin + ip_offset); 1498 1499 inst = ip->instance_number; 1500 hw_id = le16_to_cpu(ip->hw_id); 1501 if (amdgpu_discovery_validate_ip(adev, inst, hw_id)) 1502 goto next_ip; 1503 1504 num_base_address = ip->num_base_address; 1505 1506 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 1507 hw_id_names[le16_to_cpu(ip->hw_id)], 1508 le16_to_cpu(ip->hw_id), 1509 ip->instance_number, 1510 ip->major, ip->minor, 1511 ip->revision); 1512 1513 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 1514 /* Bit [5:0]: original revision value 1515 * Bit [7:6]: en/decode capability: 1516 * 0b00 : VCN function normally 1517 * 0b10 : encode is disabled 1518 * 0b01 : decode is disabled 1519 */ 1520 if (adev->vcn.num_vcn_inst < 1521 AMDGPU_MAX_VCN_INSTANCES) { 1522 adev->vcn.inst[adev->vcn.num_vcn_inst].vcn_config = 1523 ip->revision & 0xc0; 1524 adev->vcn.num_vcn_inst++; 1525 adev->vcn.inst_mask |= 1526 (1U << ip->instance_number); 1527 adev->jpeg.inst_mask |= 1528 (1U << ip->instance_number); 1529 } else { 1530 dev_err(adev->dev, "Too many VCN instances: %d vs %d\n", 1531 adev->vcn.num_vcn_inst + 1, 1532 AMDGPU_MAX_VCN_INSTANCES); 1533 } 1534 ip->revision &= ~0xc0; 1535 } 1536 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 1537 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 1538 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 1539 le16_to_cpu(ip->hw_id) == SDMA3_HWID) { 1540 if (adev->sdma.num_instances < 1541 AMDGPU_MAX_SDMA_INSTANCES) { 1542 adev->sdma.num_instances++; 1543 adev->sdma.sdma_mask |= 1544 (1U << ip->instance_number); 1545 } else { 1546 dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n", 1547 adev->sdma.num_instances + 1, 1548 AMDGPU_MAX_SDMA_INSTANCES); 1549 } 1550 } 1551 1552 if (le16_to_cpu(ip->hw_id) == VPE_HWID) { 1553 if (adev->vpe.num_instances < AMDGPU_MAX_VPE_INSTANCES) 1554 adev->vpe.num_instances++; 1555 else 1556 dev_err(adev->dev, "Too many VPE instances: %d vs %d\n", 1557 adev->vpe.num_instances + 1, 1558 AMDGPU_MAX_VPE_INSTANCES); 1559 } 1560 1561 if (le16_to_cpu(ip->hw_id) == UMC_HWID) { 1562 adev->gmc.num_umc++; 1563 adev->umc.node_inst_num++; 1564 } 1565 1566 if (le16_to_cpu(ip->hw_id) == GC_HWID) 1567 adev->gfx.xcc_mask |= 1568 (1U << ip->instance_number); 1569 1570 if (!wafl_ver && le16_to_cpu(ip->hw_id) == WAFLC_HWID) 1571 wafl_ver = IP_VERSION_FULL(ip->major, ip->minor, 1572 ip->revision, 0, 0); 1573 1574 for (k = 0; k < num_base_address; k++) { 1575 /* 1576 * convert the endianness of base addresses in place, 1577 * so that we don't need to convert them when accessing adev->reg_offset. 1578 */ 1579 if (ihdr->base_addr_64_bit) 1580 /* Truncate the 64bit base address from ip discovery 1581 * and only store lower 32bit ip base in reg_offset[]. 1582 * Bits > 32 follows ASIC specific format, thus just 1583 * discard them and handle it within specific ASIC. 1584 * By this way reg_offset[] and related helpers can 1585 * stay unchanged. 1586 * The base address is in dwords, thus clear the 1587 * highest 2 bits to store. 1588 */ 1589 ip->base_address[k] = 1590 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF; 1591 else 1592 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 1593 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 1594 } 1595 1596 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 1597 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) && 1598 hw_id_map[hw_ip] != 0) { 1599 DRM_DEBUG("set register base offset for %s\n", 1600 hw_id_names[le16_to_cpu(ip->hw_id)]); 1601 adev->reg_offset[hw_ip][ip->instance_number] = 1602 ip->base_address; 1603 /* Instance support is somewhat inconsistent. 1604 * SDMA is a good example. Sienna cichlid has 4 total 1605 * SDMA instances, each enumerated separately (HWIDs 1606 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 1607 * but they are enumerated as multiple instances of the 1608 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 1609 * example. On most chips there are multiple instances 1610 * with the same HWID. 1611 */ 1612 1613 if (ihdr->version < 3) { 1614 subrev = 0; 1615 variant = 0; 1616 } else { 1617 subrev = ip->sub_revision; 1618 variant = ip->variant; 1619 } 1620 1621 adev->ip_versions[hw_ip] 1622 [ip->instance_number] = 1623 IP_VERSION_FULL(ip->major, 1624 ip->minor, 1625 ip->revision, 1626 variant, 1627 subrev); 1628 } 1629 } 1630 1631 next_ip: 1632 if (ihdr->base_addr_64_bit) 1633 ip_offset += struct_size(ip, base_address_64, ip->num_base_address); 1634 else 1635 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1636 } 1637 } 1638 1639 if (wafl_ver && !adev->ip_versions[XGMI_HWIP][0]) 1640 adev->ip_versions[XGMI_HWIP][0] = wafl_ver; 1641 1642 return 0; 1643 } 1644 1645 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 1646 { 1647 uint8_t *discovery_bin = adev->discovery.bin; 1648 struct ip_discovery_header *ihdr; 1649 struct table_info *info; 1650 int vcn_harvest_count = 0; 1651 int umc_harvest_count = 0; 1652 uint16_t ihdr_ver; 1653 1654 if (amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY)) 1655 return; 1656 ihdr = (struct ip_discovery_header *)(discovery_bin + 1657 le16_to_cpu(info->offset)); 1658 ihdr_ver = le16_to_cpu(ihdr->version); 1659 /* 1660 * Harvest table does not fit Navi1x and legacy GPUs, 1661 * so read harvest bit per IP data structure to set 1662 * harvest configuration. 1663 */ 1664 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 2, 0) && 1665 ihdr_ver <= 2) { 1666 if ((adev->pdev->device == 0x731E && 1667 (adev->pdev->revision == 0xC6 || 1668 adev->pdev->revision == 0xC7)) || 1669 (adev->pdev->device == 0x7340 && 1670 adev->pdev->revision == 0xC9) || 1671 (adev->pdev->device == 0x7360 && 1672 adev->pdev->revision == 0xC7)) 1673 amdgpu_discovery_read_harvest_bit_per_ip(adev, 1674 &vcn_harvest_count); 1675 } else { 1676 amdgpu_discovery_read_from_harvest_table(adev, 1677 &vcn_harvest_count, 1678 &umc_harvest_count); 1679 } 1680 1681 amdgpu_discovery_harvest_config_quirk(adev); 1682 1683 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 1684 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 1685 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 1686 } 1687 1688 if (umc_harvest_count < adev->gmc.num_umc) { 1689 adev->gmc.num_umc -= umc_harvest_count; 1690 } 1691 } 1692 1693 union gc_info { 1694 struct gc_info_v1_0 v1; 1695 struct gc_info_v1_1 v1_1; 1696 struct gc_info_v1_2 v1_2; 1697 struct gc_info_v1_3 v1_3; 1698 struct gc_info_v2_0 v2; 1699 struct gc_info_v2_1 v2_1; 1700 }; 1701 1702 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 1703 { 1704 uint8_t *discovery_bin = adev->discovery.bin; 1705 struct table_info *info; 1706 union gc_info *gc_info; 1707 u16 offset; 1708 1709 if (!discovery_bin) { 1710 DRM_ERROR("ip discovery uninitialized\n"); 1711 return -EINVAL; 1712 } 1713 1714 if (amdgpu_discovery_get_table_info(adev, &info, GC)) 1715 return -EINVAL; 1716 offset = le16_to_cpu(info->offset); 1717 1718 if (!offset) 1719 return 0; 1720 1721 gc_info = (union gc_info *)(discovery_bin + offset); 1722 1723 switch (le16_to_cpu(gc_info->v1.header.version_major)) { 1724 case 1: 1725 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); 1726 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 1727 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); 1728 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1729 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); 1730 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); 1731 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); 1732 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); 1733 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); 1734 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); 1735 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); 1736 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); 1737 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); 1738 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); 1739 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); 1740 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / 1741 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1742 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); 1743 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 1) { 1744 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa); 1745 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface); 1746 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps); 1747 } 1748 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 2) { 1749 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg); 1750 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size); 1751 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp); 1752 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc); 1753 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc); 1754 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa); 1755 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance); 1756 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu); 1757 } 1758 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 3) { 1759 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v1_3.gc_tcp_size_per_cu); 1760 adev->gfx.config.gc_tcp_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcp_cache_line_size); 1761 adev->gfx.config.gc_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_size_per_sqc); 1762 adev->gfx.config.gc_instruction_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_line_size); 1763 adev->gfx.config.gc_scalar_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_size_per_sqc); 1764 adev->gfx.config.gc_scalar_data_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_line_size); 1765 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v1_3.gc_tcc_size); 1766 adev->gfx.config.gc_tcc_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcc_cache_line_size); 1767 } 1768 break; 1769 case 2: 1770 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); 1771 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); 1772 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1773 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); 1774 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); 1775 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); 1776 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); 1777 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); 1778 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); 1779 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); 1780 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); 1781 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); 1782 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); 1783 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); 1784 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / 1785 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1786 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); 1787 if (le16_to_cpu(gc_info->v2.header.version_minor) == 1) { 1788 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh); 1789 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu); 1790 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XCD */ 1791 adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc); 1792 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_cache_size_per_sqc); 1793 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_size_per_sqc); 1794 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */ 1795 } 1796 break; 1797 default: 1798 dev_err(adev->dev, 1799 "Unhandled GC info table %d.%d\n", 1800 le16_to_cpu(gc_info->v1.header.version_major), 1801 le16_to_cpu(gc_info->v1.header.version_minor)); 1802 return -EINVAL; 1803 } 1804 return 0; 1805 } 1806 1807 union mall_info { 1808 struct mall_info_v1_0 v1; 1809 struct mall_info_v2_0 v2; 1810 }; 1811 1812 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) 1813 { 1814 uint8_t *discovery_bin = adev->discovery.bin; 1815 struct table_info *info; 1816 union mall_info *mall_info; 1817 u32 u, mall_size_per_umc, m_s_present, half_use; 1818 u64 mall_size; 1819 u16 offset; 1820 1821 if (!discovery_bin) { 1822 DRM_ERROR("ip discovery uninitialized\n"); 1823 return -EINVAL; 1824 } 1825 1826 if (amdgpu_discovery_get_table_info(adev, &info, MALL_INFO)) 1827 return -EINVAL; 1828 offset = le16_to_cpu(info->offset); 1829 1830 if (!offset) 1831 return 0; 1832 1833 mall_info = (union mall_info *)(discovery_bin + offset); 1834 1835 switch (le16_to_cpu(mall_info->v1.header.version_major)) { 1836 case 1: 1837 mall_size = 0; 1838 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m); 1839 m_s_present = le32_to_cpu(mall_info->v1.m_s_present); 1840 half_use = le32_to_cpu(mall_info->v1.m_half_use); 1841 for (u = 0; u < adev->gmc.num_umc; u++) { 1842 if (m_s_present & (1 << u)) 1843 mall_size += mall_size_per_umc * 2; 1844 else if (half_use & (1 << u)) 1845 mall_size += mall_size_per_umc / 2; 1846 else 1847 mall_size += mall_size_per_umc; 1848 } 1849 adev->gmc.mall_size = mall_size; 1850 adev->gmc.m_half_use = half_use; 1851 break; 1852 case 2: 1853 mall_size_per_umc = le32_to_cpu(mall_info->v2.mall_size_per_umc); 1854 adev->gmc.mall_size = (uint64_t)mall_size_per_umc * adev->gmc.num_umc; 1855 break; 1856 default: 1857 dev_err(adev->dev, 1858 "Unhandled MALL info table %d.%d\n", 1859 le16_to_cpu(mall_info->v1.header.version_major), 1860 le16_to_cpu(mall_info->v1.header.version_minor)); 1861 return -EINVAL; 1862 } 1863 return 0; 1864 } 1865 1866 union vcn_info { 1867 struct vcn_info_v1_0 v1; 1868 }; 1869 1870 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) 1871 { 1872 uint8_t *discovery_bin = adev->discovery.bin; 1873 struct table_info *info; 1874 union vcn_info *vcn_info; 1875 u16 offset; 1876 int v; 1877 1878 if (!discovery_bin) { 1879 DRM_ERROR("ip discovery uninitialized\n"); 1880 return -EINVAL; 1881 } 1882 1883 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1884 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES 1885 * but that may change in the future with new GPUs so keep this 1886 * check for defensive purposes. 1887 */ 1888 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { 1889 dev_err(adev->dev, "invalid vcn instances\n"); 1890 return -EINVAL; 1891 } 1892 1893 if (amdgpu_discovery_get_table_info(adev, &info, VCN_INFO)) 1894 return -EINVAL; 1895 offset = le16_to_cpu(info->offset); 1896 1897 if (!offset) 1898 return 0; 1899 1900 vcn_info = (union vcn_info *)(discovery_bin + offset); 1901 1902 switch (le16_to_cpu(vcn_info->v1.header.version_major)) { 1903 case 1: 1904 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1905 * so this won't overflow. 1906 */ 1907 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { 1908 adev->vcn.inst[v].vcn_codec_disable_mask = 1909 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits); 1910 } 1911 break; 1912 default: 1913 dev_err(adev->dev, 1914 "Unhandled VCN info table %d.%d\n", 1915 le16_to_cpu(vcn_info->v1.header.version_major), 1916 le16_to_cpu(vcn_info->v1.header.version_minor)); 1917 return -EINVAL; 1918 } 1919 return 0; 1920 } 1921 1922 union nps_info { 1923 struct nps_info_v1_0 v1; 1924 }; 1925 1926 static int amdgpu_discovery_refresh_nps_info(struct amdgpu_device *adev, 1927 union nps_info *nps_data) 1928 { 1929 uint64_t vram_size, pos, offset; 1930 struct nps_info_header *nhdr; 1931 struct binary_header bhdr; 1932 struct binary_header_v2 bhdrv2; 1933 uint16_t checksum; 1934 1935 vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 1936 pos = vram_size - DISCOVERY_TMR_OFFSET; 1937 amdgpu_device_vram_access(adev, pos, &bhdr, sizeof(bhdr), false); 1938 1939 switch (bhdr.version_major) { 1940 case 2: 1941 amdgpu_device_vram_access(adev, pos, &bhdrv2, sizeof(bhdrv2), false); 1942 offset = le16_to_cpu(bhdrv2.table_list[NPS_INFO].offset); 1943 checksum = le16_to_cpu(bhdrv2.table_list[NPS_INFO].checksum); 1944 break; 1945 case 1: 1946 offset = le16_to_cpu(bhdr.table_list[NPS_INFO].offset); 1947 checksum = le16_to_cpu(bhdr.table_list[NPS_INFO].checksum); 1948 break; 1949 default: 1950 return -EINVAL; 1951 } 1952 1953 amdgpu_device_vram_access(adev, (pos + offset), nps_data, 1954 sizeof(*nps_data), false); 1955 1956 nhdr = (struct nps_info_header *)(nps_data); 1957 if (!amdgpu_discovery_verify_checksum(adev, (uint8_t *)nps_data, 1958 le32_to_cpu(nhdr->size_bytes), 1959 checksum)) { 1960 dev_err(adev->dev, "nps data refresh, checksum mismatch\n"); 1961 return -EINVAL; 1962 } 1963 1964 return 0; 1965 } 1966 1967 int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, 1968 uint32_t *nps_type, 1969 struct amdgpu_gmc_memrange **ranges, 1970 int *range_cnt, bool refresh) 1971 { 1972 uint8_t *discovery_bin = adev->discovery.bin; 1973 struct amdgpu_gmc_memrange *mem_ranges; 1974 struct table_info *info; 1975 union nps_info *nps_info; 1976 union nps_info nps_data; 1977 u16 offset; 1978 int i, r; 1979 1980 if (!nps_type || !range_cnt || !ranges) 1981 return -EINVAL; 1982 1983 if (refresh) { 1984 r = amdgpu_discovery_refresh_nps_info(adev, &nps_data); 1985 if (r) 1986 return r; 1987 nps_info = &nps_data; 1988 } else { 1989 if (!discovery_bin) { 1990 dev_err(adev->dev, 1991 "fetch mem range failed, ip discovery uninitialized\n"); 1992 return -EINVAL; 1993 } 1994 1995 if (amdgpu_discovery_get_table_info(adev, &info, NPS_INFO)) 1996 return -EINVAL; 1997 offset = le16_to_cpu(info->offset); 1998 1999 if (!offset) 2000 return -ENOENT; 2001 2002 /* If verification fails, return as if NPS table doesn't exist */ 2003 if (amdgpu_discovery_verify_npsinfo(adev, info)) 2004 return -ENOENT; 2005 2006 nps_info = (union nps_info *)(discovery_bin + offset); 2007 } 2008 2009 switch (le16_to_cpu(nps_info->v1.header.version_major)) { 2010 case 1: 2011 mem_ranges = kvzalloc_objs(*mem_ranges, nps_info->v1.count); 2012 if (!mem_ranges) 2013 return -ENOMEM; 2014 *nps_type = nps_info->v1.nps_type; 2015 *range_cnt = nps_info->v1.count; 2016 for (i = 0; i < *range_cnt; i++) { 2017 mem_ranges[i].base_address = 2018 nps_info->v1.instance_info[i].base_address; 2019 mem_ranges[i].limit_address = 2020 nps_info->v1.instance_info[i].limit_address; 2021 mem_ranges[i].nid_mask = -1; 2022 mem_ranges[i].flags = 0; 2023 } 2024 *ranges = mem_ranges; 2025 break; 2026 default: 2027 dev_err(adev->dev, "Unhandled NPS info table %d.%d\n", 2028 le16_to_cpu(nps_info->v1.header.version_major), 2029 le16_to_cpu(nps_info->v1.header.version_minor)); 2030 return -EINVAL; 2031 } 2032 2033 return 0; 2034 } 2035 2036 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 2037 { 2038 /* what IP to use for this? */ 2039 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2040 case IP_VERSION(9, 0, 1): 2041 case IP_VERSION(9, 1, 0): 2042 case IP_VERSION(9, 2, 1): 2043 case IP_VERSION(9, 2, 2): 2044 case IP_VERSION(9, 3, 0): 2045 case IP_VERSION(9, 4, 0): 2046 case IP_VERSION(9, 4, 1): 2047 case IP_VERSION(9, 4, 2): 2048 case IP_VERSION(9, 4, 3): 2049 case IP_VERSION(9, 4, 4): 2050 case IP_VERSION(9, 5, 0): 2051 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 2052 break; 2053 case IP_VERSION(10, 1, 10): 2054 case IP_VERSION(10, 1, 1): 2055 case IP_VERSION(10, 1, 2): 2056 case IP_VERSION(10, 1, 3): 2057 case IP_VERSION(10, 1, 4): 2058 case IP_VERSION(10, 3, 0): 2059 case IP_VERSION(10, 3, 1): 2060 case IP_VERSION(10, 3, 2): 2061 case IP_VERSION(10, 3, 3): 2062 case IP_VERSION(10, 3, 4): 2063 case IP_VERSION(10, 3, 5): 2064 case IP_VERSION(10, 3, 6): 2065 case IP_VERSION(10, 3, 7): 2066 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 2067 break; 2068 case IP_VERSION(11, 0, 0): 2069 case IP_VERSION(11, 0, 1): 2070 case IP_VERSION(11, 0, 2): 2071 case IP_VERSION(11, 0, 3): 2072 case IP_VERSION(11, 0, 4): 2073 case IP_VERSION(11, 5, 0): 2074 case IP_VERSION(11, 5, 1): 2075 case IP_VERSION(11, 5, 2): 2076 case IP_VERSION(11, 5, 3): 2077 case IP_VERSION(11, 5, 4): 2078 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); 2079 break; 2080 case IP_VERSION(12, 0, 0): 2081 case IP_VERSION(12, 0, 1): 2082 amdgpu_device_ip_block_add(adev, &soc24_common_ip_block); 2083 break; 2084 case IP_VERSION(12, 1, 0): 2085 amdgpu_device_ip_block_add(adev, &soc_v1_0_common_ip_block); 2086 break; 2087 default: 2088 dev_err(adev->dev, 2089 "Failed to add common ip block(GC_HWIP:0x%x)\n", 2090 amdgpu_ip_version(adev, GC_HWIP, 0)); 2091 return -EINVAL; 2092 } 2093 return 0; 2094 } 2095 2096 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 2097 { 2098 /* use GC or MMHUB IP version */ 2099 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2100 case IP_VERSION(9, 0, 1): 2101 case IP_VERSION(9, 1, 0): 2102 case IP_VERSION(9, 2, 1): 2103 case IP_VERSION(9, 2, 2): 2104 case IP_VERSION(9, 3, 0): 2105 case IP_VERSION(9, 4, 0): 2106 case IP_VERSION(9, 4, 1): 2107 case IP_VERSION(9, 4, 2): 2108 case IP_VERSION(9, 4, 3): 2109 case IP_VERSION(9, 4, 4): 2110 case IP_VERSION(9, 5, 0): 2111 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 2112 break; 2113 case IP_VERSION(10, 1, 10): 2114 case IP_VERSION(10, 1, 1): 2115 case IP_VERSION(10, 1, 2): 2116 case IP_VERSION(10, 1, 3): 2117 case IP_VERSION(10, 1, 4): 2118 case IP_VERSION(10, 3, 0): 2119 case IP_VERSION(10, 3, 1): 2120 case IP_VERSION(10, 3, 2): 2121 case IP_VERSION(10, 3, 3): 2122 case IP_VERSION(10, 3, 4): 2123 case IP_VERSION(10, 3, 5): 2124 case IP_VERSION(10, 3, 6): 2125 case IP_VERSION(10, 3, 7): 2126 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 2127 break; 2128 case IP_VERSION(11, 0, 0): 2129 case IP_VERSION(11, 0, 1): 2130 case IP_VERSION(11, 0, 2): 2131 case IP_VERSION(11, 0, 3): 2132 case IP_VERSION(11, 0, 4): 2133 case IP_VERSION(11, 5, 0): 2134 case IP_VERSION(11, 5, 1): 2135 case IP_VERSION(11, 5, 2): 2136 case IP_VERSION(11, 5, 3): 2137 case IP_VERSION(11, 5, 4): 2138 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block); 2139 break; 2140 case IP_VERSION(12, 0, 0): 2141 case IP_VERSION(12, 0, 1): 2142 case IP_VERSION(12, 1, 0): 2143 amdgpu_device_ip_block_add(adev, &gmc_v12_0_ip_block); 2144 break; 2145 default: 2146 dev_err(adev->dev, "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 2147 amdgpu_ip_version(adev, GC_HWIP, 0)); 2148 return -EINVAL; 2149 } 2150 return 0; 2151 } 2152 2153 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 2154 { 2155 switch (amdgpu_ip_version(adev, OSSSYS_HWIP, 0)) { 2156 case IP_VERSION(4, 0, 0): 2157 case IP_VERSION(4, 0, 1): 2158 case IP_VERSION(4, 1, 0): 2159 case IP_VERSION(4, 1, 1): 2160 case IP_VERSION(4, 3, 0): 2161 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 2162 break; 2163 case IP_VERSION(4, 2, 0): 2164 case IP_VERSION(4, 2, 1): 2165 case IP_VERSION(4, 4, 0): 2166 case IP_VERSION(4, 4, 2): 2167 case IP_VERSION(4, 4, 5): 2168 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 2169 break; 2170 case IP_VERSION(5, 0, 0): 2171 case IP_VERSION(5, 0, 1): 2172 case IP_VERSION(5, 0, 2): 2173 case IP_VERSION(5, 0, 3): 2174 case IP_VERSION(5, 2, 0): 2175 case IP_VERSION(5, 2, 1): 2176 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 2177 break; 2178 case IP_VERSION(6, 0, 0): 2179 case IP_VERSION(6, 0, 1): 2180 case IP_VERSION(6, 0, 2): 2181 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block); 2182 break; 2183 case IP_VERSION(6, 1, 0): 2184 case IP_VERSION(6, 1, 1): 2185 amdgpu_device_ip_block_add(adev, &ih_v6_1_ip_block); 2186 break; 2187 case IP_VERSION(7, 0, 0): 2188 case IP_VERSION(7, 1, 0): 2189 amdgpu_device_ip_block_add(adev, &ih_v7_0_ip_block); 2190 break; 2191 default: 2192 dev_err(adev->dev, 2193 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 2194 amdgpu_ip_version(adev, OSSSYS_HWIP, 0)); 2195 return -EINVAL; 2196 } 2197 return 0; 2198 } 2199 2200 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 2201 { 2202 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 2203 case IP_VERSION(9, 0, 0): 2204 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 2205 break; 2206 case IP_VERSION(10, 0, 0): 2207 case IP_VERSION(10, 0, 1): 2208 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 2209 break; 2210 case IP_VERSION(11, 0, 0): 2211 case IP_VERSION(11, 0, 2): 2212 case IP_VERSION(11, 0, 4): 2213 case IP_VERSION(11, 0, 5): 2214 case IP_VERSION(11, 0, 9): 2215 case IP_VERSION(11, 0, 7): 2216 case IP_VERSION(11, 0, 11): 2217 case IP_VERSION(11, 0, 12): 2218 case IP_VERSION(11, 0, 13): 2219 case IP_VERSION(11, 5, 0): 2220 case IP_VERSION(11, 5, 2): 2221 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 2222 break; 2223 case IP_VERSION(11, 0, 8): 2224 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 2225 break; 2226 case IP_VERSION(11, 0, 3): 2227 case IP_VERSION(12, 0, 1): 2228 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 2229 break; 2230 case IP_VERSION(13, 0, 0): 2231 case IP_VERSION(13, 0, 1): 2232 case IP_VERSION(13, 0, 2): 2233 case IP_VERSION(13, 0, 3): 2234 case IP_VERSION(13, 0, 5): 2235 case IP_VERSION(13, 0, 6): 2236 case IP_VERSION(13, 0, 7): 2237 case IP_VERSION(13, 0, 8): 2238 case IP_VERSION(13, 0, 10): 2239 case IP_VERSION(13, 0, 11): 2240 case IP_VERSION(13, 0, 12): 2241 case IP_VERSION(13, 0, 14): 2242 case IP_VERSION(13, 0, 15): 2243 case IP_VERSION(14, 0, 0): 2244 case IP_VERSION(14, 0, 1): 2245 case IP_VERSION(14, 0, 4): 2246 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 2247 break; 2248 case IP_VERSION(13, 0, 4): 2249 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block); 2250 break; 2251 case IP_VERSION(14, 0, 2): 2252 case IP_VERSION(14, 0, 3): 2253 case IP_VERSION(14, 0, 5): 2254 amdgpu_device_ip_block_add(adev, &psp_v14_0_ip_block); 2255 break; 2256 case IP_VERSION(15, 0, 0): 2257 amdgpu_device_ip_block_add(adev, &psp_v15_0_ip_block); 2258 break; 2259 case IP_VERSION(15, 0, 8): 2260 amdgpu_device_ip_block_add(adev, &psp_v15_0_8_ip_block); 2261 break; 2262 default: 2263 dev_err(adev->dev, 2264 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 2265 amdgpu_ip_version(adev, MP0_HWIP, 0)); 2266 return -EINVAL; 2267 } 2268 return 0; 2269 } 2270 2271 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 2272 { 2273 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2274 case IP_VERSION(9, 0, 0): 2275 case IP_VERSION(10, 0, 0): 2276 case IP_VERSION(10, 0, 1): 2277 case IP_VERSION(11, 0, 2): 2278 if (adev->asic_type == CHIP_ARCTURUS) 2279 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2280 else 2281 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 2282 break; 2283 case IP_VERSION(11, 0, 0): 2284 case IP_VERSION(11, 0, 5): 2285 case IP_VERSION(11, 0, 9): 2286 case IP_VERSION(11, 0, 7): 2287 case IP_VERSION(11, 0, 11): 2288 case IP_VERSION(11, 0, 12): 2289 case IP_VERSION(11, 0, 13): 2290 case IP_VERSION(11, 5, 0): 2291 case IP_VERSION(11, 5, 2): 2292 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2293 break; 2294 case IP_VERSION(11, 0, 8): 2295 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) 2296 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2297 break; 2298 case IP_VERSION(12, 0, 0): 2299 case IP_VERSION(12, 0, 1): 2300 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 2301 break; 2302 case IP_VERSION(13, 0, 0): 2303 case IP_VERSION(13, 0, 1): 2304 case IP_VERSION(13, 0, 2): 2305 case IP_VERSION(13, 0, 3): 2306 case IP_VERSION(13, 0, 4): 2307 case IP_VERSION(13, 0, 5): 2308 case IP_VERSION(13, 0, 6): 2309 case IP_VERSION(13, 0, 7): 2310 case IP_VERSION(13, 0, 8): 2311 case IP_VERSION(13, 0, 10): 2312 case IP_VERSION(13, 0, 11): 2313 case IP_VERSION(13, 0, 14): 2314 case IP_VERSION(13, 0, 12): 2315 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 2316 break; 2317 case IP_VERSION(14, 0, 0): 2318 case IP_VERSION(14, 0, 1): 2319 case IP_VERSION(14, 0, 2): 2320 case IP_VERSION(14, 0, 3): 2321 case IP_VERSION(14, 0, 4): 2322 case IP_VERSION(14, 0, 5): 2323 amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block); 2324 break; 2325 case IP_VERSION(15, 0, 0): 2326 amdgpu_device_ip_block_add(adev, &smu_v15_0_ip_block); 2327 break; 2328 default: 2329 dev_err(adev->dev, 2330 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 2331 amdgpu_ip_version(adev, MP1_HWIP, 0)); 2332 return -EINVAL; 2333 } 2334 return 0; 2335 } 2336 2337 #if defined(CONFIG_DRM_AMD_DC) 2338 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev) 2339 { 2340 amdgpu_device_set_sriov_virtual_display(adev); 2341 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2342 } 2343 #endif 2344 2345 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 2346 { 2347 if (adev->enable_virtual_display) { 2348 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2349 return 0; 2350 } 2351 2352 if (!amdgpu_device_has_dc_support(adev)) 2353 return 0; 2354 2355 #if defined(CONFIG_DRM_AMD_DC) 2356 if (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2357 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2358 case IP_VERSION(1, 0, 0): 2359 case IP_VERSION(1, 0, 1): 2360 case IP_VERSION(2, 0, 2): 2361 case IP_VERSION(2, 0, 0): 2362 case IP_VERSION(2, 0, 3): 2363 case IP_VERSION(2, 1, 0): 2364 case IP_VERSION(3, 0, 0): 2365 case IP_VERSION(3, 0, 2): 2366 case IP_VERSION(3, 0, 3): 2367 case IP_VERSION(3, 0, 1): 2368 case IP_VERSION(3, 1, 2): 2369 case IP_VERSION(3, 1, 3): 2370 case IP_VERSION(3, 1, 4): 2371 case IP_VERSION(3, 1, 5): 2372 case IP_VERSION(3, 1, 6): 2373 case IP_VERSION(3, 2, 0): 2374 case IP_VERSION(3, 2, 1): 2375 case IP_VERSION(3, 5, 0): 2376 case IP_VERSION(3, 5, 1): 2377 case IP_VERSION(3, 6, 0): 2378 case IP_VERSION(4, 1, 0): 2379 case IP_VERSION(4, 2, 0): 2380 /* TODO: Fix IP version. DC code expects version 4.0.1 */ 2381 if (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(4, 1, 0)) 2382 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(4, 0, 1); 2383 2384 if (amdgpu_sriov_vf(adev)) 2385 amdgpu_discovery_set_sriov_display(adev); 2386 else 2387 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2388 break; 2389 default: 2390 dev_err(adev->dev, 2391 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 2392 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2393 return -EINVAL; 2394 } 2395 } else if (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2396 switch (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2397 case IP_VERSION(12, 0, 0): 2398 case IP_VERSION(12, 0, 1): 2399 case IP_VERSION(12, 1, 0): 2400 if (amdgpu_sriov_vf(adev)) 2401 amdgpu_discovery_set_sriov_display(adev); 2402 else 2403 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2404 break; 2405 default: 2406 dev_err(adev->dev, 2407 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 2408 amdgpu_ip_version(adev, DCI_HWIP, 0)); 2409 return -EINVAL; 2410 } 2411 } 2412 #endif 2413 return 0; 2414 } 2415 2416 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 2417 { 2418 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2419 case IP_VERSION(9, 0, 1): 2420 case IP_VERSION(9, 1, 0): 2421 case IP_VERSION(9, 2, 1): 2422 case IP_VERSION(9, 2, 2): 2423 case IP_VERSION(9, 3, 0): 2424 case IP_VERSION(9, 4, 0): 2425 case IP_VERSION(9, 4, 1): 2426 case IP_VERSION(9, 4, 2): 2427 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 2428 break; 2429 case IP_VERSION(9, 4, 3): 2430 case IP_VERSION(9, 4, 4): 2431 case IP_VERSION(9, 5, 0): 2432 amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block); 2433 break; 2434 case IP_VERSION(10, 1, 10): 2435 case IP_VERSION(10, 1, 2): 2436 case IP_VERSION(10, 1, 1): 2437 case IP_VERSION(10, 1, 3): 2438 case IP_VERSION(10, 1, 4): 2439 case IP_VERSION(10, 3, 0): 2440 case IP_VERSION(10, 3, 2): 2441 case IP_VERSION(10, 3, 1): 2442 case IP_VERSION(10, 3, 4): 2443 case IP_VERSION(10, 3, 5): 2444 case IP_VERSION(10, 3, 6): 2445 case IP_VERSION(10, 3, 3): 2446 case IP_VERSION(10, 3, 7): 2447 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 2448 break; 2449 case IP_VERSION(11, 0, 0): 2450 case IP_VERSION(11, 0, 1): 2451 case IP_VERSION(11, 0, 2): 2452 case IP_VERSION(11, 0, 3): 2453 case IP_VERSION(11, 0, 4): 2454 case IP_VERSION(11, 5, 0): 2455 case IP_VERSION(11, 5, 1): 2456 case IP_VERSION(11, 5, 2): 2457 case IP_VERSION(11, 5, 3): 2458 case IP_VERSION(11, 5, 4): 2459 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); 2460 break; 2461 case IP_VERSION(12, 0, 0): 2462 case IP_VERSION(12, 0, 1): 2463 amdgpu_device_ip_block_add(adev, &gfx_v12_0_ip_block); 2464 break; 2465 case IP_VERSION(12, 1, 0): 2466 amdgpu_device_ip_block_add(adev, &gfx_v12_1_ip_block); 2467 break; 2468 default: 2469 dev_err(adev->dev, "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 2470 amdgpu_ip_version(adev, GC_HWIP, 0)); 2471 return -EINVAL; 2472 } 2473 return 0; 2474 } 2475 2476 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 2477 { 2478 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 2479 case IP_VERSION(4, 0, 0): 2480 case IP_VERSION(4, 0, 1): 2481 case IP_VERSION(4, 1, 0): 2482 case IP_VERSION(4, 1, 1): 2483 case IP_VERSION(4, 1, 2): 2484 case IP_VERSION(4, 2, 0): 2485 case IP_VERSION(4, 2, 2): 2486 case IP_VERSION(4, 4, 0): 2487 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 2488 break; 2489 case IP_VERSION(4, 4, 2): 2490 case IP_VERSION(4, 4, 5): 2491 case IP_VERSION(4, 4, 4): 2492 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block); 2493 break; 2494 case IP_VERSION(5, 0, 0): 2495 case IP_VERSION(5, 0, 1): 2496 case IP_VERSION(5, 0, 2): 2497 case IP_VERSION(5, 0, 5): 2498 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 2499 break; 2500 case IP_VERSION(5, 2, 0): 2501 case IP_VERSION(5, 2, 2): 2502 case IP_VERSION(5, 2, 4): 2503 case IP_VERSION(5, 2, 5): 2504 case IP_VERSION(5, 2, 6): 2505 case IP_VERSION(5, 2, 3): 2506 case IP_VERSION(5, 2, 1): 2507 case IP_VERSION(5, 2, 7): 2508 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 2509 break; 2510 case IP_VERSION(6, 0, 0): 2511 case IP_VERSION(6, 0, 1): 2512 case IP_VERSION(6, 0, 2): 2513 case IP_VERSION(6, 0, 3): 2514 case IP_VERSION(6, 1, 0): 2515 case IP_VERSION(6, 1, 1): 2516 case IP_VERSION(6, 1, 2): 2517 case IP_VERSION(6, 1, 3): 2518 case IP_VERSION(6, 1, 4): 2519 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block); 2520 break; 2521 case IP_VERSION(7, 0, 0): 2522 case IP_VERSION(7, 0, 1): 2523 amdgpu_device_ip_block_add(adev, &sdma_v7_0_ip_block); 2524 break; 2525 case IP_VERSION(7, 1, 0): 2526 amdgpu_device_ip_block_add(adev, &sdma_v7_1_ip_block); 2527 break; 2528 default: 2529 dev_err(adev->dev, 2530 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 2531 amdgpu_ip_version(adev, SDMA0_HWIP, 0)); 2532 return -EINVAL; 2533 } 2534 2535 return 0; 2536 } 2537 2538 static int amdgpu_discovery_set_ras_ip_blocks(struct amdgpu_device *adev) 2539 { 2540 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 2541 case IP_VERSION(13, 0, 6): 2542 case IP_VERSION(13, 0, 12): 2543 case IP_VERSION(13, 0, 14): 2544 amdgpu_device_ip_block_add(adev, &ras_v1_0_ip_block); 2545 break; 2546 default: 2547 break; 2548 } 2549 return 0; 2550 } 2551 2552 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 2553 { 2554 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2555 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2556 case IP_VERSION(7, 0, 0): 2557 case IP_VERSION(7, 2, 0): 2558 /* UVD is not supported on vega20 SR-IOV */ 2559 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2560 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 2561 break; 2562 default: 2563 dev_err(adev->dev, 2564 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 2565 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2566 return -EINVAL; 2567 } 2568 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2569 case IP_VERSION(4, 0, 0): 2570 case IP_VERSION(4, 1, 0): 2571 /* VCE is not supported on vega20 SR-IOV */ 2572 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2573 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 2574 break; 2575 default: 2576 dev_err(adev->dev, 2577 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 2578 amdgpu_ip_version(adev, VCE_HWIP, 0)); 2579 return -EINVAL; 2580 } 2581 } else { 2582 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2583 case IP_VERSION(1, 0, 0): 2584 case IP_VERSION(1, 0, 1): 2585 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 2586 break; 2587 case IP_VERSION(2, 0, 0): 2588 case IP_VERSION(2, 0, 2): 2589 case IP_VERSION(2, 2, 0): 2590 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 2591 if (!amdgpu_sriov_vf(adev)) 2592 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 2593 break; 2594 case IP_VERSION(2, 0, 3): 2595 break; 2596 case IP_VERSION(2, 5, 0): 2597 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 2598 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 2599 break; 2600 case IP_VERSION(2, 6, 0): 2601 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 2602 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 2603 break; 2604 case IP_VERSION(3, 0, 0): 2605 case IP_VERSION(3, 0, 16): 2606 case IP_VERSION(3, 1, 1): 2607 case IP_VERSION(3, 1, 2): 2608 case IP_VERSION(3, 0, 2): 2609 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2610 if (!amdgpu_sriov_vf(adev)) 2611 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 2612 break; 2613 case IP_VERSION(3, 0, 33): 2614 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2615 break; 2616 case IP_VERSION(4, 0, 0): 2617 case IP_VERSION(4, 0, 2): 2618 case IP_VERSION(4, 0, 4): 2619 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block); 2620 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block); 2621 break; 2622 case IP_VERSION(4, 0, 3): 2623 amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block); 2624 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block); 2625 break; 2626 case IP_VERSION(4, 0, 5): 2627 case IP_VERSION(4, 0, 6): 2628 amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block); 2629 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block); 2630 break; 2631 case IP_VERSION(5, 0, 0): 2632 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block); 2633 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block); 2634 break; 2635 case IP_VERSION(5, 3, 0): 2636 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block); 2637 amdgpu_device_ip_block_add(adev, &jpeg_v5_3_0_ip_block); 2638 break; 2639 case IP_VERSION(5, 0, 1): 2640 amdgpu_device_ip_block_add(adev, &vcn_v5_0_1_ip_block); 2641 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_1_ip_block); 2642 break; 2643 default: 2644 dev_err(adev->dev, 2645 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 2646 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2647 return -EINVAL; 2648 } 2649 } 2650 return 0; 2651 } 2652 2653 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 2654 { 2655 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2656 case IP_VERSION(11, 0, 0): 2657 case IP_VERSION(11, 0, 1): 2658 case IP_VERSION(11, 0, 2): 2659 case IP_VERSION(11, 0, 3): 2660 case IP_VERSION(11, 0, 4): 2661 case IP_VERSION(11, 5, 0): 2662 case IP_VERSION(11, 5, 1): 2663 case IP_VERSION(11, 5, 2): 2664 case IP_VERSION(11, 5, 3): 2665 case IP_VERSION(11, 5, 4): 2666 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block); 2667 adev->enable_mes = true; 2668 adev->enable_mes_kiq = true; 2669 break; 2670 case IP_VERSION(12, 0, 0): 2671 case IP_VERSION(12, 0, 1): 2672 amdgpu_device_ip_block_add(adev, &mes_v12_0_ip_block); 2673 adev->enable_mes = true; 2674 adev->enable_mes_kiq = true; 2675 if (amdgpu_uni_mes) 2676 adev->enable_uni_mes = true; 2677 break; 2678 case IP_VERSION(12, 1, 0): 2679 amdgpu_device_ip_block_add(adev, &mes_v12_1_ip_block); 2680 adev->enable_mes = true; 2681 adev->enable_mes_kiq = true; 2682 if (amdgpu_uni_mes) 2683 adev->enable_uni_mes = true; 2684 break; 2685 default: 2686 break; 2687 } 2688 return 0; 2689 } 2690 2691 static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev) 2692 { 2693 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2694 case IP_VERSION(9, 4, 3): 2695 case IP_VERSION(9, 4, 4): 2696 case IP_VERSION(9, 5, 0): 2697 aqua_vanjaram_init_soc_config(adev); 2698 break; 2699 case IP_VERSION(12, 1, 0): 2700 soc_v1_0_init_soc_config(adev); 2701 break; 2702 default: 2703 break; 2704 } 2705 } 2706 2707 static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev) 2708 { 2709 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) { 2710 case IP_VERSION(6, 1, 0): 2711 case IP_VERSION(6, 1, 1): 2712 case IP_VERSION(6, 1, 3): 2713 amdgpu_device_ip_block_add(adev, &vpe_v6_1_ip_block); 2714 break; 2715 default: 2716 break; 2717 } 2718 2719 return 0; 2720 } 2721 2722 static int amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device *adev) 2723 { 2724 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) { 2725 case IP_VERSION(4, 0, 5): 2726 case IP_VERSION(4, 0, 6): 2727 if (amdgpu_umsch_mm & 0x1) { 2728 amdgpu_device_ip_block_add(adev, &umsch_mm_v4_0_ip_block); 2729 adev->enable_umsch_mm = true; 2730 } 2731 break; 2732 default: 2733 break; 2734 } 2735 2736 return 0; 2737 } 2738 2739 static int amdgpu_discovery_set_isp_ip_blocks(struct amdgpu_device *adev) 2740 { 2741 #if defined(CONFIG_DRM_AMD_ISP) 2742 switch (amdgpu_ip_version(adev, ISP_HWIP, 0)) { 2743 case IP_VERSION(4, 1, 0): 2744 amdgpu_device_ip_block_add(adev, &isp_v4_1_0_ip_block); 2745 break; 2746 case IP_VERSION(4, 1, 1): 2747 amdgpu_device_ip_block_add(adev, &isp_v4_1_1_ip_block); 2748 break; 2749 default: 2750 break; 2751 } 2752 #endif 2753 2754 return 0; 2755 } 2756 2757 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 2758 { 2759 int r; 2760 2761 switch (adev->asic_type) { 2762 case CHIP_VEGA10: 2763 /* This is not fatal. We only need the discovery 2764 * binary for sysfs. We don't need it for a 2765 * functional system. 2766 */ 2767 amdgpu_discovery_init(adev); 2768 vega10_reg_base_init(adev); 2769 adev->sdma.num_instances = 2; 2770 adev->sdma.sdma_mask = 3; 2771 adev->gmc.num_umc = 4; 2772 adev->gfx.xcc_mask = 1; 2773 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2774 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2775 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 2776 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 2777 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 2778 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 2779 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2780 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 2781 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 2782 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2783 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2784 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2785 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 2786 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 2787 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2788 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2789 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 2790 break; 2791 case CHIP_VEGA12: 2792 /* This is not fatal. We only need the discovery 2793 * binary for sysfs. We don't need it for a 2794 * functional system. 2795 */ 2796 amdgpu_discovery_init(adev); 2797 vega10_reg_base_init(adev); 2798 adev->sdma.num_instances = 2; 2799 adev->sdma.sdma_mask = 3; 2800 adev->gmc.num_umc = 4; 2801 adev->gfx.xcc_mask = 1; 2802 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2803 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2804 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 2805 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 2806 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 2807 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 2808 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 2809 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 2810 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 2811 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2812 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2813 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2814 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 2815 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 2816 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2817 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2818 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 2819 break; 2820 case CHIP_RAVEN: 2821 /* This is not fatal. We only need the discovery 2822 * binary for sysfs. We don't need it for a 2823 * functional system. 2824 */ 2825 amdgpu_discovery_init(adev); 2826 vega10_reg_base_init(adev); 2827 adev->sdma.num_instances = 1; 2828 adev->sdma.sdma_mask = 1; 2829 adev->vcn.num_vcn_inst = 1; 2830 adev->gmc.num_umc = 2; 2831 adev->gfx.xcc_mask = 1; 2832 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 2833 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2834 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2835 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 2836 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 2837 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 2838 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 2839 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 2840 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 2841 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 2842 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 2843 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 2844 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 2845 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 2846 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 2847 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 2848 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 2849 } else { 2850 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2851 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2852 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 2853 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 2854 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 2855 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2856 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 2857 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 2858 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 2859 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 2860 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 2861 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 2862 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 2863 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 2864 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 2865 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 2866 } 2867 break; 2868 case CHIP_VEGA20: 2869 /* This is not fatal. We only need the discovery 2870 * binary for sysfs. We don't need it for a 2871 * functional system. 2872 */ 2873 amdgpu_discovery_init(adev); 2874 vega20_reg_base_init(adev); 2875 adev->sdma.num_instances = 2; 2876 adev->sdma.sdma_mask = 3; 2877 adev->gmc.num_umc = 8; 2878 adev->gfx.xcc_mask = 1; 2879 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2880 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2881 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 2882 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 2883 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 2884 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 2885 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 2886 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 2887 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 2888 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 2889 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2890 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 2891 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 2892 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 2893 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 2894 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 2895 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 2896 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 2897 break; 2898 case CHIP_ARCTURUS: 2899 /* This is not fatal. We only need the discovery 2900 * binary for sysfs. We don't need it for a 2901 * functional system. 2902 */ 2903 amdgpu_discovery_init(adev); 2904 arct_reg_base_init(adev); 2905 adev->sdma.num_instances = 8; 2906 adev->sdma.sdma_mask = 0xff; 2907 adev->vcn.num_vcn_inst = 2; 2908 adev->gmc.num_umc = 8; 2909 adev->gfx.xcc_mask = 1; 2910 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2911 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2912 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 2913 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 2914 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 2915 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 2916 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 2917 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 2918 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 2919 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 2920 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 2921 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 2922 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 2923 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 2924 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 2925 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 2926 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2927 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 2928 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 2929 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 2930 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 2931 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 2932 break; 2933 case CHIP_ALDEBARAN: 2934 /* This is not fatal. We only need the discovery 2935 * binary for sysfs. We don't need it for a 2936 * functional system. 2937 */ 2938 amdgpu_discovery_init(adev); 2939 aldebaran_reg_base_init(adev); 2940 adev->sdma.num_instances = 5; 2941 adev->sdma.sdma_mask = 0x1f; 2942 adev->vcn.num_vcn_inst = 2; 2943 adev->gmc.num_umc = 4; 2944 adev->gfx.xcc_mask = 1; 2945 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2946 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2947 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 2948 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 2949 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 2950 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 2951 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 2952 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 2953 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 2954 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 2955 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 2956 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 2957 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 2958 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 2959 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 2960 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 2961 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 2962 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 2963 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 2964 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 2965 break; 2966 case CHIP_CYAN_SKILLFISH: 2967 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 2968 r = amdgpu_discovery_reg_base_init(adev); 2969 if (r) 2970 return -EINVAL; 2971 2972 amdgpu_discovery_harvest_ip(adev); 2973 amdgpu_discovery_get_gfx_info(adev); 2974 amdgpu_discovery_get_mall_info(adev); 2975 amdgpu_discovery_get_vcn_info(adev); 2976 } else { 2977 cyan_skillfish_reg_base_init(adev); 2978 adev->sdma.num_instances = 2; 2979 adev->sdma.sdma_mask = 3; 2980 adev->gfx.xcc_mask = 1; 2981 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(2, 0, 3); 2982 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(2, 0, 3); 2983 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(5, 0, 1); 2984 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(5, 0, 1); 2985 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(5, 0, 1); 2986 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(5, 0, 1); 2987 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 5, 0); 2988 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(2, 1, 1); 2989 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(8, 1, 1); 2990 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 8); 2991 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 8); 2992 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 1); 2993 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 8); 2994 adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 1, 3); 2995 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 0, 3); 2996 } 2997 break; 2998 default: 2999 r = amdgpu_discovery_reg_base_init(adev); 3000 if (r) { 3001 drm_err(&adev->ddev, "discovery failed: %d\n", r); 3002 return r; 3003 } 3004 3005 amdgpu_discovery_harvest_ip(adev); 3006 amdgpu_discovery_get_gfx_info(adev); 3007 amdgpu_discovery_get_mall_info(adev); 3008 amdgpu_discovery_get_vcn_info(adev); 3009 break; 3010 } 3011 3012 amdgpu_discovery_init_soc_config(adev); 3013 amdgpu_discovery_sysfs_init(adev); 3014 3015 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3016 case IP_VERSION(9, 0, 1): 3017 case IP_VERSION(9, 2, 1): 3018 case IP_VERSION(9, 4, 0): 3019 case IP_VERSION(9, 4, 1): 3020 case IP_VERSION(9, 4, 2): 3021 case IP_VERSION(9, 4, 3): 3022 case IP_VERSION(9, 4, 4): 3023 case IP_VERSION(9, 5, 0): 3024 adev->family = AMDGPU_FAMILY_AI; 3025 break; 3026 case IP_VERSION(9, 1, 0): 3027 case IP_VERSION(9, 2, 2): 3028 case IP_VERSION(9, 3, 0): 3029 adev->family = AMDGPU_FAMILY_RV; 3030 break; 3031 case IP_VERSION(10, 1, 10): 3032 case IP_VERSION(10, 1, 1): 3033 case IP_VERSION(10, 1, 2): 3034 case IP_VERSION(10, 1, 3): 3035 case IP_VERSION(10, 1, 4): 3036 case IP_VERSION(10, 3, 0): 3037 case IP_VERSION(10, 3, 2): 3038 case IP_VERSION(10, 3, 4): 3039 case IP_VERSION(10, 3, 5): 3040 adev->family = AMDGPU_FAMILY_NV; 3041 break; 3042 case IP_VERSION(10, 3, 1): 3043 adev->family = AMDGPU_FAMILY_VGH; 3044 adev->apu_flags |= AMD_APU_IS_VANGOGH; 3045 break; 3046 case IP_VERSION(10, 3, 3): 3047 adev->family = AMDGPU_FAMILY_YC; 3048 break; 3049 case IP_VERSION(10, 3, 6): 3050 adev->family = AMDGPU_FAMILY_GC_10_3_6; 3051 break; 3052 case IP_VERSION(10, 3, 7): 3053 adev->family = AMDGPU_FAMILY_GC_10_3_7; 3054 break; 3055 case IP_VERSION(11, 0, 0): 3056 case IP_VERSION(11, 0, 2): 3057 case IP_VERSION(11, 0, 3): 3058 adev->family = AMDGPU_FAMILY_GC_11_0_0; 3059 break; 3060 case IP_VERSION(11, 0, 1): 3061 case IP_VERSION(11, 0, 4): 3062 adev->family = AMDGPU_FAMILY_GC_11_0_1; 3063 break; 3064 case IP_VERSION(11, 5, 0): 3065 case IP_VERSION(11, 5, 1): 3066 case IP_VERSION(11, 5, 2): 3067 case IP_VERSION(11, 5, 3): 3068 adev->family = AMDGPU_FAMILY_GC_11_5_0; 3069 break; 3070 case IP_VERSION(11, 5, 4): 3071 adev->family = AMDGPU_FAMILY_GC_11_5_4; 3072 break; 3073 case IP_VERSION(12, 0, 0): 3074 case IP_VERSION(12, 0, 1): 3075 case IP_VERSION(12, 1, 0): 3076 adev->family = AMDGPU_FAMILY_GC_12_0_0; 3077 break; 3078 default: 3079 return -EINVAL; 3080 } 3081 3082 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3083 case IP_VERSION(9, 1, 0): 3084 case IP_VERSION(9, 2, 2): 3085 case IP_VERSION(9, 3, 0): 3086 case IP_VERSION(10, 1, 3): 3087 case IP_VERSION(10, 1, 4): 3088 case IP_VERSION(10, 3, 1): 3089 case IP_VERSION(10, 3, 3): 3090 case IP_VERSION(10, 3, 6): 3091 case IP_VERSION(10, 3, 7): 3092 case IP_VERSION(11, 0, 1): 3093 case IP_VERSION(11, 0, 4): 3094 case IP_VERSION(11, 5, 0): 3095 case IP_VERSION(11, 5, 1): 3096 case IP_VERSION(11, 5, 2): 3097 case IP_VERSION(11, 5, 3): 3098 case IP_VERSION(11, 5, 4): 3099 adev->flags |= AMD_IS_APU; 3100 break; 3101 default: 3102 break; 3103 } 3104 3105 /* set NBIO version */ 3106 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 3107 case IP_VERSION(6, 1, 0): 3108 case IP_VERSION(6, 2, 0): 3109 adev->nbio.funcs = &nbio_v6_1_funcs; 3110 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 3111 break; 3112 case IP_VERSION(7, 0, 0): 3113 case IP_VERSION(7, 0, 1): 3114 case IP_VERSION(2, 5, 0): 3115 adev->nbio.funcs = &nbio_v7_0_funcs; 3116 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 3117 break; 3118 case IP_VERSION(7, 4, 0): 3119 case IP_VERSION(7, 4, 1): 3120 case IP_VERSION(7, 4, 4): 3121 adev->nbio.funcs = &nbio_v7_4_funcs; 3122 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 3123 break; 3124 case IP_VERSION(7, 9, 0): 3125 case IP_VERSION(7, 9, 1): 3126 adev->nbio.funcs = &nbio_v7_9_funcs; 3127 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg; 3128 break; 3129 case IP_VERSION(7, 11, 0): 3130 case IP_VERSION(7, 11, 1): 3131 case IP_VERSION(7, 11, 2): 3132 case IP_VERSION(7, 11, 3): 3133 adev->nbio.funcs = &nbio_v7_11_funcs; 3134 adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg; 3135 break; 3136 case IP_VERSION(7, 2, 0): 3137 case IP_VERSION(7, 2, 1): 3138 case IP_VERSION(7, 3, 0): 3139 case IP_VERSION(7, 5, 0): 3140 case IP_VERSION(7, 5, 1): 3141 adev->nbio.funcs = &nbio_v7_2_funcs; 3142 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 3143 break; 3144 case IP_VERSION(2, 1, 1): 3145 case IP_VERSION(2, 3, 0): 3146 case IP_VERSION(2, 3, 1): 3147 case IP_VERSION(2, 3, 2): 3148 case IP_VERSION(3, 3, 0): 3149 case IP_VERSION(3, 3, 1): 3150 case IP_VERSION(3, 3, 2): 3151 case IP_VERSION(3, 3, 3): 3152 adev->nbio.funcs = &nbio_v2_3_funcs; 3153 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 3154 break; 3155 case IP_VERSION(4, 3, 0): 3156 case IP_VERSION(4, 3, 1): 3157 if (amdgpu_sriov_vf(adev)) 3158 adev->nbio.funcs = &nbio_v4_3_sriov_funcs; 3159 else 3160 adev->nbio.funcs = &nbio_v4_3_funcs; 3161 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg; 3162 break; 3163 case IP_VERSION(7, 7, 0): 3164 case IP_VERSION(7, 7, 1): 3165 adev->nbio.funcs = &nbio_v7_7_funcs; 3166 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg; 3167 break; 3168 case IP_VERSION(6, 3, 1): 3169 case IP_VERSION(7, 11, 4): 3170 adev->nbio.funcs = &nbif_v6_3_1_funcs; 3171 adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg; 3172 break; 3173 default: 3174 break; 3175 } 3176 3177 switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) { 3178 case IP_VERSION(4, 0, 0): 3179 case IP_VERSION(4, 0, 1): 3180 case IP_VERSION(4, 1, 0): 3181 case IP_VERSION(4, 1, 1): 3182 case IP_VERSION(4, 1, 2): 3183 case IP_VERSION(4, 2, 0): 3184 case IP_VERSION(4, 2, 1): 3185 case IP_VERSION(4, 4, 0): 3186 case IP_VERSION(4, 4, 2): 3187 case IP_VERSION(4, 4, 5): 3188 adev->hdp.funcs = &hdp_v4_0_funcs; 3189 break; 3190 case IP_VERSION(5, 0, 0): 3191 case IP_VERSION(5, 0, 1): 3192 case IP_VERSION(5, 0, 2): 3193 case IP_VERSION(5, 0, 3): 3194 case IP_VERSION(5, 0, 4): 3195 case IP_VERSION(5, 2, 0): 3196 adev->hdp.funcs = &hdp_v5_0_funcs; 3197 break; 3198 case IP_VERSION(5, 2, 1): 3199 adev->hdp.funcs = &hdp_v5_2_funcs; 3200 break; 3201 case IP_VERSION(6, 0, 0): 3202 case IP_VERSION(6, 0, 1): 3203 case IP_VERSION(6, 1, 0): 3204 case IP_VERSION(6, 1, 1): 3205 adev->hdp.funcs = &hdp_v6_0_funcs; 3206 break; 3207 case IP_VERSION(7, 0, 0): 3208 adev->hdp.funcs = &hdp_v7_0_funcs; 3209 break; 3210 default: 3211 break; 3212 } 3213 3214 switch (amdgpu_ip_version(adev, DF_HWIP, 0)) { 3215 case IP_VERSION(3, 6, 0): 3216 case IP_VERSION(3, 6, 1): 3217 case IP_VERSION(3, 6, 2): 3218 adev->df.funcs = &df_v3_6_funcs; 3219 break; 3220 case IP_VERSION(2, 1, 0): 3221 case IP_VERSION(2, 1, 1): 3222 case IP_VERSION(2, 5, 0): 3223 case IP_VERSION(3, 5, 1): 3224 case IP_VERSION(3, 5, 2): 3225 adev->df.funcs = &df_v1_7_funcs; 3226 break; 3227 case IP_VERSION(4, 3, 0): 3228 adev->df.funcs = &df_v4_3_funcs; 3229 break; 3230 case IP_VERSION(4, 6, 2): 3231 adev->df.funcs = &df_v4_6_2_funcs; 3232 break; 3233 case IP_VERSION(4, 15, 0): 3234 case IP_VERSION(4, 15, 1): 3235 adev->df.funcs = &df_v4_15_funcs; 3236 break; 3237 default: 3238 break; 3239 } 3240 3241 switch (amdgpu_ip_version(adev, SMUIO_HWIP, 0)) { 3242 case IP_VERSION(9, 0, 0): 3243 case IP_VERSION(9, 0, 1): 3244 case IP_VERSION(10, 0, 0): 3245 case IP_VERSION(10, 0, 1): 3246 case IP_VERSION(10, 0, 2): 3247 adev->smuio.funcs = &smuio_v9_0_funcs; 3248 break; 3249 case IP_VERSION(11, 0, 0): 3250 case IP_VERSION(11, 0, 2): 3251 case IP_VERSION(11, 0, 3): 3252 case IP_VERSION(11, 0, 4): 3253 case IP_VERSION(11, 0, 7): 3254 case IP_VERSION(11, 0, 8): 3255 adev->smuio.funcs = &smuio_v11_0_funcs; 3256 break; 3257 case IP_VERSION(11, 0, 6): 3258 case IP_VERSION(11, 0, 10): 3259 case IP_VERSION(11, 0, 11): 3260 case IP_VERSION(11, 5, 0): 3261 case IP_VERSION(11, 5, 2): 3262 case IP_VERSION(13, 0, 1): 3263 case IP_VERSION(13, 0, 9): 3264 case IP_VERSION(13, 0, 10): 3265 adev->smuio.funcs = &smuio_v11_0_6_funcs; 3266 break; 3267 case IP_VERSION(13, 0, 2): 3268 adev->smuio.funcs = &smuio_v13_0_funcs; 3269 break; 3270 case IP_VERSION(13, 0, 3): 3271 case IP_VERSION(13, 0, 11): 3272 adev->smuio.funcs = &smuio_v13_0_3_funcs; 3273 if (adev->smuio.funcs->get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) { 3274 adev->flags |= AMD_IS_APU; 3275 } 3276 break; 3277 case IP_VERSION(13, 0, 6): 3278 case IP_VERSION(13, 0, 8): 3279 case IP_VERSION(14, 0, 0): 3280 case IP_VERSION(14, 0, 1): 3281 adev->smuio.funcs = &smuio_v13_0_6_funcs; 3282 break; 3283 case IP_VERSION(14, 0, 2): 3284 adev->smuio.funcs = &smuio_v14_0_2_funcs; 3285 break; 3286 case IP_VERSION(15, 0, 0): 3287 adev->smuio.funcs = &smuio_v15_0_0_funcs; 3288 break; 3289 case IP_VERSION(15, 0, 8): 3290 adev->smuio.funcs = &smuio_v15_0_8_funcs; 3291 break; 3292 default: 3293 break; 3294 } 3295 3296 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { 3297 case IP_VERSION(6, 0, 0): 3298 case IP_VERSION(6, 0, 1): 3299 case IP_VERSION(6, 0, 2): 3300 case IP_VERSION(6, 0, 3): 3301 adev->lsdma.funcs = &lsdma_v6_0_funcs; 3302 break; 3303 case IP_VERSION(7, 0, 0): 3304 case IP_VERSION(7, 0, 1): 3305 adev->lsdma.funcs = &lsdma_v7_0_funcs; 3306 break; 3307 case IP_VERSION(7, 1, 0): 3308 adev->lsdma.funcs = &lsdma_v7_1_funcs; 3309 break; 3310 default: 3311 break; 3312 } 3313 3314 r = amdgpu_discovery_set_common_ip_blocks(adev); 3315 if (r) 3316 return r; 3317 3318 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 3319 if (r) 3320 return r; 3321 3322 /* For SR-IOV, PSP needs to be initialized before IH */ 3323 if (amdgpu_sriov_vf(adev)) { 3324 r = amdgpu_discovery_set_psp_ip_blocks(adev); 3325 if (r) 3326 return r; 3327 r = amdgpu_discovery_set_ih_ip_blocks(adev); 3328 if (r) 3329 return r; 3330 } else { 3331 r = amdgpu_discovery_set_ih_ip_blocks(adev); 3332 if (r) 3333 return r; 3334 3335 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3336 r = amdgpu_discovery_set_psp_ip_blocks(adev); 3337 if (r) 3338 return r; 3339 } 3340 } 3341 3342 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3343 r = amdgpu_discovery_set_smu_ip_blocks(adev); 3344 if (r) 3345 return r; 3346 } 3347 3348 r = amdgpu_discovery_set_display_ip_blocks(adev); 3349 if (r) 3350 return r; 3351 3352 r = amdgpu_discovery_set_gc_ip_blocks(adev); 3353 if (r) 3354 return r; 3355 3356 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 3357 if (r) 3358 return r; 3359 3360 r = amdgpu_discovery_set_ras_ip_blocks(adev); 3361 if (r) 3362 return r; 3363 3364 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 3365 !amdgpu_sriov_vf(adev) && 3366 amdgpu_dpm == 1) || 3367 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && 3368 amdgpu_dpm == 1)) { 3369 r = amdgpu_discovery_set_smu_ip_blocks(adev); 3370 if (r) 3371 return r; 3372 } 3373 3374 r = amdgpu_discovery_set_mm_ip_blocks(adev); 3375 if (r) 3376 return r; 3377 3378 r = amdgpu_discovery_set_mes_ip_blocks(adev); 3379 if (r) 3380 return r; 3381 3382 r = amdgpu_discovery_set_vpe_ip_blocks(adev); 3383 if (r) 3384 return r; 3385 3386 r = amdgpu_discovery_set_umsch_mm_ip_blocks(adev); 3387 if (r) 3388 return r; 3389 3390 r = amdgpu_discovery_set_isp_ip_blocks(adev); 3391 if (r) 3392 return r; 3393 return 0; 3394 } 3395 3396