1 /* 2 * Copyright 2018-2024 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_discovery.h" 28 #include "soc15_hw_ip.h" 29 #include "discovery.h" 30 #include "amdgpu_ras.h" 31 32 #include "soc15.h" 33 #include "gfx_v9_0.h" 34 #include "gfx_v9_4_3.h" 35 #include "gmc_v9_0.h" 36 #include "df_v1_7.h" 37 #include "df_v3_6.h" 38 #include "df_v4_3.h" 39 #include "df_v4_6_2.h" 40 #include "df_v4_15.h" 41 #include "nbio_v6_1.h" 42 #include "nbio_v7_0.h" 43 #include "nbio_v7_4.h" 44 #include "nbio_v7_9.h" 45 #include "nbio_v7_11.h" 46 #include "hdp_v4_0.h" 47 #include "vega10_ih.h" 48 #include "vega20_ih.h" 49 #include "sdma_v4_0.h" 50 #include "sdma_v4_4_2.h" 51 #include "uvd_v7_0.h" 52 #include "vce_v4_0.h" 53 #include "vcn_v1_0.h" 54 #include "vcn_v2_5.h" 55 #include "jpeg_v2_5.h" 56 #include "smuio_v9_0.h" 57 #include "gmc_v10_0.h" 58 #include "gmc_v11_0.h" 59 #include "gmc_v12_0.h" 60 #include "gfxhub_v2_0.h" 61 #include "mmhub_v2_0.h" 62 #include "nbio_v2_3.h" 63 #include "nbio_v4_3.h" 64 #include "nbio_v7_2.h" 65 #include "nbio_v7_7.h" 66 #include "nbif_v6_3_1.h" 67 #include "hdp_v5_0.h" 68 #include "hdp_v5_2.h" 69 #include "hdp_v6_0.h" 70 #include "hdp_v7_0.h" 71 #include "nv.h" 72 #include "soc21.h" 73 #include "soc24.h" 74 #include "soc_v1_0.h" 75 #include "navi10_ih.h" 76 #include "ih_v6_0.h" 77 #include "ih_v6_1.h" 78 #include "ih_v7_0.h" 79 #include "gfx_v10_0.h" 80 #include "gfx_v11_0.h" 81 #include "gfx_v12_0.h" 82 #include "gfx_v12_1.h" 83 #include "sdma_v5_0.h" 84 #include "sdma_v5_2.h" 85 #include "sdma_v6_0.h" 86 #include "sdma_v7_0.h" 87 #include "sdma_v7_1.h" 88 #include "lsdma_v6_0.h" 89 #include "lsdma_v7_0.h" 90 #include "vcn_v2_0.h" 91 #include "jpeg_v2_0.h" 92 #include "vcn_v3_0.h" 93 #include "jpeg_v3_0.h" 94 #include "vcn_v4_0.h" 95 #include "jpeg_v4_0.h" 96 #include "vcn_v4_0_3.h" 97 #include "jpeg_v4_0_3.h" 98 #include "vcn_v4_0_5.h" 99 #include "jpeg_v4_0_5.h" 100 #include "amdgpu_vkms.h" 101 #include "mes_v11_0.h" 102 #include "mes_v12_0.h" 103 #include "mes_v12_1.h" 104 #include "smuio_v11_0.h" 105 #include "smuio_v11_0_6.h" 106 #include "smuio_v13_0.h" 107 #include "smuio_v13_0_3.h" 108 #include "smuio_v13_0_6.h" 109 #include "smuio_v14_0_2.h" 110 #include "smuio_v15_0_8.h" 111 #include "vcn_v5_0_0.h" 112 #include "vcn_v5_0_1.h" 113 #include "jpeg_v5_0_0.h" 114 #include "jpeg_v5_0_1.h" 115 #include "amdgpu_ras_mgr.h" 116 117 #include "amdgpu_vpe.h" 118 #if defined(CONFIG_DRM_AMD_ISP) 119 #include "amdgpu_isp.h" 120 #endif 121 122 MODULE_FIRMWARE("amdgpu/ip_discovery.bin"); 123 MODULE_FIRMWARE("amdgpu/vega10_ip_discovery.bin"); 124 MODULE_FIRMWARE("amdgpu/vega12_ip_discovery.bin"); 125 MODULE_FIRMWARE("amdgpu/vega20_ip_discovery.bin"); 126 MODULE_FIRMWARE("amdgpu/raven_ip_discovery.bin"); 127 MODULE_FIRMWARE("amdgpu/raven2_ip_discovery.bin"); 128 MODULE_FIRMWARE("amdgpu/picasso_ip_discovery.bin"); 129 MODULE_FIRMWARE("amdgpu/arcturus_ip_discovery.bin"); 130 MODULE_FIRMWARE("amdgpu/aldebaran_ip_discovery.bin"); 131 132 #define mmIP_DISCOVERY_VERSION 0x16A00 133 #define mmRCC_CONFIG_MEMSIZE 0xde3 134 #define mmMP0_SMN_C2PMSG_33 0x16061 135 #define mmMM_INDEX 0x0 136 #define mmMM_INDEX_HI 0x6 137 #define mmMM_DATA 0x1 138 139 static const char *hw_id_names[HW_ID_MAX] = { 140 [MP1_HWID] = "MP1", 141 [MP2_HWID] = "MP2", 142 [THM_HWID] = "THM", 143 [SMUIO_HWID] = "SMUIO", 144 [FUSE_HWID] = "FUSE", 145 [CLKA_HWID] = "CLKA", 146 [PWR_HWID] = "PWR", 147 [GC_HWID] = "GC", 148 [UVD_HWID] = "UVD", 149 [AUDIO_AZ_HWID] = "AUDIO_AZ", 150 [ACP_HWID] = "ACP", 151 [DCI_HWID] = "DCI", 152 [DMU_HWID] = "DMU", 153 [DCO_HWID] = "DCO", 154 [DIO_HWID] = "DIO", 155 [XDMA_HWID] = "XDMA", 156 [DCEAZ_HWID] = "DCEAZ", 157 [DAZ_HWID] = "DAZ", 158 [SDPMUX_HWID] = "SDPMUX", 159 [NTB_HWID] = "NTB", 160 [IOHC_HWID] = "IOHC", 161 [L2IMU_HWID] = "L2IMU", 162 [VCE_HWID] = "VCE", 163 [MMHUB_HWID] = "MMHUB", 164 [ATHUB_HWID] = "ATHUB", 165 [DBGU_NBIO_HWID] = "DBGU_NBIO", 166 [DFX_HWID] = "DFX", 167 [DBGU0_HWID] = "DBGU0", 168 [DBGU1_HWID] = "DBGU1", 169 [OSSSYS_HWID] = "OSSSYS", 170 [HDP_HWID] = "HDP", 171 [SDMA0_HWID] = "SDMA0", 172 [SDMA1_HWID] = "SDMA1", 173 [SDMA2_HWID] = "SDMA2", 174 [SDMA3_HWID] = "SDMA3", 175 [LSDMA_HWID] = "LSDMA", 176 [ISP_HWID] = "ISP", 177 [DBGU_IO_HWID] = "DBGU_IO", 178 [DF_HWID] = "DF", 179 [CLKB_HWID] = "CLKB", 180 [FCH_HWID] = "FCH", 181 [DFX_DAP_HWID] = "DFX_DAP", 182 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 183 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 184 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 185 [L1IMU3_HWID] = "L1IMU3", 186 [L1IMU4_HWID] = "L1IMU4", 187 [L1IMU5_HWID] = "L1IMU5", 188 [L1IMU6_HWID] = "L1IMU6", 189 [L1IMU7_HWID] = "L1IMU7", 190 [L1IMU8_HWID] = "L1IMU8", 191 [L1IMU9_HWID] = "L1IMU9", 192 [L1IMU10_HWID] = "L1IMU10", 193 [L1IMU11_HWID] = "L1IMU11", 194 [L1IMU12_HWID] = "L1IMU12", 195 [L1IMU13_HWID] = "L1IMU13", 196 [L1IMU14_HWID] = "L1IMU14", 197 [L1IMU15_HWID] = "L1IMU15", 198 [WAFLC_HWID] = "WAFLC", 199 [FCH_USB_PD_HWID] = "FCH_USB_PD", 200 [PCIE_HWID] = "PCIE", 201 [PCS_HWID] = "PCS", 202 [DDCL_HWID] = "DDCL", 203 [SST_HWID] = "SST", 204 [IOAGR_HWID] = "IOAGR", 205 [NBIF_HWID] = "NBIF", 206 [IOAPIC_HWID] = "IOAPIC", 207 [SYSTEMHUB_HWID] = "SYSTEMHUB", 208 [NTBCCP_HWID] = "NTBCCP", 209 [UMC_HWID] = "UMC", 210 [SATA_HWID] = "SATA", 211 [USB_HWID] = "USB", 212 [CCXSEC_HWID] = "CCXSEC", 213 [XGMI_HWID] = "XGMI", 214 [XGBE_HWID] = "XGBE", 215 [MP0_HWID] = "MP0", 216 [VPE_HWID] = "VPE", 217 [ATU_HWID] = "ATU", 218 [AIGC_HWID] = "AIGC", 219 }; 220 221 static int hw_id_map[MAX_HWIP] = { 222 [GC_HWIP] = GC_HWID, 223 [HDP_HWIP] = HDP_HWID, 224 [SDMA0_HWIP] = SDMA0_HWID, 225 [SDMA1_HWIP] = SDMA1_HWID, 226 [SDMA2_HWIP] = SDMA2_HWID, 227 [SDMA3_HWIP] = SDMA3_HWID, 228 [LSDMA_HWIP] = LSDMA_HWID, 229 [MMHUB_HWIP] = MMHUB_HWID, 230 [ATHUB_HWIP] = ATHUB_HWID, 231 [NBIO_HWIP] = NBIF_HWID, 232 [MP0_HWIP] = MP0_HWID, 233 [MP1_HWIP] = MP1_HWID, 234 [UVD_HWIP] = UVD_HWID, 235 [VCE_HWIP] = VCE_HWID, 236 [DF_HWIP] = DF_HWID, 237 [DCE_HWIP] = DMU_HWID, 238 [OSSSYS_HWIP] = OSSSYS_HWID, 239 [SMUIO_HWIP] = SMUIO_HWID, 240 [PWR_HWIP] = PWR_HWID, 241 [NBIF_HWIP] = NBIF_HWID, 242 [THM_HWIP] = THM_HWID, 243 [CLK_HWIP] = CLKA_HWID, 244 [UMC_HWIP] = UMC_HWID, 245 [XGMI_HWIP] = XGMI_HWID, 246 [DCI_HWIP] = DCI_HWID, 247 [PCIE_HWIP] = PCIE_HWID, 248 [VPE_HWIP] = VPE_HWID, 249 [ISP_HWIP] = ISP_HWID, 250 [ATU_HWIP] = ATU_HWID, 251 }; 252 253 static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary) 254 { 255 u64 tmr_offset, tmr_size, pos; 256 void *discv_regn; 257 int ret; 258 259 ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size); 260 if (ret) 261 return ret; 262 263 pos = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET; 264 265 /* This region is read-only and reserved from system use */ 266 discv_regn = memremap(pos, adev->discovery.size, MEMREMAP_WC); 267 if (discv_regn) { 268 memcpy(binary, discv_regn, adev->discovery.size); 269 memunmap(discv_regn); 270 return 0; 271 } 272 273 return -ENOENT; 274 } 275 276 #define IP_DISCOVERY_V2 2 277 #define IP_DISCOVERY_V4 4 278 279 static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, 280 uint8_t *binary) 281 { 282 bool sz_valid = true; 283 uint64_t vram_size; 284 int i, ret = 0; 285 u32 msg; 286 287 if (!amdgpu_sriov_vf(adev)) { 288 /* It can take up to two second for IFWI init to complete on some dGPUs, 289 * but generally it should be in the 60-100ms range. Normally this starts 290 * as soon as the device gets power so by the time the OS loads this has long 291 * completed. However, when a card is hotplugged via e.g., USB4, we need to 292 * wait for this to complete. Once the C2PMSG is updated, we can 293 * continue. 294 */ 295 296 for (i = 0; i < 2000; i++) { 297 msg = RREG32(mmMP0_SMN_C2PMSG_33); 298 if (msg & 0x80000000) 299 break; 300 msleep(1); 301 } 302 } 303 304 vram_size = RREG32(mmRCC_CONFIG_MEMSIZE); 305 if (!vram_size || vram_size == U32_MAX) 306 sz_valid = false; 307 else 308 vram_size <<= 20; 309 310 /* 311 * If in VRAM, discovery TMR is marked for reservation. If it is in system mem, 312 * then it is not required to be reserved. 313 */ 314 if (sz_valid) { 315 if (amdgpu_sriov_vf(adev) && adev->virt.is_dynamic_crit_regn_enabled) { 316 /* For SRIOV VFs with dynamic critical region enabled, 317 * we will get the IPD binary via below call. 318 * If dynamic critical is disabled, fall through to normal seq. 319 */ 320 if (amdgpu_virt_get_dynamic_data_info(adev, 321 AMD_SRIOV_MSG_IPD_TABLE_ID, binary, 322 &adev->discovery.size)) { 323 dev_err(adev->dev, 324 "failed to read discovery info from dynamic critical region."); 325 ret = -EINVAL; 326 goto exit; 327 } 328 } else { 329 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; 330 331 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, 332 adev->discovery.size, false); 333 adev->discovery.reserve_tmr = true; 334 } 335 } else { 336 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); 337 } 338 339 if (ret) 340 dev_err(adev->dev, 341 "failed to read discovery info from memory, vram size read: %llx", 342 vram_size); 343 exit: 344 return ret; 345 } 346 347 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, 348 uint8_t *binary, 349 const char *fw_name) 350 { 351 const struct firmware *fw; 352 int r; 353 354 r = firmware_request_nowarn(&fw, fw_name, adev->dev); 355 if (r) { 356 if (amdgpu_discovery == 2) 357 dev_err(adev->dev, "can't load firmware \"%s\"\n", fw_name); 358 else 359 drm_info(&adev->ddev, "Optional firmware \"%s\" was not found\n", fw_name); 360 return r; 361 } 362 363 memcpy((u8 *)binary, (u8 *)fw->data, fw->size); 364 release_firmware(fw); 365 366 return 0; 367 } 368 369 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 370 { 371 uint16_t checksum = 0; 372 int i; 373 374 for (i = 0; i < size; i++) 375 checksum += data[i]; 376 377 return checksum; 378 } 379 380 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size, 381 uint16_t expected) 382 { 383 return !!(amdgpu_discovery_calculate_checksum(data, size) == expected); 384 } 385 386 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 387 { 388 struct binary_header *bhdr; 389 bhdr = (struct binary_header *)binary; 390 391 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 392 } 393 394 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) 395 { 396 /* 397 * So far, apply this quirk only on those Navy Flounder boards which 398 * have a bad harvest table of VCN config. 399 */ 400 if ((amdgpu_ip_version(adev, UVD_HWIP, 1) == IP_VERSION(3, 0, 1)) && 401 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 2))) { 402 switch (adev->pdev->revision) { 403 case 0xC1: 404 case 0xC2: 405 case 0xC3: 406 case 0xC5: 407 case 0xC7: 408 case 0xCF: 409 case 0xDF: 410 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 411 adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1; 412 break; 413 default: 414 break; 415 } 416 } 417 } 418 419 static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev, 420 struct binary_header *bhdr) 421 { 422 uint8_t *discovery_bin = adev->discovery.bin; 423 struct table_info *info; 424 uint16_t checksum; 425 uint16_t offset; 426 427 info = &bhdr->table_list[NPS_INFO]; 428 offset = le16_to_cpu(info->offset); 429 checksum = le16_to_cpu(info->checksum); 430 431 struct nps_info_header *nhdr = 432 (struct nps_info_header *)(discovery_bin + offset); 433 434 if (le32_to_cpu(nhdr->table_id) != NPS_INFO_TABLE_ID) { 435 dev_dbg(adev->dev, "invalid ip discovery nps info table id\n"); 436 return -EINVAL; 437 } 438 439 if (!amdgpu_discovery_verify_checksum(discovery_bin + offset, 440 le32_to_cpu(nhdr->size_bytes), 441 checksum)) { 442 dev_dbg(adev->dev, "invalid nps info data table checksum\n"); 443 return -EINVAL; 444 } 445 446 return 0; 447 } 448 449 static const char *amdgpu_discovery_get_fw_name(struct amdgpu_device *adev) 450 { 451 if (amdgpu_discovery == 2) { 452 /* Assume there is valid discovery TMR in VRAM even if binary is sideloaded */ 453 adev->discovery.reserve_tmr = true; 454 return "amdgpu/ip_discovery.bin"; 455 } 456 457 switch (adev->asic_type) { 458 case CHIP_VEGA10: 459 return "amdgpu/vega10_ip_discovery.bin"; 460 case CHIP_VEGA12: 461 return "amdgpu/vega12_ip_discovery.bin"; 462 case CHIP_RAVEN: 463 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 464 return "amdgpu/raven2_ip_discovery.bin"; 465 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 466 return "amdgpu/picasso_ip_discovery.bin"; 467 else 468 return "amdgpu/raven_ip_discovery.bin"; 469 case CHIP_VEGA20: 470 return "amdgpu/vega20_ip_discovery.bin"; 471 case CHIP_ARCTURUS: 472 return "amdgpu/arcturus_ip_discovery.bin"; 473 case CHIP_ALDEBARAN: 474 return "amdgpu/aldebaran_ip_discovery.bin"; 475 default: 476 return NULL; 477 } 478 } 479 480 static int amdgpu_discovery_init(struct amdgpu_device *adev) 481 { 482 struct table_info *info; 483 struct binary_header *bhdr; 484 uint8_t *discovery_bin; 485 const char *fw_name; 486 uint16_t offset; 487 uint16_t size; 488 uint16_t checksum; 489 int r; 490 491 adev->discovery.bin = kzalloc(DISCOVERY_TMR_SIZE, GFP_KERNEL); 492 if (!adev->discovery.bin) 493 return -ENOMEM; 494 adev->discovery.size = DISCOVERY_TMR_SIZE; 495 adev->discovery.debugfs_blob.data = adev->discovery.bin; 496 adev->discovery.debugfs_blob.size = adev->discovery.size; 497 498 discovery_bin = adev->discovery.bin; 499 /* Read from file if it is the preferred option */ 500 fw_name = amdgpu_discovery_get_fw_name(adev); 501 if (fw_name != NULL) { 502 drm_dbg(&adev->ddev, "use ip discovery information from file"); 503 r = amdgpu_discovery_read_binary_from_file(adev, discovery_bin, 504 fw_name); 505 if (r) 506 goto out; 507 } else { 508 drm_dbg(&adev->ddev, "use ip discovery information from memory"); 509 r = amdgpu_discovery_read_binary_from_mem(adev, discovery_bin); 510 if (r) 511 goto out; 512 } 513 514 /* check the ip discovery binary signature */ 515 if (!amdgpu_discovery_verify_binary_signature(discovery_bin)) { 516 dev_err(adev->dev, 517 "get invalid ip discovery binary signature\n"); 518 r = -EINVAL; 519 goto out; 520 } 521 522 bhdr = (struct binary_header *)discovery_bin; 523 524 offset = offsetof(struct binary_header, binary_checksum) + 525 sizeof(bhdr->binary_checksum); 526 size = le16_to_cpu(bhdr->binary_size) - offset; 527 checksum = le16_to_cpu(bhdr->binary_checksum); 528 529 if (!amdgpu_discovery_verify_checksum(discovery_bin + offset, size, 530 checksum)) { 531 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 532 r = -EINVAL; 533 goto out; 534 } 535 536 info = &bhdr->table_list[IP_DISCOVERY]; 537 offset = le16_to_cpu(info->offset); 538 checksum = le16_to_cpu(info->checksum); 539 540 if (offset) { 541 struct ip_discovery_header *ihdr = 542 (struct ip_discovery_header *)(discovery_bin + offset); 543 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { 544 dev_err(adev->dev, "invalid ip discovery data table signature\n"); 545 r = -EINVAL; 546 goto out; 547 } 548 549 if (!amdgpu_discovery_verify_checksum(discovery_bin + offset, 550 le16_to_cpu(ihdr->size), 551 checksum)) { 552 dev_err(adev->dev, "invalid ip discovery data table checksum\n"); 553 r = -EINVAL; 554 goto out; 555 } 556 } 557 558 info = &bhdr->table_list[GC]; 559 offset = le16_to_cpu(info->offset); 560 checksum = le16_to_cpu(info->checksum); 561 562 if (offset) { 563 struct gpu_info_header *ghdr = 564 (struct gpu_info_header *)(discovery_bin + offset); 565 566 if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) { 567 dev_err(adev->dev, "invalid ip discovery gc table id\n"); 568 r = -EINVAL; 569 goto out; 570 } 571 572 if (!amdgpu_discovery_verify_checksum(discovery_bin + offset, 573 le32_to_cpu(ghdr->size), 574 checksum)) { 575 dev_err(adev->dev, "invalid gc data table checksum\n"); 576 r = -EINVAL; 577 goto out; 578 } 579 } 580 581 info = &bhdr->table_list[HARVEST_INFO]; 582 offset = le16_to_cpu(info->offset); 583 checksum = le16_to_cpu(info->checksum); 584 585 if (offset) { 586 struct harvest_info_header *hhdr = 587 (struct harvest_info_header *)(discovery_bin + offset); 588 589 if (le32_to_cpu(hhdr->signature) != HARVEST_TABLE_SIGNATURE) { 590 dev_err(adev->dev, "invalid ip discovery harvest table signature\n"); 591 r = -EINVAL; 592 goto out; 593 } 594 595 if (!amdgpu_discovery_verify_checksum( 596 discovery_bin + offset, 597 sizeof(struct harvest_table), checksum)) { 598 dev_err(adev->dev, "invalid harvest data table checksum\n"); 599 r = -EINVAL; 600 goto out; 601 } 602 } 603 604 info = &bhdr->table_list[VCN_INFO]; 605 offset = le16_to_cpu(info->offset); 606 checksum = le16_to_cpu(info->checksum); 607 608 if (offset) { 609 struct vcn_info_header *vhdr = 610 (struct vcn_info_header *)(discovery_bin + offset); 611 612 if (le32_to_cpu(vhdr->table_id) != VCN_INFO_TABLE_ID) { 613 dev_err(adev->dev, "invalid ip discovery vcn table id\n"); 614 r = -EINVAL; 615 goto out; 616 } 617 618 if (!amdgpu_discovery_verify_checksum( 619 discovery_bin + offset, 620 le32_to_cpu(vhdr->size_bytes), checksum)) { 621 dev_err(adev->dev, "invalid vcn data table checksum\n"); 622 r = -EINVAL; 623 goto out; 624 } 625 } 626 627 info = &bhdr->table_list[MALL_INFO]; 628 offset = le16_to_cpu(info->offset); 629 checksum = le16_to_cpu(info->checksum); 630 631 if (0 && offset) { 632 struct mall_info_header *mhdr = 633 (struct mall_info_header *)(discovery_bin + offset); 634 635 if (le32_to_cpu(mhdr->table_id) != MALL_INFO_TABLE_ID) { 636 dev_err(adev->dev, "invalid ip discovery mall table id\n"); 637 r = -EINVAL; 638 goto out; 639 } 640 641 if (!amdgpu_discovery_verify_checksum( 642 discovery_bin + offset, 643 le32_to_cpu(mhdr->size_bytes), checksum)) { 644 dev_err(adev->dev, "invalid mall data table checksum\n"); 645 r = -EINVAL; 646 goto out; 647 } 648 } 649 650 return 0; 651 652 out: 653 kfree(adev->discovery.bin); 654 adev->discovery.bin = NULL; 655 if ((amdgpu_discovery != 2) && 656 (RREG32(mmIP_DISCOVERY_VERSION) == 4)) 657 amdgpu_ras_query_boot_status(adev, 4); 658 return r; 659 } 660 661 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev); 662 663 void amdgpu_discovery_fini(struct amdgpu_device *adev) 664 { 665 amdgpu_discovery_sysfs_fini(adev); 666 kfree(adev->discovery.bin); 667 adev->discovery.bin = NULL; 668 } 669 670 static int amdgpu_discovery_validate_ip(struct amdgpu_device *adev, 671 uint8_t instance, uint16_t hw_id) 672 { 673 if (instance >= HWIP_MAX_INSTANCE) { 674 dev_err(adev->dev, 675 "Unexpected instance_number (%d) from ip discovery blob\n", 676 instance); 677 return -EINVAL; 678 } 679 if (hw_id >= HW_ID_MAX) { 680 dev_err(adev->dev, 681 "Unexpected hw_id (%d) from ip discovery blob\n", 682 hw_id); 683 return -EINVAL; 684 } 685 686 return 0; 687 } 688 689 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev, 690 uint32_t *vcn_harvest_count) 691 { 692 uint8_t *discovery_bin = adev->discovery.bin; 693 struct binary_header *bhdr; 694 struct ip_discovery_header *ihdr; 695 struct die_header *dhdr; 696 struct ip *ip; 697 uint16_t die_offset, ip_offset, num_dies, num_ips; 698 uint16_t hw_id; 699 uint8_t inst; 700 int i, j; 701 702 bhdr = (struct binary_header *)discovery_bin; 703 ihdr = (struct ip_discovery_header 704 *)(discovery_bin + 705 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 706 num_dies = le16_to_cpu(ihdr->num_dies); 707 708 /* scan harvest bit of all IP data structures */ 709 for (i = 0; i < num_dies; i++) { 710 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 711 dhdr = (struct die_header *)(discovery_bin + die_offset); 712 num_ips = le16_to_cpu(dhdr->num_ips); 713 ip_offset = die_offset + sizeof(*dhdr); 714 715 for (j = 0; j < num_ips; j++) { 716 ip = (struct ip *)(discovery_bin + ip_offset); 717 inst = ip->number_instance; 718 hw_id = le16_to_cpu(ip->hw_id); 719 if (amdgpu_discovery_validate_ip(adev, inst, hw_id)) 720 goto next_ip; 721 722 if (ip->harvest == 1) { 723 switch (hw_id) { 724 case VCN_HWID: 725 (*vcn_harvest_count)++; 726 if (inst == 0) { 727 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 728 adev->vcn.inst_mask &= 729 ~AMDGPU_VCN_HARVEST_VCN0; 730 adev->jpeg.inst_mask &= 731 ~AMDGPU_VCN_HARVEST_VCN0; 732 } else { 733 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 734 adev->vcn.inst_mask &= 735 ~AMDGPU_VCN_HARVEST_VCN1; 736 adev->jpeg.inst_mask &= 737 ~AMDGPU_VCN_HARVEST_VCN1; 738 } 739 break; 740 case DMU_HWID: 741 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 742 break; 743 default: 744 break; 745 } 746 } 747 next_ip: 748 ip_offset += struct_size(ip, base_address, 749 ip->num_base_address); 750 } 751 } 752 } 753 754 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, 755 uint32_t *vcn_harvest_count, 756 uint32_t *umc_harvest_count) 757 { 758 uint8_t *discovery_bin = adev->discovery.bin; 759 struct binary_header *bhdr; 760 struct harvest_table *harvest_info; 761 u16 offset; 762 int i; 763 uint32_t umc_harvest_config = 0; 764 765 bhdr = (struct binary_header *)discovery_bin; 766 offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset); 767 768 if (!offset) { 769 dev_err(adev->dev, "invalid harvest table offset\n"); 770 return; 771 } 772 773 harvest_info = (struct harvest_table *)(discovery_bin + offset); 774 775 for (i = 0; i < 32; i++) { 776 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) 777 break; 778 779 switch (le16_to_cpu(harvest_info->list[i].hw_id)) { 780 case VCN_HWID: 781 (*vcn_harvest_count)++; 782 adev->vcn.harvest_config |= 783 (1 << harvest_info->list[i].number_instance); 784 adev->jpeg.harvest_config |= 785 (1 << harvest_info->list[i].number_instance); 786 787 adev->vcn.inst_mask &= 788 ~(1U << harvest_info->list[i].number_instance); 789 adev->jpeg.inst_mask &= 790 ~(1U << harvest_info->list[i].number_instance); 791 break; 792 case DMU_HWID: 793 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 794 break; 795 case UMC_HWID: 796 umc_harvest_config |= 797 1 << (le16_to_cpu(harvest_info->list[i].number_instance)); 798 (*umc_harvest_count)++; 799 break; 800 case GC_HWID: 801 adev->gfx.xcc_mask &= 802 ~(1U << harvest_info->list[i].number_instance); 803 break; 804 case SDMA0_HWID: 805 adev->sdma.sdma_mask &= 806 ~(1U << harvest_info->list[i].number_instance); 807 break; 808 #if defined(CONFIG_DRM_AMD_ISP) 809 case ISP_HWID: 810 adev->isp.harvest_config |= 811 ~(1U << harvest_info->list[i].number_instance); 812 break; 813 #endif 814 default: 815 break; 816 } 817 } 818 819 adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) & 820 ~umc_harvest_config; 821 } 822 823 /* ================================================== */ 824 825 struct ip_hw_instance { 826 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */ 827 828 int hw_id; 829 u8 num_instance; 830 u8 major, minor, revision; 831 u8 harvest; 832 833 int num_base_addresses; 834 u32 base_addr[] __counted_by(num_base_addresses); 835 }; 836 837 struct ip_hw_id { 838 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */ 839 int hw_id; 840 }; 841 842 struct ip_die_entry { 843 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */ 844 u16 num_ips; 845 }; 846 847 /* -------------------------------------------------- */ 848 849 struct ip_hw_instance_attr { 850 struct attribute attr; 851 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf); 852 }; 853 854 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf) 855 { 856 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id); 857 } 858 859 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf) 860 { 861 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance); 862 } 863 864 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf) 865 { 866 return sysfs_emit(buf, "%d\n", ip_hw_instance->major); 867 } 868 869 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf) 870 { 871 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor); 872 } 873 874 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf) 875 { 876 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision); 877 } 878 879 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf) 880 { 881 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest); 882 } 883 884 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf) 885 { 886 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses); 887 } 888 889 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) 890 { 891 ssize_t res, at; 892 int ii; 893 894 for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 895 /* Here we satisfy the condition that, at + size <= PAGE_SIZE. 896 */ 897 if (at + 12 > PAGE_SIZE) 898 break; 899 res = sysfs_emit_at(buf, at, "0x%08X\n", 900 ip_hw_instance->base_addr[ii]); 901 if (res <= 0) 902 break; 903 at += res; 904 } 905 906 return res < 0 ? res : at; 907 } 908 909 static struct ip_hw_instance_attr ip_hw_attr[] = { 910 __ATTR_RO(hw_id), 911 __ATTR_RO(num_instance), 912 __ATTR_RO(major), 913 __ATTR_RO(minor), 914 __ATTR_RO(revision), 915 __ATTR_RO(harvest), 916 __ATTR_RO(num_base_addresses), 917 __ATTR_RO(base_addr), 918 }; 919 920 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; 921 ATTRIBUTE_GROUPS(ip_hw_instance); 922 923 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) 924 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) 925 926 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj, 927 struct attribute *attr, 928 char *buf) 929 { 930 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 931 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr); 932 933 if (!ip_hw_attr->show) 934 return -EIO; 935 936 return ip_hw_attr->show(ip_hw_instance, buf); 937 } 938 939 static const struct sysfs_ops ip_hw_instance_sysfs_ops = { 940 .show = ip_hw_instance_attr_show, 941 }; 942 943 static void ip_hw_instance_release(struct kobject *kobj) 944 { 945 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 946 947 kfree(ip_hw_instance); 948 } 949 950 static const struct kobj_type ip_hw_instance_ktype = { 951 .release = ip_hw_instance_release, 952 .sysfs_ops = &ip_hw_instance_sysfs_ops, 953 .default_groups = ip_hw_instance_groups, 954 }; 955 956 /* -------------------------------------------------- */ 957 958 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset) 959 960 static void ip_hw_id_release(struct kobject *kobj) 961 { 962 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj); 963 964 if (!list_empty(&ip_hw_id->hw_id_kset.list)) 965 DRM_ERROR("ip_hw_id->hw_id_kset is not empty"); 966 kfree(ip_hw_id); 967 } 968 969 static const struct kobj_type ip_hw_id_ktype = { 970 .release = ip_hw_id_release, 971 .sysfs_ops = &kobj_sysfs_ops, 972 }; 973 974 /* -------------------------------------------------- */ 975 976 static void die_kobj_release(struct kobject *kobj); 977 static void ip_disc_release(struct kobject *kobj); 978 979 struct ip_die_entry_attribute { 980 struct attribute attr; 981 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf); 982 }; 983 984 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr) 985 986 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf) 987 { 988 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips); 989 } 990 991 /* If there are more ip_die_entry attrs, other than the number of IPs, 992 * we can make this intro an array of attrs, and then initialize 993 * ip_die_entry_attrs in a loop. 994 */ 995 static struct ip_die_entry_attribute num_ips_attr = 996 __ATTR_RO(num_ips); 997 998 static struct attribute *ip_die_entry_attrs[] = { 999 &num_ips_attr.attr, 1000 NULL, 1001 }; 1002 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ 1003 1004 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) 1005 1006 static ssize_t ip_die_entry_attr_show(struct kobject *kobj, 1007 struct attribute *attr, 1008 char *buf) 1009 { 1010 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr); 1011 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 1012 1013 if (!ip_die_entry_attr->show) 1014 return -EIO; 1015 1016 return ip_die_entry_attr->show(ip_die_entry, buf); 1017 } 1018 1019 static void ip_die_entry_release(struct kobject *kobj) 1020 { 1021 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 1022 1023 if (!list_empty(&ip_die_entry->ip_kset.list)) 1024 DRM_ERROR("ip_die_entry->ip_kset is not empty"); 1025 kfree(ip_die_entry); 1026 } 1027 1028 static const struct sysfs_ops ip_die_entry_sysfs_ops = { 1029 .show = ip_die_entry_attr_show, 1030 }; 1031 1032 static const struct kobj_type ip_die_entry_ktype = { 1033 .release = ip_die_entry_release, 1034 .sysfs_ops = &ip_die_entry_sysfs_ops, 1035 .default_groups = ip_die_entry_groups, 1036 }; 1037 1038 static const struct kobj_type die_kobj_ktype = { 1039 .release = die_kobj_release, 1040 .sysfs_ops = &kobj_sysfs_ops, 1041 }; 1042 1043 static const struct kobj_type ip_discovery_ktype = { 1044 .release = ip_disc_release, 1045 .sysfs_ops = &kobj_sysfs_ops, 1046 }; 1047 1048 struct ip_discovery_top { 1049 struct kobject kobj; /* ip_discovery/ */ 1050 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */ 1051 struct amdgpu_device *adev; 1052 }; 1053 1054 static void die_kobj_release(struct kobject *kobj) 1055 { 1056 struct ip_discovery_top *ip_top = container_of(to_kset(kobj), 1057 struct ip_discovery_top, 1058 die_kset); 1059 if (!list_empty(&ip_top->die_kset.list)) 1060 DRM_ERROR("ip_top->die_kset is not empty"); 1061 } 1062 1063 static void ip_disc_release(struct kobject *kobj) 1064 { 1065 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top, 1066 kobj); 1067 struct amdgpu_device *adev = ip_top->adev; 1068 1069 kfree(ip_top); 1070 adev->discovery.ip_top = NULL; 1071 } 1072 1073 static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev, 1074 uint16_t hw_id, uint8_t inst) 1075 { 1076 uint8_t harvest = 0; 1077 1078 /* Until a uniform way is figured, get mask based on hwid */ 1079 switch (hw_id) { 1080 case VCN_HWID: 1081 /* VCN vs UVD+VCE */ 1082 if (!amdgpu_ip_version(adev, VCE_HWIP, 0)) 1083 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0; 1084 break; 1085 case DMU_HWID: 1086 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK) 1087 harvest = 0x1; 1088 break; 1089 case UMC_HWID: 1090 /* TODO: It needs another parsing; for now, ignore.*/ 1091 break; 1092 case GC_HWID: 1093 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; 1094 break; 1095 case SDMA0_HWID: 1096 harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0; 1097 break; 1098 default: 1099 break; 1100 } 1101 1102 return harvest; 1103 } 1104 1105 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, 1106 struct ip_die_entry *ip_die_entry, 1107 const size_t _ip_offset, const int num_ips, 1108 bool reg_base_64) 1109 { 1110 uint8_t *discovery_bin = adev->discovery.bin; 1111 int ii, jj, kk, res; 1112 uint16_t hw_id; 1113 uint8_t inst; 1114 1115 DRM_DEBUG("num_ips:%d", num_ips); 1116 1117 /* Find all IPs of a given HW ID, and add their instance to 1118 * #die/#hw_id/#instance/<attributes> 1119 */ 1120 for (ii = 0; ii < HW_ID_MAX; ii++) { 1121 struct ip_hw_id *ip_hw_id = NULL; 1122 size_t ip_offset = _ip_offset; 1123 1124 for (jj = 0; jj < num_ips; jj++) { 1125 struct ip_v4 *ip; 1126 struct ip_hw_instance *ip_hw_instance; 1127 1128 ip = (struct ip_v4 *)(discovery_bin + ip_offset); 1129 inst = ip->instance_number; 1130 hw_id = le16_to_cpu(ip->hw_id); 1131 if (amdgpu_discovery_validate_ip(adev, inst, hw_id) || 1132 hw_id != ii) 1133 goto next_ip; 1134 1135 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset); 1136 1137 /* We have a hw_id match; register the hw 1138 * block if not yet registered. 1139 */ 1140 if (!ip_hw_id) { 1141 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL); 1142 if (!ip_hw_id) 1143 return -ENOMEM; 1144 ip_hw_id->hw_id = ii; 1145 1146 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii); 1147 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset; 1148 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype; 1149 res = kset_register(&ip_hw_id->hw_id_kset); 1150 if (res) { 1151 DRM_ERROR("Couldn't register ip_hw_id kset"); 1152 kfree(ip_hw_id); 1153 return res; 1154 } 1155 if (hw_id_names[ii]) { 1156 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj, 1157 &ip_hw_id->hw_id_kset.kobj, 1158 hw_id_names[ii]); 1159 if (res) { 1160 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n", 1161 hw_id_names[ii], 1162 kobject_name(&ip_die_entry->ip_kset.kobj)); 1163 } 1164 } 1165 } 1166 1167 /* Now register its instance. 1168 */ 1169 ip_hw_instance = kzalloc(struct_size(ip_hw_instance, 1170 base_addr, 1171 ip->num_base_address), 1172 GFP_KERNEL); 1173 if (!ip_hw_instance) { 1174 DRM_ERROR("no memory for ip_hw_instance"); 1175 return -ENOMEM; 1176 } 1177 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */ 1178 ip_hw_instance->num_instance = ip->instance_number; 1179 ip_hw_instance->major = ip->major; 1180 ip_hw_instance->minor = ip->minor; 1181 ip_hw_instance->revision = ip->revision; 1182 ip_hw_instance->harvest = 1183 amdgpu_discovery_get_harvest_info( 1184 adev, ip_hw_instance->hw_id, 1185 ip_hw_instance->num_instance); 1186 ip_hw_instance->num_base_addresses = ip->num_base_address; 1187 1188 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) { 1189 if (reg_base_64) 1190 ip_hw_instance->base_addr[kk] = 1191 lower_32_bits(le64_to_cpu(ip->base_address_64[kk])) & 0x3FFFFFFF; 1192 else 1193 ip_hw_instance->base_addr[kk] = ip->base_address[kk]; 1194 } 1195 1196 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); 1197 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; 1198 res = kobject_add(&ip_hw_instance->kobj, NULL, 1199 "%d", ip_hw_instance->num_instance); 1200 next_ip: 1201 if (reg_base_64) 1202 ip_offset += struct_size(ip, base_address_64, 1203 ip->num_base_address); 1204 else 1205 ip_offset += struct_size(ip, base_address, 1206 ip->num_base_address); 1207 } 1208 } 1209 1210 return 0; 1211 } 1212 1213 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) 1214 { 1215 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1216 uint8_t *discovery_bin = adev->discovery.bin; 1217 struct binary_header *bhdr; 1218 struct ip_discovery_header *ihdr; 1219 struct die_header *dhdr; 1220 struct kset *die_kset = &ip_top->die_kset; 1221 u16 num_dies, die_offset, num_ips; 1222 size_t ip_offset; 1223 int ii, res; 1224 1225 bhdr = (struct binary_header *)discovery_bin; 1226 ihdr = (struct ip_discovery_header 1227 *)(discovery_bin + 1228 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1229 num_dies = le16_to_cpu(ihdr->num_dies); 1230 1231 DRM_DEBUG("number of dies: %d\n", num_dies); 1232 1233 for (ii = 0; ii < num_dies; ii++) { 1234 struct ip_die_entry *ip_die_entry; 1235 1236 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); 1237 dhdr = (struct die_header *)(discovery_bin + die_offset); 1238 num_ips = le16_to_cpu(dhdr->num_ips); 1239 ip_offset = die_offset + sizeof(*dhdr); 1240 1241 /* Add the die to the kset. 1242 * 1243 * dhdr->die_id == ii, which was checked in 1244 * amdgpu_discovery_reg_base_init(). 1245 */ 1246 1247 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL); 1248 if (!ip_die_entry) 1249 return -ENOMEM; 1250 1251 ip_die_entry->num_ips = num_ips; 1252 1253 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id)); 1254 ip_die_entry->ip_kset.kobj.kset = die_kset; 1255 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype; 1256 res = kset_register(&ip_die_entry->ip_kset); 1257 if (res) { 1258 DRM_ERROR("Couldn't register ip_die_entry kset"); 1259 kfree(ip_die_entry); 1260 return res; 1261 } 1262 1263 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips, !!ihdr->base_addr_64_bit); 1264 } 1265 1266 return 0; 1267 } 1268 1269 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) 1270 { 1271 uint8_t *discovery_bin = adev->discovery.bin; 1272 struct ip_discovery_top *ip_top; 1273 struct kset *die_kset; 1274 int res, ii; 1275 1276 if (!discovery_bin) 1277 return -EINVAL; 1278 1279 ip_top = kzalloc(sizeof(*ip_top), GFP_KERNEL); 1280 if (!ip_top) 1281 return -ENOMEM; 1282 1283 ip_top->adev = adev; 1284 adev->discovery.ip_top = ip_top; 1285 res = kobject_init_and_add(&ip_top->kobj, &ip_discovery_ktype, 1286 &adev->dev->kobj, "ip_discovery"); 1287 if (res) { 1288 DRM_ERROR("Couldn't init and add ip_discovery/"); 1289 goto Err; 1290 } 1291 1292 die_kset = &ip_top->die_kset; 1293 kobject_set_name(&die_kset->kobj, "%s", "die"); 1294 die_kset->kobj.parent = &ip_top->kobj; 1295 die_kset->kobj.ktype = &die_kobj_ktype; 1296 res = kset_register(&ip_top->die_kset); 1297 if (res) { 1298 DRM_ERROR("Couldn't register die_kset"); 1299 goto Err; 1300 } 1301 1302 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++) 1303 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr; 1304 ip_hw_instance_attrs[ii] = NULL; 1305 1306 res = amdgpu_discovery_sysfs_recurse(adev); 1307 1308 return res; 1309 Err: 1310 kobject_put(&ip_top->kobj); 1311 return res; 1312 } 1313 1314 /* -------------------------------------------------- */ 1315 1316 #define list_to_kobj(el) container_of(el, struct kobject, entry) 1317 1318 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id) 1319 { 1320 struct list_head *el, *tmp; 1321 struct kset *hw_id_kset; 1322 1323 hw_id_kset = &ip_hw_id->hw_id_kset; 1324 spin_lock(&hw_id_kset->list_lock); 1325 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) { 1326 list_del_init(el); 1327 spin_unlock(&hw_id_kset->list_lock); 1328 /* kobject is embedded in ip_hw_instance */ 1329 kobject_put(list_to_kobj(el)); 1330 spin_lock(&hw_id_kset->list_lock); 1331 } 1332 spin_unlock(&hw_id_kset->list_lock); 1333 kobject_put(&ip_hw_id->hw_id_kset.kobj); 1334 } 1335 1336 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry) 1337 { 1338 struct list_head *el, *tmp; 1339 struct kset *ip_kset; 1340 1341 ip_kset = &ip_die_entry->ip_kset; 1342 spin_lock(&ip_kset->list_lock); 1343 list_for_each_prev_safe(el, tmp, &ip_kset->list) { 1344 list_del_init(el); 1345 spin_unlock(&ip_kset->list_lock); 1346 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el))); 1347 spin_lock(&ip_kset->list_lock); 1348 } 1349 spin_unlock(&ip_kset->list_lock); 1350 kobject_put(&ip_die_entry->ip_kset.kobj); 1351 } 1352 1353 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) 1354 { 1355 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1356 struct list_head *el, *tmp; 1357 struct kset *die_kset; 1358 1359 die_kset = &ip_top->die_kset; 1360 spin_lock(&die_kset->list_lock); 1361 list_for_each_prev_safe(el, tmp, &die_kset->list) { 1362 list_del_init(el); 1363 spin_unlock(&die_kset->list_lock); 1364 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 1365 spin_lock(&die_kset->list_lock); 1366 } 1367 spin_unlock(&die_kset->list_lock); 1368 kobject_put(&ip_top->die_kset.kobj); 1369 kobject_put(&ip_top->kobj); 1370 } 1371 1372 /* ================================================== */ 1373 1374 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 1375 { 1376 uint8_t num_base_address, subrev, variant; 1377 struct binary_header *bhdr; 1378 struct ip_discovery_header *ihdr; 1379 struct die_header *dhdr; 1380 uint8_t *discovery_bin; 1381 struct ip_v4 *ip; 1382 uint16_t die_offset; 1383 uint16_t ip_offset; 1384 uint16_t num_dies; 1385 uint32_t wafl_ver; 1386 uint16_t num_ips; 1387 uint16_t hw_id; 1388 uint8_t inst; 1389 int hw_ip; 1390 int i, j, k; 1391 int r; 1392 1393 r = amdgpu_discovery_init(adev); 1394 if (r) 1395 return r; 1396 discovery_bin = adev->discovery.bin; 1397 wafl_ver = 0; 1398 adev->gfx.xcc_mask = 0; 1399 adev->sdma.sdma_mask = 0; 1400 adev->vcn.inst_mask = 0; 1401 adev->jpeg.inst_mask = 0; 1402 bhdr = (struct binary_header *)discovery_bin; 1403 ihdr = (struct ip_discovery_header 1404 *)(discovery_bin + 1405 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1406 num_dies = le16_to_cpu(ihdr->num_dies); 1407 1408 DRM_DEBUG("number of dies: %d\n", num_dies); 1409 1410 for (i = 0; i < num_dies; i++) { 1411 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1412 dhdr = (struct die_header *)(discovery_bin + die_offset); 1413 num_ips = le16_to_cpu(dhdr->num_ips); 1414 ip_offset = die_offset + sizeof(*dhdr); 1415 1416 if (le16_to_cpu(dhdr->die_id) != i) { 1417 DRM_ERROR("invalid die id %d, expected %d\n", 1418 le16_to_cpu(dhdr->die_id), i); 1419 return -EINVAL; 1420 } 1421 1422 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 1423 le16_to_cpu(dhdr->die_id), num_ips); 1424 1425 for (j = 0; j < num_ips; j++) { 1426 ip = (struct ip_v4 *)(discovery_bin + ip_offset); 1427 1428 inst = ip->instance_number; 1429 hw_id = le16_to_cpu(ip->hw_id); 1430 if (amdgpu_discovery_validate_ip(adev, inst, hw_id)) 1431 goto next_ip; 1432 1433 num_base_address = ip->num_base_address; 1434 1435 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 1436 hw_id_names[le16_to_cpu(ip->hw_id)], 1437 le16_to_cpu(ip->hw_id), 1438 ip->instance_number, 1439 ip->major, ip->minor, 1440 ip->revision); 1441 1442 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 1443 /* Bit [5:0]: original revision value 1444 * Bit [7:6]: en/decode capability: 1445 * 0b00 : VCN function normally 1446 * 0b10 : encode is disabled 1447 * 0b01 : decode is disabled 1448 */ 1449 if (adev->vcn.num_vcn_inst < 1450 AMDGPU_MAX_VCN_INSTANCES) { 1451 adev->vcn.inst[adev->vcn.num_vcn_inst].vcn_config = 1452 ip->revision & 0xc0; 1453 adev->vcn.num_vcn_inst++; 1454 adev->vcn.inst_mask |= 1455 (1U << ip->instance_number); 1456 adev->jpeg.inst_mask |= 1457 (1U << ip->instance_number); 1458 } else { 1459 dev_err(adev->dev, "Too many VCN instances: %d vs %d\n", 1460 adev->vcn.num_vcn_inst + 1, 1461 AMDGPU_MAX_VCN_INSTANCES); 1462 } 1463 ip->revision &= ~0xc0; 1464 } 1465 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 1466 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 1467 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 1468 le16_to_cpu(ip->hw_id) == SDMA3_HWID) { 1469 if (adev->sdma.num_instances < 1470 AMDGPU_MAX_SDMA_INSTANCES) { 1471 adev->sdma.num_instances++; 1472 adev->sdma.sdma_mask |= 1473 (1U << ip->instance_number); 1474 } else { 1475 dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n", 1476 adev->sdma.num_instances + 1, 1477 AMDGPU_MAX_SDMA_INSTANCES); 1478 } 1479 } 1480 1481 if (le16_to_cpu(ip->hw_id) == VPE_HWID) { 1482 if (adev->vpe.num_instances < AMDGPU_MAX_VPE_INSTANCES) 1483 adev->vpe.num_instances++; 1484 else 1485 dev_err(adev->dev, "Too many VPE instances: %d vs %d\n", 1486 adev->vpe.num_instances + 1, 1487 AMDGPU_MAX_VPE_INSTANCES); 1488 } 1489 1490 if (le16_to_cpu(ip->hw_id) == UMC_HWID) { 1491 adev->gmc.num_umc++; 1492 adev->umc.node_inst_num++; 1493 } 1494 1495 if (le16_to_cpu(ip->hw_id) == GC_HWID) 1496 adev->gfx.xcc_mask |= 1497 (1U << ip->instance_number); 1498 1499 if (!wafl_ver && le16_to_cpu(ip->hw_id) == WAFLC_HWID) 1500 wafl_ver = IP_VERSION_FULL(ip->major, ip->minor, 1501 ip->revision, 0, 0); 1502 1503 for (k = 0; k < num_base_address; k++) { 1504 /* 1505 * convert the endianness of base addresses in place, 1506 * so that we don't need to convert them when accessing adev->reg_offset. 1507 */ 1508 if (ihdr->base_addr_64_bit) 1509 /* Truncate the 64bit base address from ip discovery 1510 * and only store lower 32bit ip base in reg_offset[]. 1511 * Bits > 32 follows ASIC specific format, thus just 1512 * discard them and handle it within specific ASIC. 1513 * By this way reg_offset[] and related helpers can 1514 * stay unchanged. 1515 * The base address is in dwords, thus clear the 1516 * highest 2 bits to store. 1517 */ 1518 ip->base_address[k] = 1519 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF; 1520 else 1521 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 1522 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 1523 } 1524 1525 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 1526 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) && 1527 hw_id_map[hw_ip] != 0) { 1528 DRM_DEBUG("set register base offset for %s\n", 1529 hw_id_names[le16_to_cpu(ip->hw_id)]); 1530 adev->reg_offset[hw_ip][ip->instance_number] = 1531 ip->base_address; 1532 /* Instance support is somewhat inconsistent. 1533 * SDMA is a good example. Sienna cichlid has 4 total 1534 * SDMA instances, each enumerated separately (HWIDs 1535 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 1536 * but they are enumerated as multiple instances of the 1537 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 1538 * example. On most chips there are multiple instances 1539 * with the same HWID. 1540 */ 1541 1542 if (ihdr->version < 3) { 1543 subrev = 0; 1544 variant = 0; 1545 } else { 1546 subrev = ip->sub_revision; 1547 variant = ip->variant; 1548 } 1549 1550 adev->ip_versions[hw_ip] 1551 [ip->instance_number] = 1552 IP_VERSION_FULL(ip->major, 1553 ip->minor, 1554 ip->revision, 1555 variant, 1556 subrev); 1557 } 1558 } 1559 1560 next_ip: 1561 if (ihdr->base_addr_64_bit) 1562 ip_offset += struct_size(ip, base_address_64, ip->num_base_address); 1563 else 1564 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1565 } 1566 } 1567 1568 if (wafl_ver && !adev->ip_versions[XGMI_HWIP][0]) 1569 adev->ip_versions[XGMI_HWIP][0] = wafl_ver; 1570 1571 return 0; 1572 } 1573 1574 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 1575 { 1576 uint8_t *discovery_bin = adev->discovery.bin; 1577 struct ip_discovery_header *ihdr; 1578 struct binary_header *bhdr; 1579 int vcn_harvest_count = 0; 1580 int umc_harvest_count = 0; 1581 uint16_t offset, ihdr_ver; 1582 1583 bhdr = (struct binary_header *)discovery_bin; 1584 offset = le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset); 1585 ihdr = (struct ip_discovery_header *)(discovery_bin + offset); 1586 ihdr_ver = le16_to_cpu(ihdr->version); 1587 /* 1588 * Harvest table does not fit Navi1x and legacy GPUs, 1589 * so read harvest bit per IP data structure to set 1590 * harvest configuration. 1591 */ 1592 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 2, 0) && 1593 ihdr_ver <= 2) { 1594 if ((adev->pdev->device == 0x731E && 1595 (adev->pdev->revision == 0xC6 || 1596 adev->pdev->revision == 0xC7)) || 1597 (adev->pdev->device == 0x7340 && 1598 adev->pdev->revision == 0xC9) || 1599 (adev->pdev->device == 0x7360 && 1600 adev->pdev->revision == 0xC7)) 1601 amdgpu_discovery_read_harvest_bit_per_ip(adev, 1602 &vcn_harvest_count); 1603 } else { 1604 amdgpu_discovery_read_from_harvest_table(adev, 1605 &vcn_harvest_count, 1606 &umc_harvest_count); 1607 } 1608 1609 amdgpu_discovery_harvest_config_quirk(adev); 1610 1611 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 1612 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 1613 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 1614 } 1615 1616 if (umc_harvest_count < adev->gmc.num_umc) { 1617 adev->gmc.num_umc -= umc_harvest_count; 1618 } 1619 } 1620 1621 union gc_info { 1622 struct gc_info_v1_0 v1; 1623 struct gc_info_v1_1 v1_1; 1624 struct gc_info_v1_2 v1_2; 1625 struct gc_info_v1_3 v1_3; 1626 struct gc_info_v2_0 v2; 1627 struct gc_info_v2_1 v2_1; 1628 }; 1629 1630 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 1631 { 1632 uint8_t *discovery_bin = adev->discovery.bin; 1633 struct binary_header *bhdr; 1634 union gc_info *gc_info; 1635 u16 offset; 1636 1637 if (!discovery_bin) { 1638 DRM_ERROR("ip discovery uninitialized\n"); 1639 return -EINVAL; 1640 } 1641 1642 bhdr = (struct binary_header *)discovery_bin; 1643 offset = le16_to_cpu(bhdr->table_list[GC].offset); 1644 1645 if (!offset) 1646 return 0; 1647 1648 gc_info = (union gc_info *)(discovery_bin + offset); 1649 1650 switch (le16_to_cpu(gc_info->v1.header.version_major)) { 1651 case 1: 1652 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); 1653 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 1654 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); 1655 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1656 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); 1657 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); 1658 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); 1659 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); 1660 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); 1661 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); 1662 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); 1663 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); 1664 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); 1665 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); 1666 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); 1667 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / 1668 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1669 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); 1670 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 1) { 1671 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa); 1672 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface); 1673 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps); 1674 } 1675 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 2) { 1676 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg); 1677 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size); 1678 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp); 1679 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc); 1680 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc); 1681 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa); 1682 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance); 1683 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu); 1684 } 1685 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 3) { 1686 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v1_3.gc_tcp_size_per_cu); 1687 adev->gfx.config.gc_tcp_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcp_cache_line_size); 1688 adev->gfx.config.gc_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_size_per_sqc); 1689 adev->gfx.config.gc_instruction_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_line_size); 1690 adev->gfx.config.gc_scalar_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_size_per_sqc); 1691 adev->gfx.config.gc_scalar_data_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_line_size); 1692 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v1_3.gc_tcc_size); 1693 adev->gfx.config.gc_tcc_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcc_cache_line_size); 1694 } 1695 break; 1696 case 2: 1697 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); 1698 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); 1699 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1700 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); 1701 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); 1702 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); 1703 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); 1704 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); 1705 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); 1706 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); 1707 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); 1708 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); 1709 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); 1710 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); 1711 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / 1712 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1713 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); 1714 if (le16_to_cpu(gc_info->v2.header.version_minor) == 1) { 1715 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh); 1716 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu); 1717 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XCD */ 1718 adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc); 1719 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_cache_size_per_sqc); 1720 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_size_per_sqc); 1721 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */ 1722 } 1723 break; 1724 default: 1725 dev_err(adev->dev, 1726 "Unhandled GC info table %d.%d\n", 1727 le16_to_cpu(gc_info->v1.header.version_major), 1728 le16_to_cpu(gc_info->v1.header.version_minor)); 1729 return -EINVAL; 1730 } 1731 return 0; 1732 } 1733 1734 union mall_info { 1735 struct mall_info_v1_0 v1; 1736 struct mall_info_v2_0 v2; 1737 }; 1738 1739 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) 1740 { 1741 uint8_t *discovery_bin = adev->discovery.bin; 1742 struct binary_header *bhdr; 1743 union mall_info *mall_info; 1744 u32 u, mall_size_per_umc, m_s_present, half_use; 1745 u64 mall_size; 1746 u16 offset; 1747 1748 if (!discovery_bin) { 1749 DRM_ERROR("ip discovery uninitialized\n"); 1750 return -EINVAL; 1751 } 1752 1753 bhdr = (struct binary_header *)discovery_bin; 1754 offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset); 1755 1756 if (!offset) 1757 return 0; 1758 1759 mall_info = (union mall_info *)(discovery_bin + offset); 1760 1761 switch (le16_to_cpu(mall_info->v1.header.version_major)) { 1762 case 1: 1763 mall_size = 0; 1764 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m); 1765 m_s_present = le32_to_cpu(mall_info->v1.m_s_present); 1766 half_use = le32_to_cpu(mall_info->v1.m_half_use); 1767 for (u = 0; u < adev->gmc.num_umc; u++) { 1768 if (m_s_present & (1 << u)) 1769 mall_size += mall_size_per_umc * 2; 1770 else if (half_use & (1 << u)) 1771 mall_size += mall_size_per_umc / 2; 1772 else 1773 mall_size += mall_size_per_umc; 1774 } 1775 adev->gmc.mall_size = mall_size; 1776 adev->gmc.m_half_use = half_use; 1777 break; 1778 case 2: 1779 mall_size_per_umc = le32_to_cpu(mall_info->v2.mall_size_per_umc); 1780 adev->gmc.mall_size = (uint64_t)mall_size_per_umc * adev->gmc.num_umc; 1781 break; 1782 default: 1783 dev_err(adev->dev, 1784 "Unhandled MALL info table %d.%d\n", 1785 le16_to_cpu(mall_info->v1.header.version_major), 1786 le16_to_cpu(mall_info->v1.header.version_minor)); 1787 return -EINVAL; 1788 } 1789 return 0; 1790 } 1791 1792 union vcn_info { 1793 struct vcn_info_v1_0 v1; 1794 }; 1795 1796 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) 1797 { 1798 uint8_t *discovery_bin = adev->discovery.bin; 1799 struct binary_header *bhdr; 1800 union vcn_info *vcn_info; 1801 u16 offset; 1802 int v; 1803 1804 if (!discovery_bin) { 1805 DRM_ERROR("ip discovery uninitialized\n"); 1806 return -EINVAL; 1807 } 1808 1809 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1810 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES 1811 * but that may change in the future with new GPUs so keep this 1812 * check for defensive purposes. 1813 */ 1814 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { 1815 dev_err(adev->dev, "invalid vcn instances\n"); 1816 return -EINVAL; 1817 } 1818 1819 bhdr = (struct binary_header *)discovery_bin; 1820 offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset); 1821 1822 if (!offset) 1823 return 0; 1824 1825 vcn_info = (union vcn_info *)(discovery_bin + offset); 1826 1827 switch (le16_to_cpu(vcn_info->v1.header.version_major)) { 1828 case 1: 1829 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1830 * so this won't overflow. 1831 */ 1832 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { 1833 adev->vcn.inst[v].vcn_codec_disable_mask = 1834 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits); 1835 } 1836 break; 1837 default: 1838 dev_err(adev->dev, 1839 "Unhandled VCN info table %d.%d\n", 1840 le16_to_cpu(vcn_info->v1.header.version_major), 1841 le16_to_cpu(vcn_info->v1.header.version_minor)); 1842 return -EINVAL; 1843 } 1844 return 0; 1845 } 1846 1847 union nps_info { 1848 struct nps_info_v1_0 v1; 1849 }; 1850 1851 static int amdgpu_discovery_refresh_nps_info(struct amdgpu_device *adev, 1852 union nps_info *nps_data) 1853 { 1854 uint64_t vram_size, pos, offset; 1855 struct nps_info_header *nhdr; 1856 struct binary_header bhdr; 1857 uint16_t checksum; 1858 1859 vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 1860 pos = vram_size - DISCOVERY_TMR_OFFSET; 1861 amdgpu_device_vram_access(adev, pos, &bhdr, sizeof(bhdr), false); 1862 1863 offset = le16_to_cpu(bhdr.table_list[NPS_INFO].offset); 1864 checksum = le16_to_cpu(bhdr.table_list[NPS_INFO].checksum); 1865 1866 amdgpu_device_vram_access(adev, (pos + offset), nps_data, 1867 sizeof(*nps_data), false); 1868 1869 nhdr = (struct nps_info_header *)(nps_data); 1870 if (!amdgpu_discovery_verify_checksum((uint8_t *)nps_data, 1871 le32_to_cpu(nhdr->size_bytes), 1872 checksum)) { 1873 dev_err(adev->dev, "nps data refresh, checksum mismatch\n"); 1874 return -EINVAL; 1875 } 1876 1877 return 0; 1878 } 1879 1880 int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, 1881 uint32_t *nps_type, 1882 struct amdgpu_gmc_memrange **ranges, 1883 int *range_cnt, bool refresh) 1884 { 1885 uint8_t *discovery_bin = adev->discovery.bin; 1886 struct amdgpu_gmc_memrange *mem_ranges; 1887 struct binary_header *bhdr; 1888 union nps_info *nps_info; 1889 union nps_info nps_data; 1890 u16 offset; 1891 int i, r; 1892 1893 if (!nps_type || !range_cnt || !ranges) 1894 return -EINVAL; 1895 1896 if (refresh) { 1897 r = amdgpu_discovery_refresh_nps_info(adev, &nps_data); 1898 if (r) 1899 return r; 1900 nps_info = &nps_data; 1901 } else { 1902 if (!discovery_bin) { 1903 dev_err(adev->dev, 1904 "fetch mem range failed, ip discovery uninitialized\n"); 1905 return -EINVAL; 1906 } 1907 1908 bhdr = (struct binary_header *)discovery_bin; 1909 offset = le16_to_cpu(bhdr->table_list[NPS_INFO].offset); 1910 1911 if (!offset) 1912 return -ENOENT; 1913 1914 /* If verification fails, return as if NPS table doesn't exist */ 1915 if (amdgpu_discovery_verify_npsinfo(adev, bhdr)) 1916 return -ENOENT; 1917 1918 nps_info = (union nps_info *)(discovery_bin + offset); 1919 } 1920 1921 switch (le16_to_cpu(nps_info->v1.header.version_major)) { 1922 case 1: 1923 mem_ranges = kvcalloc(nps_info->v1.count, 1924 sizeof(*mem_ranges), 1925 GFP_KERNEL); 1926 if (!mem_ranges) 1927 return -ENOMEM; 1928 *nps_type = nps_info->v1.nps_type; 1929 *range_cnt = nps_info->v1.count; 1930 for (i = 0; i < *range_cnt; i++) { 1931 mem_ranges[i].base_address = 1932 nps_info->v1.instance_info[i].base_address; 1933 mem_ranges[i].limit_address = 1934 nps_info->v1.instance_info[i].limit_address; 1935 mem_ranges[i].nid_mask = -1; 1936 mem_ranges[i].flags = 0; 1937 } 1938 *ranges = mem_ranges; 1939 break; 1940 default: 1941 dev_err(adev->dev, "Unhandled NPS info table %d.%d\n", 1942 le16_to_cpu(nps_info->v1.header.version_major), 1943 le16_to_cpu(nps_info->v1.header.version_minor)); 1944 return -EINVAL; 1945 } 1946 1947 return 0; 1948 } 1949 1950 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 1951 { 1952 /* what IP to use for this? */ 1953 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1954 case IP_VERSION(9, 0, 1): 1955 case IP_VERSION(9, 1, 0): 1956 case IP_VERSION(9, 2, 1): 1957 case IP_VERSION(9, 2, 2): 1958 case IP_VERSION(9, 3, 0): 1959 case IP_VERSION(9, 4, 0): 1960 case IP_VERSION(9, 4, 1): 1961 case IP_VERSION(9, 4, 2): 1962 case IP_VERSION(9, 4, 3): 1963 case IP_VERSION(9, 4, 4): 1964 case IP_VERSION(9, 5, 0): 1965 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 1966 break; 1967 case IP_VERSION(10, 1, 10): 1968 case IP_VERSION(10, 1, 1): 1969 case IP_VERSION(10, 1, 2): 1970 case IP_VERSION(10, 1, 3): 1971 case IP_VERSION(10, 1, 4): 1972 case IP_VERSION(10, 3, 0): 1973 case IP_VERSION(10, 3, 1): 1974 case IP_VERSION(10, 3, 2): 1975 case IP_VERSION(10, 3, 3): 1976 case IP_VERSION(10, 3, 4): 1977 case IP_VERSION(10, 3, 5): 1978 case IP_VERSION(10, 3, 6): 1979 case IP_VERSION(10, 3, 7): 1980 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 1981 break; 1982 case IP_VERSION(11, 0, 0): 1983 case IP_VERSION(11, 0, 1): 1984 case IP_VERSION(11, 0, 2): 1985 case IP_VERSION(11, 0, 3): 1986 case IP_VERSION(11, 0, 4): 1987 case IP_VERSION(11, 5, 0): 1988 case IP_VERSION(11, 5, 1): 1989 case IP_VERSION(11, 5, 2): 1990 case IP_VERSION(11, 5, 3): 1991 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); 1992 break; 1993 case IP_VERSION(12, 0, 0): 1994 case IP_VERSION(12, 0, 1): 1995 amdgpu_device_ip_block_add(adev, &soc24_common_ip_block); 1996 break; 1997 case IP_VERSION(12, 1, 0): 1998 amdgpu_device_ip_block_add(adev, &soc_v1_0_common_ip_block); 1999 break; 2000 default: 2001 dev_err(adev->dev, 2002 "Failed to add common ip block(GC_HWIP:0x%x)\n", 2003 amdgpu_ip_version(adev, GC_HWIP, 0)); 2004 return -EINVAL; 2005 } 2006 return 0; 2007 } 2008 2009 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 2010 { 2011 /* use GC or MMHUB IP version */ 2012 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2013 case IP_VERSION(9, 0, 1): 2014 case IP_VERSION(9, 1, 0): 2015 case IP_VERSION(9, 2, 1): 2016 case IP_VERSION(9, 2, 2): 2017 case IP_VERSION(9, 3, 0): 2018 case IP_VERSION(9, 4, 0): 2019 case IP_VERSION(9, 4, 1): 2020 case IP_VERSION(9, 4, 2): 2021 case IP_VERSION(9, 4, 3): 2022 case IP_VERSION(9, 4, 4): 2023 case IP_VERSION(9, 5, 0): 2024 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 2025 break; 2026 case IP_VERSION(10, 1, 10): 2027 case IP_VERSION(10, 1, 1): 2028 case IP_VERSION(10, 1, 2): 2029 case IP_VERSION(10, 1, 3): 2030 case IP_VERSION(10, 1, 4): 2031 case IP_VERSION(10, 3, 0): 2032 case IP_VERSION(10, 3, 1): 2033 case IP_VERSION(10, 3, 2): 2034 case IP_VERSION(10, 3, 3): 2035 case IP_VERSION(10, 3, 4): 2036 case IP_VERSION(10, 3, 5): 2037 case IP_VERSION(10, 3, 6): 2038 case IP_VERSION(10, 3, 7): 2039 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 2040 break; 2041 case IP_VERSION(11, 0, 0): 2042 case IP_VERSION(11, 0, 1): 2043 case IP_VERSION(11, 0, 2): 2044 case IP_VERSION(11, 0, 3): 2045 case IP_VERSION(11, 0, 4): 2046 case IP_VERSION(11, 5, 0): 2047 case IP_VERSION(11, 5, 1): 2048 case IP_VERSION(11, 5, 2): 2049 case IP_VERSION(11, 5, 3): 2050 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block); 2051 break; 2052 case IP_VERSION(12, 0, 0): 2053 case IP_VERSION(12, 0, 1): 2054 case IP_VERSION(12, 1, 0): 2055 amdgpu_device_ip_block_add(adev, &gmc_v12_0_ip_block); 2056 break; 2057 default: 2058 dev_err(adev->dev, "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 2059 amdgpu_ip_version(adev, GC_HWIP, 0)); 2060 return -EINVAL; 2061 } 2062 return 0; 2063 } 2064 2065 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 2066 { 2067 switch (amdgpu_ip_version(adev, OSSSYS_HWIP, 0)) { 2068 case IP_VERSION(4, 0, 0): 2069 case IP_VERSION(4, 0, 1): 2070 case IP_VERSION(4, 1, 0): 2071 case IP_VERSION(4, 1, 1): 2072 case IP_VERSION(4, 3, 0): 2073 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 2074 break; 2075 case IP_VERSION(4, 2, 0): 2076 case IP_VERSION(4, 2, 1): 2077 case IP_VERSION(4, 4, 0): 2078 case IP_VERSION(4, 4, 2): 2079 case IP_VERSION(4, 4, 5): 2080 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 2081 break; 2082 case IP_VERSION(5, 0, 0): 2083 case IP_VERSION(5, 0, 1): 2084 case IP_VERSION(5, 0, 2): 2085 case IP_VERSION(5, 0, 3): 2086 case IP_VERSION(5, 2, 0): 2087 case IP_VERSION(5, 2, 1): 2088 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 2089 break; 2090 case IP_VERSION(6, 0, 0): 2091 case IP_VERSION(6, 0, 1): 2092 case IP_VERSION(6, 0, 2): 2093 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block); 2094 break; 2095 case IP_VERSION(6, 1, 0): 2096 amdgpu_device_ip_block_add(adev, &ih_v6_1_ip_block); 2097 break; 2098 case IP_VERSION(7, 0, 0): 2099 case IP_VERSION(7, 1, 0): 2100 amdgpu_device_ip_block_add(adev, &ih_v7_0_ip_block); 2101 break; 2102 default: 2103 dev_err(adev->dev, 2104 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 2105 amdgpu_ip_version(adev, OSSSYS_HWIP, 0)); 2106 return -EINVAL; 2107 } 2108 return 0; 2109 } 2110 2111 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 2112 { 2113 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 2114 case IP_VERSION(9, 0, 0): 2115 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 2116 break; 2117 case IP_VERSION(10, 0, 0): 2118 case IP_VERSION(10, 0, 1): 2119 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 2120 break; 2121 case IP_VERSION(11, 0, 0): 2122 case IP_VERSION(11, 0, 2): 2123 case IP_VERSION(11, 0, 4): 2124 case IP_VERSION(11, 0, 5): 2125 case IP_VERSION(11, 0, 9): 2126 case IP_VERSION(11, 0, 7): 2127 case IP_VERSION(11, 0, 11): 2128 case IP_VERSION(11, 0, 12): 2129 case IP_VERSION(11, 0, 13): 2130 case IP_VERSION(11, 5, 0): 2131 case IP_VERSION(11, 5, 2): 2132 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 2133 break; 2134 case IP_VERSION(11, 0, 8): 2135 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 2136 break; 2137 case IP_VERSION(11, 0, 3): 2138 case IP_VERSION(12, 0, 1): 2139 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 2140 break; 2141 case IP_VERSION(13, 0, 0): 2142 case IP_VERSION(13, 0, 1): 2143 case IP_VERSION(13, 0, 2): 2144 case IP_VERSION(13, 0, 3): 2145 case IP_VERSION(13, 0, 5): 2146 case IP_VERSION(13, 0, 6): 2147 case IP_VERSION(13, 0, 7): 2148 case IP_VERSION(13, 0, 8): 2149 case IP_VERSION(13, 0, 10): 2150 case IP_VERSION(13, 0, 11): 2151 case IP_VERSION(13, 0, 12): 2152 case IP_VERSION(13, 0, 14): 2153 case IP_VERSION(14, 0, 0): 2154 case IP_VERSION(14, 0, 1): 2155 case IP_VERSION(14, 0, 4): 2156 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 2157 break; 2158 case IP_VERSION(13, 0, 4): 2159 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block); 2160 break; 2161 case IP_VERSION(14, 0, 2): 2162 case IP_VERSION(14, 0, 3): 2163 case IP_VERSION(14, 0, 5): 2164 amdgpu_device_ip_block_add(adev, &psp_v14_0_ip_block); 2165 break; 2166 case IP_VERSION(15, 0, 8): 2167 amdgpu_device_ip_block_add(adev, &psp_v15_0_8_ip_block); 2168 break; 2169 default: 2170 dev_err(adev->dev, 2171 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 2172 amdgpu_ip_version(adev, MP0_HWIP, 0)); 2173 return -EINVAL; 2174 } 2175 return 0; 2176 } 2177 2178 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 2179 { 2180 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2181 case IP_VERSION(9, 0, 0): 2182 case IP_VERSION(10, 0, 0): 2183 case IP_VERSION(10, 0, 1): 2184 case IP_VERSION(11, 0, 2): 2185 if (adev->asic_type == CHIP_ARCTURUS) 2186 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2187 else 2188 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 2189 break; 2190 case IP_VERSION(11, 0, 0): 2191 case IP_VERSION(11, 0, 5): 2192 case IP_VERSION(11, 0, 9): 2193 case IP_VERSION(11, 0, 7): 2194 case IP_VERSION(11, 0, 11): 2195 case IP_VERSION(11, 0, 12): 2196 case IP_VERSION(11, 0, 13): 2197 case IP_VERSION(11, 5, 0): 2198 case IP_VERSION(11, 5, 2): 2199 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2200 break; 2201 case IP_VERSION(11, 0, 8): 2202 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) 2203 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2204 break; 2205 case IP_VERSION(12, 0, 0): 2206 case IP_VERSION(12, 0, 1): 2207 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 2208 break; 2209 case IP_VERSION(13, 0, 0): 2210 case IP_VERSION(13, 0, 1): 2211 case IP_VERSION(13, 0, 2): 2212 case IP_VERSION(13, 0, 3): 2213 case IP_VERSION(13, 0, 4): 2214 case IP_VERSION(13, 0, 5): 2215 case IP_VERSION(13, 0, 6): 2216 case IP_VERSION(13, 0, 7): 2217 case IP_VERSION(13, 0, 8): 2218 case IP_VERSION(13, 0, 10): 2219 case IP_VERSION(13, 0, 11): 2220 case IP_VERSION(13, 0, 14): 2221 case IP_VERSION(13, 0, 12): 2222 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 2223 break; 2224 case IP_VERSION(14, 0, 0): 2225 case IP_VERSION(14, 0, 1): 2226 case IP_VERSION(14, 0, 2): 2227 case IP_VERSION(14, 0, 3): 2228 case IP_VERSION(14, 0, 4): 2229 case IP_VERSION(14, 0, 5): 2230 amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block); 2231 break; 2232 default: 2233 dev_err(adev->dev, 2234 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 2235 amdgpu_ip_version(adev, MP1_HWIP, 0)); 2236 return -EINVAL; 2237 } 2238 return 0; 2239 } 2240 2241 #if defined(CONFIG_DRM_AMD_DC) 2242 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev) 2243 { 2244 amdgpu_device_set_sriov_virtual_display(adev); 2245 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2246 } 2247 #endif 2248 2249 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 2250 { 2251 if (adev->enable_virtual_display) { 2252 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2253 return 0; 2254 } 2255 2256 if (!amdgpu_device_has_dc_support(adev)) 2257 return 0; 2258 2259 #if defined(CONFIG_DRM_AMD_DC) 2260 if (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2261 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2262 case IP_VERSION(1, 0, 0): 2263 case IP_VERSION(1, 0, 1): 2264 case IP_VERSION(2, 0, 2): 2265 case IP_VERSION(2, 0, 0): 2266 case IP_VERSION(2, 0, 3): 2267 case IP_VERSION(2, 1, 0): 2268 case IP_VERSION(3, 0, 0): 2269 case IP_VERSION(3, 0, 2): 2270 case IP_VERSION(3, 0, 3): 2271 case IP_VERSION(3, 0, 1): 2272 case IP_VERSION(3, 1, 2): 2273 case IP_VERSION(3, 1, 3): 2274 case IP_VERSION(3, 1, 4): 2275 case IP_VERSION(3, 1, 5): 2276 case IP_VERSION(3, 1, 6): 2277 case IP_VERSION(3, 2, 0): 2278 case IP_VERSION(3, 2, 1): 2279 case IP_VERSION(3, 5, 0): 2280 case IP_VERSION(3, 5, 1): 2281 case IP_VERSION(3, 6, 0): 2282 case IP_VERSION(4, 1, 0): 2283 /* TODO: Fix IP version. DC code expects version 4.0.1 */ 2284 if (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(4, 1, 0)) 2285 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(4, 0, 1); 2286 2287 if (amdgpu_sriov_vf(adev)) 2288 amdgpu_discovery_set_sriov_display(adev); 2289 else 2290 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2291 break; 2292 default: 2293 dev_err(adev->dev, 2294 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 2295 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2296 return -EINVAL; 2297 } 2298 } else if (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2299 switch (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2300 case IP_VERSION(12, 0, 0): 2301 case IP_VERSION(12, 0, 1): 2302 case IP_VERSION(12, 1, 0): 2303 if (amdgpu_sriov_vf(adev)) 2304 amdgpu_discovery_set_sriov_display(adev); 2305 else 2306 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2307 break; 2308 default: 2309 dev_err(adev->dev, 2310 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 2311 amdgpu_ip_version(adev, DCI_HWIP, 0)); 2312 return -EINVAL; 2313 } 2314 } 2315 #endif 2316 return 0; 2317 } 2318 2319 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 2320 { 2321 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2322 case IP_VERSION(9, 0, 1): 2323 case IP_VERSION(9, 1, 0): 2324 case IP_VERSION(9, 2, 1): 2325 case IP_VERSION(9, 2, 2): 2326 case IP_VERSION(9, 3, 0): 2327 case IP_VERSION(9, 4, 0): 2328 case IP_VERSION(9, 4, 1): 2329 case IP_VERSION(9, 4, 2): 2330 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 2331 break; 2332 case IP_VERSION(9, 4, 3): 2333 case IP_VERSION(9, 4, 4): 2334 case IP_VERSION(9, 5, 0): 2335 amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block); 2336 break; 2337 case IP_VERSION(10, 1, 10): 2338 case IP_VERSION(10, 1, 2): 2339 case IP_VERSION(10, 1, 1): 2340 case IP_VERSION(10, 1, 3): 2341 case IP_VERSION(10, 1, 4): 2342 case IP_VERSION(10, 3, 0): 2343 case IP_VERSION(10, 3, 2): 2344 case IP_VERSION(10, 3, 1): 2345 case IP_VERSION(10, 3, 4): 2346 case IP_VERSION(10, 3, 5): 2347 case IP_VERSION(10, 3, 6): 2348 case IP_VERSION(10, 3, 3): 2349 case IP_VERSION(10, 3, 7): 2350 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 2351 break; 2352 case IP_VERSION(11, 0, 0): 2353 case IP_VERSION(11, 0, 1): 2354 case IP_VERSION(11, 0, 2): 2355 case IP_VERSION(11, 0, 3): 2356 case IP_VERSION(11, 0, 4): 2357 case IP_VERSION(11, 5, 0): 2358 case IP_VERSION(11, 5, 1): 2359 case IP_VERSION(11, 5, 2): 2360 case IP_VERSION(11, 5, 3): 2361 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); 2362 break; 2363 case IP_VERSION(12, 0, 0): 2364 case IP_VERSION(12, 0, 1): 2365 amdgpu_device_ip_block_add(adev, &gfx_v12_0_ip_block); 2366 break; 2367 case IP_VERSION(12, 1, 0): 2368 amdgpu_device_ip_block_add(adev, &gfx_v12_1_ip_block); 2369 break; 2370 default: 2371 dev_err(adev->dev, "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 2372 amdgpu_ip_version(adev, GC_HWIP, 0)); 2373 return -EINVAL; 2374 } 2375 return 0; 2376 } 2377 2378 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 2379 { 2380 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 2381 case IP_VERSION(4, 0, 0): 2382 case IP_VERSION(4, 0, 1): 2383 case IP_VERSION(4, 1, 0): 2384 case IP_VERSION(4, 1, 1): 2385 case IP_VERSION(4, 1, 2): 2386 case IP_VERSION(4, 2, 0): 2387 case IP_VERSION(4, 2, 2): 2388 case IP_VERSION(4, 4, 0): 2389 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 2390 break; 2391 case IP_VERSION(4, 4, 2): 2392 case IP_VERSION(4, 4, 5): 2393 case IP_VERSION(4, 4, 4): 2394 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block); 2395 break; 2396 case IP_VERSION(5, 0, 0): 2397 case IP_VERSION(5, 0, 1): 2398 case IP_VERSION(5, 0, 2): 2399 case IP_VERSION(5, 0, 5): 2400 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 2401 break; 2402 case IP_VERSION(5, 2, 0): 2403 case IP_VERSION(5, 2, 2): 2404 case IP_VERSION(5, 2, 4): 2405 case IP_VERSION(5, 2, 5): 2406 case IP_VERSION(5, 2, 6): 2407 case IP_VERSION(5, 2, 3): 2408 case IP_VERSION(5, 2, 1): 2409 case IP_VERSION(5, 2, 7): 2410 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 2411 break; 2412 case IP_VERSION(6, 0, 0): 2413 case IP_VERSION(6, 0, 1): 2414 case IP_VERSION(6, 0, 2): 2415 case IP_VERSION(6, 0, 3): 2416 case IP_VERSION(6, 1, 0): 2417 case IP_VERSION(6, 1, 1): 2418 case IP_VERSION(6, 1, 2): 2419 case IP_VERSION(6, 1, 3): 2420 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block); 2421 break; 2422 case IP_VERSION(7, 0, 0): 2423 case IP_VERSION(7, 0, 1): 2424 amdgpu_device_ip_block_add(adev, &sdma_v7_0_ip_block); 2425 break; 2426 case IP_VERSION(7, 1, 0): 2427 amdgpu_device_ip_block_add(adev, &sdma_v7_1_ip_block); 2428 break; 2429 default: 2430 dev_err(adev->dev, 2431 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 2432 amdgpu_ip_version(adev, SDMA0_HWIP, 0)); 2433 return -EINVAL; 2434 } 2435 2436 return 0; 2437 } 2438 2439 static int amdgpu_discovery_set_ras_ip_blocks(struct amdgpu_device *adev) 2440 { 2441 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 2442 case IP_VERSION(13, 0, 6): 2443 case IP_VERSION(13, 0, 12): 2444 case IP_VERSION(13, 0, 14): 2445 amdgpu_device_ip_block_add(adev, &ras_v1_0_ip_block); 2446 break; 2447 default: 2448 break; 2449 } 2450 return 0; 2451 } 2452 2453 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 2454 { 2455 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2456 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2457 case IP_VERSION(7, 0, 0): 2458 case IP_VERSION(7, 2, 0): 2459 /* UVD is not supported on vega20 SR-IOV */ 2460 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2461 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 2462 break; 2463 default: 2464 dev_err(adev->dev, 2465 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 2466 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2467 return -EINVAL; 2468 } 2469 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2470 case IP_VERSION(4, 0, 0): 2471 case IP_VERSION(4, 1, 0): 2472 /* VCE is not supported on vega20 SR-IOV */ 2473 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2474 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 2475 break; 2476 default: 2477 dev_err(adev->dev, 2478 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 2479 amdgpu_ip_version(adev, VCE_HWIP, 0)); 2480 return -EINVAL; 2481 } 2482 } else { 2483 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2484 case IP_VERSION(1, 0, 0): 2485 case IP_VERSION(1, 0, 1): 2486 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 2487 break; 2488 case IP_VERSION(2, 0, 0): 2489 case IP_VERSION(2, 0, 2): 2490 case IP_VERSION(2, 2, 0): 2491 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 2492 if (!amdgpu_sriov_vf(adev)) 2493 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 2494 break; 2495 case IP_VERSION(2, 0, 3): 2496 break; 2497 case IP_VERSION(2, 5, 0): 2498 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 2499 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 2500 break; 2501 case IP_VERSION(2, 6, 0): 2502 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 2503 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 2504 break; 2505 case IP_VERSION(3, 0, 0): 2506 case IP_VERSION(3, 0, 16): 2507 case IP_VERSION(3, 1, 1): 2508 case IP_VERSION(3, 1, 2): 2509 case IP_VERSION(3, 0, 2): 2510 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2511 if (!amdgpu_sriov_vf(adev)) 2512 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 2513 break; 2514 case IP_VERSION(3, 0, 33): 2515 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2516 break; 2517 case IP_VERSION(4, 0, 0): 2518 case IP_VERSION(4, 0, 2): 2519 case IP_VERSION(4, 0, 4): 2520 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block); 2521 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block); 2522 break; 2523 case IP_VERSION(4, 0, 3): 2524 amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block); 2525 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block); 2526 break; 2527 case IP_VERSION(4, 0, 5): 2528 case IP_VERSION(4, 0, 6): 2529 amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block); 2530 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block); 2531 break; 2532 case IP_VERSION(5, 0, 0): 2533 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block); 2534 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block); 2535 break; 2536 case IP_VERSION(5, 0, 1): 2537 amdgpu_device_ip_block_add(adev, &vcn_v5_0_1_ip_block); 2538 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_1_ip_block); 2539 break; 2540 default: 2541 dev_err(adev->dev, 2542 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 2543 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2544 return -EINVAL; 2545 } 2546 } 2547 return 0; 2548 } 2549 2550 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 2551 { 2552 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2553 case IP_VERSION(11, 0, 0): 2554 case IP_VERSION(11, 0, 1): 2555 case IP_VERSION(11, 0, 2): 2556 case IP_VERSION(11, 0, 3): 2557 case IP_VERSION(11, 0, 4): 2558 case IP_VERSION(11, 5, 0): 2559 case IP_VERSION(11, 5, 1): 2560 case IP_VERSION(11, 5, 2): 2561 case IP_VERSION(11, 5, 3): 2562 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block); 2563 adev->enable_mes = true; 2564 adev->enable_mes_kiq = true; 2565 break; 2566 case IP_VERSION(12, 0, 0): 2567 case IP_VERSION(12, 0, 1): 2568 amdgpu_device_ip_block_add(adev, &mes_v12_0_ip_block); 2569 adev->enable_mes = true; 2570 adev->enable_mes_kiq = true; 2571 if (amdgpu_uni_mes) 2572 adev->enable_uni_mes = true; 2573 break; 2574 case IP_VERSION(12, 1, 0): 2575 amdgpu_device_ip_block_add(adev, &mes_v12_1_ip_block); 2576 adev->enable_mes = true; 2577 adev->enable_mes_kiq = true; 2578 if (amdgpu_uni_mes) 2579 adev->enable_uni_mes = true; 2580 break; 2581 default: 2582 break; 2583 } 2584 return 0; 2585 } 2586 2587 static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev) 2588 { 2589 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2590 case IP_VERSION(9, 4, 3): 2591 case IP_VERSION(9, 4, 4): 2592 case IP_VERSION(9, 5, 0): 2593 aqua_vanjaram_init_soc_config(adev); 2594 break; 2595 case IP_VERSION(12, 1, 0): 2596 soc_v1_0_init_soc_config(adev); 2597 break; 2598 default: 2599 break; 2600 } 2601 } 2602 2603 static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev) 2604 { 2605 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) { 2606 case IP_VERSION(6, 1, 0): 2607 case IP_VERSION(6, 1, 1): 2608 case IP_VERSION(6, 1, 3): 2609 amdgpu_device_ip_block_add(adev, &vpe_v6_1_ip_block); 2610 break; 2611 default: 2612 break; 2613 } 2614 2615 return 0; 2616 } 2617 2618 static int amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device *adev) 2619 { 2620 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) { 2621 case IP_VERSION(4, 0, 5): 2622 case IP_VERSION(4, 0, 6): 2623 if (amdgpu_umsch_mm & 0x1) { 2624 amdgpu_device_ip_block_add(adev, &umsch_mm_v4_0_ip_block); 2625 adev->enable_umsch_mm = true; 2626 } 2627 break; 2628 default: 2629 break; 2630 } 2631 2632 return 0; 2633 } 2634 2635 static int amdgpu_discovery_set_isp_ip_blocks(struct amdgpu_device *adev) 2636 { 2637 #if defined(CONFIG_DRM_AMD_ISP) 2638 switch (amdgpu_ip_version(adev, ISP_HWIP, 0)) { 2639 case IP_VERSION(4, 1, 0): 2640 amdgpu_device_ip_block_add(adev, &isp_v4_1_0_ip_block); 2641 break; 2642 case IP_VERSION(4, 1, 1): 2643 amdgpu_device_ip_block_add(adev, &isp_v4_1_1_ip_block); 2644 break; 2645 default: 2646 break; 2647 } 2648 #endif 2649 2650 return 0; 2651 } 2652 2653 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 2654 { 2655 int r; 2656 2657 switch (adev->asic_type) { 2658 case CHIP_VEGA10: 2659 /* This is not fatal. We only need the discovery 2660 * binary for sysfs. We don't need it for a 2661 * functional system. 2662 */ 2663 amdgpu_discovery_init(adev); 2664 vega10_reg_base_init(adev); 2665 adev->sdma.num_instances = 2; 2666 adev->sdma.sdma_mask = 3; 2667 adev->gmc.num_umc = 4; 2668 adev->gfx.xcc_mask = 1; 2669 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2670 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2671 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 2672 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 2673 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 2674 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 2675 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2676 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 2677 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 2678 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2679 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2680 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2681 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 2682 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 2683 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2684 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2685 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 2686 break; 2687 case CHIP_VEGA12: 2688 /* This is not fatal. We only need the discovery 2689 * binary for sysfs. We don't need it for a 2690 * functional system. 2691 */ 2692 amdgpu_discovery_init(adev); 2693 vega10_reg_base_init(adev); 2694 adev->sdma.num_instances = 2; 2695 adev->sdma.sdma_mask = 3; 2696 adev->gmc.num_umc = 4; 2697 adev->gfx.xcc_mask = 1; 2698 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2699 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2700 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 2701 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 2702 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 2703 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 2704 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 2705 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 2706 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 2707 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2708 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2709 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2710 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 2711 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 2712 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2713 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2714 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 2715 break; 2716 case CHIP_RAVEN: 2717 /* This is not fatal. We only need the discovery 2718 * binary for sysfs. We don't need it for a 2719 * functional system. 2720 */ 2721 amdgpu_discovery_init(adev); 2722 vega10_reg_base_init(adev); 2723 adev->sdma.num_instances = 1; 2724 adev->sdma.sdma_mask = 1; 2725 adev->vcn.num_vcn_inst = 1; 2726 adev->gmc.num_umc = 2; 2727 adev->gfx.xcc_mask = 1; 2728 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 2729 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2730 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2731 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 2732 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 2733 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 2734 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 2735 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 2736 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 2737 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 2738 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 2739 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 2740 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 2741 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 2742 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 2743 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 2744 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 2745 } else { 2746 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2747 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2748 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 2749 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 2750 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 2751 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2752 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 2753 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 2754 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 2755 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 2756 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 2757 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 2758 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 2759 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 2760 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 2761 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 2762 } 2763 break; 2764 case CHIP_VEGA20: 2765 /* This is not fatal. We only need the discovery 2766 * binary for sysfs. We don't need it for a 2767 * functional system. 2768 */ 2769 amdgpu_discovery_init(adev); 2770 vega20_reg_base_init(adev); 2771 adev->sdma.num_instances = 2; 2772 adev->sdma.sdma_mask = 3; 2773 adev->gmc.num_umc = 8; 2774 adev->gfx.xcc_mask = 1; 2775 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2776 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2777 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 2778 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 2779 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 2780 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 2781 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 2782 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 2783 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 2784 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 2785 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2786 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 2787 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 2788 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 2789 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 2790 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 2791 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 2792 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 2793 break; 2794 case CHIP_ARCTURUS: 2795 /* This is not fatal. We only need the discovery 2796 * binary for sysfs. We don't need it for a 2797 * functional system. 2798 */ 2799 amdgpu_discovery_init(adev); 2800 arct_reg_base_init(adev); 2801 adev->sdma.num_instances = 8; 2802 adev->sdma.sdma_mask = 0xff; 2803 adev->vcn.num_vcn_inst = 2; 2804 adev->gmc.num_umc = 8; 2805 adev->gfx.xcc_mask = 1; 2806 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2807 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2808 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 2809 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 2810 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 2811 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 2812 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 2813 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 2814 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 2815 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 2816 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 2817 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 2818 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 2819 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 2820 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 2821 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 2822 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2823 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 2824 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 2825 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 2826 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 2827 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 2828 break; 2829 case CHIP_ALDEBARAN: 2830 /* This is not fatal. We only need the discovery 2831 * binary for sysfs. We don't need it for a 2832 * functional system. 2833 */ 2834 amdgpu_discovery_init(adev); 2835 aldebaran_reg_base_init(adev); 2836 adev->sdma.num_instances = 5; 2837 adev->sdma.sdma_mask = 0x1f; 2838 adev->vcn.num_vcn_inst = 2; 2839 adev->gmc.num_umc = 4; 2840 adev->gfx.xcc_mask = 1; 2841 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2842 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2843 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 2844 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 2845 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 2846 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 2847 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 2848 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 2849 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 2850 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 2851 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 2852 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 2853 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 2854 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 2855 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 2856 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 2857 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 2858 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 2859 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 2860 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 2861 break; 2862 case CHIP_CYAN_SKILLFISH: 2863 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 2864 r = amdgpu_discovery_reg_base_init(adev); 2865 if (r) 2866 return -EINVAL; 2867 2868 amdgpu_discovery_harvest_ip(adev); 2869 amdgpu_discovery_get_gfx_info(adev); 2870 amdgpu_discovery_get_mall_info(adev); 2871 amdgpu_discovery_get_vcn_info(adev); 2872 } else { 2873 cyan_skillfish_reg_base_init(adev); 2874 adev->sdma.num_instances = 2; 2875 adev->sdma.sdma_mask = 3; 2876 adev->gfx.xcc_mask = 1; 2877 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(2, 0, 3); 2878 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(2, 0, 3); 2879 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(5, 0, 1); 2880 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(5, 0, 1); 2881 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(5, 0, 1); 2882 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(5, 0, 1); 2883 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 5, 0); 2884 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(2, 1, 1); 2885 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(8, 1, 1); 2886 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 8); 2887 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 8); 2888 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 1); 2889 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 8); 2890 adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 1, 3); 2891 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 0, 3); 2892 } 2893 break; 2894 default: 2895 r = amdgpu_discovery_reg_base_init(adev); 2896 if (r) { 2897 drm_err(&adev->ddev, "discovery failed: %d\n", r); 2898 return r; 2899 } 2900 2901 amdgpu_discovery_harvest_ip(adev); 2902 amdgpu_discovery_get_gfx_info(adev); 2903 amdgpu_discovery_get_mall_info(adev); 2904 amdgpu_discovery_get_vcn_info(adev); 2905 break; 2906 } 2907 2908 amdgpu_discovery_init_soc_config(adev); 2909 amdgpu_discovery_sysfs_init(adev); 2910 2911 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2912 case IP_VERSION(9, 0, 1): 2913 case IP_VERSION(9, 2, 1): 2914 case IP_VERSION(9, 4, 0): 2915 case IP_VERSION(9, 4, 1): 2916 case IP_VERSION(9, 4, 2): 2917 case IP_VERSION(9, 4, 3): 2918 case IP_VERSION(9, 4, 4): 2919 case IP_VERSION(9, 5, 0): 2920 adev->family = AMDGPU_FAMILY_AI; 2921 break; 2922 case IP_VERSION(9, 1, 0): 2923 case IP_VERSION(9, 2, 2): 2924 case IP_VERSION(9, 3, 0): 2925 adev->family = AMDGPU_FAMILY_RV; 2926 break; 2927 case IP_VERSION(10, 1, 10): 2928 case IP_VERSION(10, 1, 1): 2929 case IP_VERSION(10, 1, 2): 2930 case IP_VERSION(10, 1, 3): 2931 case IP_VERSION(10, 1, 4): 2932 case IP_VERSION(10, 3, 0): 2933 case IP_VERSION(10, 3, 2): 2934 case IP_VERSION(10, 3, 4): 2935 case IP_VERSION(10, 3, 5): 2936 adev->family = AMDGPU_FAMILY_NV; 2937 break; 2938 case IP_VERSION(10, 3, 1): 2939 adev->family = AMDGPU_FAMILY_VGH; 2940 adev->apu_flags |= AMD_APU_IS_VANGOGH; 2941 break; 2942 case IP_VERSION(10, 3, 3): 2943 adev->family = AMDGPU_FAMILY_YC; 2944 break; 2945 case IP_VERSION(10, 3, 6): 2946 adev->family = AMDGPU_FAMILY_GC_10_3_6; 2947 break; 2948 case IP_VERSION(10, 3, 7): 2949 adev->family = AMDGPU_FAMILY_GC_10_3_7; 2950 break; 2951 case IP_VERSION(11, 0, 0): 2952 case IP_VERSION(11, 0, 2): 2953 case IP_VERSION(11, 0, 3): 2954 adev->family = AMDGPU_FAMILY_GC_11_0_0; 2955 break; 2956 case IP_VERSION(11, 0, 1): 2957 case IP_VERSION(11, 0, 4): 2958 adev->family = AMDGPU_FAMILY_GC_11_0_1; 2959 break; 2960 case IP_VERSION(11, 5, 0): 2961 case IP_VERSION(11, 5, 1): 2962 case IP_VERSION(11, 5, 2): 2963 case IP_VERSION(11, 5, 3): 2964 adev->family = AMDGPU_FAMILY_GC_11_5_0; 2965 break; 2966 case IP_VERSION(12, 0, 0): 2967 case IP_VERSION(12, 0, 1): 2968 case IP_VERSION(12, 1, 0): 2969 adev->family = AMDGPU_FAMILY_GC_12_0_0; 2970 break; 2971 default: 2972 return -EINVAL; 2973 } 2974 2975 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2976 case IP_VERSION(9, 1, 0): 2977 case IP_VERSION(9, 2, 2): 2978 case IP_VERSION(9, 3, 0): 2979 case IP_VERSION(10, 1, 3): 2980 case IP_VERSION(10, 1, 4): 2981 case IP_VERSION(10, 3, 1): 2982 case IP_VERSION(10, 3, 3): 2983 case IP_VERSION(10, 3, 6): 2984 case IP_VERSION(10, 3, 7): 2985 case IP_VERSION(11, 0, 1): 2986 case IP_VERSION(11, 0, 4): 2987 case IP_VERSION(11, 5, 0): 2988 case IP_VERSION(11, 5, 1): 2989 case IP_VERSION(11, 5, 2): 2990 case IP_VERSION(11, 5, 3): 2991 adev->flags |= AMD_IS_APU; 2992 break; 2993 default: 2994 break; 2995 } 2996 2997 /* set NBIO version */ 2998 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 2999 case IP_VERSION(6, 1, 0): 3000 case IP_VERSION(6, 2, 0): 3001 adev->nbio.funcs = &nbio_v6_1_funcs; 3002 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 3003 break; 3004 case IP_VERSION(7, 0, 0): 3005 case IP_VERSION(7, 0, 1): 3006 case IP_VERSION(2, 5, 0): 3007 adev->nbio.funcs = &nbio_v7_0_funcs; 3008 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 3009 break; 3010 case IP_VERSION(7, 4, 0): 3011 case IP_VERSION(7, 4, 1): 3012 case IP_VERSION(7, 4, 4): 3013 adev->nbio.funcs = &nbio_v7_4_funcs; 3014 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 3015 break; 3016 case IP_VERSION(7, 9, 0): 3017 case IP_VERSION(7, 9, 1): 3018 adev->nbio.funcs = &nbio_v7_9_funcs; 3019 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg; 3020 break; 3021 case IP_VERSION(7, 11, 0): 3022 case IP_VERSION(7, 11, 1): 3023 case IP_VERSION(7, 11, 2): 3024 case IP_VERSION(7, 11, 3): 3025 adev->nbio.funcs = &nbio_v7_11_funcs; 3026 adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg; 3027 break; 3028 case IP_VERSION(7, 2, 0): 3029 case IP_VERSION(7, 2, 1): 3030 case IP_VERSION(7, 3, 0): 3031 case IP_VERSION(7, 5, 0): 3032 case IP_VERSION(7, 5, 1): 3033 adev->nbio.funcs = &nbio_v7_2_funcs; 3034 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 3035 break; 3036 case IP_VERSION(2, 1, 1): 3037 case IP_VERSION(2, 3, 0): 3038 case IP_VERSION(2, 3, 1): 3039 case IP_VERSION(2, 3, 2): 3040 case IP_VERSION(3, 3, 0): 3041 case IP_VERSION(3, 3, 1): 3042 case IP_VERSION(3, 3, 2): 3043 case IP_VERSION(3, 3, 3): 3044 adev->nbio.funcs = &nbio_v2_3_funcs; 3045 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 3046 break; 3047 case IP_VERSION(4, 3, 0): 3048 case IP_VERSION(4, 3, 1): 3049 if (amdgpu_sriov_vf(adev)) 3050 adev->nbio.funcs = &nbio_v4_3_sriov_funcs; 3051 else 3052 adev->nbio.funcs = &nbio_v4_3_funcs; 3053 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg; 3054 break; 3055 case IP_VERSION(7, 7, 0): 3056 case IP_VERSION(7, 7, 1): 3057 adev->nbio.funcs = &nbio_v7_7_funcs; 3058 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg; 3059 break; 3060 case IP_VERSION(6, 3, 1): 3061 adev->nbio.funcs = &nbif_v6_3_1_funcs; 3062 adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg; 3063 break; 3064 default: 3065 break; 3066 } 3067 3068 switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) { 3069 case IP_VERSION(4, 0, 0): 3070 case IP_VERSION(4, 0, 1): 3071 case IP_VERSION(4, 1, 0): 3072 case IP_VERSION(4, 1, 1): 3073 case IP_VERSION(4, 1, 2): 3074 case IP_VERSION(4, 2, 0): 3075 case IP_VERSION(4, 2, 1): 3076 case IP_VERSION(4, 4, 0): 3077 case IP_VERSION(4, 4, 2): 3078 case IP_VERSION(4, 4, 5): 3079 adev->hdp.funcs = &hdp_v4_0_funcs; 3080 break; 3081 case IP_VERSION(5, 0, 0): 3082 case IP_VERSION(5, 0, 1): 3083 case IP_VERSION(5, 0, 2): 3084 case IP_VERSION(5, 0, 3): 3085 case IP_VERSION(5, 0, 4): 3086 case IP_VERSION(5, 2, 0): 3087 adev->hdp.funcs = &hdp_v5_0_funcs; 3088 break; 3089 case IP_VERSION(5, 2, 1): 3090 adev->hdp.funcs = &hdp_v5_2_funcs; 3091 break; 3092 case IP_VERSION(6, 0, 0): 3093 case IP_VERSION(6, 0, 1): 3094 case IP_VERSION(6, 1, 0): 3095 adev->hdp.funcs = &hdp_v6_0_funcs; 3096 break; 3097 case IP_VERSION(7, 0, 0): 3098 adev->hdp.funcs = &hdp_v7_0_funcs; 3099 break; 3100 default: 3101 break; 3102 } 3103 3104 switch (amdgpu_ip_version(adev, DF_HWIP, 0)) { 3105 case IP_VERSION(3, 6, 0): 3106 case IP_VERSION(3, 6, 1): 3107 case IP_VERSION(3, 6, 2): 3108 adev->df.funcs = &df_v3_6_funcs; 3109 break; 3110 case IP_VERSION(2, 1, 0): 3111 case IP_VERSION(2, 1, 1): 3112 case IP_VERSION(2, 5, 0): 3113 case IP_VERSION(3, 5, 1): 3114 case IP_VERSION(3, 5, 2): 3115 adev->df.funcs = &df_v1_7_funcs; 3116 break; 3117 case IP_VERSION(4, 3, 0): 3118 adev->df.funcs = &df_v4_3_funcs; 3119 break; 3120 case IP_VERSION(4, 6, 2): 3121 adev->df.funcs = &df_v4_6_2_funcs; 3122 break; 3123 case IP_VERSION(4, 15, 0): 3124 case IP_VERSION(4, 15, 1): 3125 adev->df.funcs = &df_v4_15_funcs; 3126 break; 3127 default: 3128 break; 3129 } 3130 3131 switch (amdgpu_ip_version(adev, SMUIO_HWIP, 0)) { 3132 case IP_VERSION(9, 0, 0): 3133 case IP_VERSION(9, 0, 1): 3134 case IP_VERSION(10, 0, 0): 3135 case IP_VERSION(10, 0, 1): 3136 case IP_VERSION(10, 0, 2): 3137 adev->smuio.funcs = &smuio_v9_0_funcs; 3138 break; 3139 case IP_VERSION(11, 0, 0): 3140 case IP_VERSION(11, 0, 2): 3141 case IP_VERSION(11, 0, 3): 3142 case IP_VERSION(11, 0, 4): 3143 case IP_VERSION(11, 0, 7): 3144 case IP_VERSION(11, 0, 8): 3145 adev->smuio.funcs = &smuio_v11_0_funcs; 3146 break; 3147 case IP_VERSION(11, 0, 6): 3148 case IP_VERSION(11, 0, 10): 3149 case IP_VERSION(11, 0, 11): 3150 case IP_VERSION(11, 5, 0): 3151 case IP_VERSION(11, 5, 2): 3152 case IP_VERSION(13, 0, 1): 3153 case IP_VERSION(13, 0, 9): 3154 case IP_VERSION(13, 0, 10): 3155 adev->smuio.funcs = &smuio_v11_0_6_funcs; 3156 break; 3157 case IP_VERSION(13, 0, 2): 3158 adev->smuio.funcs = &smuio_v13_0_funcs; 3159 break; 3160 case IP_VERSION(13, 0, 3): 3161 case IP_VERSION(13, 0, 11): 3162 adev->smuio.funcs = &smuio_v13_0_3_funcs; 3163 if (adev->smuio.funcs->get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) { 3164 adev->flags |= AMD_IS_APU; 3165 } 3166 break; 3167 case IP_VERSION(13, 0, 6): 3168 case IP_VERSION(13, 0, 8): 3169 case IP_VERSION(14, 0, 0): 3170 case IP_VERSION(14, 0, 1): 3171 adev->smuio.funcs = &smuio_v13_0_6_funcs; 3172 break; 3173 case IP_VERSION(14, 0, 2): 3174 adev->smuio.funcs = &smuio_v14_0_2_funcs; 3175 break; 3176 case IP_VERSION(15, 0, 8): 3177 adev->smuio.funcs = &smuio_v15_0_8_funcs; 3178 break; 3179 default: 3180 break; 3181 } 3182 3183 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { 3184 case IP_VERSION(6, 0, 0): 3185 case IP_VERSION(6, 0, 1): 3186 case IP_VERSION(6, 0, 2): 3187 case IP_VERSION(6, 0, 3): 3188 adev->lsdma.funcs = &lsdma_v6_0_funcs; 3189 break; 3190 case IP_VERSION(7, 0, 0): 3191 case IP_VERSION(7, 0, 1): 3192 adev->lsdma.funcs = &lsdma_v7_0_funcs; 3193 break; 3194 default: 3195 break; 3196 } 3197 3198 r = amdgpu_discovery_set_common_ip_blocks(adev); 3199 if (r) 3200 return r; 3201 3202 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 3203 if (r) 3204 return r; 3205 3206 /* For SR-IOV, PSP needs to be initialized before IH */ 3207 if (amdgpu_sriov_vf(adev)) { 3208 r = amdgpu_discovery_set_psp_ip_blocks(adev); 3209 if (r) 3210 return r; 3211 r = amdgpu_discovery_set_ih_ip_blocks(adev); 3212 if (r) 3213 return r; 3214 } else { 3215 r = amdgpu_discovery_set_ih_ip_blocks(adev); 3216 if (r) 3217 return r; 3218 3219 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3220 r = amdgpu_discovery_set_psp_ip_blocks(adev); 3221 if (r) 3222 return r; 3223 } 3224 } 3225 3226 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3227 r = amdgpu_discovery_set_smu_ip_blocks(adev); 3228 if (r) 3229 return r; 3230 } 3231 3232 r = amdgpu_discovery_set_display_ip_blocks(adev); 3233 if (r) 3234 return r; 3235 3236 r = amdgpu_discovery_set_gc_ip_blocks(adev); 3237 if (r) 3238 return r; 3239 3240 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 3241 if (r) 3242 return r; 3243 3244 r = amdgpu_discovery_set_ras_ip_blocks(adev); 3245 if (r) 3246 return r; 3247 3248 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 3249 !amdgpu_sriov_vf(adev) && 3250 amdgpu_dpm == 1) || 3251 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && 3252 amdgpu_dpm == 1)) { 3253 r = amdgpu_discovery_set_smu_ip_blocks(adev); 3254 if (r) 3255 return r; 3256 } 3257 3258 r = amdgpu_discovery_set_mm_ip_blocks(adev); 3259 if (r) 3260 return r; 3261 3262 r = amdgpu_discovery_set_mes_ip_blocks(adev); 3263 if (r) 3264 return r; 3265 3266 r = amdgpu_discovery_set_vpe_ip_blocks(adev); 3267 if (r) 3268 return r; 3269 3270 r = amdgpu_discovery_set_umsch_mm_ip_blocks(adev); 3271 if (r) 3272 return r; 3273 3274 r = amdgpu_discovery_set_isp_ip_blocks(adev); 3275 if (r) 3276 return r; 3277 return 0; 3278 } 3279 3280