1 /* 2 * Copyright 2018-2024 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_discovery.h" 28 #include "soc15_hw_ip.h" 29 #include "discovery.h" 30 #include "amdgpu_ras.h" 31 32 #include "soc15.h" 33 #include "gfx_v9_0.h" 34 #include "gfx_v9_4_3.h" 35 #include "gmc_v9_0.h" 36 #include "df_v1_7.h" 37 #include "df_v3_6.h" 38 #include "df_v4_3.h" 39 #include "df_v4_6_2.h" 40 #include "df_v4_15.h" 41 #include "nbio_v6_1.h" 42 #include "nbio_v7_0.h" 43 #include "nbio_v7_4.h" 44 #include "nbio_v7_9.h" 45 #include "nbio_v7_11.h" 46 #include "hdp_v4_0.h" 47 #include "vega10_ih.h" 48 #include "vega20_ih.h" 49 #include "sdma_v4_0.h" 50 #include "sdma_v4_4_2.h" 51 #include "uvd_v7_0.h" 52 #include "vce_v4_0.h" 53 #include "vcn_v1_0.h" 54 #include "vcn_v2_5.h" 55 #include "jpeg_v2_5.h" 56 #include "smuio_v9_0.h" 57 #include "gmc_v10_0.h" 58 #include "gmc_v11_0.h" 59 #include "gmc_v12_0.h" 60 #include "gfxhub_v2_0.h" 61 #include "mmhub_v2_0.h" 62 #include "nbio_v2_3.h" 63 #include "nbio_v4_3.h" 64 #include "nbio_v7_2.h" 65 #include "nbio_v7_7.h" 66 #include "nbif_v6_3_1.h" 67 #include "hdp_v5_0.h" 68 #include "hdp_v5_2.h" 69 #include "hdp_v6_0.h" 70 #include "hdp_v7_0.h" 71 #include "nv.h" 72 #include "soc21.h" 73 #include "soc24.h" 74 #include "soc_v1_0.h" 75 #include "navi10_ih.h" 76 #include "ih_v6_0.h" 77 #include "ih_v6_1.h" 78 #include "ih_v7_0.h" 79 #include "gfx_v10_0.h" 80 #include "gfx_v11_0.h" 81 #include "gfx_v12_0.h" 82 #include "sdma_v5_0.h" 83 #include "sdma_v5_2.h" 84 #include "sdma_v6_0.h" 85 #include "sdma_v7_0.h" 86 #include "sdma_v7_1.h" 87 #include "lsdma_v6_0.h" 88 #include "lsdma_v7_0.h" 89 #include "vcn_v2_0.h" 90 #include "jpeg_v2_0.h" 91 #include "vcn_v3_0.h" 92 #include "jpeg_v3_0.h" 93 #include "vcn_v4_0.h" 94 #include "jpeg_v4_0.h" 95 #include "vcn_v4_0_3.h" 96 #include "jpeg_v4_0_3.h" 97 #include "vcn_v4_0_5.h" 98 #include "jpeg_v4_0_5.h" 99 #include "amdgpu_vkms.h" 100 #include "mes_v11_0.h" 101 #include "mes_v12_0.h" 102 #include "mes_v12_1.h" 103 #include "smuio_v11_0.h" 104 #include "smuio_v11_0_6.h" 105 #include "smuio_v13_0.h" 106 #include "smuio_v13_0_3.h" 107 #include "smuio_v13_0_6.h" 108 #include "smuio_v14_0_2.h" 109 #include "smuio_v15_0_8.h" 110 #include "vcn_v5_0_0.h" 111 #include "vcn_v5_0_1.h" 112 #include "jpeg_v5_0_0.h" 113 #include "jpeg_v5_0_1.h" 114 #include "amdgpu_ras_mgr.h" 115 116 #include "amdgpu_vpe.h" 117 #if defined(CONFIG_DRM_AMD_ISP) 118 #include "amdgpu_isp.h" 119 #endif 120 121 MODULE_FIRMWARE("amdgpu/ip_discovery.bin"); 122 MODULE_FIRMWARE("amdgpu/vega10_ip_discovery.bin"); 123 MODULE_FIRMWARE("amdgpu/vega12_ip_discovery.bin"); 124 MODULE_FIRMWARE("amdgpu/vega20_ip_discovery.bin"); 125 MODULE_FIRMWARE("amdgpu/raven_ip_discovery.bin"); 126 MODULE_FIRMWARE("amdgpu/raven2_ip_discovery.bin"); 127 MODULE_FIRMWARE("amdgpu/picasso_ip_discovery.bin"); 128 MODULE_FIRMWARE("amdgpu/arcturus_ip_discovery.bin"); 129 MODULE_FIRMWARE("amdgpu/aldebaran_ip_discovery.bin"); 130 131 #define mmIP_DISCOVERY_VERSION 0x16A00 132 #define mmRCC_CONFIG_MEMSIZE 0xde3 133 #define mmMP0_SMN_C2PMSG_33 0x16061 134 #define mmMM_INDEX 0x0 135 #define mmMM_INDEX_HI 0x6 136 #define mmMM_DATA 0x1 137 138 static const char *hw_id_names[HW_ID_MAX] = { 139 [MP1_HWID] = "MP1", 140 [MP2_HWID] = "MP2", 141 [THM_HWID] = "THM", 142 [SMUIO_HWID] = "SMUIO", 143 [FUSE_HWID] = "FUSE", 144 [CLKA_HWID] = "CLKA", 145 [PWR_HWID] = "PWR", 146 [GC_HWID] = "GC", 147 [UVD_HWID] = "UVD", 148 [AUDIO_AZ_HWID] = "AUDIO_AZ", 149 [ACP_HWID] = "ACP", 150 [DCI_HWID] = "DCI", 151 [DMU_HWID] = "DMU", 152 [DCO_HWID] = "DCO", 153 [DIO_HWID] = "DIO", 154 [XDMA_HWID] = "XDMA", 155 [DCEAZ_HWID] = "DCEAZ", 156 [DAZ_HWID] = "DAZ", 157 [SDPMUX_HWID] = "SDPMUX", 158 [NTB_HWID] = "NTB", 159 [IOHC_HWID] = "IOHC", 160 [L2IMU_HWID] = "L2IMU", 161 [VCE_HWID] = "VCE", 162 [MMHUB_HWID] = "MMHUB", 163 [ATHUB_HWID] = "ATHUB", 164 [DBGU_NBIO_HWID] = "DBGU_NBIO", 165 [DFX_HWID] = "DFX", 166 [DBGU0_HWID] = "DBGU0", 167 [DBGU1_HWID] = "DBGU1", 168 [OSSSYS_HWID] = "OSSSYS", 169 [HDP_HWID] = "HDP", 170 [SDMA0_HWID] = "SDMA0", 171 [SDMA1_HWID] = "SDMA1", 172 [SDMA2_HWID] = "SDMA2", 173 [SDMA3_HWID] = "SDMA3", 174 [LSDMA_HWID] = "LSDMA", 175 [ISP_HWID] = "ISP", 176 [DBGU_IO_HWID] = "DBGU_IO", 177 [DF_HWID] = "DF", 178 [CLKB_HWID] = "CLKB", 179 [FCH_HWID] = "FCH", 180 [DFX_DAP_HWID] = "DFX_DAP", 181 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 182 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 183 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 184 [L1IMU3_HWID] = "L1IMU3", 185 [L1IMU4_HWID] = "L1IMU4", 186 [L1IMU5_HWID] = "L1IMU5", 187 [L1IMU6_HWID] = "L1IMU6", 188 [L1IMU7_HWID] = "L1IMU7", 189 [L1IMU8_HWID] = "L1IMU8", 190 [L1IMU9_HWID] = "L1IMU9", 191 [L1IMU10_HWID] = "L1IMU10", 192 [L1IMU11_HWID] = "L1IMU11", 193 [L1IMU12_HWID] = "L1IMU12", 194 [L1IMU13_HWID] = "L1IMU13", 195 [L1IMU14_HWID] = "L1IMU14", 196 [L1IMU15_HWID] = "L1IMU15", 197 [WAFLC_HWID] = "WAFLC", 198 [FCH_USB_PD_HWID] = "FCH_USB_PD", 199 [PCIE_HWID] = "PCIE", 200 [PCS_HWID] = "PCS", 201 [DDCL_HWID] = "DDCL", 202 [SST_HWID] = "SST", 203 [IOAGR_HWID] = "IOAGR", 204 [NBIF_HWID] = "NBIF", 205 [IOAPIC_HWID] = "IOAPIC", 206 [SYSTEMHUB_HWID] = "SYSTEMHUB", 207 [NTBCCP_HWID] = "NTBCCP", 208 [UMC_HWID] = "UMC", 209 [SATA_HWID] = "SATA", 210 [USB_HWID] = "USB", 211 [CCXSEC_HWID] = "CCXSEC", 212 [XGMI_HWID] = "XGMI", 213 [XGBE_HWID] = "XGBE", 214 [MP0_HWID] = "MP0", 215 [VPE_HWID] = "VPE", 216 [ATU_HWID] = "ATU", 217 [AIGC_HWID] = "AIGC", 218 }; 219 220 static int hw_id_map[MAX_HWIP] = { 221 [GC_HWIP] = GC_HWID, 222 [HDP_HWIP] = HDP_HWID, 223 [SDMA0_HWIP] = SDMA0_HWID, 224 [SDMA1_HWIP] = SDMA1_HWID, 225 [SDMA2_HWIP] = SDMA2_HWID, 226 [SDMA3_HWIP] = SDMA3_HWID, 227 [LSDMA_HWIP] = LSDMA_HWID, 228 [MMHUB_HWIP] = MMHUB_HWID, 229 [ATHUB_HWIP] = ATHUB_HWID, 230 [NBIO_HWIP] = NBIF_HWID, 231 [MP0_HWIP] = MP0_HWID, 232 [MP1_HWIP] = MP1_HWID, 233 [UVD_HWIP] = UVD_HWID, 234 [VCE_HWIP] = VCE_HWID, 235 [DF_HWIP] = DF_HWID, 236 [DCE_HWIP] = DMU_HWID, 237 [OSSSYS_HWIP] = OSSSYS_HWID, 238 [SMUIO_HWIP] = SMUIO_HWID, 239 [PWR_HWIP] = PWR_HWID, 240 [NBIF_HWIP] = NBIF_HWID, 241 [THM_HWIP] = THM_HWID, 242 [CLK_HWIP] = CLKA_HWID, 243 [UMC_HWIP] = UMC_HWID, 244 [XGMI_HWIP] = XGMI_HWID, 245 [DCI_HWIP] = DCI_HWID, 246 [PCIE_HWIP] = PCIE_HWID, 247 [VPE_HWIP] = VPE_HWID, 248 [ISP_HWIP] = ISP_HWID, 249 [ATU_HWIP] = ATU_HWID, 250 }; 251 252 static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary) 253 { 254 u64 tmr_offset, tmr_size, pos; 255 void *discv_regn; 256 int ret; 257 258 ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size); 259 if (ret) 260 return ret; 261 262 pos = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET; 263 264 /* This region is read-only and reserved from system use */ 265 discv_regn = memremap(pos, adev->discovery.size, MEMREMAP_WC); 266 if (discv_regn) { 267 memcpy(binary, discv_regn, adev->discovery.size); 268 memunmap(discv_regn); 269 return 0; 270 } 271 272 return -ENOENT; 273 } 274 275 #define IP_DISCOVERY_V2 2 276 #define IP_DISCOVERY_V4 4 277 278 static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, 279 uint8_t *binary) 280 { 281 bool sz_valid = true; 282 uint64_t vram_size; 283 int i, ret = 0; 284 u32 msg; 285 286 if (!amdgpu_sriov_vf(adev)) { 287 /* It can take up to two second for IFWI init to complete on some dGPUs, 288 * but generally it should be in the 60-100ms range. Normally this starts 289 * as soon as the device gets power so by the time the OS loads this has long 290 * completed. However, when a card is hotplugged via e.g., USB4, we need to 291 * wait for this to complete. Once the C2PMSG is updated, we can 292 * continue. 293 */ 294 295 for (i = 0; i < 2000; i++) { 296 msg = RREG32(mmMP0_SMN_C2PMSG_33); 297 if (msg & 0x80000000) 298 break; 299 msleep(1); 300 } 301 } 302 303 vram_size = RREG32(mmRCC_CONFIG_MEMSIZE); 304 if (!vram_size || vram_size == U32_MAX) 305 sz_valid = false; 306 else 307 vram_size <<= 20; 308 309 /* 310 * If in VRAM, discovery TMR is marked for reservation. If it is in system mem, 311 * then it is not required to be reserved. 312 */ 313 if (sz_valid) { 314 if (amdgpu_sriov_vf(adev) && adev->virt.is_dynamic_crit_regn_enabled) { 315 /* For SRIOV VFs with dynamic critical region enabled, 316 * we will get the IPD binary via below call. 317 * If dynamic critical is disabled, fall through to normal seq. 318 */ 319 if (amdgpu_virt_get_dynamic_data_info(adev, 320 AMD_SRIOV_MSG_IPD_TABLE_ID, binary, 321 &adev->discovery.size)) { 322 dev_err(adev->dev, 323 "failed to read discovery info from dynamic critical region."); 324 ret = -EINVAL; 325 goto exit; 326 } 327 } else { 328 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; 329 330 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, 331 adev->discovery.size, false); 332 adev->discovery.reserve_tmr = true; 333 } 334 } else { 335 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); 336 } 337 338 if (ret) 339 dev_err(adev->dev, 340 "failed to read discovery info from memory, vram size read: %llx", 341 vram_size); 342 exit: 343 return ret; 344 } 345 346 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, 347 uint8_t *binary, 348 const char *fw_name) 349 { 350 const struct firmware *fw; 351 int r; 352 353 r = firmware_request_nowarn(&fw, fw_name, adev->dev); 354 if (r) { 355 if (amdgpu_discovery == 2) 356 dev_err(adev->dev, "can't load firmware \"%s\"\n", fw_name); 357 else 358 drm_info(&adev->ddev, "Optional firmware \"%s\" was not found\n", fw_name); 359 return r; 360 } 361 362 memcpy((u8 *)binary, (u8 *)fw->data, fw->size); 363 release_firmware(fw); 364 365 return 0; 366 } 367 368 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 369 { 370 uint16_t checksum = 0; 371 int i; 372 373 for (i = 0; i < size; i++) 374 checksum += data[i]; 375 376 return checksum; 377 } 378 379 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size, 380 uint16_t expected) 381 { 382 return !!(amdgpu_discovery_calculate_checksum(data, size) == expected); 383 } 384 385 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 386 { 387 struct binary_header *bhdr; 388 bhdr = (struct binary_header *)binary; 389 390 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 391 } 392 393 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) 394 { 395 /* 396 * So far, apply this quirk only on those Navy Flounder boards which 397 * have a bad harvest table of VCN config. 398 */ 399 if ((amdgpu_ip_version(adev, UVD_HWIP, 1) == IP_VERSION(3, 0, 1)) && 400 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 2))) { 401 switch (adev->pdev->revision) { 402 case 0xC1: 403 case 0xC2: 404 case 0xC3: 405 case 0xC5: 406 case 0xC7: 407 case 0xCF: 408 case 0xDF: 409 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 410 adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1; 411 break; 412 default: 413 break; 414 } 415 } 416 } 417 418 static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev, 419 struct binary_header *bhdr) 420 { 421 uint8_t *discovery_bin = adev->discovery.bin; 422 struct table_info *info; 423 uint16_t checksum; 424 uint16_t offset; 425 426 info = &bhdr->table_list[NPS_INFO]; 427 offset = le16_to_cpu(info->offset); 428 checksum = le16_to_cpu(info->checksum); 429 430 struct nps_info_header *nhdr = 431 (struct nps_info_header *)(discovery_bin + offset); 432 433 if (le32_to_cpu(nhdr->table_id) != NPS_INFO_TABLE_ID) { 434 dev_dbg(adev->dev, "invalid ip discovery nps info table id\n"); 435 return -EINVAL; 436 } 437 438 if (!amdgpu_discovery_verify_checksum(discovery_bin + offset, 439 le32_to_cpu(nhdr->size_bytes), 440 checksum)) { 441 dev_dbg(adev->dev, "invalid nps info data table checksum\n"); 442 return -EINVAL; 443 } 444 445 return 0; 446 } 447 448 static const char *amdgpu_discovery_get_fw_name(struct amdgpu_device *adev) 449 { 450 if (amdgpu_discovery == 2) { 451 /* Assume there is valid discovery TMR in VRAM even if binary is sideloaded */ 452 adev->discovery.reserve_tmr = true; 453 return "amdgpu/ip_discovery.bin"; 454 } 455 456 switch (adev->asic_type) { 457 case CHIP_VEGA10: 458 return "amdgpu/vega10_ip_discovery.bin"; 459 case CHIP_VEGA12: 460 return "amdgpu/vega12_ip_discovery.bin"; 461 case CHIP_RAVEN: 462 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 463 return "amdgpu/raven2_ip_discovery.bin"; 464 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 465 return "amdgpu/picasso_ip_discovery.bin"; 466 else 467 return "amdgpu/raven_ip_discovery.bin"; 468 case CHIP_VEGA20: 469 return "amdgpu/vega20_ip_discovery.bin"; 470 case CHIP_ARCTURUS: 471 return "amdgpu/arcturus_ip_discovery.bin"; 472 case CHIP_ALDEBARAN: 473 return "amdgpu/aldebaran_ip_discovery.bin"; 474 default: 475 return NULL; 476 } 477 } 478 479 static int amdgpu_discovery_init(struct amdgpu_device *adev) 480 { 481 struct table_info *info; 482 struct binary_header *bhdr; 483 uint8_t *discovery_bin; 484 const char *fw_name; 485 uint16_t offset; 486 uint16_t size; 487 uint16_t checksum; 488 int r; 489 490 adev->discovery.bin = kzalloc(DISCOVERY_TMR_SIZE, GFP_KERNEL); 491 if (!adev->discovery.bin) 492 return -ENOMEM; 493 adev->discovery.size = DISCOVERY_TMR_SIZE; 494 adev->discovery.debugfs_blob.data = adev->discovery.bin; 495 adev->discovery.debugfs_blob.size = adev->discovery.size; 496 497 discovery_bin = adev->discovery.bin; 498 /* Read from file if it is the preferred option */ 499 fw_name = amdgpu_discovery_get_fw_name(adev); 500 if (fw_name != NULL) { 501 drm_dbg(&adev->ddev, "use ip discovery information from file"); 502 r = amdgpu_discovery_read_binary_from_file(adev, discovery_bin, 503 fw_name); 504 if (r) 505 goto out; 506 } else { 507 drm_dbg(&adev->ddev, "use ip discovery information from memory"); 508 r = amdgpu_discovery_read_binary_from_mem(adev, discovery_bin); 509 if (r) 510 goto out; 511 } 512 513 /* check the ip discovery binary signature */ 514 if (!amdgpu_discovery_verify_binary_signature(discovery_bin)) { 515 dev_err(adev->dev, 516 "get invalid ip discovery binary signature\n"); 517 r = -EINVAL; 518 goto out; 519 } 520 521 bhdr = (struct binary_header *)discovery_bin; 522 523 offset = offsetof(struct binary_header, binary_checksum) + 524 sizeof(bhdr->binary_checksum); 525 size = le16_to_cpu(bhdr->binary_size) - offset; 526 checksum = le16_to_cpu(bhdr->binary_checksum); 527 528 if (!amdgpu_discovery_verify_checksum(discovery_bin + offset, size, 529 checksum)) { 530 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 531 r = -EINVAL; 532 goto out; 533 } 534 535 info = &bhdr->table_list[IP_DISCOVERY]; 536 offset = le16_to_cpu(info->offset); 537 checksum = le16_to_cpu(info->checksum); 538 539 if (offset) { 540 struct ip_discovery_header *ihdr = 541 (struct ip_discovery_header *)(discovery_bin + offset); 542 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { 543 dev_err(adev->dev, "invalid ip discovery data table signature\n"); 544 r = -EINVAL; 545 goto out; 546 } 547 548 if (!amdgpu_discovery_verify_checksum(discovery_bin + offset, 549 le16_to_cpu(ihdr->size), 550 checksum)) { 551 dev_err(adev->dev, "invalid ip discovery data table checksum\n"); 552 r = -EINVAL; 553 goto out; 554 } 555 } 556 557 info = &bhdr->table_list[GC]; 558 offset = le16_to_cpu(info->offset); 559 checksum = le16_to_cpu(info->checksum); 560 561 if (offset) { 562 struct gpu_info_header *ghdr = 563 (struct gpu_info_header *)(discovery_bin + offset); 564 565 if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) { 566 dev_err(adev->dev, "invalid ip discovery gc table id\n"); 567 r = -EINVAL; 568 goto out; 569 } 570 571 if (!amdgpu_discovery_verify_checksum(discovery_bin + offset, 572 le32_to_cpu(ghdr->size), 573 checksum)) { 574 dev_err(adev->dev, "invalid gc data table checksum\n"); 575 r = -EINVAL; 576 goto out; 577 } 578 } 579 580 info = &bhdr->table_list[HARVEST_INFO]; 581 offset = le16_to_cpu(info->offset); 582 checksum = le16_to_cpu(info->checksum); 583 584 if (offset) { 585 struct harvest_info_header *hhdr = 586 (struct harvest_info_header *)(discovery_bin + offset); 587 588 if (le32_to_cpu(hhdr->signature) != HARVEST_TABLE_SIGNATURE) { 589 dev_err(adev->dev, "invalid ip discovery harvest table signature\n"); 590 r = -EINVAL; 591 goto out; 592 } 593 594 if (!amdgpu_discovery_verify_checksum( 595 discovery_bin + offset, 596 sizeof(struct harvest_table), checksum)) { 597 dev_err(adev->dev, "invalid harvest data table checksum\n"); 598 r = -EINVAL; 599 goto out; 600 } 601 } 602 603 info = &bhdr->table_list[VCN_INFO]; 604 offset = le16_to_cpu(info->offset); 605 checksum = le16_to_cpu(info->checksum); 606 607 if (offset) { 608 struct vcn_info_header *vhdr = 609 (struct vcn_info_header *)(discovery_bin + offset); 610 611 if (le32_to_cpu(vhdr->table_id) != VCN_INFO_TABLE_ID) { 612 dev_err(adev->dev, "invalid ip discovery vcn table id\n"); 613 r = -EINVAL; 614 goto out; 615 } 616 617 if (!amdgpu_discovery_verify_checksum( 618 discovery_bin + offset, 619 le32_to_cpu(vhdr->size_bytes), checksum)) { 620 dev_err(adev->dev, "invalid vcn data table checksum\n"); 621 r = -EINVAL; 622 goto out; 623 } 624 } 625 626 info = &bhdr->table_list[MALL_INFO]; 627 offset = le16_to_cpu(info->offset); 628 checksum = le16_to_cpu(info->checksum); 629 630 if (0 && offset) { 631 struct mall_info_header *mhdr = 632 (struct mall_info_header *)(discovery_bin + offset); 633 634 if (le32_to_cpu(mhdr->table_id) != MALL_INFO_TABLE_ID) { 635 dev_err(adev->dev, "invalid ip discovery mall table id\n"); 636 r = -EINVAL; 637 goto out; 638 } 639 640 if (!amdgpu_discovery_verify_checksum( 641 discovery_bin + offset, 642 le32_to_cpu(mhdr->size_bytes), checksum)) { 643 dev_err(adev->dev, "invalid mall data table checksum\n"); 644 r = -EINVAL; 645 goto out; 646 } 647 } 648 649 return 0; 650 651 out: 652 kfree(adev->discovery.bin); 653 adev->discovery.bin = NULL; 654 if ((amdgpu_discovery != 2) && 655 (RREG32(mmIP_DISCOVERY_VERSION) == 4)) 656 amdgpu_ras_query_boot_status(adev, 4); 657 return r; 658 } 659 660 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev); 661 662 void amdgpu_discovery_fini(struct amdgpu_device *adev) 663 { 664 amdgpu_discovery_sysfs_fini(adev); 665 kfree(adev->discovery.bin); 666 adev->discovery.bin = NULL; 667 } 668 669 static int amdgpu_discovery_validate_ip(struct amdgpu_device *adev, 670 uint8_t instance, uint16_t hw_id) 671 { 672 if (instance >= HWIP_MAX_INSTANCE) { 673 dev_err(adev->dev, 674 "Unexpected instance_number (%d) from ip discovery blob\n", 675 instance); 676 return -EINVAL; 677 } 678 if (hw_id >= HW_ID_MAX) { 679 dev_err(adev->dev, 680 "Unexpected hw_id (%d) from ip discovery blob\n", 681 hw_id); 682 return -EINVAL; 683 } 684 685 return 0; 686 } 687 688 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev, 689 uint32_t *vcn_harvest_count) 690 { 691 uint8_t *discovery_bin = adev->discovery.bin; 692 struct binary_header *bhdr; 693 struct ip_discovery_header *ihdr; 694 struct die_header *dhdr; 695 struct ip *ip; 696 uint16_t die_offset, ip_offset, num_dies, num_ips; 697 uint16_t hw_id; 698 uint8_t inst; 699 int i, j; 700 701 bhdr = (struct binary_header *)discovery_bin; 702 ihdr = (struct ip_discovery_header 703 *)(discovery_bin + 704 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 705 num_dies = le16_to_cpu(ihdr->num_dies); 706 707 /* scan harvest bit of all IP data structures */ 708 for (i = 0; i < num_dies; i++) { 709 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 710 dhdr = (struct die_header *)(discovery_bin + die_offset); 711 num_ips = le16_to_cpu(dhdr->num_ips); 712 ip_offset = die_offset + sizeof(*dhdr); 713 714 for (j = 0; j < num_ips; j++) { 715 ip = (struct ip *)(discovery_bin + ip_offset); 716 inst = ip->number_instance; 717 hw_id = le16_to_cpu(ip->hw_id); 718 if (amdgpu_discovery_validate_ip(adev, inst, hw_id)) 719 goto next_ip; 720 721 if (ip->harvest == 1) { 722 switch (hw_id) { 723 case VCN_HWID: 724 (*vcn_harvest_count)++; 725 if (inst == 0) { 726 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 727 adev->vcn.inst_mask &= 728 ~AMDGPU_VCN_HARVEST_VCN0; 729 adev->jpeg.inst_mask &= 730 ~AMDGPU_VCN_HARVEST_VCN0; 731 } else { 732 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 733 adev->vcn.inst_mask &= 734 ~AMDGPU_VCN_HARVEST_VCN1; 735 adev->jpeg.inst_mask &= 736 ~AMDGPU_VCN_HARVEST_VCN1; 737 } 738 break; 739 case DMU_HWID: 740 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 741 break; 742 default: 743 break; 744 } 745 } 746 next_ip: 747 ip_offset += struct_size(ip, base_address, 748 ip->num_base_address); 749 } 750 } 751 } 752 753 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, 754 uint32_t *vcn_harvest_count, 755 uint32_t *umc_harvest_count) 756 { 757 uint8_t *discovery_bin = adev->discovery.bin; 758 struct binary_header *bhdr; 759 struct harvest_table *harvest_info; 760 u16 offset; 761 int i; 762 uint32_t umc_harvest_config = 0; 763 764 bhdr = (struct binary_header *)discovery_bin; 765 offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset); 766 767 if (!offset) { 768 dev_err(adev->dev, "invalid harvest table offset\n"); 769 return; 770 } 771 772 harvest_info = (struct harvest_table *)(discovery_bin + offset); 773 774 for (i = 0; i < 32; i++) { 775 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) 776 break; 777 778 switch (le16_to_cpu(harvest_info->list[i].hw_id)) { 779 case VCN_HWID: 780 (*vcn_harvest_count)++; 781 adev->vcn.harvest_config |= 782 (1 << harvest_info->list[i].number_instance); 783 adev->jpeg.harvest_config |= 784 (1 << harvest_info->list[i].number_instance); 785 786 adev->vcn.inst_mask &= 787 ~(1U << harvest_info->list[i].number_instance); 788 adev->jpeg.inst_mask &= 789 ~(1U << harvest_info->list[i].number_instance); 790 break; 791 case DMU_HWID: 792 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 793 break; 794 case UMC_HWID: 795 umc_harvest_config |= 796 1 << (le16_to_cpu(harvest_info->list[i].number_instance)); 797 (*umc_harvest_count)++; 798 break; 799 case GC_HWID: 800 adev->gfx.xcc_mask &= 801 ~(1U << harvest_info->list[i].number_instance); 802 break; 803 case SDMA0_HWID: 804 adev->sdma.sdma_mask &= 805 ~(1U << harvest_info->list[i].number_instance); 806 break; 807 #if defined(CONFIG_DRM_AMD_ISP) 808 case ISP_HWID: 809 adev->isp.harvest_config |= 810 ~(1U << harvest_info->list[i].number_instance); 811 break; 812 #endif 813 default: 814 break; 815 } 816 } 817 818 adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) & 819 ~umc_harvest_config; 820 } 821 822 /* ================================================== */ 823 824 struct ip_hw_instance { 825 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */ 826 827 int hw_id; 828 u8 num_instance; 829 u8 major, minor, revision; 830 u8 harvest; 831 832 int num_base_addresses; 833 u32 base_addr[] __counted_by(num_base_addresses); 834 }; 835 836 struct ip_hw_id { 837 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */ 838 int hw_id; 839 }; 840 841 struct ip_die_entry { 842 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */ 843 u16 num_ips; 844 }; 845 846 /* -------------------------------------------------- */ 847 848 struct ip_hw_instance_attr { 849 struct attribute attr; 850 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf); 851 }; 852 853 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf) 854 { 855 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id); 856 } 857 858 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf) 859 { 860 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance); 861 } 862 863 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf) 864 { 865 return sysfs_emit(buf, "%d\n", ip_hw_instance->major); 866 } 867 868 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf) 869 { 870 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor); 871 } 872 873 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf) 874 { 875 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision); 876 } 877 878 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf) 879 { 880 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest); 881 } 882 883 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf) 884 { 885 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses); 886 } 887 888 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) 889 { 890 ssize_t res, at; 891 int ii; 892 893 for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 894 /* Here we satisfy the condition that, at + size <= PAGE_SIZE. 895 */ 896 if (at + 12 > PAGE_SIZE) 897 break; 898 res = sysfs_emit_at(buf, at, "0x%08X\n", 899 ip_hw_instance->base_addr[ii]); 900 if (res <= 0) 901 break; 902 at += res; 903 } 904 905 return res < 0 ? res : at; 906 } 907 908 static struct ip_hw_instance_attr ip_hw_attr[] = { 909 __ATTR_RO(hw_id), 910 __ATTR_RO(num_instance), 911 __ATTR_RO(major), 912 __ATTR_RO(minor), 913 __ATTR_RO(revision), 914 __ATTR_RO(harvest), 915 __ATTR_RO(num_base_addresses), 916 __ATTR_RO(base_addr), 917 }; 918 919 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; 920 ATTRIBUTE_GROUPS(ip_hw_instance); 921 922 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) 923 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) 924 925 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj, 926 struct attribute *attr, 927 char *buf) 928 { 929 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 930 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr); 931 932 if (!ip_hw_attr->show) 933 return -EIO; 934 935 return ip_hw_attr->show(ip_hw_instance, buf); 936 } 937 938 static const struct sysfs_ops ip_hw_instance_sysfs_ops = { 939 .show = ip_hw_instance_attr_show, 940 }; 941 942 static void ip_hw_instance_release(struct kobject *kobj) 943 { 944 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 945 946 kfree(ip_hw_instance); 947 } 948 949 static const struct kobj_type ip_hw_instance_ktype = { 950 .release = ip_hw_instance_release, 951 .sysfs_ops = &ip_hw_instance_sysfs_ops, 952 .default_groups = ip_hw_instance_groups, 953 }; 954 955 /* -------------------------------------------------- */ 956 957 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset) 958 959 static void ip_hw_id_release(struct kobject *kobj) 960 { 961 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj); 962 963 if (!list_empty(&ip_hw_id->hw_id_kset.list)) 964 DRM_ERROR("ip_hw_id->hw_id_kset is not empty"); 965 kfree(ip_hw_id); 966 } 967 968 static const struct kobj_type ip_hw_id_ktype = { 969 .release = ip_hw_id_release, 970 .sysfs_ops = &kobj_sysfs_ops, 971 }; 972 973 /* -------------------------------------------------- */ 974 975 static void die_kobj_release(struct kobject *kobj); 976 static void ip_disc_release(struct kobject *kobj); 977 978 struct ip_die_entry_attribute { 979 struct attribute attr; 980 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf); 981 }; 982 983 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr) 984 985 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf) 986 { 987 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips); 988 } 989 990 /* If there are more ip_die_entry attrs, other than the number of IPs, 991 * we can make this intro an array of attrs, and then initialize 992 * ip_die_entry_attrs in a loop. 993 */ 994 static struct ip_die_entry_attribute num_ips_attr = 995 __ATTR_RO(num_ips); 996 997 static struct attribute *ip_die_entry_attrs[] = { 998 &num_ips_attr.attr, 999 NULL, 1000 }; 1001 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ 1002 1003 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) 1004 1005 static ssize_t ip_die_entry_attr_show(struct kobject *kobj, 1006 struct attribute *attr, 1007 char *buf) 1008 { 1009 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr); 1010 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 1011 1012 if (!ip_die_entry_attr->show) 1013 return -EIO; 1014 1015 return ip_die_entry_attr->show(ip_die_entry, buf); 1016 } 1017 1018 static void ip_die_entry_release(struct kobject *kobj) 1019 { 1020 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 1021 1022 if (!list_empty(&ip_die_entry->ip_kset.list)) 1023 DRM_ERROR("ip_die_entry->ip_kset is not empty"); 1024 kfree(ip_die_entry); 1025 } 1026 1027 static const struct sysfs_ops ip_die_entry_sysfs_ops = { 1028 .show = ip_die_entry_attr_show, 1029 }; 1030 1031 static const struct kobj_type ip_die_entry_ktype = { 1032 .release = ip_die_entry_release, 1033 .sysfs_ops = &ip_die_entry_sysfs_ops, 1034 .default_groups = ip_die_entry_groups, 1035 }; 1036 1037 static const struct kobj_type die_kobj_ktype = { 1038 .release = die_kobj_release, 1039 .sysfs_ops = &kobj_sysfs_ops, 1040 }; 1041 1042 static const struct kobj_type ip_discovery_ktype = { 1043 .release = ip_disc_release, 1044 .sysfs_ops = &kobj_sysfs_ops, 1045 }; 1046 1047 struct ip_discovery_top { 1048 struct kobject kobj; /* ip_discovery/ */ 1049 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */ 1050 struct amdgpu_device *adev; 1051 }; 1052 1053 static void die_kobj_release(struct kobject *kobj) 1054 { 1055 struct ip_discovery_top *ip_top = container_of(to_kset(kobj), 1056 struct ip_discovery_top, 1057 die_kset); 1058 if (!list_empty(&ip_top->die_kset.list)) 1059 DRM_ERROR("ip_top->die_kset is not empty"); 1060 } 1061 1062 static void ip_disc_release(struct kobject *kobj) 1063 { 1064 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top, 1065 kobj); 1066 struct amdgpu_device *adev = ip_top->adev; 1067 1068 kfree(ip_top); 1069 adev->discovery.ip_top = NULL; 1070 } 1071 1072 static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev, 1073 uint16_t hw_id, uint8_t inst) 1074 { 1075 uint8_t harvest = 0; 1076 1077 /* Until a uniform way is figured, get mask based on hwid */ 1078 switch (hw_id) { 1079 case VCN_HWID: 1080 /* VCN vs UVD+VCE */ 1081 if (!amdgpu_ip_version(adev, VCE_HWIP, 0)) 1082 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0; 1083 break; 1084 case DMU_HWID: 1085 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK) 1086 harvest = 0x1; 1087 break; 1088 case UMC_HWID: 1089 /* TODO: It needs another parsing; for now, ignore.*/ 1090 break; 1091 case GC_HWID: 1092 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; 1093 break; 1094 case SDMA0_HWID: 1095 harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0; 1096 break; 1097 default: 1098 break; 1099 } 1100 1101 return harvest; 1102 } 1103 1104 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, 1105 struct ip_die_entry *ip_die_entry, 1106 const size_t _ip_offset, const int num_ips, 1107 bool reg_base_64) 1108 { 1109 uint8_t *discovery_bin = adev->discovery.bin; 1110 int ii, jj, kk, res; 1111 uint16_t hw_id; 1112 uint8_t inst; 1113 1114 DRM_DEBUG("num_ips:%d", num_ips); 1115 1116 /* Find all IPs of a given HW ID, and add their instance to 1117 * #die/#hw_id/#instance/<attributes> 1118 */ 1119 for (ii = 0; ii < HW_ID_MAX; ii++) { 1120 struct ip_hw_id *ip_hw_id = NULL; 1121 size_t ip_offset = _ip_offset; 1122 1123 for (jj = 0; jj < num_ips; jj++) { 1124 struct ip_v4 *ip; 1125 struct ip_hw_instance *ip_hw_instance; 1126 1127 ip = (struct ip_v4 *)(discovery_bin + ip_offset); 1128 inst = ip->instance_number; 1129 hw_id = le16_to_cpu(ip->hw_id); 1130 if (amdgpu_discovery_validate_ip(adev, inst, hw_id) || 1131 hw_id != ii) 1132 goto next_ip; 1133 1134 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset); 1135 1136 /* We have a hw_id match; register the hw 1137 * block if not yet registered. 1138 */ 1139 if (!ip_hw_id) { 1140 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL); 1141 if (!ip_hw_id) 1142 return -ENOMEM; 1143 ip_hw_id->hw_id = ii; 1144 1145 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii); 1146 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset; 1147 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype; 1148 res = kset_register(&ip_hw_id->hw_id_kset); 1149 if (res) { 1150 DRM_ERROR("Couldn't register ip_hw_id kset"); 1151 kfree(ip_hw_id); 1152 return res; 1153 } 1154 if (hw_id_names[ii]) { 1155 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj, 1156 &ip_hw_id->hw_id_kset.kobj, 1157 hw_id_names[ii]); 1158 if (res) { 1159 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n", 1160 hw_id_names[ii], 1161 kobject_name(&ip_die_entry->ip_kset.kobj)); 1162 } 1163 } 1164 } 1165 1166 /* Now register its instance. 1167 */ 1168 ip_hw_instance = kzalloc(struct_size(ip_hw_instance, 1169 base_addr, 1170 ip->num_base_address), 1171 GFP_KERNEL); 1172 if (!ip_hw_instance) { 1173 DRM_ERROR("no memory for ip_hw_instance"); 1174 return -ENOMEM; 1175 } 1176 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */ 1177 ip_hw_instance->num_instance = ip->instance_number; 1178 ip_hw_instance->major = ip->major; 1179 ip_hw_instance->minor = ip->minor; 1180 ip_hw_instance->revision = ip->revision; 1181 ip_hw_instance->harvest = 1182 amdgpu_discovery_get_harvest_info( 1183 adev, ip_hw_instance->hw_id, 1184 ip_hw_instance->num_instance); 1185 ip_hw_instance->num_base_addresses = ip->num_base_address; 1186 1187 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) { 1188 if (reg_base_64) 1189 ip_hw_instance->base_addr[kk] = 1190 lower_32_bits(le64_to_cpu(ip->base_address_64[kk])) & 0x3FFFFFFF; 1191 else 1192 ip_hw_instance->base_addr[kk] = ip->base_address[kk]; 1193 } 1194 1195 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); 1196 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; 1197 res = kobject_add(&ip_hw_instance->kobj, NULL, 1198 "%d", ip_hw_instance->num_instance); 1199 next_ip: 1200 if (reg_base_64) 1201 ip_offset += struct_size(ip, base_address_64, 1202 ip->num_base_address); 1203 else 1204 ip_offset += struct_size(ip, base_address, 1205 ip->num_base_address); 1206 } 1207 } 1208 1209 return 0; 1210 } 1211 1212 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) 1213 { 1214 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1215 uint8_t *discovery_bin = adev->discovery.bin; 1216 struct binary_header *bhdr; 1217 struct ip_discovery_header *ihdr; 1218 struct die_header *dhdr; 1219 struct kset *die_kset = &ip_top->die_kset; 1220 u16 num_dies, die_offset, num_ips; 1221 size_t ip_offset; 1222 int ii, res; 1223 1224 bhdr = (struct binary_header *)discovery_bin; 1225 ihdr = (struct ip_discovery_header 1226 *)(discovery_bin + 1227 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1228 num_dies = le16_to_cpu(ihdr->num_dies); 1229 1230 DRM_DEBUG("number of dies: %d\n", num_dies); 1231 1232 for (ii = 0; ii < num_dies; ii++) { 1233 struct ip_die_entry *ip_die_entry; 1234 1235 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); 1236 dhdr = (struct die_header *)(discovery_bin + die_offset); 1237 num_ips = le16_to_cpu(dhdr->num_ips); 1238 ip_offset = die_offset + sizeof(*dhdr); 1239 1240 /* Add the die to the kset. 1241 * 1242 * dhdr->die_id == ii, which was checked in 1243 * amdgpu_discovery_reg_base_init(). 1244 */ 1245 1246 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL); 1247 if (!ip_die_entry) 1248 return -ENOMEM; 1249 1250 ip_die_entry->num_ips = num_ips; 1251 1252 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id)); 1253 ip_die_entry->ip_kset.kobj.kset = die_kset; 1254 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype; 1255 res = kset_register(&ip_die_entry->ip_kset); 1256 if (res) { 1257 DRM_ERROR("Couldn't register ip_die_entry kset"); 1258 kfree(ip_die_entry); 1259 return res; 1260 } 1261 1262 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips, !!ihdr->base_addr_64_bit); 1263 } 1264 1265 return 0; 1266 } 1267 1268 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) 1269 { 1270 uint8_t *discovery_bin = adev->discovery.bin; 1271 struct ip_discovery_top *ip_top; 1272 struct kset *die_kset; 1273 int res, ii; 1274 1275 if (!discovery_bin) 1276 return -EINVAL; 1277 1278 ip_top = kzalloc(sizeof(*ip_top), GFP_KERNEL); 1279 if (!ip_top) 1280 return -ENOMEM; 1281 1282 ip_top->adev = adev; 1283 adev->discovery.ip_top = ip_top; 1284 res = kobject_init_and_add(&ip_top->kobj, &ip_discovery_ktype, 1285 &adev->dev->kobj, "ip_discovery"); 1286 if (res) { 1287 DRM_ERROR("Couldn't init and add ip_discovery/"); 1288 goto Err; 1289 } 1290 1291 die_kset = &ip_top->die_kset; 1292 kobject_set_name(&die_kset->kobj, "%s", "die"); 1293 die_kset->kobj.parent = &ip_top->kobj; 1294 die_kset->kobj.ktype = &die_kobj_ktype; 1295 res = kset_register(&ip_top->die_kset); 1296 if (res) { 1297 DRM_ERROR("Couldn't register die_kset"); 1298 goto Err; 1299 } 1300 1301 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++) 1302 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr; 1303 ip_hw_instance_attrs[ii] = NULL; 1304 1305 res = amdgpu_discovery_sysfs_recurse(adev); 1306 1307 return res; 1308 Err: 1309 kobject_put(&ip_top->kobj); 1310 return res; 1311 } 1312 1313 /* -------------------------------------------------- */ 1314 1315 #define list_to_kobj(el) container_of(el, struct kobject, entry) 1316 1317 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id) 1318 { 1319 struct list_head *el, *tmp; 1320 struct kset *hw_id_kset; 1321 1322 hw_id_kset = &ip_hw_id->hw_id_kset; 1323 spin_lock(&hw_id_kset->list_lock); 1324 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) { 1325 list_del_init(el); 1326 spin_unlock(&hw_id_kset->list_lock); 1327 /* kobject is embedded in ip_hw_instance */ 1328 kobject_put(list_to_kobj(el)); 1329 spin_lock(&hw_id_kset->list_lock); 1330 } 1331 spin_unlock(&hw_id_kset->list_lock); 1332 kobject_put(&ip_hw_id->hw_id_kset.kobj); 1333 } 1334 1335 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry) 1336 { 1337 struct list_head *el, *tmp; 1338 struct kset *ip_kset; 1339 1340 ip_kset = &ip_die_entry->ip_kset; 1341 spin_lock(&ip_kset->list_lock); 1342 list_for_each_prev_safe(el, tmp, &ip_kset->list) { 1343 list_del_init(el); 1344 spin_unlock(&ip_kset->list_lock); 1345 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el))); 1346 spin_lock(&ip_kset->list_lock); 1347 } 1348 spin_unlock(&ip_kset->list_lock); 1349 kobject_put(&ip_die_entry->ip_kset.kobj); 1350 } 1351 1352 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) 1353 { 1354 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1355 struct list_head *el, *tmp; 1356 struct kset *die_kset; 1357 1358 die_kset = &ip_top->die_kset; 1359 spin_lock(&die_kset->list_lock); 1360 list_for_each_prev_safe(el, tmp, &die_kset->list) { 1361 list_del_init(el); 1362 spin_unlock(&die_kset->list_lock); 1363 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 1364 spin_lock(&die_kset->list_lock); 1365 } 1366 spin_unlock(&die_kset->list_lock); 1367 kobject_put(&ip_top->die_kset.kobj); 1368 kobject_put(&ip_top->kobj); 1369 } 1370 1371 /* ================================================== */ 1372 1373 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 1374 { 1375 uint8_t num_base_address, subrev, variant; 1376 struct binary_header *bhdr; 1377 struct ip_discovery_header *ihdr; 1378 struct die_header *dhdr; 1379 uint8_t *discovery_bin; 1380 struct ip_v4 *ip; 1381 uint16_t die_offset; 1382 uint16_t ip_offset; 1383 uint16_t num_dies; 1384 uint32_t wafl_ver; 1385 uint16_t num_ips; 1386 uint16_t hw_id; 1387 uint8_t inst; 1388 int hw_ip; 1389 int i, j, k; 1390 int r; 1391 1392 r = amdgpu_discovery_init(adev); 1393 if (r) 1394 return r; 1395 discovery_bin = adev->discovery.bin; 1396 wafl_ver = 0; 1397 adev->gfx.xcc_mask = 0; 1398 adev->sdma.sdma_mask = 0; 1399 adev->vcn.inst_mask = 0; 1400 adev->jpeg.inst_mask = 0; 1401 bhdr = (struct binary_header *)discovery_bin; 1402 ihdr = (struct ip_discovery_header 1403 *)(discovery_bin + 1404 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 1405 num_dies = le16_to_cpu(ihdr->num_dies); 1406 1407 DRM_DEBUG("number of dies: %d\n", num_dies); 1408 1409 for (i = 0; i < num_dies; i++) { 1410 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1411 dhdr = (struct die_header *)(discovery_bin + die_offset); 1412 num_ips = le16_to_cpu(dhdr->num_ips); 1413 ip_offset = die_offset + sizeof(*dhdr); 1414 1415 if (le16_to_cpu(dhdr->die_id) != i) { 1416 DRM_ERROR("invalid die id %d, expected %d\n", 1417 le16_to_cpu(dhdr->die_id), i); 1418 return -EINVAL; 1419 } 1420 1421 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 1422 le16_to_cpu(dhdr->die_id), num_ips); 1423 1424 for (j = 0; j < num_ips; j++) { 1425 ip = (struct ip_v4 *)(discovery_bin + ip_offset); 1426 1427 inst = ip->instance_number; 1428 hw_id = le16_to_cpu(ip->hw_id); 1429 if (amdgpu_discovery_validate_ip(adev, inst, hw_id)) 1430 goto next_ip; 1431 1432 num_base_address = ip->num_base_address; 1433 1434 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 1435 hw_id_names[le16_to_cpu(ip->hw_id)], 1436 le16_to_cpu(ip->hw_id), 1437 ip->instance_number, 1438 ip->major, ip->minor, 1439 ip->revision); 1440 1441 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 1442 /* Bit [5:0]: original revision value 1443 * Bit [7:6]: en/decode capability: 1444 * 0b00 : VCN function normally 1445 * 0b10 : encode is disabled 1446 * 0b01 : decode is disabled 1447 */ 1448 if (adev->vcn.num_vcn_inst < 1449 AMDGPU_MAX_VCN_INSTANCES) { 1450 adev->vcn.inst[adev->vcn.num_vcn_inst].vcn_config = 1451 ip->revision & 0xc0; 1452 adev->vcn.num_vcn_inst++; 1453 adev->vcn.inst_mask |= 1454 (1U << ip->instance_number); 1455 adev->jpeg.inst_mask |= 1456 (1U << ip->instance_number); 1457 } else { 1458 dev_err(adev->dev, "Too many VCN instances: %d vs %d\n", 1459 adev->vcn.num_vcn_inst + 1, 1460 AMDGPU_MAX_VCN_INSTANCES); 1461 } 1462 ip->revision &= ~0xc0; 1463 } 1464 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 1465 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 1466 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 1467 le16_to_cpu(ip->hw_id) == SDMA3_HWID) { 1468 if (adev->sdma.num_instances < 1469 AMDGPU_MAX_SDMA_INSTANCES) { 1470 adev->sdma.num_instances++; 1471 adev->sdma.sdma_mask |= 1472 (1U << ip->instance_number); 1473 } else { 1474 dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n", 1475 adev->sdma.num_instances + 1, 1476 AMDGPU_MAX_SDMA_INSTANCES); 1477 } 1478 } 1479 1480 if (le16_to_cpu(ip->hw_id) == VPE_HWID) { 1481 if (adev->vpe.num_instances < AMDGPU_MAX_VPE_INSTANCES) 1482 adev->vpe.num_instances++; 1483 else 1484 dev_err(adev->dev, "Too many VPE instances: %d vs %d\n", 1485 adev->vpe.num_instances + 1, 1486 AMDGPU_MAX_VPE_INSTANCES); 1487 } 1488 1489 if (le16_to_cpu(ip->hw_id) == UMC_HWID) { 1490 adev->gmc.num_umc++; 1491 adev->umc.node_inst_num++; 1492 } 1493 1494 if (le16_to_cpu(ip->hw_id) == GC_HWID) 1495 adev->gfx.xcc_mask |= 1496 (1U << ip->instance_number); 1497 1498 if (!wafl_ver && le16_to_cpu(ip->hw_id) == WAFLC_HWID) 1499 wafl_ver = IP_VERSION_FULL(ip->major, ip->minor, 1500 ip->revision, 0, 0); 1501 1502 for (k = 0; k < num_base_address; k++) { 1503 /* 1504 * convert the endianness of base addresses in place, 1505 * so that we don't need to convert them when accessing adev->reg_offset. 1506 */ 1507 if (ihdr->base_addr_64_bit) 1508 /* Truncate the 64bit base address from ip discovery 1509 * and only store lower 32bit ip base in reg_offset[]. 1510 * Bits > 32 follows ASIC specific format, thus just 1511 * discard them and handle it within specific ASIC. 1512 * By this way reg_offset[] and related helpers can 1513 * stay unchanged. 1514 * The base address is in dwords, thus clear the 1515 * highest 2 bits to store. 1516 */ 1517 ip->base_address[k] = 1518 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF; 1519 else 1520 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 1521 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 1522 } 1523 1524 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 1525 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) && 1526 hw_id_map[hw_ip] != 0) { 1527 DRM_DEBUG("set register base offset for %s\n", 1528 hw_id_names[le16_to_cpu(ip->hw_id)]); 1529 adev->reg_offset[hw_ip][ip->instance_number] = 1530 ip->base_address; 1531 /* Instance support is somewhat inconsistent. 1532 * SDMA is a good example. Sienna cichlid has 4 total 1533 * SDMA instances, each enumerated separately (HWIDs 1534 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 1535 * but they are enumerated as multiple instances of the 1536 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 1537 * example. On most chips there are multiple instances 1538 * with the same HWID. 1539 */ 1540 1541 if (ihdr->version < 3) { 1542 subrev = 0; 1543 variant = 0; 1544 } else { 1545 subrev = ip->sub_revision; 1546 variant = ip->variant; 1547 } 1548 1549 adev->ip_versions[hw_ip] 1550 [ip->instance_number] = 1551 IP_VERSION_FULL(ip->major, 1552 ip->minor, 1553 ip->revision, 1554 variant, 1555 subrev); 1556 } 1557 } 1558 1559 next_ip: 1560 if (ihdr->base_addr_64_bit) 1561 ip_offset += struct_size(ip, base_address_64, ip->num_base_address); 1562 else 1563 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1564 } 1565 } 1566 1567 if (wafl_ver && !adev->ip_versions[XGMI_HWIP][0]) 1568 adev->ip_versions[XGMI_HWIP][0] = wafl_ver; 1569 1570 return 0; 1571 } 1572 1573 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 1574 { 1575 uint8_t *discovery_bin = adev->discovery.bin; 1576 struct ip_discovery_header *ihdr; 1577 struct binary_header *bhdr; 1578 int vcn_harvest_count = 0; 1579 int umc_harvest_count = 0; 1580 uint16_t offset, ihdr_ver; 1581 1582 bhdr = (struct binary_header *)discovery_bin; 1583 offset = le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset); 1584 ihdr = (struct ip_discovery_header *)(discovery_bin + offset); 1585 ihdr_ver = le16_to_cpu(ihdr->version); 1586 /* 1587 * Harvest table does not fit Navi1x and legacy GPUs, 1588 * so read harvest bit per IP data structure to set 1589 * harvest configuration. 1590 */ 1591 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 2, 0) && 1592 ihdr_ver <= 2) { 1593 if ((adev->pdev->device == 0x731E && 1594 (adev->pdev->revision == 0xC6 || 1595 adev->pdev->revision == 0xC7)) || 1596 (adev->pdev->device == 0x7340 && 1597 adev->pdev->revision == 0xC9) || 1598 (adev->pdev->device == 0x7360 && 1599 adev->pdev->revision == 0xC7)) 1600 amdgpu_discovery_read_harvest_bit_per_ip(adev, 1601 &vcn_harvest_count); 1602 } else { 1603 amdgpu_discovery_read_from_harvest_table(adev, 1604 &vcn_harvest_count, 1605 &umc_harvest_count); 1606 } 1607 1608 amdgpu_discovery_harvest_config_quirk(adev); 1609 1610 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 1611 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 1612 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 1613 } 1614 1615 if (umc_harvest_count < adev->gmc.num_umc) { 1616 adev->gmc.num_umc -= umc_harvest_count; 1617 } 1618 } 1619 1620 union gc_info { 1621 struct gc_info_v1_0 v1; 1622 struct gc_info_v1_1 v1_1; 1623 struct gc_info_v1_2 v1_2; 1624 struct gc_info_v1_3 v1_3; 1625 struct gc_info_v2_0 v2; 1626 struct gc_info_v2_1 v2_1; 1627 }; 1628 1629 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 1630 { 1631 uint8_t *discovery_bin = adev->discovery.bin; 1632 struct binary_header *bhdr; 1633 union gc_info *gc_info; 1634 u16 offset; 1635 1636 if (!discovery_bin) { 1637 DRM_ERROR("ip discovery uninitialized\n"); 1638 return -EINVAL; 1639 } 1640 1641 bhdr = (struct binary_header *)discovery_bin; 1642 offset = le16_to_cpu(bhdr->table_list[GC].offset); 1643 1644 if (!offset) 1645 return 0; 1646 1647 gc_info = (union gc_info *)(discovery_bin + offset); 1648 1649 switch (le16_to_cpu(gc_info->v1.header.version_major)) { 1650 case 1: 1651 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); 1652 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 1653 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); 1654 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1655 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); 1656 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); 1657 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); 1658 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); 1659 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); 1660 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); 1661 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); 1662 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); 1663 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); 1664 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); 1665 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); 1666 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / 1667 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1668 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); 1669 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 1) { 1670 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa); 1671 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface); 1672 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps); 1673 } 1674 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 2) { 1675 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg); 1676 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size); 1677 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp); 1678 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc); 1679 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc); 1680 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa); 1681 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance); 1682 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu); 1683 } 1684 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 3) { 1685 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v1_3.gc_tcp_size_per_cu); 1686 adev->gfx.config.gc_tcp_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcp_cache_line_size); 1687 adev->gfx.config.gc_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_size_per_sqc); 1688 adev->gfx.config.gc_instruction_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_line_size); 1689 adev->gfx.config.gc_scalar_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_size_per_sqc); 1690 adev->gfx.config.gc_scalar_data_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_line_size); 1691 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v1_3.gc_tcc_size); 1692 adev->gfx.config.gc_tcc_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcc_cache_line_size); 1693 } 1694 break; 1695 case 2: 1696 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); 1697 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); 1698 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1699 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); 1700 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); 1701 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); 1702 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); 1703 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); 1704 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); 1705 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); 1706 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); 1707 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); 1708 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); 1709 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); 1710 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / 1711 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1712 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); 1713 if (le16_to_cpu(gc_info->v2.header.version_minor) == 1) { 1714 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh); 1715 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu); 1716 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XCD */ 1717 adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc); 1718 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_cache_size_per_sqc); 1719 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_size_per_sqc); 1720 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */ 1721 } 1722 break; 1723 default: 1724 dev_err(adev->dev, 1725 "Unhandled GC info table %d.%d\n", 1726 le16_to_cpu(gc_info->v1.header.version_major), 1727 le16_to_cpu(gc_info->v1.header.version_minor)); 1728 return -EINVAL; 1729 } 1730 return 0; 1731 } 1732 1733 union mall_info { 1734 struct mall_info_v1_0 v1; 1735 struct mall_info_v2_0 v2; 1736 }; 1737 1738 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) 1739 { 1740 uint8_t *discovery_bin = adev->discovery.bin; 1741 struct binary_header *bhdr; 1742 union mall_info *mall_info; 1743 u32 u, mall_size_per_umc, m_s_present, half_use; 1744 u64 mall_size; 1745 u16 offset; 1746 1747 if (!discovery_bin) { 1748 DRM_ERROR("ip discovery uninitialized\n"); 1749 return -EINVAL; 1750 } 1751 1752 bhdr = (struct binary_header *)discovery_bin; 1753 offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset); 1754 1755 if (!offset) 1756 return 0; 1757 1758 mall_info = (union mall_info *)(discovery_bin + offset); 1759 1760 switch (le16_to_cpu(mall_info->v1.header.version_major)) { 1761 case 1: 1762 mall_size = 0; 1763 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m); 1764 m_s_present = le32_to_cpu(mall_info->v1.m_s_present); 1765 half_use = le32_to_cpu(mall_info->v1.m_half_use); 1766 for (u = 0; u < adev->gmc.num_umc; u++) { 1767 if (m_s_present & (1 << u)) 1768 mall_size += mall_size_per_umc * 2; 1769 else if (half_use & (1 << u)) 1770 mall_size += mall_size_per_umc / 2; 1771 else 1772 mall_size += mall_size_per_umc; 1773 } 1774 adev->gmc.mall_size = mall_size; 1775 adev->gmc.m_half_use = half_use; 1776 break; 1777 case 2: 1778 mall_size_per_umc = le32_to_cpu(mall_info->v2.mall_size_per_umc); 1779 adev->gmc.mall_size = (uint64_t)mall_size_per_umc * adev->gmc.num_umc; 1780 break; 1781 default: 1782 dev_err(adev->dev, 1783 "Unhandled MALL info table %d.%d\n", 1784 le16_to_cpu(mall_info->v1.header.version_major), 1785 le16_to_cpu(mall_info->v1.header.version_minor)); 1786 return -EINVAL; 1787 } 1788 return 0; 1789 } 1790 1791 union vcn_info { 1792 struct vcn_info_v1_0 v1; 1793 }; 1794 1795 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) 1796 { 1797 uint8_t *discovery_bin = adev->discovery.bin; 1798 struct binary_header *bhdr; 1799 union vcn_info *vcn_info; 1800 u16 offset; 1801 int v; 1802 1803 if (!discovery_bin) { 1804 DRM_ERROR("ip discovery uninitialized\n"); 1805 return -EINVAL; 1806 } 1807 1808 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1809 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES 1810 * but that may change in the future with new GPUs so keep this 1811 * check for defensive purposes. 1812 */ 1813 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { 1814 dev_err(adev->dev, "invalid vcn instances\n"); 1815 return -EINVAL; 1816 } 1817 1818 bhdr = (struct binary_header *)discovery_bin; 1819 offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset); 1820 1821 if (!offset) 1822 return 0; 1823 1824 vcn_info = (union vcn_info *)(discovery_bin + offset); 1825 1826 switch (le16_to_cpu(vcn_info->v1.header.version_major)) { 1827 case 1: 1828 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1829 * so this won't overflow. 1830 */ 1831 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { 1832 adev->vcn.inst[v].vcn_codec_disable_mask = 1833 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits); 1834 } 1835 break; 1836 default: 1837 dev_err(adev->dev, 1838 "Unhandled VCN info table %d.%d\n", 1839 le16_to_cpu(vcn_info->v1.header.version_major), 1840 le16_to_cpu(vcn_info->v1.header.version_minor)); 1841 return -EINVAL; 1842 } 1843 return 0; 1844 } 1845 1846 union nps_info { 1847 struct nps_info_v1_0 v1; 1848 }; 1849 1850 static int amdgpu_discovery_refresh_nps_info(struct amdgpu_device *adev, 1851 union nps_info *nps_data) 1852 { 1853 uint64_t vram_size, pos, offset; 1854 struct nps_info_header *nhdr; 1855 struct binary_header bhdr; 1856 uint16_t checksum; 1857 1858 vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 1859 pos = vram_size - DISCOVERY_TMR_OFFSET; 1860 amdgpu_device_vram_access(adev, pos, &bhdr, sizeof(bhdr), false); 1861 1862 offset = le16_to_cpu(bhdr.table_list[NPS_INFO].offset); 1863 checksum = le16_to_cpu(bhdr.table_list[NPS_INFO].checksum); 1864 1865 amdgpu_device_vram_access(adev, (pos + offset), nps_data, 1866 sizeof(*nps_data), false); 1867 1868 nhdr = (struct nps_info_header *)(nps_data); 1869 if (!amdgpu_discovery_verify_checksum((uint8_t *)nps_data, 1870 le32_to_cpu(nhdr->size_bytes), 1871 checksum)) { 1872 dev_err(adev->dev, "nps data refresh, checksum mismatch\n"); 1873 return -EINVAL; 1874 } 1875 1876 return 0; 1877 } 1878 1879 int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, 1880 uint32_t *nps_type, 1881 struct amdgpu_gmc_memrange **ranges, 1882 int *range_cnt, bool refresh) 1883 { 1884 uint8_t *discovery_bin = adev->discovery.bin; 1885 struct amdgpu_gmc_memrange *mem_ranges; 1886 struct binary_header *bhdr; 1887 union nps_info *nps_info; 1888 union nps_info nps_data; 1889 u16 offset; 1890 int i, r; 1891 1892 if (!nps_type || !range_cnt || !ranges) 1893 return -EINVAL; 1894 1895 if (refresh) { 1896 r = amdgpu_discovery_refresh_nps_info(adev, &nps_data); 1897 if (r) 1898 return r; 1899 nps_info = &nps_data; 1900 } else { 1901 if (!discovery_bin) { 1902 dev_err(adev->dev, 1903 "fetch mem range failed, ip discovery uninitialized\n"); 1904 return -EINVAL; 1905 } 1906 1907 bhdr = (struct binary_header *)discovery_bin; 1908 offset = le16_to_cpu(bhdr->table_list[NPS_INFO].offset); 1909 1910 if (!offset) 1911 return -ENOENT; 1912 1913 /* If verification fails, return as if NPS table doesn't exist */ 1914 if (amdgpu_discovery_verify_npsinfo(adev, bhdr)) 1915 return -ENOENT; 1916 1917 nps_info = (union nps_info *)(discovery_bin + offset); 1918 } 1919 1920 switch (le16_to_cpu(nps_info->v1.header.version_major)) { 1921 case 1: 1922 mem_ranges = kvcalloc(nps_info->v1.count, 1923 sizeof(*mem_ranges), 1924 GFP_KERNEL); 1925 if (!mem_ranges) 1926 return -ENOMEM; 1927 *nps_type = nps_info->v1.nps_type; 1928 *range_cnt = nps_info->v1.count; 1929 for (i = 0; i < *range_cnt; i++) { 1930 mem_ranges[i].base_address = 1931 nps_info->v1.instance_info[i].base_address; 1932 mem_ranges[i].limit_address = 1933 nps_info->v1.instance_info[i].limit_address; 1934 mem_ranges[i].nid_mask = -1; 1935 mem_ranges[i].flags = 0; 1936 } 1937 *ranges = mem_ranges; 1938 break; 1939 default: 1940 dev_err(adev->dev, "Unhandled NPS info table %d.%d\n", 1941 le16_to_cpu(nps_info->v1.header.version_major), 1942 le16_to_cpu(nps_info->v1.header.version_minor)); 1943 return -EINVAL; 1944 } 1945 1946 return 0; 1947 } 1948 1949 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 1950 { 1951 /* what IP to use for this? */ 1952 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1953 case IP_VERSION(9, 0, 1): 1954 case IP_VERSION(9, 1, 0): 1955 case IP_VERSION(9, 2, 1): 1956 case IP_VERSION(9, 2, 2): 1957 case IP_VERSION(9, 3, 0): 1958 case IP_VERSION(9, 4, 0): 1959 case IP_VERSION(9, 4, 1): 1960 case IP_VERSION(9, 4, 2): 1961 case IP_VERSION(9, 4, 3): 1962 case IP_VERSION(9, 4, 4): 1963 case IP_VERSION(9, 5, 0): 1964 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 1965 break; 1966 case IP_VERSION(10, 1, 10): 1967 case IP_VERSION(10, 1, 1): 1968 case IP_VERSION(10, 1, 2): 1969 case IP_VERSION(10, 1, 3): 1970 case IP_VERSION(10, 1, 4): 1971 case IP_VERSION(10, 3, 0): 1972 case IP_VERSION(10, 3, 1): 1973 case IP_VERSION(10, 3, 2): 1974 case IP_VERSION(10, 3, 3): 1975 case IP_VERSION(10, 3, 4): 1976 case IP_VERSION(10, 3, 5): 1977 case IP_VERSION(10, 3, 6): 1978 case IP_VERSION(10, 3, 7): 1979 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 1980 break; 1981 case IP_VERSION(11, 0, 0): 1982 case IP_VERSION(11, 0, 1): 1983 case IP_VERSION(11, 0, 2): 1984 case IP_VERSION(11, 0, 3): 1985 case IP_VERSION(11, 0, 4): 1986 case IP_VERSION(11, 5, 0): 1987 case IP_VERSION(11, 5, 1): 1988 case IP_VERSION(11, 5, 2): 1989 case IP_VERSION(11, 5, 3): 1990 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); 1991 break; 1992 case IP_VERSION(12, 0, 0): 1993 case IP_VERSION(12, 0, 1): 1994 amdgpu_device_ip_block_add(adev, &soc24_common_ip_block); 1995 break; 1996 case IP_VERSION(12, 1, 0): 1997 amdgpu_device_ip_block_add(adev, &soc_v1_0_common_ip_block); 1998 break; 1999 default: 2000 dev_err(adev->dev, 2001 "Failed to add common ip block(GC_HWIP:0x%x)\n", 2002 amdgpu_ip_version(adev, GC_HWIP, 0)); 2003 return -EINVAL; 2004 } 2005 return 0; 2006 } 2007 2008 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 2009 { 2010 /* use GC or MMHUB IP version */ 2011 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2012 case IP_VERSION(9, 0, 1): 2013 case IP_VERSION(9, 1, 0): 2014 case IP_VERSION(9, 2, 1): 2015 case IP_VERSION(9, 2, 2): 2016 case IP_VERSION(9, 3, 0): 2017 case IP_VERSION(9, 4, 0): 2018 case IP_VERSION(9, 4, 1): 2019 case IP_VERSION(9, 4, 2): 2020 case IP_VERSION(9, 4, 3): 2021 case IP_VERSION(9, 4, 4): 2022 case IP_VERSION(9, 5, 0): 2023 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 2024 break; 2025 case IP_VERSION(10, 1, 10): 2026 case IP_VERSION(10, 1, 1): 2027 case IP_VERSION(10, 1, 2): 2028 case IP_VERSION(10, 1, 3): 2029 case IP_VERSION(10, 1, 4): 2030 case IP_VERSION(10, 3, 0): 2031 case IP_VERSION(10, 3, 1): 2032 case IP_VERSION(10, 3, 2): 2033 case IP_VERSION(10, 3, 3): 2034 case IP_VERSION(10, 3, 4): 2035 case IP_VERSION(10, 3, 5): 2036 case IP_VERSION(10, 3, 6): 2037 case IP_VERSION(10, 3, 7): 2038 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 2039 break; 2040 case IP_VERSION(11, 0, 0): 2041 case IP_VERSION(11, 0, 1): 2042 case IP_VERSION(11, 0, 2): 2043 case IP_VERSION(11, 0, 3): 2044 case IP_VERSION(11, 0, 4): 2045 case IP_VERSION(11, 5, 0): 2046 case IP_VERSION(11, 5, 1): 2047 case IP_VERSION(11, 5, 2): 2048 case IP_VERSION(11, 5, 3): 2049 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block); 2050 break; 2051 case IP_VERSION(12, 0, 0): 2052 case IP_VERSION(12, 0, 1): 2053 case IP_VERSION(12, 1, 0): 2054 amdgpu_device_ip_block_add(adev, &gmc_v12_0_ip_block); 2055 break; 2056 default: 2057 dev_err(adev->dev, "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 2058 amdgpu_ip_version(adev, GC_HWIP, 0)); 2059 return -EINVAL; 2060 } 2061 return 0; 2062 } 2063 2064 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 2065 { 2066 switch (amdgpu_ip_version(adev, OSSSYS_HWIP, 0)) { 2067 case IP_VERSION(4, 0, 0): 2068 case IP_VERSION(4, 0, 1): 2069 case IP_VERSION(4, 1, 0): 2070 case IP_VERSION(4, 1, 1): 2071 case IP_VERSION(4, 3, 0): 2072 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 2073 break; 2074 case IP_VERSION(4, 2, 0): 2075 case IP_VERSION(4, 2, 1): 2076 case IP_VERSION(4, 4, 0): 2077 case IP_VERSION(4, 4, 2): 2078 case IP_VERSION(4, 4, 5): 2079 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 2080 break; 2081 case IP_VERSION(5, 0, 0): 2082 case IP_VERSION(5, 0, 1): 2083 case IP_VERSION(5, 0, 2): 2084 case IP_VERSION(5, 0, 3): 2085 case IP_VERSION(5, 2, 0): 2086 case IP_VERSION(5, 2, 1): 2087 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 2088 break; 2089 case IP_VERSION(6, 0, 0): 2090 case IP_VERSION(6, 0, 1): 2091 case IP_VERSION(6, 0, 2): 2092 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block); 2093 break; 2094 case IP_VERSION(6, 1, 0): 2095 amdgpu_device_ip_block_add(adev, &ih_v6_1_ip_block); 2096 break; 2097 case IP_VERSION(7, 0, 0): 2098 case IP_VERSION(7, 1, 0): 2099 amdgpu_device_ip_block_add(adev, &ih_v7_0_ip_block); 2100 break; 2101 default: 2102 dev_err(adev->dev, 2103 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 2104 amdgpu_ip_version(adev, OSSSYS_HWIP, 0)); 2105 return -EINVAL; 2106 } 2107 return 0; 2108 } 2109 2110 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 2111 { 2112 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 2113 case IP_VERSION(9, 0, 0): 2114 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 2115 break; 2116 case IP_VERSION(10, 0, 0): 2117 case IP_VERSION(10, 0, 1): 2118 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 2119 break; 2120 case IP_VERSION(11, 0, 0): 2121 case IP_VERSION(11, 0, 2): 2122 case IP_VERSION(11, 0, 4): 2123 case IP_VERSION(11, 0, 5): 2124 case IP_VERSION(11, 0, 9): 2125 case IP_VERSION(11, 0, 7): 2126 case IP_VERSION(11, 0, 11): 2127 case IP_VERSION(11, 0, 12): 2128 case IP_VERSION(11, 0, 13): 2129 case IP_VERSION(11, 5, 0): 2130 case IP_VERSION(11, 5, 2): 2131 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 2132 break; 2133 case IP_VERSION(11, 0, 8): 2134 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 2135 break; 2136 case IP_VERSION(11, 0, 3): 2137 case IP_VERSION(12, 0, 1): 2138 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 2139 break; 2140 case IP_VERSION(13, 0, 0): 2141 case IP_VERSION(13, 0, 1): 2142 case IP_VERSION(13, 0, 2): 2143 case IP_VERSION(13, 0, 3): 2144 case IP_VERSION(13, 0, 5): 2145 case IP_VERSION(13, 0, 6): 2146 case IP_VERSION(13, 0, 7): 2147 case IP_VERSION(13, 0, 8): 2148 case IP_VERSION(13, 0, 10): 2149 case IP_VERSION(13, 0, 11): 2150 case IP_VERSION(13, 0, 12): 2151 case IP_VERSION(13, 0, 14): 2152 case IP_VERSION(14, 0, 0): 2153 case IP_VERSION(14, 0, 1): 2154 case IP_VERSION(14, 0, 4): 2155 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 2156 break; 2157 case IP_VERSION(13, 0, 4): 2158 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block); 2159 break; 2160 case IP_VERSION(14, 0, 2): 2161 case IP_VERSION(14, 0, 3): 2162 case IP_VERSION(14, 0, 5): 2163 amdgpu_device_ip_block_add(adev, &psp_v14_0_ip_block); 2164 break; 2165 case IP_VERSION(15, 0, 8): 2166 amdgpu_device_ip_block_add(adev, &psp_v15_0_8_ip_block); 2167 break; 2168 default: 2169 dev_err(adev->dev, 2170 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 2171 amdgpu_ip_version(adev, MP0_HWIP, 0)); 2172 return -EINVAL; 2173 } 2174 return 0; 2175 } 2176 2177 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 2178 { 2179 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2180 case IP_VERSION(9, 0, 0): 2181 case IP_VERSION(10, 0, 0): 2182 case IP_VERSION(10, 0, 1): 2183 case IP_VERSION(11, 0, 2): 2184 if (adev->asic_type == CHIP_ARCTURUS) 2185 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2186 else 2187 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 2188 break; 2189 case IP_VERSION(11, 0, 0): 2190 case IP_VERSION(11, 0, 5): 2191 case IP_VERSION(11, 0, 9): 2192 case IP_VERSION(11, 0, 7): 2193 case IP_VERSION(11, 0, 11): 2194 case IP_VERSION(11, 0, 12): 2195 case IP_VERSION(11, 0, 13): 2196 case IP_VERSION(11, 5, 0): 2197 case IP_VERSION(11, 5, 2): 2198 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2199 break; 2200 case IP_VERSION(11, 0, 8): 2201 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) 2202 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2203 break; 2204 case IP_VERSION(12, 0, 0): 2205 case IP_VERSION(12, 0, 1): 2206 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 2207 break; 2208 case IP_VERSION(13, 0, 0): 2209 case IP_VERSION(13, 0, 1): 2210 case IP_VERSION(13, 0, 2): 2211 case IP_VERSION(13, 0, 3): 2212 case IP_VERSION(13, 0, 4): 2213 case IP_VERSION(13, 0, 5): 2214 case IP_VERSION(13, 0, 6): 2215 case IP_VERSION(13, 0, 7): 2216 case IP_VERSION(13, 0, 8): 2217 case IP_VERSION(13, 0, 10): 2218 case IP_VERSION(13, 0, 11): 2219 case IP_VERSION(13, 0, 14): 2220 case IP_VERSION(13, 0, 12): 2221 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 2222 break; 2223 case IP_VERSION(14, 0, 0): 2224 case IP_VERSION(14, 0, 1): 2225 case IP_VERSION(14, 0, 2): 2226 case IP_VERSION(14, 0, 3): 2227 case IP_VERSION(14, 0, 4): 2228 case IP_VERSION(14, 0, 5): 2229 amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block); 2230 break; 2231 default: 2232 dev_err(adev->dev, 2233 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 2234 amdgpu_ip_version(adev, MP1_HWIP, 0)); 2235 return -EINVAL; 2236 } 2237 return 0; 2238 } 2239 2240 #if defined(CONFIG_DRM_AMD_DC) 2241 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev) 2242 { 2243 amdgpu_device_set_sriov_virtual_display(adev); 2244 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2245 } 2246 #endif 2247 2248 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 2249 { 2250 if (adev->enable_virtual_display) { 2251 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2252 return 0; 2253 } 2254 2255 if (!amdgpu_device_has_dc_support(adev)) 2256 return 0; 2257 2258 #if defined(CONFIG_DRM_AMD_DC) 2259 if (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2260 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2261 case IP_VERSION(1, 0, 0): 2262 case IP_VERSION(1, 0, 1): 2263 case IP_VERSION(2, 0, 2): 2264 case IP_VERSION(2, 0, 0): 2265 case IP_VERSION(2, 0, 3): 2266 case IP_VERSION(2, 1, 0): 2267 case IP_VERSION(3, 0, 0): 2268 case IP_VERSION(3, 0, 2): 2269 case IP_VERSION(3, 0, 3): 2270 case IP_VERSION(3, 0, 1): 2271 case IP_VERSION(3, 1, 2): 2272 case IP_VERSION(3, 1, 3): 2273 case IP_VERSION(3, 1, 4): 2274 case IP_VERSION(3, 1, 5): 2275 case IP_VERSION(3, 1, 6): 2276 case IP_VERSION(3, 2, 0): 2277 case IP_VERSION(3, 2, 1): 2278 case IP_VERSION(3, 5, 0): 2279 case IP_VERSION(3, 5, 1): 2280 case IP_VERSION(3, 6, 0): 2281 case IP_VERSION(4, 1, 0): 2282 /* TODO: Fix IP version. DC code expects version 4.0.1 */ 2283 if (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(4, 1, 0)) 2284 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(4, 0, 1); 2285 2286 if (amdgpu_sriov_vf(adev)) 2287 amdgpu_discovery_set_sriov_display(adev); 2288 else 2289 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2290 break; 2291 default: 2292 dev_err(adev->dev, 2293 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 2294 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2295 return -EINVAL; 2296 } 2297 } else if (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2298 switch (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2299 case IP_VERSION(12, 0, 0): 2300 case IP_VERSION(12, 0, 1): 2301 case IP_VERSION(12, 1, 0): 2302 if (amdgpu_sriov_vf(adev)) 2303 amdgpu_discovery_set_sriov_display(adev); 2304 else 2305 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2306 break; 2307 default: 2308 dev_err(adev->dev, 2309 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 2310 amdgpu_ip_version(adev, DCI_HWIP, 0)); 2311 return -EINVAL; 2312 } 2313 } 2314 #endif 2315 return 0; 2316 } 2317 2318 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 2319 { 2320 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2321 case IP_VERSION(9, 0, 1): 2322 case IP_VERSION(9, 1, 0): 2323 case IP_VERSION(9, 2, 1): 2324 case IP_VERSION(9, 2, 2): 2325 case IP_VERSION(9, 3, 0): 2326 case IP_VERSION(9, 4, 0): 2327 case IP_VERSION(9, 4, 1): 2328 case IP_VERSION(9, 4, 2): 2329 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 2330 break; 2331 case IP_VERSION(9, 4, 3): 2332 case IP_VERSION(9, 4, 4): 2333 case IP_VERSION(9, 5, 0): 2334 amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block); 2335 break; 2336 case IP_VERSION(10, 1, 10): 2337 case IP_VERSION(10, 1, 2): 2338 case IP_VERSION(10, 1, 1): 2339 case IP_VERSION(10, 1, 3): 2340 case IP_VERSION(10, 1, 4): 2341 case IP_VERSION(10, 3, 0): 2342 case IP_VERSION(10, 3, 2): 2343 case IP_VERSION(10, 3, 1): 2344 case IP_VERSION(10, 3, 4): 2345 case IP_VERSION(10, 3, 5): 2346 case IP_VERSION(10, 3, 6): 2347 case IP_VERSION(10, 3, 3): 2348 case IP_VERSION(10, 3, 7): 2349 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 2350 break; 2351 case IP_VERSION(11, 0, 0): 2352 case IP_VERSION(11, 0, 1): 2353 case IP_VERSION(11, 0, 2): 2354 case IP_VERSION(11, 0, 3): 2355 case IP_VERSION(11, 0, 4): 2356 case IP_VERSION(11, 5, 0): 2357 case IP_VERSION(11, 5, 1): 2358 case IP_VERSION(11, 5, 2): 2359 case IP_VERSION(11, 5, 3): 2360 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); 2361 break; 2362 case IP_VERSION(12, 0, 0): 2363 case IP_VERSION(12, 0, 1): 2364 amdgpu_device_ip_block_add(adev, &gfx_v12_0_ip_block); 2365 break; 2366 default: 2367 dev_err(adev->dev, "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 2368 amdgpu_ip_version(adev, GC_HWIP, 0)); 2369 return -EINVAL; 2370 } 2371 return 0; 2372 } 2373 2374 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 2375 { 2376 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 2377 case IP_VERSION(4, 0, 0): 2378 case IP_VERSION(4, 0, 1): 2379 case IP_VERSION(4, 1, 0): 2380 case IP_VERSION(4, 1, 1): 2381 case IP_VERSION(4, 1, 2): 2382 case IP_VERSION(4, 2, 0): 2383 case IP_VERSION(4, 2, 2): 2384 case IP_VERSION(4, 4, 0): 2385 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 2386 break; 2387 case IP_VERSION(4, 4, 2): 2388 case IP_VERSION(4, 4, 5): 2389 case IP_VERSION(4, 4, 4): 2390 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block); 2391 break; 2392 case IP_VERSION(5, 0, 0): 2393 case IP_VERSION(5, 0, 1): 2394 case IP_VERSION(5, 0, 2): 2395 case IP_VERSION(5, 0, 5): 2396 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 2397 break; 2398 case IP_VERSION(5, 2, 0): 2399 case IP_VERSION(5, 2, 2): 2400 case IP_VERSION(5, 2, 4): 2401 case IP_VERSION(5, 2, 5): 2402 case IP_VERSION(5, 2, 6): 2403 case IP_VERSION(5, 2, 3): 2404 case IP_VERSION(5, 2, 1): 2405 case IP_VERSION(5, 2, 7): 2406 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 2407 break; 2408 case IP_VERSION(6, 0, 0): 2409 case IP_VERSION(6, 0, 1): 2410 case IP_VERSION(6, 0, 2): 2411 case IP_VERSION(6, 0, 3): 2412 case IP_VERSION(6, 1, 0): 2413 case IP_VERSION(6, 1, 1): 2414 case IP_VERSION(6, 1, 2): 2415 case IP_VERSION(6, 1, 3): 2416 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block); 2417 break; 2418 case IP_VERSION(7, 0, 0): 2419 case IP_VERSION(7, 0, 1): 2420 amdgpu_device_ip_block_add(adev, &sdma_v7_0_ip_block); 2421 break; 2422 case IP_VERSION(7, 1, 0): 2423 amdgpu_device_ip_block_add(adev, &sdma_v7_1_ip_block); 2424 break; 2425 default: 2426 dev_err(adev->dev, 2427 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 2428 amdgpu_ip_version(adev, SDMA0_HWIP, 0)); 2429 return -EINVAL; 2430 } 2431 2432 return 0; 2433 } 2434 2435 static int amdgpu_discovery_set_ras_ip_blocks(struct amdgpu_device *adev) 2436 { 2437 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 2438 case IP_VERSION(13, 0, 6): 2439 case IP_VERSION(13, 0, 12): 2440 case IP_VERSION(13, 0, 14): 2441 amdgpu_device_ip_block_add(adev, &ras_v1_0_ip_block); 2442 break; 2443 default: 2444 break; 2445 } 2446 return 0; 2447 } 2448 2449 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 2450 { 2451 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2452 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2453 case IP_VERSION(7, 0, 0): 2454 case IP_VERSION(7, 2, 0): 2455 /* UVD is not supported on vega20 SR-IOV */ 2456 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2457 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 2458 break; 2459 default: 2460 dev_err(adev->dev, 2461 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 2462 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2463 return -EINVAL; 2464 } 2465 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2466 case IP_VERSION(4, 0, 0): 2467 case IP_VERSION(4, 1, 0): 2468 /* VCE is not supported on vega20 SR-IOV */ 2469 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2470 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 2471 break; 2472 default: 2473 dev_err(adev->dev, 2474 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 2475 amdgpu_ip_version(adev, VCE_HWIP, 0)); 2476 return -EINVAL; 2477 } 2478 } else { 2479 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2480 case IP_VERSION(1, 0, 0): 2481 case IP_VERSION(1, 0, 1): 2482 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 2483 break; 2484 case IP_VERSION(2, 0, 0): 2485 case IP_VERSION(2, 0, 2): 2486 case IP_VERSION(2, 2, 0): 2487 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 2488 if (!amdgpu_sriov_vf(adev)) 2489 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 2490 break; 2491 case IP_VERSION(2, 0, 3): 2492 break; 2493 case IP_VERSION(2, 5, 0): 2494 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 2495 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 2496 break; 2497 case IP_VERSION(2, 6, 0): 2498 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 2499 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 2500 break; 2501 case IP_VERSION(3, 0, 0): 2502 case IP_VERSION(3, 0, 16): 2503 case IP_VERSION(3, 1, 1): 2504 case IP_VERSION(3, 1, 2): 2505 case IP_VERSION(3, 0, 2): 2506 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2507 if (!amdgpu_sriov_vf(adev)) 2508 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 2509 break; 2510 case IP_VERSION(3, 0, 33): 2511 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2512 break; 2513 case IP_VERSION(4, 0, 0): 2514 case IP_VERSION(4, 0, 2): 2515 case IP_VERSION(4, 0, 4): 2516 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block); 2517 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block); 2518 break; 2519 case IP_VERSION(4, 0, 3): 2520 amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block); 2521 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block); 2522 break; 2523 case IP_VERSION(4, 0, 5): 2524 case IP_VERSION(4, 0, 6): 2525 amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block); 2526 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block); 2527 break; 2528 case IP_VERSION(5, 0, 0): 2529 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block); 2530 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block); 2531 break; 2532 case IP_VERSION(5, 0, 1): 2533 amdgpu_device_ip_block_add(adev, &vcn_v5_0_1_ip_block); 2534 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_1_ip_block); 2535 break; 2536 default: 2537 dev_err(adev->dev, 2538 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 2539 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2540 return -EINVAL; 2541 } 2542 } 2543 return 0; 2544 } 2545 2546 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 2547 { 2548 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2549 case IP_VERSION(11, 0, 0): 2550 case IP_VERSION(11, 0, 1): 2551 case IP_VERSION(11, 0, 2): 2552 case IP_VERSION(11, 0, 3): 2553 case IP_VERSION(11, 0, 4): 2554 case IP_VERSION(11, 5, 0): 2555 case IP_VERSION(11, 5, 1): 2556 case IP_VERSION(11, 5, 2): 2557 case IP_VERSION(11, 5, 3): 2558 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block); 2559 adev->enable_mes = true; 2560 adev->enable_mes_kiq = true; 2561 break; 2562 case IP_VERSION(12, 0, 0): 2563 case IP_VERSION(12, 0, 1): 2564 amdgpu_device_ip_block_add(adev, &mes_v12_0_ip_block); 2565 adev->enable_mes = true; 2566 adev->enable_mes_kiq = true; 2567 if (amdgpu_uni_mes) 2568 adev->enable_uni_mes = true; 2569 break; 2570 case IP_VERSION(12, 1, 0): 2571 amdgpu_device_ip_block_add(adev, &mes_v12_1_ip_block); 2572 adev->enable_mes = true; 2573 adev->enable_mes_kiq = true; 2574 if (amdgpu_uni_mes) 2575 adev->enable_uni_mes = true; 2576 break; 2577 default: 2578 break; 2579 } 2580 return 0; 2581 } 2582 2583 static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev) 2584 { 2585 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2586 case IP_VERSION(9, 4, 3): 2587 case IP_VERSION(9, 4, 4): 2588 case IP_VERSION(9, 5, 0): 2589 aqua_vanjaram_init_soc_config(adev); 2590 break; 2591 default: 2592 break; 2593 } 2594 } 2595 2596 static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev) 2597 { 2598 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) { 2599 case IP_VERSION(6, 1, 0): 2600 case IP_VERSION(6, 1, 1): 2601 case IP_VERSION(6, 1, 3): 2602 amdgpu_device_ip_block_add(adev, &vpe_v6_1_ip_block); 2603 break; 2604 default: 2605 break; 2606 } 2607 2608 return 0; 2609 } 2610 2611 static int amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device *adev) 2612 { 2613 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) { 2614 case IP_VERSION(4, 0, 5): 2615 case IP_VERSION(4, 0, 6): 2616 if (amdgpu_umsch_mm & 0x1) { 2617 amdgpu_device_ip_block_add(adev, &umsch_mm_v4_0_ip_block); 2618 adev->enable_umsch_mm = true; 2619 } 2620 break; 2621 default: 2622 break; 2623 } 2624 2625 return 0; 2626 } 2627 2628 static int amdgpu_discovery_set_isp_ip_blocks(struct amdgpu_device *adev) 2629 { 2630 #if defined(CONFIG_DRM_AMD_ISP) 2631 switch (amdgpu_ip_version(adev, ISP_HWIP, 0)) { 2632 case IP_VERSION(4, 1, 0): 2633 amdgpu_device_ip_block_add(adev, &isp_v4_1_0_ip_block); 2634 break; 2635 case IP_VERSION(4, 1, 1): 2636 amdgpu_device_ip_block_add(adev, &isp_v4_1_1_ip_block); 2637 break; 2638 default: 2639 break; 2640 } 2641 #endif 2642 2643 return 0; 2644 } 2645 2646 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 2647 { 2648 int r; 2649 2650 switch (adev->asic_type) { 2651 case CHIP_VEGA10: 2652 /* This is not fatal. We only need the discovery 2653 * binary for sysfs. We don't need it for a 2654 * functional system. 2655 */ 2656 amdgpu_discovery_init(adev); 2657 vega10_reg_base_init(adev); 2658 adev->sdma.num_instances = 2; 2659 adev->sdma.sdma_mask = 3; 2660 adev->gmc.num_umc = 4; 2661 adev->gfx.xcc_mask = 1; 2662 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2663 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2664 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 2665 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 2666 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 2667 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 2668 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2669 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 2670 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 2671 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2672 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2673 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2674 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 2675 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 2676 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2677 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2678 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 2679 break; 2680 case CHIP_VEGA12: 2681 /* This is not fatal. We only need the discovery 2682 * binary for sysfs. We don't need it for a 2683 * functional system. 2684 */ 2685 amdgpu_discovery_init(adev); 2686 vega10_reg_base_init(adev); 2687 adev->sdma.num_instances = 2; 2688 adev->sdma.sdma_mask = 3; 2689 adev->gmc.num_umc = 4; 2690 adev->gfx.xcc_mask = 1; 2691 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2692 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2693 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 2694 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 2695 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 2696 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 2697 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 2698 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 2699 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 2700 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2701 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2702 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2703 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 2704 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 2705 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2706 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2707 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 2708 break; 2709 case CHIP_RAVEN: 2710 /* This is not fatal. We only need the discovery 2711 * binary for sysfs. We don't need it for a 2712 * functional system. 2713 */ 2714 amdgpu_discovery_init(adev); 2715 vega10_reg_base_init(adev); 2716 adev->sdma.num_instances = 1; 2717 adev->sdma.sdma_mask = 1; 2718 adev->vcn.num_vcn_inst = 1; 2719 adev->gmc.num_umc = 2; 2720 adev->gfx.xcc_mask = 1; 2721 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 2722 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2723 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2724 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 2725 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 2726 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 2727 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 2728 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 2729 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 2730 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 2731 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 2732 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 2733 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 2734 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 2735 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 2736 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 2737 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 2738 } else { 2739 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2740 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2741 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 2742 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 2743 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 2744 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2745 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 2746 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 2747 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 2748 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 2749 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 2750 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 2751 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 2752 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 2753 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 2754 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 2755 } 2756 break; 2757 case CHIP_VEGA20: 2758 /* This is not fatal. We only need the discovery 2759 * binary for sysfs. We don't need it for a 2760 * functional system. 2761 */ 2762 amdgpu_discovery_init(adev); 2763 vega20_reg_base_init(adev); 2764 adev->sdma.num_instances = 2; 2765 adev->sdma.sdma_mask = 3; 2766 adev->gmc.num_umc = 8; 2767 adev->gfx.xcc_mask = 1; 2768 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2769 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2770 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 2771 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 2772 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 2773 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 2774 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 2775 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 2776 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 2777 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 2778 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2779 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 2780 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 2781 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 2782 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 2783 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 2784 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 2785 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 2786 break; 2787 case CHIP_ARCTURUS: 2788 /* This is not fatal. We only need the discovery 2789 * binary for sysfs. We don't need it for a 2790 * functional system. 2791 */ 2792 amdgpu_discovery_init(adev); 2793 arct_reg_base_init(adev); 2794 adev->sdma.num_instances = 8; 2795 adev->sdma.sdma_mask = 0xff; 2796 adev->vcn.num_vcn_inst = 2; 2797 adev->gmc.num_umc = 8; 2798 adev->gfx.xcc_mask = 1; 2799 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2800 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2801 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 2802 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 2803 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 2804 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 2805 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 2806 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 2807 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 2808 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 2809 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 2810 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 2811 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 2812 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 2813 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 2814 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 2815 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2816 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 2817 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 2818 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 2819 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 2820 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 2821 break; 2822 case CHIP_ALDEBARAN: 2823 /* This is not fatal. We only need the discovery 2824 * binary for sysfs. We don't need it for a 2825 * functional system. 2826 */ 2827 amdgpu_discovery_init(adev); 2828 aldebaran_reg_base_init(adev); 2829 adev->sdma.num_instances = 5; 2830 adev->sdma.sdma_mask = 0x1f; 2831 adev->vcn.num_vcn_inst = 2; 2832 adev->gmc.num_umc = 4; 2833 adev->gfx.xcc_mask = 1; 2834 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2835 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2836 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 2837 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 2838 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 2839 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 2840 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 2841 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 2842 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 2843 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 2844 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 2845 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 2846 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 2847 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 2848 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 2849 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 2850 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 2851 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 2852 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 2853 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 2854 break; 2855 case CHIP_CYAN_SKILLFISH: 2856 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 2857 r = amdgpu_discovery_reg_base_init(adev); 2858 if (r) 2859 return -EINVAL; 2860 2861 amdgpu_discovery_harvest_ip(adev); 2862 amdgpu_discovery_get_gfx_info(adev); 2863 amdgpu_discovery_get_mall_info(adev); 2864 amdgpu_discovery_get_vcn_info(adev); 2865 } else { 2866 cyan_skillfish_reg_base_init(adev); 2867 adev->sdma.num_instances = 2; 2868 adev->sdma.sdma_mask = 3; 2869 adev->gfx.xcc_mask = 1; 2870 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(2, 0, 3); 2871 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(2, 0, 3); 2872 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(5, 0, 1); 2873 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(5, 0, 1); 2874 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(5, 0, 1); 2875 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(5, 0, 1); 2876 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 5, 0); 2877 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(2, 1, 1); 2878 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(8, 1, 1); 2879 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 8); 2880 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 8); 2881 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 1); 2882 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 8); 2883 adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 1, 3); 2884 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 0, 3); 2885 } 2886 break; 2887 default: 2888 r = amdgpu_discovery_reg_base_init(adev); 2889 if (r) { 2890 drm_err(&adev->ddev, "discovery failed: %d\n", r); 2891 return r; 2892 } 2893 2894 amdgpu_discovery_harvest_ip(adev); 2895 amdgpu_discovery_get_gfx_info(adev); 2896 amdgpu_discovery_get_mall_info(adev); 2897 amdgpu_discovery_get_vcn_info(adev); 2898 break; 2899 } 2900 2901 amdgpu_discovery_init_soc_config(adev); 2902 amdgpu_discovery_sysfs_init(adev); 2903 2904 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2905 case IP_VERSION(9, 0, 1): 2906 case IP_VERSION(9, 2, 1): 2907 case IP_VERSION(9, 4, 0): 2908 case IP_VERSION(9, 4, 1): 2909 case IP_VERSION(9, 4, 2): 2910 case IP_VERSION(9, 4, 3): 2911 case IP_VERSION(9, 4, 4): 2912 case IP_VERSION(9, 5, 0): 2913 adev->family = AMDGPU_FAMILY_AI; 2914 break; 2915 case IP_VERSION(9, 1, 0): 2916 case IP_VERSION(9, 2, 2): 2917 case IP_VERSION(9, 3, 0): 2918 adev->family = AMDGPU_FAMILY_RV; 2919 break; 2920 case IP_VERSION(10, 1, 10): 2921 case IP_VERSION(10, 1, 1): 2922 case IP_VERSION(10, 1, 2): 2923 case IP_VERSION(10, 1, 3): 2924 case IP_VERSION(10, 1, 4): 2925 case IP_VERSION(10, 3, 0): 2926 case IP_VERSION(10, 3, 2): 2927 case IP_VERSION(10, 3, 4): 2928 case IP_VERSION(10, 3, 5): 2929 adev->family = AMDGPU_FAMILY_NV; 2930 break; 2931 case IP_VERSION(10, 3, 1): 2932 adev->family = AMDGPU_FAMILY_VGH; 2933 adev->apu_flags |= AMD_APU_IS_VANGOGH; 2934 break; 2935 case IP_VERSION(10, 3, 3): 2936 adev->family = AMDGPU_FAMILY_YC; 2937 break; 2938 case IP_VERSION(10, 3, 6): 2939 adev->family = AMDGPU_FAMILY_GC_10_3_6; 2940 break; 2941 case IP_VERSION(10, 3, 7): 2942 adev->family = AMDGPU_FAMILY_GC_10_3_7; 2943 break; 2944 case IP_VERSION(11, 0, 0): 2945 case IP_VERSION(11, 0, 2): 2946 case IP_VERSION(11, 0, 3): 2947 adev->family = AMDGPU_FAMILY_GC_11_0_0; 2948 break; 2949 case IP_VERSION(11, 0, 1): 2950 case IP_VERSION(11, 0, 4): 2951 adev->family = AMDGPU_FAMILY_GC_11_0_1; 2952 break; 2953 case IP_VERSION(11, 5, 0): 2954 case IP_VERSION(11, 5, 1): 2955 case IP_VERSION(11, 5, 2): 2956 case IP_VERSION(11, 5, 3): 2957 adev->family = AMDGPU_FAMILY_GC_11_5_0; 2958 break; 2959 case IP_VERSION(12, 0, 0): 2960 case IP_VERSION(12, 0, 1): 2961 case IP_VERSION(12, 1, 0): 2962 adev->family = AMDGPU_FAMILY_GC_12_0_0; 2963 break; 2964 default: 2965 return -EINVAL; 2966 } 2967 2968 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2969 case IP_VERSION(9, 1, 0): 2970 case IP_VERSION(9, 2, 2): 2971 case IP_VERSION(9, 3, 0): 2972 case IP_VERSION(10, 1, 3): 2973 case IP_VERSION(10, 1, 4): 2974 case IP_VERSION(10, 3, 1): 2975 case IP_VERSION(10, 3, 3): 2976 case IP_VERSION(10, 3, 6): 2977 case IP_VERSION(10, 3, 7): 2978 case IP_VERSION(11, 0, 1): 2979 case IP_VERSION(11, 0, 4): 2980 case IP_VERSION(11, 5, 0): 2981 case IP_VERSION(11, 5, 1): 2982 case IP_VERSION(11, 5, 2): 2983 case IP_VERSION(11, 5, 3): 2984 adev->flags |= AMD_IS_APU; 2985 break; 2986 default: 2987 break; 2988 } 2989 2990 /* set NBIO version */ 2991 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 2992 case IP_VERSION(6, 1, 0): 2993 case IP_VERSION(6, 2, 0): 2994 adev->nbio.funcs = &nbio_v6_1_funcs; 2995 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 2996 break; 2997 case IP_VERSION(7, 0, 0): 2998 case IP_VERSION(7, 0, 1): 2999 case IP_VERSION(2, 5, 0): 3000 adev->nbio.funcs = &nbio_v7_0_funcs; 3001 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 3002 break; 3003 case IP_VERSION(7, 4, 0): 3004 case IP_VERSION(7, 4, 1): 3005 case IP_VERSION(7, 4, 4): 3006 adev->nbio.funcs = &nbio_v7_4_funcs; 3007 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 3008 break; 3009 case IP_VERSION(7, 9, 0): 3010 case IP_VERSION(7, 9, 1): 3011 adev->nbio.funcs = &nbio_v7_9_funcs; 3012 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg; 3013 break; 3014 case IP_VERSION(7, 11, 0): 3015 case IP_VERSION(7, 11, 1): 3016 case IP_VERSION(7, 11, 2): 3017 case IP_VERSION(7, 11, 3): 3018 adev->nbio.funcs = &nbio_v7_11_funcs; 3019 adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg; 3020 break; 3021 case IP_VERSION(7, 2, 0): 3022 case IP_VERSION(7, 2, 1): 3023 case IP_VERSION(7, 3, 0): 3024 case IP_VERSION(7, 5, 0): 3025 case IP_VERSION(7, 5, 1): 3026 adev->nbio.funcs = &nbio_v7_2_funcs; 3027 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 3028 break; 3029 case IP_VERSION(2, 1, 1): 3030 case IP_VERSION(2, 3, 0): 3031 case IP_VERSION(2, 3, 1): 3032 case IP_VERSION(2, 3, 2): 3033 case IP_VERSION(3, 3, 0): 3034 case IP_VERSION(3, 3, 1): 3035 case IP_VERSION(3, 3, 2): 3036 case IP_VERSION(3, 3, 3): 3037 adev->nbio.funcs = &nbio_v2_3_funcs; 3038 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 3039 break; 3040 case IP_VERSION(4, 3, 0): 3041 case IP_VERSION(4, 3, 1): 3042 if (amdgpu_sriov_vf(adev)) 3043 adev->nbio.funcs = &nbio_v4_3_sriov_funcs; 3044 else 3045 adev->nbio.funcs = &nbio_v4_3_funcs; 3046 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg; 3047 break; 3048 case IP_VERSION(7, 7, 0): 3049 case IP_VERSION(7, 7, 1): 3050 adev->nbio.funcs = &nbio_v7_7_funcs; 3051 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg; 3052 break; 3053 case IP_VERSION(6, 3, 1): 3054 adev->nbio.funcs = &nbif_v6_3_1_funcs; 3055 adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg; 3056 break; 3057 default: 3058 break; 3059 } 3060 3061 switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) { 3062 case IP_VERSION(4, 0, 0): 3063 case IP_VERSION(4, 0, 1): 3064 case IP_VERSION(4, 1, 0): 3065 case IP_VERSION(4, 1, 1): 3066 case IP_VERSION(4, 1, 2): 3067 case IP_VERSION(4, 2, 0): 3068 case IP_VERSION(4, 2, 1): 3069 case IP_VERSION(4, 4, 0): 3070 case IP_VERSION(4, 4, 2): 3071 case IP_VERSION(4, 4, 5): 3072 adev->hdp.funcs = &hdp_v4_0_funcs; 3073 break; 3074 case IP_VERSION(5, 0, 0): 3075 case IP_VERSION(5, 0, 1): 3076 case IP_VERSION(5, 0, 2): 3077 case IP_VERSION(5, 0, 3): 3078 case IP_VERSION(5, 0, 4): 3079 case IP_VERSION(5, 2, 0): 3080 adev->hdp.funcs = &hdp_v5_0_funcs; 3081 break; 3082 case IP_VERSION(5, 2, 1): 3083 adev->hdp.funcs = &hdp_v5_2_funcs; 3084 break; 3085 case IP_VERSION(6, 0, 0): 3086 case IP_VERSION(6, 0, 1): 3087 case IP_VERSION(6, 1, 0): 3088 adev->hdp.funcs = &hdp_v6_0_funcs; 3089 break; 3090 case IP_VERSION(7, 0, 0): 3091 adev->hdp.funcs = &hdp_v7_0_funcs; 3092 break; 3093 default: 3094 break; 3095 } 3096 3097 switch (amdgpu_ip_version(adev, DF_HWIP, 0)) { 3098 case IP_VERSION(3, 6, 0): 3099 case IP_VERSION(3, 6, 1): 3100 case IP_VERSION(3, 6, 2): 3101 adev->df.funcs = &df_v3_6_funcs; 3102 break; 3103 case IP_VERSION(2, 1, 0): 3104 case IP_VERSION(2, 1, 1): 3105 case IP_VERSION(2, 5, 0): 3106 case IP_VERSION(3, 5, 1): 3107 case IP_VERSION(3, 5, 2): 3108 adev->df.funcs = &df_v1_7_funcs; 3109 break; 3110 case IP_VERSION(4, 3, 0): 3111 adev->df.funcs = &df_v4_3_funcs; 3112 break; 3113 case IP_VERSION(4, 6, 2): 3114 adev->df.funcs = &df_v4_6_2_funcs; 3115 break; 3116 case IP_VERSION(4, 15, 0): 3117 case IP_VERSION(4, 15, 1): 3118 adev->df.funcs = &df_v4_15_funcs; 3119 break; 3120 default: 3121 break; 3122 } 3123 3124 switch (amdgpu_ip_version(adev, SMUIO_HWIP, 0)) { 3125 case IP_VERSION(9, 0, 0): 3126 case IP_VERSION(9, 0, 1): 3127 case IP_VERSION(10, 0, 0): 3128 case IP_VERSION(10, 0, 1): 3129 case IP_VERSION(10, 0, 2): 3130 adev->smuio.funcs = &smuio_v9_0_funcs; 3131 break; 3132 case IP_VERSION(11, 0, 0): 3133 case IP_VERSION(11, 0, 2): 3134 case IP_VERSION(11, 0, 3): 3135 case IP_VERSION(11, 0, 4): 3136 case IP_VERSION(11, 0, 7): 3137 case IP_VERSION(11, 0, 8): 3138 adev->smuio.funcs = &smuio_v11_0_funcs; 3139 break; 3140 case IP_VERSION(11, 0, 6): 3141 case IP_VERSION(11, 0, 10): 3142 case IP_VERSION(11, 0, 11): 3143 case IP_VERSION(11, 5, 0): 3144 case IP_VERSION(11, 5, 2): 3145 case IP_VERSION(13, 0, 1): 3146 case IP_VERSION(13, 0, 9): 3147 case IP_VERSION(13, 0, 10): 3148 adev->smuio.funcs = &smuio_v11_0_6_funcs; 3149 break; 3150 case IP_VERSION(13, 0, 2): 3151 adev->smuio.funcs = &smuio_v13_0_funcs; 3152 break; 3153 case IP_VERSION(13, 0, 3): 3154 case IP_VERSION(13, 0, 11): 3155 adev->smuio.funcs = &smuio_v13_0_3_funcs; 3156 if (adev->smuio.funcs->get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) { 3157 adev->flags |= AMD_IS_APU; 3158 } 3159 break; 3160 case IP_VERSION(13, 0, 6): 3161 case IP_VERSION(13, 0, 8): 3162 case IP_VERSION(14, 0, 0): 3163 case IP_VERSION(14, 0, 1): 3164 adev->smuio.funcs = &smuio_v13_0_6_funcs; 3165 break; 3166 case IP_VERSION(14, 0, 2): 3167 adev->smuio.funcs = &smuio_v14_0_2_funcs; 3168 break; 3169 case IP_VERSION(15, 0, 8): 3170 adev->smuio.funcs = &smuio_v15_0_8_funcs; 3171 break; 3172 default: 3173 break; 3174 } 3175 3176 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { 3177 case IP_VERSION(6, 0, 0): 3178 case IP_VERSION(6, 0, 1): 3179 case IP_VERSION(6, 0, 2): 3180 case IP_VERSION(6, 0, 3): 3181 adev->lsdma.funcs = &lsdma_v6_0_funcs; 3182 break; 3183 case IP_VERSION(7, 0, 0): 3184 case IP_VERSION(7, 0, 1): 3185 adev->lsdma.funcs = &lsdma_v7_0_funcs; 3186 break; 3187 default: 3188 break; 3189 } 3190 3191 r = amdgpu_discovery_set_common_ip_blocks(adev); 3192 if (r) 3193 return r; 3194 3195 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 3196 if (r) 3197 return r; 3198 3199 /* For SR-IOV, PSP needs to be initialized before IH */ 3200 if (amdgpu_sriov_vf(adev)) { 3201 r = amdgpu_discovery_set_psp_ip_blocks(adev); 3202 if (r) 3203 return r; 3204 r = amdgpu_discovery_set_ih_ip_blocks(adev); 3205 if (r) 3206 return r; 3207 } else { 3208 r = amdgpu_discovery_set_ih_ip_blocks(adev); 3209 if (r) 3210 return r; 3211 3212 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3213 r = amdgpu_discovery_set_psp_ip_blocks(adev); 3214 if (r) 3215 return r; 3216 } 3217 } 3218 3219 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3220 r = amdgpu_discovery_set_smu_ip_blocks(adev); 3221 if (r) 3222 return r; 3223 } 3224 3225 r = amdgpu_discovery_set_display_ip_blocks(adev); 3226 if (r) 3227 return r; 3228 3229 r = amdgpu_discovery_set_gc_ip_blocks(adev); 3230 if (r) 3231 return r; 3232 3233 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 3234 if (r) 3235 return r; 3236 3237 r = amdgpu_discovery_set_ras_ip_blocks(adev); 3238 if (r) 3239 return r; 3240 3241 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 3242 !amdgpu_sriov_vf(adev) && 3243 amdgpu_dpm == 1) || 3244 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && 3245 amdgpu_dpm == 1)) { 3246 r = amdgpu_discovery_set_smu_ip_blocks(adev); 3247 if (r) 3248 return r; 3249 } 3250 3251 r = amdgpu_discovery_set_mm_ip_blocks(adev); 3252 if (r) 3253 return r; 3254 3255 r = amdgpu_discovery_set_mes_ip_blocks(adev); 3256 if (r) 3257 return r; 3258 3259 r = amdgpu_discovery_set_vpe_ip_blocks(adev); 3260 if (r) 3261 return r; 3262 3263 r = amdgpu_discovery_set_umsch_mm_ip_blocks(adev); 3264 if (r) 3265 return r; 3266 3267 r = amdgpu_discovery_set_isp_ip_blocks(adev); 3268 if (r) 3269 return r; 3270 return 0; 3271 } 3272 3273