1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: monk liu <monk.liu@amd.com> 23 */ 24 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 28 static int amdgpu_ctx_init(struct amdgpu_device *adev, struct amdgpu_ctx *ctx) 29 { 30 unsigned i, j; 31 int r; 32 33 memset(ctx, 0, sizeof(*ctx)); 34 ctx->adev = adev; 35 kref_init(&ctx->refcount); 36 spin_lock_init(&ctx->ring_lock); 37 ctx->fences = kcalloc(amdgpu_sched_jobs * AMDGPU_MAX_RINGS, 38 sizeof(struct dma_fence*), GFP_KERNEL); 39 if (!ctx->fences) 40 return -ENOMEM; 41 42 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 43 ctx->rings[i].sequence = 1; 44 ctx->rings[i].fences = &ctx->fences[amdgpu_sched_jobs * i]; 45 } 46 47 ctx->reset_counter = atomic_read(&adev->gpu_reset_counter); 48 49 /* create context entity for each ring */ 50 for (i = 0; i < adev->num_rings; i++) { 51 struct amdgpu_ring *ring = adev->rings[i]; 52 struct amd_sched_rq *rq; 53 54 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; 55 r = amd_sched_entity_init(&ring->sched, &ctx->rings[i].entity, 56 rq, amdgpu_sched_jobs); 57 if (r) 58 goto failed; 59 } 60 61 return 0; 62 63 failed: 64 for (j = 0; j < i; j++) 65 amd_sched_entity_fini(&adev->rings[j]->sched, 66 &ctx->rings[j].entity); 67 kfree(ctx->fences); 68 ctx->fences = NULL; 69 return r; 70 } 71 72 static void amdgpu_ctx_fini(struct amdgpu_ctx *ctx) 73 { 74 struct amdgpu_device *adev = ctx->adev; 75 unsigned i, j; 76 77 if (!adev) 78 return; 79 80 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) 81 for (j = 0; j < amdgpu_sched_jobs; ++j) 82 dma_fence_put(ctx->rings[i].fences[j]); 83 kfree(ctx->fences); 84 ctx->fences = NULL; 85 86 for (i = 0; i < adev->num_rings; i++) 87 amd_sched_entity_fini(&adev->rings[i]->sched, 88 &ctx->rings[i].entity); 89 } 90 91 static int amdgpu_ctx_alloc(struct amdgpu_device *adev, 92 struct amdgpu_fpriv *fpriv, 93 uint32_t *id) 94 { 95 struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; 96 struct amdgpu_ctx *ctx; 97 int r; 98 99 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL); 100 if (!ctx) 101 return -ENOMEM; 102 103 mutex_lock(&mgr->lock); 104 r = idr_alloc(&mgr->ctx_handles, ctx, 1, 0, GFP_KERNEL); 105 if (r < 0) { 106 mutex_unlock(&mgr->lock); 107 kfree(ctx); 108 return r; 109 } 110 *id = (uint32_t)r; 111 r = amdgpu_ctx_init(adev, ctx); 112 if (r) { 113 idr_remove(&mgr->ctx_handles, *id); 114 *id = 0; 115 kfree(ctx); 116 } 117 mutex_unlock(&mgr->lock); 118 return r; 119 } 120 121 static void amdgpu_ctx_do_release(struct kref *ref) 122 { 123 struct amdgpu_ctx *ctx; 124 125 ctx = container_of(ref, struct amdgpu_ctx, refcount); 126 127 amdgpu_ctx_fini(ctx); 128 129 kfree(ctx); 130 } 131 132 static int amdgpu_ctx_free(struct amdgpu_fpriv *fpriv, uint32_t id) 133 { 134 struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; 135 struct amdgpu_ctx *ctx; 136 137 mutex_lock(&mgr->lock); 138 ctx = idr_remove(&mgr->ctx_handles, id); 139 if (ctx) 140 kref_put(&ctx->refcount, amdgpu_ctx_do_release); 141 mutex_unlock(&mgr->lock); 142 return ctx ? 0 : -EINVAL; 143 } 144 145 static int amdgpu_ctx_query(struct amdgpu_device *adev, 146 struct amdgpu_fpriv *fpriv, uint32_t id, 147 union drm_amdgpu_ctx_out *out) 148 { 149 struct amdgpu_ctx *ctx; 150 struct amdgpu_ctx_mgr *mgr; 151 unsigned reset_counter; 152 153 if (!fpriv) 154 return -EINVAL; 155 156 mgr = &fpriv->ctx_mgr; 157 mutex_lock(&mgr->lock); 158 ctx = idr_find(&mgr->ctx_handles, id); 159 if (!ctx) { 160 mutex_unlock(&mgr->lock); 161 return -EINVAL; 162 } 163 164 /* TODO: these two are always zero */ 165 out->state.flags = 0x0; 166 out->state.hangs = 0x0; 167 168 /* determine if a GPU reset has occured since the last call */ 169 reset_counter = atomic_read(&adev->gpu_reset_counter); 170 /* TODO: this should ideally return NO, GUILTY, or INNOCENT. */ 171 if (ctx->reset_counter == reset_counter) 172 out->state.reset_status = AMDGPU_CTX_NO_RESET; 173 else 174 out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET; 175 ctx->reset_counter = reset_counter; 176 177 mutex_unlock(&mgr->lock); 178 return 0; 179 } 180 181 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 182 struct drm_file *filp) 183 { 184 int r; 185 uint32_t id; 186 187 union drm_amdgpu_ctx *args = data; 188 struct amdgpu_device *adev = dev->dev_private; 189 struct amdgpu_fpriv *fpriv = filp->driver_priv; 190 191 r = 0; 192 id = args->in.ctx_id; 193 194 switch (args->in.op) { 195 case AMDGPU_CTX_OP_ALLOC_CTX: 196 r = amdgpu_ctx_alloc(adev, fpriv, &id); 197 args->out.alloc.ctx_id = id; 198 break; 199 case AMDGPU_CTX_OP_FREE_CTX: 200 r = amdgpu_ctx_free(fpriv, id); 201 break; 202 case AMDGPU_CTX_OP_QUERY_STATE: 203 r = amdgpu_ctx_query(adev, fpriv, id, &args->out); 204 break; 205 default: 206 return -EINVAL; 207 } 208 209 return r; 210 } 211 212 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id) 213 { 214 struct amdgpu_ctx *ctx; 215 struct amdgpu_ctx_mgr *mgr; 216 217 if (!fpriv) 218 return NULL; 219 220 mgr = &fpriv->ctx_mgr; 221 222 mutex_lock(&mgr->lock); 223 ctx = idr_find(&mgr->ctx_handles, id); 224 if (ctx) 225 kref_get(&ctx->refcount); 226 mutex_unlock(&mgr->lock); 227 return ctx; 228 } 229 230 int amdgpu_ctx_put(struct amdgpu_ctx *ctx) 231 { 232 if (ctx == NULL) 233 return -EINVAL; 234 235 kref_put(&ctx->refcount, amdgpu_ctx_do_release); 236 return 0; 237 } 238 239 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 240 struct dma_fence *fence) 241 { 242 struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx]; 243 uint64_t seq = cring->sequence; 244 unsigned idx = 0; 245 struct dma_fence *other = NULL; 246 247 idx = seq & (amdgpu_sched_jobs - 1); 248 other = cring->fences[idx]; 249 if (other) { 250 signed long r; 251 r = dma_fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT); 252 if (r < 0) 253 DRM_ERROR("Error (%ld) waiting for fence!\n", r); 254 } 255 256 dma_fence_get(fence); 257 258 spin_lock(&ctx->ring_lock); 259 cring->fences[idx] = fence; 260 cring->sequence++; 261 spin_unlock(&ctx->ring_lock); 262 263 dma_fence_put(other); 264 265 return seq; 266 } 267 268 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 269 struct amdgpu_ring *ring, uint64_t seq) 270 { 271 struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx]; 272 struct dma_fence *fence; 273 274 spin_lock(&ctx->ring_lock); 275 276 if (seq >= cring->sequence) { 277 spin_unlock(&ctx->ring_lock); 278 return ERR_PTR(-EINVAL); 279 } 280 281 282 if (seq + amdgpu_sched_jobs < cring->sequence) { 283 spin_unlock(&ctx->ring_lock); 284 return NULL; 285 } 286 287 fence = dma_fence_get(cring->fences[seq & (amdgpu_sched_jobs - 1)]); 288 spin_unlock(&ctx->ring_lock); 289 290 return fence; 291 } 292 293 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr) 294 { 295 mutex_init(&mgr->lock); 296 idr_init(&mgr->ctx_handles); 297 } 298 299 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr) 300 { 301 struct amdgpu_ctx *ctx; 302 struct idr *idp; 303 uint32_t id; 304 305 idp = &mgr->ctx_handles; 306 307 idr_for_each_entry(idp, ctx, id) { 308 if (kref_put(&ctx->refcount, amdgpu_ctx_do_release) != 1) 309 DRM_ERROR("ctx %p is still alive\n", ctx); 310 } 311 312 idr_destroy(&mgr->ctx_handles); 313 mutex_destroy(&mgr->lock); 314 } 315