1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: monk liu <monk.liu@amd.com> 23 */ 24 25 #include <drm/drm_auth.h> 26 #include <drm/drm_drv.h> 27 #include "amdgpu.h" 28 #include "amdgpu_sched.h" 29 #include "amdgpu_ras.h" 30 #include <linux/nospec.h> 31 32 #define to_amdgpu_ctx_entity(e) \ 33 container_of((e), struct amdgpu_ctx_entity, entity) 34 35 const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM] = { 36 [AMDGPU_HW_IP_GFX] = 1, 37 [AMDGPU_HW_IP_COMPUTE] = 4, 38 [AMDGPU_HW_IP_DMA] = 2, 39 [AMDGPU_HW_IP_UVD] = 1, 40 [AMDGPU_HW_IP_VCE] = 1, 41 [AMDGPU_HW_IP_UVD_ENC] = 1, 42 [AMDGPU_HW_IP_VCN_DEC] = 1, 43 [AMDGPU_HW_IP_VCN_ENC] = 1, 44 [AMDGPU_HW_IP_VCN_JPEG] = 1, 45 [AMDGPU_HW_IP_VPE] = 1, 46 }; 47 48 bool amdgpu_ctx_priority_is_valid(int32_t ctx_prio) 49 { 50 switch (ctx_prio) { 51 case AMDGPU_CTX_PRIORITY_VERY_LOW: 52 case AMDGPU_CTX_PRIORITY_LOW: 53 case AMDGPU_CTX_PRIORITY_NORMAL: 54 case AMDGPU_CTX_PRIORITY_HIGH: 55 case AMDGPU_CTX_PRIORITY_VERY_HIGH: 56 return true; 57 default: 58 case AMDGPU_CTX_PRIORITY_UNSET: 59 /* UNSET priority is not valid and we don't carry that 60 * around, but set it to NORMAL in the only place this 61 * function is called, amdgpu_ctx_ioctl(). 62 */ 63 return false; 64 } 65 } 66 67 static enum drm_sched_priority 68 amdgpu_ctx_to_drm_sched_prio(int32_t ctx_prio) 69 { 70 switch (ctx_prio) { 71 case AMDGPU_CTX_PRIORITY_UNSET: 72 pr_warn_once("AMD-->DRM context priority value UNSET-->NORMAL"); 73 return DRM_SCHED_PRIORITY_NORMAL; 74 75 case AMDGPU_CTX_PRIORITY_VERY_LOW: 76 return DRM_SCHED_PRIORITY_LOW; 77 78 case AMDGPU_CTX_PRIORITY_LOW: 79 return DRM_SCHED_PRIORITY_LOW; 80 81 case AMDGPU_CTX_PRIORITY_NORMAL: 82 return DRM_SCHED_PRIORITY_NORMAL; 83 84 case AMDGPU_CTX_PRIORITY_HIGH: 85 return DRM_SCHED_PRIORITY_HIGH; 86 87 case AMDGPU_CTX_PRIORITY_VERY_HIGH: 88 return DRM_SCHED_PRIORITY_HIGH; 89 90 /* This should not happen as we sanitized userspace provided priority 91 * already, WARN if this happens. 92 */ 93 default: 94 WARN(1, "Invalid context priority %d\n", ctx_prio); 95 return DRM_SCHED_PRIORITY_NORMAL; 96 } 97 98 } 99 100 static int amdgpu_ctx_priority_permit(struct drm_file *filp, 101 int32_t priority) 102 { 103 /* NORMAL and below are accessible by everyone */ 104 if (priority <= AMDGPU_CTX_PRIORITY_NORMAL) 105 return 0; 106 107 if (capable(CAP_SYS_NICE)) 108 return 0; 109 110 if (drm_is_current_master(filp)) 111 return 0; 112 113 return -EACCES; 114 } 115 116 static enum amdgpu_gfx_pipe_priority amdgpu_ctx_prio_to_gfx_pipe_prio(int32_t prio) 117 { 118 switch (prio) { 119 case AMDGPU_CTX_PRIORITY_HIGH: 120 case AMDGPU_CTX_PRIORITY_VERY_HIGH: 121 return AMDGPU_GFX_PIPE_PRIO_HIGH; 122 default: 123 return AMDGPU_GFX_PIPE_PRIO_NORMAL; 124 } 125 } 126 127 static enum amdgpu_ring_priority_level amdgpu_ctx_sched_prio_to_ring_prio(int32_t prio) 128 { 129 switch (prio) { 130 case AMDGPU_CTX_PRIORITY_HIGH: 131 return AMDGPU_RING_PRIO_1; 132 case AMDGPU_CTX_PRIORITY_VERY_HIGH: 133 return AMDGPU_RING_PRIO_2; 134 default: 135 return AMDGPU_RING_PRIO_0; 136 } 137 } 138 139 static unsigned int amdgpu_ctx_get_hw_prio(struct amdgpu_ctx *ctx, u32 hw_ip) 140 { 141 struct amdgpu_device *adev = ctx->mgr->adev; 142 unsigned int hw_prio; 143 int32_t ctx_prio; 144 145 ctx_prio = (ctx->override_priority == AMDGPU_CTX_PRIORITY_UNSET) ? 146 ctx->init_priority : ctx->override_priority; 147 148 switch (hw_ip) { 149 case AMDGPU_HW_IP_GFX: 150 case AMDGPU_HW_IP_COMPUTE: 151 hw_prio = amdgpu_ctx_prio_to_gfx_pipe_prio(ctx_prio); 152 break; 153 case AMDGPU_HW_IP_VCE: 154 case AMDGPU_HW_IP_VCN_ENC: 155 hw_prio = amdgpu_ctx_sched_prio_to_ring_prio(ctx_prio); 156 break; 157 default: 158 hw_prio = AMDGPU_RING_PRIO_DEFAULT; 159 break; 160 } 161 162 hw_ip = array_index_nospec(hw_ip, AMDGPU_HW_IP_NUM); 163 if (adev->gpu_sched[hw_ip][hw_prio].num_scheds == 0) 164 hw_prio = AMDGPU_RING_PRIO_DEFAULT; 165 166 return hw_prio; 167 } 168 169 /* Calculate the time spend on the hw */ 170 static ktime_t amdgpu_ctx_fence_time(struct dma_fence *fence) 171 { 172 struct drm_sched_fence *s_fence; 173 174 if (!fence) 175 return ns_to_ktime(0); 176 177 /* When the fence is not even scheduled it can't have spend time */ 178 s_fence = to_drm_sched_fence(fence); 179 if (!test_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &s_fence->scheduled.flags)) 180 return ns_to_ktime(0); 181 182 /* When it is still running account how much already spend */ 183 if (!test_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &s_fence->finished.flags)) 184 return ktime_sub(ktime_get(), s_fence->scheduled.timestamp); 185 186 return ktime_sub(s_fence->finished.timestamp, 187 s_fence->scheduled.timestamp); 188 } 189 190 static ktime_t amdgpu_ctx_entity_time(struct amdgpu_ctx *ctx, 191 struct amdgpu_ctx_entity *centity) 192 { 193 ktime_t res = ns_to_ktime(0); 194 uint32_t i; 195 196 spin_lock(&ctx->ring_lock); 197 for (i = 0; i < amdgpu_sched_jobs; i++) { 198 res = ktime_add(res, amdgpu_ctx_fence_time(centity->fences[i])); 199 } 200 spin_unlock(&ctx->ring_lock); 201 return res; 202 } 203 204 static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, u32 hw_ip, 205 const u32 ring) 206 { 207 struct drm_gpu_scheduler **scheds = NULL, *sched = NULL; 208 struct amdgpu_device *adev = ctx->mgr->adev; 209 struct amdgpu_ctx_entity *entity; 210 enum drm_sched_priority drm_prio; 211 unsigned int hw_prio, num_scheds; 212 int32_t ctx_prio; 213 int r; 214 215 entity = kzalloc(struct_size(entity, fences, amdgpu_sched_jobs), 216 GFP_KERNEL); 217 if (!entity) 218 return -ENOMEM; 219 220 ctx_prio = (ctx->override_priority == AMDGPU_CTX_PRIORITY_UNSET) ? 221 ctx->init_priority : ctx->override_priority; 222 entity->hw_ip = hw_ip; 223 entity->sequence = 1; 224 hw_prio = amdgpu_ctx_get_hw_prio(ctx, hw_ip); 225 drm_prio = amdgpu_ctx_to_drm_sched_prio(ctx_prio); 226 227 hw_ip = array_index_nospec(hw_ip, AMDGPU_HW_IP_NUM); 228 229 if (!(adev)->xcp_mgr) { 230 scheds = adev->gpu_sched[hw_ip][hw_prio].sched; 231 num_scheds = adev->gpu_sched[hw_ip][hw_prio].num_scheds; 232 } else { 233 struct amdgpu_fpriv *fpriv; 234 235 fpriv = container_of(ctx->ctx_mgr, struct amdgpu_fpriv, ctx_mgr); 236 r = amdgpu_xcp_select_scheds(adev, hw_ip, hw_prio, fpriv, 237 &num_scheds, &scheds); 238 if (r) 239 goto error_free_entity; 240 } 241 242 /* disable load balance if the hw engine retains context among dependent jobs */ 243 if (hw_ip == AMDGPU_HW_IP_VCN_ENC || 244 hw_ip == AMDGPU_HW_IP_VCN_DEC || 245 hw_ip == AMDGPU_HW_IP_UVD_ENC || 246 hw_ip == AMDGPU_HW_IP_UVD) { 247 sched = drm_sched_pick_best(scheds, num_scheds); 248 scheds = &sched; 249 num_scheds = 1; 250 } 251 252 r = drm_sched_entity_init(&entity->entity, drm_prio, scheds, num_scheds, 253 &ctx->guilty); 254 if (r) 255 goto error_free_entity; 256 257 /* It's not an error if we fail to install the new entity */ 258 if (cmpxchg(&ctx->entities[hw_ip][ring], NULL, entity)) 259 goto cleanup_entity; 260 261 return 0; 262 263 cleanup_entity: 264 drm_sched_entity_fini(&entity->entity); 265 266 error_free_entity: 267 kfree(entity); 268 269 return r; 270 } 271 272 static ktime_t amdgpu_ctx_fini_entity(struct amdgpu_device *adev, 273 struct amdgpu_ctx_entity *entity) 274 { 275 ktime_t res = ns_to_ktime(0); 276 int i; 277 278 if (!entity) 279 return res; 280 281 for (i = 0; i < amdgpu_sched_jobs; ++i) { 282 res = ktime_add(res, amdgpu_ctx_fence_time(entity->fences[i])); 283 dma_fence_put(entity->fences[i]); 284 } 285 286 amdgpu_xcp_release_sched(adev, entity); 287 288 kfree(entity); 289 return res; 290 } 291 292 static int amdgpu_ctx_get_stable_pstate(struct amdgpu_ctx *ctx, 293 u32 *stable_pstate) 294 { 295 struct amdgpu_device *adev = ctx->mgr->adev; 296 enum amd_dpm_forced_level current_level; 297 298 current_level = amdgpu_dpm_get_performance_level(adev); 299 300 switch (current_level) { 301 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 302 *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_STANDARD; 303 break; 304 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 305 *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK; 306 break; 307 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 308 *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK; 309 break; 310 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 311 *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_PEAK; 312 break; 313 default: 314 *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_NONE; 315 break; 316 } 317 return 0; 318 } 319 320 static int amdgpu_ctx_init(struct amdgpu_ctx_mgr *mgr, int32_t priority, 321 struct drm_file *filp, struct amdgpu_ctx *ctx) 322 { 323 struct amdgpu_fpriv *fpriv = filp->driver_priv; 324 u32 current_stable_pstate; 325 int r; 326 327 r = amdgpu_ctx_priority_permit(filp, priority); 328 if (r) 329 return r; 330 331 memset(ctx, 0, sizeof(*ctx)); 332 333 kref_init(&ctx->refcount); 334 ctx->mgr = mgr; 335 spin_lock_init(&ctx->ring_lock); 336 337 ctx->reset_counter = atomic_read(&mgr->adev->gpu_reset_counter); 338 ctx->reset_counter_query = ctx->reset_counter; 339 ctx->generation = amdgpu_vm_generation(mgr->adev, &fpriv->vm); 340 ctx->init_priority = priority; 341 ctx->override_priority = AMDGPU_CTX_PRIORITY_UNSET; 342 343 r = amdgpu_ctx_get_stable_pstate(ctx, ¤t_stable_pstate); 344 if (r) 345 return r; 346 347 if (mgr->adev->pm.stable_pstate_ctx) 348 ctx->stable_pstate = mgr->adev->pm.stable_pstate_ctx->stable_pstate; 349 else 350 ctx->stable_pstate = current_stable_pstate; 351 352 ctx->ctx_mgr = &(fpriv->ctx_mgr); 353 return 0; 354 } 355 356 static int amdgpu_ctx_set_stable_pstate(struct amdgpu_ctx *ctx, 357 u32 stable_pstate) 358 { 359 struct amdgpu_device *adev = ctx->mgr->adev; 360 enum amd_dpm_forced_level level; 361 u32 current_stable_pstate; 362 int r; 363 364 mutex_lock(&adev->pm.stable_pstate_ctx_lock); 365 if (adev->pm.stable_pstate_ctx && adev->pm.stable_pstate_ctx != ctx) { 366 r = -EBUSY; 367 goto done; 368 } 369 370 r = amdgpu_ctx_get_stable_pstate(ctx, ¤t_stable_pstate); 371 if (r || (stable_pstate == current_stable_pstate)) 372 goto done; 373 374 switch (stable_pstate) { 375 case AMDGPU_CTX_STABLE_PSTATE_NONE: 376 level = AMD_DPM_FORCED_LEVEL_AUTO; 377 break; 378 case AMDGPU_CTX_STABLE_PSTATE_STANDARD: 379 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD; 380 break; 381 case AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK: 382 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK; 383 break; 384 case AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK: 385 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK; 386 break; 387 case AMDGPU_CTX_STABLE_PSTATE_PEAK: 388 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 389 break; 390 default: 391 r = -EINVAL; 392 goto done; 393 } 394 395 r = amdgpu_dpm_force_performance_level(adev, level); 396 397 if (level == AMD_DPM_FORCED_LEVEL_AUTO) 398 adev->pm.stable_pstate_ctx = NULL; 399 else 400 adev->pm.stable_pstate_ctx = ctx; 401 done: 402 mutex_unlock(&adev->pm.stable_pstate_ctx_lock); 403 404 return r; 405 } 406 407 static void amdgpu_ctx_fini(struct kref *ref) 408 { 409 struct amdgpu_ctx *ctx = container_of(ref, struct amdgpu_ctx, refcount); 410 struct amdgpu_ctx_mgr *mgr = ctx->mgr; 411 struct amdgpu_device *adev = mgr->adev; 412 unsigned i, j, idx; 413 414 if (!adev) 415 return; 416 417 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 418 for (j = 0; j < AMDGPU_MAX_ENTITY_NUM; ++j) { 419 ktime_t spend; 420 421 spend = amdgpu_ctx_fini_entity(adev, ctx->entities[i][j]); 422 atomic64_add(ktime_to_ns(spend), &mgr->time_spend[i]); 423 } 424 } 425 426 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 427 amdgpu_ctx_set_stable_pstate(ctx, ctx->stable_pstate); 428 drm_dev_exit(idx); 429 } 430 431 kfree(ctx); 432 } 433 434 int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance, 435 u32 ring, struct drm_sched_entity **entity) 436 { 437 int r; 438 struct drm_sched_entity *ctx_entity; 439 440 if (hw_ip >= AMDGPU_HW_IP_NUM) { 441 drm_err(adev_to_drm(ctx->mgr->adev), 442 "unknown HW IP type: %d\n", hw_ip); 443 return -EINVAL; 444 } 445 446 /* Right now all IPs have only one instance - multiple rings. */ 447 if (instance != 0) { 448 drm_dbg(adev_to_drm(ctx->mgr->adev), 449 "invalid ip instance: %d\n", instance); 450 return -EINVAL; 451 } 452 453 if (ring >= amdgpu_ctx_num_entities[hw_ip]) { 454 drm_dbg(adev_to_drm(ctx->mgr->adev), 455 "invalid ring: %d %d\n", hw_ip, ring); 456 return -EINVAL; 457 } 458 459 if (ctx->entities[hw_ip][ring] == NULL) { 460 r = amdgpu_ctx_init_entity(ctx, hw_ip, ring); 461 if (r) 462 return r; 463 } 464 465 ctx_entity = &ctx->entities[hw_ip][ring]->entity; 466 r = drm_sched_entity_error(ctx_entity); 467 if (r) { 468 DRM_DEBUG("error entity %p\n", ctx_entity); 469 return r; 470 } 471 472 *entity = ctx_entity; 473 return 0; 474 } 475 476 static int amdgpu_ctx_alloc(struct amdgpu_device *adev, 477 struct amdgpu_fpriv *fpriv, 478 struct drm_file *filp, 479 int32_t priority, 480 uint32_t *id) 481 { 482 struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; 483 struct amdgpu_ctx *ctx; 484 int r; 485 486 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL); 487 if (!ctx) 488 return -ENOMEM; 489 490 mutex_lock(&mgr->lock); 491 r = idr_alloc(&mgr->ctx_handles, ctx, 1, AMDGPU_VM_MAX_NUM_CTX, GFP_KERNEL); 492 if (r < 0) { 493 mutex_unlock(&mgr->lock); 494 kfree(ctx); 495 return r; 496 } 497 498 *id = (uint32_t)r; 499 r = amdgpu_ctx_init(mgr, priority, filp, ctx); 500 if (r) { 501 idr_remove(&mgr->ctx_handles, *id); 502 *id = 0; 503 kfree(ctx); 504 } 505 mutex_unlock(&mgr->lock); 506 return r; 507 } 508 509 static void amdgpu_ctx_do_release(struct kref *ref) 510 { 511 struct amdgpu_ctx *ctx; 512 u32 i, j; 513 514 ctx = container_of(ref, struct amdgpu_ctx, refcount); 515 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 516 for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) { 517 if (!ctx->entities[i][j]) 518 continue; 519 520 drm_sched_entity_destroy(&ctx->entities[i][j]->entity); 521 } 522 } 523 524 amdgpu_ctx_fini(ref); 525 } 526 527 static int amdgpu_ctx_free(struct amdgpu_fpriv *fpriv, uint32_t id) 528 { 529 struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; 530 struct amdgpu_ctx *ctx; 531 532 mutex_lock(&mgr->lock); 533 ctx = idr_remove(&mgr->ctx_handles, id); 534 if (ctx) 535 kref_put(&ctx->refcount, amdgpu_ctx_do_release); 536 mutex_unlock(&mgr->lock); 537 return ctx ? 0 : -EINVAL; 538 } 539 540 static int amdgpu_ctx_query(struct amdgpu_device *adev, 541 struct amdgpu_fpriv *fpriv, uint32_t id, 542 union drm_amdgpu_ctx_out *out) 543 { 544 struct amdgpu_ctx *ctx; 545 struct amdgpu_ctx_mgr *mgr; 546 unsigned reset_counter; 547 548 if (!fpriv) 549 return -EINVAL; 550 551 mgr = &fpriv->ctx_mgr; 552 mutex_lock(&mgr->lock); 553 ctx = idr_find(&mgr->ctx_handles, id); 554 if (!ctx) { 555 mutex_unlock(&mgr->lock); 556 return -EINVAL; 557 } 558 559 /* TODO: these two are always zero */ 560 out->state.flags = 0x0; 561 out->state.hangs = 0x0; 562 563 /* determine if a GPU reset has occured since the last call */ 564 reset_counter = atomic_read(&adev->gpu_reset_counter); 565 /* TODO: this should ideally return NO, GUILTY, or INNOCENT. */ 566 if (ctx->reset_counter_query == reset_counter) 567 out->state.reset_status = AMDGPU_CTX_NO_RESET; 568 else 569 out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET; 570 ctx->reset_counter_query = reset_counter; 571 572 mutex_unlock(&mgr->lock); 573 return 0; 574 } 575 576 #define AMDGPU_RAS_COUNTE_DELAY_MS 3000 577 578 static int amdgpu_ctx_query2(struct amdgpu_device *adev, 579 struct amdgpu_fpriv *fpriv, uint32_t id, 580 union drm_amdgpu_ctx_out *out) 581 { 582 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 583 struct amdgpu_ctx *ctx; 584 struct amdgpu_ctx_mgr *mgr; 585 586 if (!fpriv) 587 return -EINVAL; 588 589 mgr = &fpriv->ctx_mgr; 590 mutex_lock(&mgr->lock); 591 ctx = idr_find(&mgr->ctx_handles, id); 592 if (!ctx) { 593 mutex_unlock(&mgr->lock); 594 return -EINVAL; 595 } 596 597 out->state.flags = 0x0; 598 out->state.hangs = 0x0; 599 600 if (ctx->reset_counter != atomic_read(&adev->gpu_reset_counter)) 601 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RESET; 602 603 if (ctx->generation != amdgpu_vm_generation(adev, &fpriv->vm)) 604 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST; 605 606 if (atomic_read(&ctx->guilty)) 607 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_GUILTY; 608 609 if (amdgpu_in_reset(adev)) 610 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS; 611 612 if (adev->ras_enabled && con) { 613 /* Return the cached values in O(1), 614 * and schedule delayed work to cache 615 * new vaues. 616 */ 617 int ce_count, ue_count; 618 619 ce_count = atomic_read(&con->ras_ce_count); 620 ue_count = atomic_read(&con->ras_ue_count); 621 622 if (ce_count != ctx->ras_counter_ce) { 623 ctx->ras_counter_ce = ce_count; 624 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_CE; 625 } 626 627 if (ue_count != ctx->ras_counter_ue) { 628 ctx->ras_counter_ue = ue_count; 629 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_UE; 630 } 631 632 schedule_delayed_work(&con->ras_counte_delay_work, 633 msecs_to_jiffies(AMDGPU_RAS_COUNTE_DELAY_MS)); 634 } 635 636 mutex_unlock(&mgr->lock); 637 return 0; 638 } 639 640 static int amdgpu_ctx_stable_pstate(struct amdgpu_device *adev, 641 struct amdgpu_fpriv *fpriv, uint32_t id, 642 bool set, u32 *stable_pstate) 643 { 644 struct amdgpu_ctx *ctx; 645 struct amdgpu_ctx_mgr *mgr; 646 int r; 647 648 if (!fpriv) 649 return -EINVAL; 650 651 mgr = &fpriv->ctx_mgr; 652 mutex_lock(&mgr->lock); 653 ctx = idr_find(&mgr->ctx_handles, id); 654 if (!ctx) { 655 mutex_unlock(&mgr->lock); 656 return -EINVAL; 657 } 658 659 if (set) 660 r = amdgpu_ctx_set_stable_pstate(ctx, *stable_pstate); 661 else 662 r = amdgpu_ctx_get_stable_pstate(ctx, stable_pstate); 663 664 mutex_unlock(&mgr->lock); 665 return r; 666 } 667 668 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 669 struct drm_file *filp) 670 { 671 int r; 672 uint32_t id, stable_pstate; 673 int32_t priority; 674 675 union drm_amdgpu_ctx *args = data; 676 struct amdgpu_device *adev = drm_to_adev(dev); 677 struct amdgpu_fpriv *fpriv = filp->driver_priv; 678 679 id = args->in.ctx_id; 680 priority = args->in.priority; 681 682 /* For backwards compatibility, we need to accept ioctls with garbage 683 * in the priority field. Garbage values in the priority field, result 684 * in the priority being set to NORMAL. 685 */ 686 if (!amdgpu_ctx_priority_is_valid(priority)) 687 priority = AMDGPU_CTX_PRIORITY_NORMAL; 688 689 switch (args->in.op) { 690 case AMDGPU_CTX_OP_ALLOC_CTX: 691 if (args->in.flags) 692 return -EINVAL; 693 r = amdgpu_ctx_alloc(adev, fpriv, filp, priority, &id); 694 args->out.alloc.ctx_id = id; 695 break; 696 case AMDGPU_CTX_OP_FREE_CTX: 697 if (args->in.flags) 698 return -EINVAL; 699 r = amdgpu_ctx_free(fpriv, id); 700 break; 701 case AMDGPU_CTX_OP_QUERY_STATE: 702 if (args->in.flags) 703 return -EINVAL; 704 r = amdgpu_ctx_query(adev, fpriv, id, &args->out); 705 break; 706 case AMDGPU_CTX_OP_QUERY_STATE2: 707 if (args->in.flags) 708 return -EINVAL; 709 r = amdgpu_ctx_query2(adev, fpriv, id, &args->out); 710 break; 711 case AMDGPU_CTX_OP_GET_STABLE_PSTATE: 712 if (args->in.flags) 713 return -EINVAL; 714 r = amdgpu_ctx_stable_pstate(adev, fpriv, id, false, &stable_pstate); 715 if (!r) 716 args->out.pstate.flags = stable_pstate; 717 break; 718 case AMDGPU_CTX_OP_SET_STABLE_PSTATE: 719 if (args->in.flags & ~AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK) 720 return -EINVAL; 721 stable_pstate = args->in.flags & AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK; 722 if (stable_pstate > AMDGPU_CTX_STABLE_PSTATE_PEAK) 723 return -EINVAL; 724 r = amdgpu_ctx_stable_pstate(adev, fpriv, id, true, &stable_pstate); 725 break; 726 default: 727 return -EINVAL; 728 } 729 730 return r; 731 } 732 733 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id) 734 { 735 struct amdgpu_ctx *ctx; 736 struct amdgpu_ctx_mgr *mgr; 737 738 if (!fpriv) 739 return NULL; 740 741 mgr = &fpriv->ctx_mgr; 742 743 mutex_lock(&mgr->lock); 744 ctx = idr_find(&mgr->ctx_handles, id); 745 if (ctx) 746 kref_get(&ctx->refcount); 747 mutex_unlock(&mgr->lock); 748 return ctx; 749 } 750 751 int amdgpu_ctx_put(struct amdgpu_ctx *ctx) 752 { 753 if (ctx == NULL) 754 return -EINVAL; 755 756 kref_put(&ctx->refcount, amdgpu_ctx_do_release); 757 return 0; 758 } 759 760 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, 761 struct drm_sched_entity *entity, 762 struct dma_fence *fence) 763 { 764 struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity); 765 uint64_t seq = centity->sequence; 766 struct dma_fence *other = NULL; 767 unsigned idx = 0; 768 769 idx = seq & (amdgpu_sched_jobs - 1); 770 other = centity->fences[idx]; 771 WARN_ON(other && !dma_fence_is_signaled(other)); 772 773 dma_fence_get(fence); 774 775 spin_lock(&ctx->ring_lock); 776 centity->fences[idx] = fence; 777 centity->sequence++; 778 spin_unlock(&ctx->ring_lock); 779 780 atomic64_add(ktime_to_ns(amdgpu_ctx_fence_time(other)), 781 &ctx->mgr->time_spend[centity->hw_ip]); 782 783 dma_fence_put(other); 784 return seq; 785 } 786 787 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 788 struct drm_sched_entity *entity, 789 uint64_t seq) 790 { 791 struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity); 792 struct dma_fence *fence; 793 794 spin_lock(&ctx->ring_lock); 795 796 if (seq == ~0ull) 797 seq = centity->sequence - 1; 798 799 if (seq >= centity->sequence) { 800 spin_unlock(&ctx->ring_lock); 801 return ERR_PTR(-EINVAL); 802 } 803 804 805 if (seq + amdgpu_sched_jobs < centity->sequence) { 806 spin_unlock(&ctx->ring_lock); 807 return NULL; 808 } 809 810 fence = dma_fence_get(centity->fences[seq & (amdgpu_sched_jobs - 1)]); 811 spin_unlock(&ctx->ring_lock); 812 813 return fence; 814 } 815 816 static void amdgpu_ctx_set_entity_priority(struct amdgpu_ctx *ctx, 817 struct amdgpu_ctx_entity *aentity, 818 int hw_ip, 819 int32_t priority) 820 { 821 struct amdgpu_device *adev = ctx->mgr->adev; 822 unsigned int hw_prio; 823 struct drm_gpu_scheduler **scheds = NULL; 824 unsigned num_scheds; 825 826 /* set sw priority */ 827 drm_sched_entity_set_priority(&aentity->entity, 828 amdgpu_ctx_to_drm_sched_prio(priority)); 829 830 /* set hw priority */ 831 if (hw_ip == AMDGPU_HW_IP_COMPUTE || hw_ip == AMDGPU_HW_IP_GFX) { 832 hw_prio = amdgpu_ctx_get_hw_prio(ctx, hw_ip); 833 hw_prio = array_index_nospec(hw_prio, AMDGPU_RING_PRIO_MAX); 834 scheds = adev->gpu_sched[hw_ip][hw_prio].sched; 835 num_scheds = adev->gpu_sched[hw_ip][hw_prio].num_scheds; 836 drm_sched_entity_modify_sched(&aentity->entity, scheds, 837 num_scheds); 838 } 839 } 840 841 void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx, 842 int32_t priority) 843 { 844 int32_t ctx_prio; 845 unsigned i, j; 846 847 ctx->override_priority = priority; 848 849 ctx_prio = (ctx->override_priority == AMDGPU_CTX_PRIORITY_UNSET) ? 850 ctx->init_priority : ctx->override_priority; 851 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 852 for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) { 853 if (!ctx->entities[i][j]) 854 continue; 855 856 amdgpu_ctx_set_entity_priority(ctx, ctx->entities[i][j], 857 i, ctx_prio); 858 } 859 } 860 } 861 862 int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, 863 struct drm_sched_entity *entity) 864 { 865 struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity); 866 struct dma_fence *other; 867 unsigned idx; 868 long r; 869 870 spin_lock(&ctx->ring_lock); 871 idx = centity->sequence & (amdgpu_sched_jobs - 1); 872 other = dma_fence_get(centity->fences[idx]); 873 spin_unlock(&ctx->ring_lock); 874 875 if (!other) 876 return 0; 877 878 r = dma_fence_wait(other, true); 879 if (r < 0 && r != -ERESTARTSYS) 880 drm_err(adev_to_drm(ctx->mgr->adev), 881 "AMDGPU: Error waiting for fence in ctx %p\n", ctx); 882 883 dma_fence_put(other); 884 return r; 885 } 886 887 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr, 888 struct amdgpu_device *adev) 889 { 890 unsigned int i; 891 892 mgr->adev = adev; 893 mutex_init(&mgr->lock); 894 idr_init_base(&mgr->ctx_handles, 1); 895 896 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) 897 atomic64_set(&mgr->time_spend[i], 0); 898 } 899 900 long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout) 901 { 902 struct amdgpu_ctx *ctx; 903 struct idr *idp; 904 uint32_t id, i, j; 905 906 idp = &mgr->ctx_handles; 907 908 mutex_lock(&mgr->lock); 909 idr_for_each_entry(idp, ctx, id) { 910 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 911 for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) { 912 struct drm_sched_entity *entity; 913 914 if (!ctx->entities[i][j]) 915 continue; 916 917 entity = &ctx->entities[i][j]->entity; 918 timeout = drm_sched_entity_flush(entity, timeout); 919 } 920 } 921 } 922 mutex_unlock(&mgr->lock); 923 return timeout; 924 } 925 926 static void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr) 927 { 928 struct amdgpu_ctx *ctx; 929 struct idr *idp; 930 uint32_t id, i, j; 931 932 idp = &mgr->ctx_handles; 933 934 idr_for_each_entry(idp, ctx, id) { 935 if (kref_read(&ctx->refcount) != 1) { 936 drm_err(adev_to_drm(mgr->adev), "ctx %p is still alive\n", ctx); 937 continue; 938 } 939 940 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 941 for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) { 942 struct drm_sched_entity *entity; 943 944 if (!ctx->entities[i][j]) 945 continue; 946 947 entity = &ctx->entities[i][j]->entity; 948 drm_sched_entity_fini(entity); 949 } 950 } 951 kref_put(&ctx->refcount, amdgpu_ctx_fini); 952 } 953 } 954 955 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr) 956 { 957 amdgpu_ctx_mgr_entity_fini(mgr); 958 idr_destroy(&mgr->ctx_handles); 959 mutex_destroy(&mgr->lock); 960 } 961 962 void amdgpu_ctx_mgr_usage(struct amdgpu_ctx_mgr *mgr, 963 ktime_t usage[AMDGPU_HW_IP_NUM]) 964 { 965 struct amdgpu_ctx *ctx; 966 unsigned int hw_ip, i; 967 uint32_t id; 968 969 /* 970 * This is a little bit racy because it can be that a ctx or a fence are 971 * destroyed just in the moment we try to account them. But that is ok 972 * since exactly that case is explicitely allowed by the interface. 973 */ 974 mutex_lock(&mgr->lock); 975 for (hw_ip = 0; hw_ip < AMDGPU_HW_IP_NUM; ++hw_ip) { 976 uint64_t ns = atomic64_read(&mgr->time_spend[hw_ip]); 977 978 usage[hw_ip] = ns_to_ktime(ns); 979 } 980 981 idr_for_each_entry(&mgr->ctx_handles, ctx, id) { 982 for (hw_ip = 0; hw_ip < AMDGPU_HW_IP_NUM; ++hw_ip) { 983 for (i = 0; i < amdgpu_ctx_num_entities[hw_ip]; ++i) { 984 struct amdgpu_ctx_entity *centity; 985 ktime_t spend; 986 987 centity = ctx->entities[hw_ip][i]; 988 if (!centity) 989 continue; 990 spend = amdgpu_ctx_entity_time(ctx, centity); 991 usage[hw_ip] = ktime_add(usage[hw_ip], spend); 992 } 993 } 994 } 995 mutex_unlock(&mgr->lock); 996 } 997