1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: monk liu <monk.liu@amd.com> 23 */ 24 25 #include <drm/drm_auth.h> 26 #include <drm/drm_drv.h> 27 #include "amdgpu.h" 28 #include "amdgpu_sched.h" 29 #include "amdgpu_ras.h" 30 #include <linux/nospec.h> 31 32 #define to_amdgpu_ctx_entity(e) \ 33 container_of((e), struct amdgpu_ctx_entity, entity) 34 35 const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM] = { 36 [AMDGPU_HW_IP_GFX] = 1, 37 [AMDGPU_HW_IP_COMPUTE] = 4, 38 [AMDGPU_HW_IP_DMA] = 2, 39 [AMDGPU_HW_IP_UVD] = 1, 40 [AMDGPU_HW_IP_VCE] = 1, 41 [AMDGPU_HW_IP_UVD_ENC] = 1, 42 [AMDGPU_HW_IP_VCN_DEC] = 1, 43 [AMDGPU_HW_IP_VCN_ENC] = 1, 44 [AMDGPU_HW_IP_VCN_JPEG] = 1, 45 [AMDGPU_HW_IP_VPE] = 1, 46 }; 47 48 bool amdgpu_ctx_priority_is_valid(int32_t ctx_prio) 49 { 50 switch (ctx_prio) { 51 case AMDGPU_CTX_PRIORITY_VERY_LOW: 52 case AMDGPU_CTX_PRIORITY_LOW: 53 case AMDGPU_CTX_PRIORITY_NORMAL: 54 case AMDGPU_CTX_PRIORITY_HIGH: 55 case AMDGPU_CTX_PRIORITY_VERY_HIGH: 56 return true; 57 default: 58 case AMDGPU_CTX_PRIORITY_UNSET: 59 /* UNSET priority is not valid and we don't carry that 60 * around, but set it to NORMAL in the only place this 61 * function is called, amdgpu_ctx_ioctl(). 62 */ 63 return false; 64 } 65 } 66 67 static enum drm_sched_priority 68 amdgpu_ctx_to_drm_sched_prio(int32_t ctx_prio) 69 { 70 switch (ctx_prio) { 71 case AMDGPU_CTX_PRIORITY_UNSET: 72 pr_warn_once("AMD-->DRM context priority value UNSET-->NORMAL"); 73 return DRM_SCHED_PRIORITY_NORMAL; 74 75 case AMDGPU_CTX_PRIORITY_VERY_LOW: 76 return DRM_SCHED_PRIORITY_LOW; 77 78 case AMDGPU_CTX_PRIORITY_LOW: 79 return DRM_SCHED_PRIORITY_LOW; 80 81 case AMDGPU_CTX_PRIORITY_NORMAL: 82 return DRM_SCHED_PRIORITY_NORMAL; 83 84 case AMDGPU_CTX_PRIORITY_HIGH: 85 return DRM_SCHED_PRIORITY_HIGH; 86 87 case AMDGPU_CTX_PRIORITY_VERY_HIGH: 88 return DRM_SCHED_PRIORITY_HIGH; 89 90 /* This should not happen as we sanitized userspace provided priority 91 * already, WARN if this happens. 92 */ 93 default: 94 WARN(1, "Invalid context priority %d\n", ctx_prio); 95 return DRM_SCHED_PRIORITY_NORMAL; 96 } 97 98 } 99 100 static int amdgpu_ctx_priority_permit(struct drm_file *filp, 101 int32_t priority) 102 { 103 /* NORMAL and below are accessible by everyone */ 104 if (priority <= AMDGPU_CTX_PRIORITY_NORMAL) 105 return 0; 106 107 if (capable(CAP_SYS_NICE)) 108 return 0; 109 110 if (drm_is_current_master(filp)) 111 return 0; 112 113 return -EACCES; 114 } 115 116 static enum amdgpu_gfx_pipe_priority amdgpu_ctx_prio_to_gfx_pipe_prio(int32_t prio) 117 { 118 switch (prio) { 119 case AMDGPU_CTX_PRIORITY_HIGH: 120 case AMDGPU_CTX_PRIORITY_VERY_HIGH: 121 return AMDGPU_GFX_PIPE_PRIO_HIGH; 122 default: 123 return AMDGPU_GFX_PIPE_PRIO_NORMAL; 124 } 125 } 126 127 static enum amdgpu_ring_priority_level amdgpu_ctx_sched_prio_to_ring_prio(int32_t prio) 128 { 129 switch (prio) { 130 case AMDGPU_CTX_PRIORITY_HIGH: 131 return AMDGPU_RING_PRIO_1; 132 case AMDGPU_CTX_PRIORITY_VERY_HIGH: 133 return AMDGPU_RING_PRIO_2; 134 default: 135 return AMDGPU_RING_PRIO_0; 136 } 137 } 138 139 static unsigned int amdgpu_ctx_get_hw_prio(struct amdgpu_ctx *ctx, u32 hw_ip) 140 { 141 struct amdgpu_device *adev = ctx->mgr->adev; 142 unsigned int hw_prio; 143 int32_t ctx_prio; 144 145 ctx_prio = (ctx->override_priority == AMDGPU_CTX_PRIORITY_UNSET) ? 146 ctx->init_priority : ctx->override_priority; 147 148 switch (hw_ip) { 149 case AMDGPU_HW_IP_GFX: 150 case AMDGPU_HW_IP_COMPUTE: 151 hw_prio = amdgpu_ctx_prio_to_gfx_pipe_prio(ctx_prio); 152 break; 153 case AMDGPU_HW_IP_VCE: 154 case AMDGPU_HW_IP_VCN_ENC: 155 hw_prio = amdgpu_ctx_sched_prio_to_ring_prio(ctx_prio); 156 break; 157 default: 158 hw_prio = AMDGPU_RING_PRIO_DEFAULT; 159 break; 160 } 161 162 hw_ip = array_index_nospec(hw_ip, AMDGPU_HW_IP_NUM); 163 if (adev->gpu_sched[hw_ip][hw_prio].num_scheds == 0) 164 hw_prio = AMDGPU_RING_PRIO_DEFAULT; 165 166 return hw_prio; 167 } 168 169 /* Calculate the time spend on the hw */ 170 static ktime_t amdgpu_ctx_fence_time(struct dma_fence *fence) 171 { 172 struct drm_sched_fence *s_fence; 173 174 if (!fence) 175 return ns_to_ktime(0); 176 177 /* When the fence is not even scheduled it can't have spend time */ 178 s_fence = to_drm_sched_fence(fence); 179 if (!test_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &s_fence->scheduled.flags)) 180 return ns_to_ktime(0); 181 182 /* When it is still running account how much already spend */ 183 if (!test_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &s_fence->finished.flags)) 184 return ktime_sub(ktime_get(), s_fence->scheduled.timestamp); 185 186 return ktime_sub(s_fence->finished.timestamp, 187 s_fence->scheduled.timestamp); 188 } 189 190 static ktime_t amdgpu_ctx_entity_time(struct amdgpu_ctx *ctx, 191 struct amdgpu_ctx_entity *centity) 192 { 193 ktime_t res = ns_to_ktime(0); 194 uint32_t i; 195 196 spin_lock(&ctx->ring_lock); 197 for (i = 0; i < amdgpu_sched_jobs; i++) { 198 res = ktime_add(res, amdgpu_ctx_fence_time(centity->fences[i])); 199 } 200 spin_unlock(&ctx->ring_lock); 201 return res; 202 } 203 204 static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, u32 hw_ip, 205 const u32 ring) 206 { 207 struct drm_gpu_scheduler **scheds = NULL, *sched = NULL; 208 struct amdgpu_device *adev = ctx->mgr->adev; 209 struct amdgpu_ctx_entity *entity; 210 enum drm_sched_priority drm_prio; 211 unsigned int hw_prio, num_scheds; 212 int32_t ctx_prio; 213 int r; 214 215 entity = kzalloc_flex(*entity, fences, amdgpu_sched_jobs); 216 if (!entity) 217 return -ENOMEM; 218 219 ctx_prio = (ctx->override_priority == AMDGPU_CTX_PRIORITY_UNSET) ? 220 ctx->init_priority : ctx->override_priority; 221 entity->hw_ip = hw_ip; 222 entity->sequence = 1; 223 hw_prio = amdgpu_ctx_get_hw_prio(ctx, hw_ip); 224 drm_prio = amdgpu_ctx_to_drm_sched_prio(ctx_prio); 225 226 hw_ip = array_index_nospec(hw_ip, AMDGPU_HW_IP_NUM); 227 228 if (!(adev)->xcp_mgr) { 229 scheds = adev->gpu_sched[hw_ip][hw_prio].sched; 230 num_scheds = adev->gpu_sched[hw_ip][hw_prio].num_scheds; 231 } else { 232 struct amdgpu_fpriv *fpriv; 233 234 /* TODO: Stop using fpriv here, we only need the xcp_id. */ 235 fpriv = container_of(ctx->mgr, struct amdgpu_fpriv, ctx_mgr); 236 r = amdgpu_xcp_select_scheds(adev, hw_ip, hw_prio, fpriv, 237 &num_scheds, &scheds); 238 if (r) 239 goto error_free_entity; 240 } 241 242 if (num_scheds == 0) { 243 r = -EINVAL; 244 goto error_free_entity; 245 } 246 247 /* disable load balance if the hw engine retains context among dependent jobs */ 248 if (hw_ip == AMDGPU_HW_IP_VCN_ENC || 249 hw_ip == AMDGPU_HW_IP_VCN_DEC || 250 hw_ip == AMDGPU_HW_IP_UVD_ENC || 251 hw_ip == AMDGPU_HW_IP_UVD) { 252 sched = drm_sched_pick_best(scheds, num_scheds); 253 scheds = &sched; 254 num_scheds = 1; 255 } 256 257 r = drm_sched_entity_init(&entity->entity, drm_prio, scheds, num_scheds, 258 NULL); 259 if (r) 260 goto error_free_entity; 261 262 /* It's not an error if we fail to install the new entity */ 263 if (cmpxchg(&ctx->entities[hw_ip][ring], NULL, entity)) 264 goto cleanup_entity; 265 266 return 0; 267 268 cleanup_entity: 269 drm_sched_entity_fini(&entity->entity); 270 271 error_free_entity: 272 kfree(entity); 273 274 return r; 275 } 276 277 static ktime_t amdgpu_ctx_fini_entity(struct amdgpu_device *adev, 278 struct amdgpu_ctx_entity *entity) 279 { 280 ktime_t res = ns_to_ktime(0); 281 int i; 282 283 if (!entity) 284 return res; 285 286 for (i = 0; i < amdgpu_sched_jobs; ++i) { 287 res = ktime_add(res, amdgpu_ctx_fence_time(entity->fences[i])); 288 dma_fence_put(entity->fences[i]); 289 } 290 291 amdgpu_xcp_release_sched(adev, entity); 292 293 kfree(entity); 294 return res; 295 } 296 297 static int amdgpu_ctx_get_stable_pstate(struct amdgpu_ctx *ctx, 298 u32 *stable_pstate) 299 { 300 struct amdgpu_device *adev = ctx->mgr->adev; 301 enum amd_dpm_forced_level current_level; 302 303 current_level = amdgpu_dpm_get_performance_level(adev); 304 305 switch (current_level) { 306 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 307 *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_STANDARD; 308 break; 309 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 310 *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK; 311 break; 312 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 313 *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK; 314 break; 315 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 316 *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_PEAK; 317 break; 318 default: 319 *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_NONE; 320 break; 321 } 322 return 0; 323 } 324 325 static int amdgpu_ctx_init(struct amdgpu_ctx_mgr *mgr, int32_t priority, 326 struct drm_file *filp, struct amdgpu_ctx *ctx) 327 { 328 struct amdgpu_fpriv *fpriv = filp->driver_priv; 329 int r; 330 331 r = amdgpu_ctx_priority_permit(filp, priority); 332 if (r) 333 return r; 334 335 memset(ctx, 0, sizeof(*ctx)); 336 337 kref_init(&ctx->refcount); 338 ctx->mgr = mgr; 339 spin_lock_init(&ctx->ring_lock); 340 341 ctx->reset_counter = atomic_read(&mgr->adev->gpu_reset_counter); 342 ctx->reset_counter_query = ctx->reset_counter; 343 ctx->generation = amdgpu_vm_generation(mgr->adev, &fpriv->vm); 344 ctx->init_priority = priority; 345 ctx->override_priority = AMDGPU_CTX_PRIORITY_UNSET; 346 ctx->stable_pstate = AMDGPU_CTX_STABLE_PSTATE_NONE; 347 348 return 0; 349 } 350 351 static int __amdgpu_ctx_set_stable_pstate(struct amdgpu_ctx *ctx, 352 u32 stable_pstate) 353 { 354 struct amdgpu_device *adev = ctx->mgr->adev; 355 enum amd_dpm_forced_level level; 356 struct amdgpu_ctx *current_ctx; 357 u32 current_stable_pstate; 358 int r = 0; 359 360 lockdep_assert_held(&adev->pm.stable_pstate_ctx_lock); 361 362 switch (stable_pstate) { 363 case AMDGPU_CTX_STABLE_PSTATE_NONE: 364 level = AMD_DPM_FORCED_LEVEL_AUTO; 365 break; 366 case AMDGPU_CTX_STABLE_PSTATE_STANDARD: 367 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD; 368 break; 369 case AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK: 370 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK; 371 break; 372 case AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK: 373 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK; 374 break; 375 case AMDGPU_CTX_STABLE_PSTATE_PEAK: 376 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 377 break; 378 default: 379 return -EINVAL; 380 } 381 382 current_ctx = adev->pm.stable_pstate_ctx; 383 if (current_ctx && current_ctx != ctx) 384 return -EBUSY; 385 386 r = amdgpu_ctx_get_stable_pstate(ctx, ¤t_stable_pstate); 387 if (r || current_stable_pstate == stable_pstate) 388 return r; 389 390 r = amdgpu_dpm_force_performance_level(adev, level); 391 if (r) 392 return r; 393 394 if (!current_ctx) { 395 adev->pm.stable_pstate_ctx = ctx; 396 /* 397 * Serialized by context taking ownership for the first time 398 * while holding adev->pm.stable_pstate_ctx_lock). 399 */ 400 WRITE_ONCE(ctx->stable_pstate, current_stable_pstate); 401 } 402 403 return 0; 404 } 405 406 static int amdgpu_ctx_set_stable_pstate(struct amdgpu_ctx *ctx, 407 u32 stable_pstate) 408 { 409 struct amdgpu_device *adev = ctx->mgr->adev; 410 int r; 411 412 mutex_lock(&adev->pm.stable_pstate_ctx_lock); 413 r = __amdgpu_ctx_set_stable_pstate(ctx, stable_pstate); 414 mutex_unlock(&adev->pm.stable_pstate_ctx_lock); 415 416 return r; 417 } 418 419 static void amdgpu_ctx_fini(struct kref *ref) 420 { 421 struct amdgpu_ctx *ctx = container_of(ref, struct amdgpu_ctx, refcount); 422 struct amdgpu_ctx_mgr *mgr = ctx->mgr; 423 struct amdgpu_device *adev = mgr->adev; 424 unsigned i, j, idx; 425 426 if (!adev) 427 return; 428 429 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 430 for (j = 0; j < AMDGPU_MAX_ENTITY_NUM; ++j) { 431 ktime_t spend; 432 433 spend = amdgpu_ctx_fini_entity(adev, ctx->entities[i][j]); 434 atomic64_add(ktime_to_ns(spend), &mgr->time_spend[i]); 435 } 436 } 437 438 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 439 mutex_lock(&adev->pm.stable_pstate_ctx_lock); 440 if (adev->pm.stable_pstate_ctx == ctx) { 441 __amdgpu_ctx_set_stable_pstate(ctx, ctx->stable_pstate); 442 adev->pm.stable_pstate_ctx = NULL; 443 } 444 mutex_unlock(&adev->pm.stable_pstate_ctx_lock); 445 drm_dev_exit(idx); 446 } 447 448 kfree(ctx); 449 } 450 451 int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance, 452 u32 ring, struct drm_sched_entity **entity) 453 { 454 int r; 455 struct drm_sched_entity *ctx_entity; 456 457 if (hw_ip >= AMDGPU_HW_IP_NUM) { 458 drm_err(adev_to_drm(ctx->mgr->adev), 459 "unknown HW IP type: %d\n", hw_ip); 460 return -EINVAL; 461 } 462 463 /* Right now all IPs have only one instance - multiple rings. */ 464 if (instance != 0) { 465 drm_dbg(adev_to_drm(ctx->mgr->adev), 466 "invalid ip instance: %d\n", instance); 467 return -EINVAL; 468 } 469 470 if (ring >= amdgpu_ctx_num_entities[hw_ip]) { 471 drm_dbg(adev_to_drm(ctx->mgr->adev), 472 "invalid ring: %d %d\n", hw_ip, ring); 473 return -EINVAL; 474 } 475 476 if (ctx->entities[hw_ip][ring] == NULL) { 477 r = amdgpu_ctx_init_entity(ctx, hw_ip, ring); 478 if (r) 479 return r; 480 } 481 482 ctx_entity = &ctx->entities[hw_ip][ring]->entity; 483 r = drm_sched_entity_error(ctx_entity); 484 if (r) { 485 DRM_DEBUG("error entity %p\n", ctx_entity); 486 return r; 487 } 488 489 *entity = ctx_entity; 490 return 0; 491 } 492 493 static int amdgpu_ctx_alloc(struct amdgpu_device *adev, 494 struct amdgpu_fpriv *fpriv, 495 struct drm_file *filp, 496 int32_t priority, 497 uint32_t *id) 498 { 499 struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; 500 struct amdgpu_ctx *ctx; 501 int r; 502 503 ctx = kmalloc_obj(*ctx); 504 if (!ctx) 505 return -ENOMEM; 506 507 mutex_lock(&mgr->lock); 508 r = idr_alloc(&mgr->ctx_handles, ctx, 1, AMDGPU_VM_MAX_NUM_CTX, GFP_KERNEL); 509 if (r < 0) { 510 mutex_unlock(&mgr->lock); 511 kfree(ctx); 512 return r; 513 } 514 515 *id = (uint32_t)r; 516 r = amdgpu_ctx_init(mgr, priority, filp, ctx); 517 if (r) { 518 idr_remove(&mgr->ctx_handles, *id); 519 *id = 0; 520 kfree(ctx); 521 } 522 mutex_unlock(&mgr->lock); 523 return r; 524 } 525 526 static void amdgpu_ctx_do_release(struct kref *ref) 527 { 528 struct amdgpu_ctx *ctx; 529 u32 i, j; 530 531 ctx = container_of(ref, struct amdgpu_ctx, refcount); 532 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 533 for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) { 534 if (!ctx->entities[i][j]) 535 continue; 536 537 drm_sched_entity_destroy(&ctx->entities[i][j]->entity); 538 } 539 } 540 541 amdgpu_ctx_fini(ref); 542 } 543 544 static int amdgpu_ctx_free(struct amdgpu_fpriv *fpriv, uint32_t id) 545 { 546 struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; 547 struct amdgpu_ctx *ctx; 548 549 mutex_lock(&mgr->lock); 550 ctx = idr_remove(&mgr->ctx_handles, id); 551 if (ctx) 552 kref_put(&ctx->refcount, amdgpu_ctx_do_release); 553 mutex_unlock(&mgr->lock); 554 return ctx ? 0 : -EINVAL; 555 } 556 557 static int amdgpu_ctx_query(struct amdgpu_device *adev, 558 struct amdgpu_fpriv *fpriv, uint32_t id, 559 union drm_amdgpu_ctx_out *out) 560 { 561 struct amdgpu_ctx *ctx; 562 struct amdgpu_ctx_mgr *mgr; 563 unsigned reset_counter; 564 565 if (!fpriv) 566 return -EINVAL; 567 568 mgr = &fpriv->ctx_mgr; 569 mutex_lock(&mgr->lock); 570 ctx = idr_find(&mgr->ctx_handles, id); 571 if (!ctx) { 572 mutex_unlock(&mgr->lock); 573 return -EINVAL; 574 } 575 576 /* TODO: these two are always zero */ 577 out->state.flags = 0x0; 578 out->state.hangs = 0x0; 579 580 /* determine if a GPU reset has occured since the last call */ 581 reset_counter = atomic_read(&adev->gpu_reset_counter); 582 /* TODO: this should ideally return NO, GUILTY, or INNOCENT. */ 583 if (ctx->reset_counter_query == reset_counter) 584 out->state.reset_status = AMDGPU_CTX_NO_RESET; 585 else 586 out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET; 587 ctx->reset_counter_query = reset_counter; 588 589 mutex_unlock(&mgr->lock); 590 return 0; 591 } 592 593 #define AMDGPU_RAS_COUNTE_DELAY_MS 3000 594 595 static bool amdgpu_ctx_guilty(struct amdgpu_ctx *ctx) 596 { 597 int i, j, r; 598 599 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 600 for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) { 601 struct amdgpu_ctx_entity *ctx_entity; 602 603 ctx_entity = ctx->entities[i][j]; 604 if (!ctx_entity) 605 continue; 606 607 r = drm_sched_entity_error(&ctx_entity->entity); 608 if (r == -ETIME) 609 return true; 610 } 611 } 612 613 return false; 614 } 615 616 static int amdgpu_ctx_query2(struct amdgpu_device *adev, 617 struct amdgpu_fpriv *fpriv, uint32_t id, 618 union drm_amdgpu_ctx_out *out) 619 { 620 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 621 struct amdgpu_ctx *ctx; 622 struct amdgpu_ctx_mgr *mgr; 623 624 if (!fpriv) 625 return -EINVAL; 626 627 mgr = &fpriv->ctx_mgr; 628 mutex_lock(&mgr->lock); 629 ctx = idr_find(&mgr->ctx_handles, id); 630 if (!ctx) { 631 mutex_unlock(&mgr->lock); 632 return -EINVAL; 633 } 634 635 out->state.flags = 0x0; 636 out->state.hangs = 0x0; 637 638 if (ctx->reset_counter != atomic_read(&adev->gpu_reset_counter)) 639 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RESET; 640 641 if (ctx->generation != amdgpu_vm_generation(adev, &fpriv->vm)) 642 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST; 643 644 if (amdgpu_ctx_guilty(ctx)) 645 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_GUILTY; 646 647 if (amdgpu_in_reset(adev)) 648 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS; 649 650 if (adev->ras_enabled && con) { 651 /* Return the cached values in O(1), 652 * and schedule delayed work to cache 653 * new vaues. 654 */ 655 int ce_count, ue_count; 656 657 ce_count = atomic_read(&con->ras_ce_count); 658 ue_count = atomic_read(&con->ras_ue_count); 659 660 if (ce_count != ctx->ras_counter_ce) { 661 ctx->ras_counter_ce = ce_count; 662 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_CE; 663 } 664 665 if (ue_count != ctx->ras_counter_ue) { 666 ctx->ras_counter_ue = ue_count; 667 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_UE; 668 } 669 670 schedule_delayed_work(&con->ras_counte_delay_work, 671 msecs_to_jiffies(AMDGPU_RAS_COUNTE_DELAY_MS)); 672 } 673 674 mutex_unlock(&mgr->lock); 675 return 0; 676 } 677 678 static int amdgpu_ctx_stable_pstate(struct amdgpu_device *adev, 679 struct amdgpu_fpriv *fpriv, uint32_t id, 680 bool set, u32 *stable_pstate) 681 { 682 struct amdgpu_ctx *ctx; 683 struct amdgpu_ctx_mgr *mgr; 684 int r; 685 686 if (!fpriv) 687 return -EINVAL; 688 689 mgr = &fpriv->ctx_mgr; 690 mutex_lock(&mgr->lock); 691 ctx = idr_find(&mgr->ctx_handles, id); 692 if (!ctx) { 693 mutex_unlock(&mgr->lock); 694 return -EINVAL; 695 } 696 697 if (set) 698 r = amdgpu_ctx_set_stable_pstate(ctx, *stable_pstate); 699 else 700 r = amdgpu_ctx_get_stable_pstate(ctx, stable_pstate); 701 702 mutex_unlock(&mgr->lock); 703 return r; 704 } 705 706 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 707 struct drm_file *filp) 708 { 709 int r; 710 uint32_t id, stable_pstate; 711 int32_t priority; 712 713 union drm_amdgpu_ctx *args = data; 714 struct amdgpu_device *adev = drm_to_adev(dev); 715 struct amdgpu_fpriv *fpriv = filp->driver_priv; 716 717 id = args->in.ctx_id; 718 priority = args->in.priority; 719 720 /* For backwards compatibility, we need to accept ioctls with garbage 721 * in the priority field. Garbage values in the priority field, result 722 * in the priority being set to NORMAL. 723 */ 724 if (!amdgpu_ctx_priority_is_valid(priority)) 725 priority = AMDGPU_CTX_PRIORITY_NORMAL; 726 727 switch (args->in.op) { 728 case AMDGPU_CTX_OP_ALLOC_CTX: 729 if (args->in.flags) 730 return -EINVAL; 731 r = amdgpu_ctx_alloc(adev, fpriv, filp, priority, &id); 732 args->out.alloc.ctx_id = id; 733 break; 734 case AMDGPU_CTX_OP_FREE_CTX: 735 if (args->in.flags) 736 return -EINVAL; 737 r = amdgpu_ctx_free(fpriv, id); 738 break; 739 case AMDGPU_CTX_OP_QUERY_STATE: 740 if (args->in.flags) 741 return -EINVAL; 742 r = amdgpu_ctx_query(adev, fpriv, id, &args->out); 743 break; 744 case AMDGPU_CTX_OP_QUERY_STATE2: 745 if (args->in.flags) 746 return -EINVAL; 747 r = amdgpu_ctx_query2(adev, fpriv, id, &args->out); 748 break; 749 case AMDGPU_CTX_OP_GET_STABLE_PSTATE: 750 if (args->in.flags) 751 return -EINVAL; 752 r = amdgpu_ctx_stable_pstate(adev, fpriv, id, false, &stable_pstate); 753 if (!r) 754 args->out.pstate.flags = stable_pstate; 755 break; 756 case AMDGPU_CTX_OP_SET_STABLE_PSTATE: 757 if (args->in.flags & ~AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK) 758 return -EINVAL; 759 stable_pstate = args->in.flags & AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK; 760 if (stable_pstate > AMDGPU_CTX_STABLE_PSTATE_PEAK) 761 return -EINVAL; 762 r = amdgpu_ctx_stable_pstate(adev, fpriv, id, true, &stable_pstate); 763 break; 764 default: 765 return -EINVAL; 766 } 767 768 return r; 769 } 770 771 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id) 772 { 773 struct amdgpu_ctx *ctx; 774 struct amdgpu_ctx_mgr *mgr; 775 776 if (!fpriv) 777 return NULL; 778 779 mgr = &fpriv->ctx_mgr; 780 781 mutex_lock(&mgr->lock); 782 ctx = idr_find(&mgr->ctx_handles, id); 783 if (ctx) 784 kref_get(&ctx->refcount); 785 mutex_unlock(&mgr->lock); 786 return ctx; 787 } 788 789 int amdgpu_ctx_put(struct amdgpu_ctx *ctx) 790 { 791 if (ctx == NULL) 792 return -EINVAL; 793 794 kref_put(&ctx->refcount, amdgpu_ctx_do_release); 795 return 0; 796 } 797 798 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, 799 struct drm_sched_entity *entity, 800 struct dma_fence *fence) 801 { 802 struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity); 803 uint64_t seq = centity->sequence; 804 struct dma_fence *other = NULL; 805 unsigned idx = 0; 806 807 idx = seq & (amdgpu_sched_jobs - 1); 808 other = centity->fences[idx]; 809 WARN_ON(other && !dma_fence_is_signaled(other)); 810 811 dma_fence_get(fence); 812 813 spin_lock(&ctx->ring_lock); 814 centity->fences[idx] = fence; 815 centity->sequence++; 816 spin_unlock(&ctx->ring_lock); 817 818 atomic64_add(ktime_to_ns(amdgpu_ctx_fence_time(other)), 819 &ctx->mgr->time_spend[centity->hw_ip]); 820 821 dma_fence_put(other); 822 return seq; 823 } 824 825 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 826 struct drm_sched_entity *entity, 827 uint64_t seq) 828 { 829 struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity); 830 struct dma_fence *fence; 831 832 spin_lock(&ctx->ring_lock); 833 834 if (seq == ~0ull) 835 seq = centity->sequence - 1; 836 837 if (seq >= centity->sequence) { 838 spin_unlock(&ctx->ring_lock); 839 return ERR_PTR(-EINVAL); 840 } 841 842 843 if (seq + amdgpu_sched_jobs < centity->sequence) { 844 spin_unlock(&ctx->ring_lock); 845 return NULL; 846 } 847 848 fence = dma_fence_get(centity->fences[seq & (amdgpu_sched_jobs - 1)]); 849 spin_unlock(&ctx->ring_lock); 850 851 return fence; 852 } 853 854 static void amdgpu_ctx_set_entity_priority(struct amdgpu_ctx *ctx, 855 struct amdgpu_ctx_entity *aentity, 856 int hw_ip, 857 int32_t priority) 858 { 859 struct amdgpu_device *adev = ctx->mgr->adev; 860 unsigned int hw_prio; 861 struct drm_gpu_scheduler **scheds = NULL; 862 unsigned num_scheds; 863 864 /* set sw priority */ 865 drm_sched_entity_set_priority(&aentity->entity, 866 amdgpu_ctx_to_drm_sched_prio(priority)); 867 868 /* set hw priority */ 869 if (hw_ip == AMDGPU_HW_IP_COMPUTE || hw_ip == AMDGPU_HW_IP_GFX) { 870 hw_prio = amdgpu_ctx_get_hw_prio(ctx, hw_ip); 871 hw_prio = array_index_nospec(hw_prio, AMDGPU_RING_PRIO_MAX); 872 scheds = adev->gpu_sched[hw_ip][hw_prio].sched; 873 num_scheds = adev->gpu_sched[hw_ip][hw_prio].num_scheds; 874 drm_sched_entity_modify_sched(&aentity->entity, scheds, 875 num_scheds); 876 } 877 } 878 879 void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx, 880 int32_t priority) 881 { 882 int32_t ctx_prio; 883 unsigned i, j; 884 885 ctx->override_priority = priority; 886 887 ctx_prio = (ctx->override_priority == AMDGPU_CTX_PRIORITY_UNSET) ? 888 ctx->init_priority : ctx->override_priority; 889 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 890 for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) { 891 if (!ctx->entities[i][j]) 892 continue; 893 894 amdgpu_ctx_set_entity_priority(ctx, ctx->entities[i][j], 895 i, ctx_prio); 896 } 897 } 898 } 899 900 int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, 901 struct drm_sched_entity *entity) 902 { 903 struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity); 904 struct dma_fence *other; 905 unsigned idx; 906 long r; 907 908 spin_lock(&ctx->ring_lock); 909 idx = centity->sequence & (amdgpu_sched_jobs - 1); 910 other = dma_fence_get(centity->fences[idx]); 911 spin_unlock(&ctx->ring_lock); 912 913 if (!other) 914 return 0; 915 916 r = dma_fence_wait(other, true); 917 if (r < 0 && r != -ERESTARTSYS) 918 drm_err(adev_to_drm(ctx->mgr->adev), 919 "AMDGPU: Error waiting for fence in ctx %p\n", ctx); 920 921 dma_fence_put(other); 922 return r; 923 } 924 925 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr, 926 struct amdgpu_device *adev) 927 { 928 unsigned int i; 929 930 mgr->adev = adev; 931 mutex_init(&mgr->lock); 932 idr_init_base(&mgr->ctx_handles, 1); 933 934 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) 935 atomic64_set(&mgr->time_spend[i], 0); 936 } 937 938 long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout) 939 { 940 struct amdgpu_ctx *ctx; 941 struct idr *idp; 942 uint32_t id, i, j; 943 944 idp = &mgr->ctx_handles; 945 946 mutex_lock(&mgr->lock); 947 idr_for_each_entry(idp, ctx, id) { 948 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 949 for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) { 950 struct drm_sched_entity *entity; 951 952 if (!ctx->entities[i][j]) 953 continue; 954 955 entity = &ctx->entities[i][j]->entity; 956 timeout = drm_sched_entity_flush(entity, timeout); 957 } 958 } 959 } 960 mutex_unlock(&mgr->lock); 961 return timeout; 962 } 963 964 static void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr) 965 { 966 struct amdgpu_ctx *ctx; 967 struct idr *idp; 968 uint32_t id, i, j; 969 970 idp = &mgr->ctx_handles; 971 972 idr_for_each_entry(idp, ctx, id) { 973 if (kref_read(&ctx->refcount) != 1) { 974 drm_err(adev_to_drm(mgr->adev), "ctx %p is still alive\n", ctx); 975 continue; 976 } 977 978 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 979 for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) { 980 struct drm_sched_entity *entity; 981 982 if (!ctx->entities[i][j]) 983 continue; 984 985 entity = &ctx->entities[i][j]->entity; 986 drm_sched_entity_fini(entity); 987 } 988 } 989 kref_put(&ctx->refcount, amdgpu_ctx_fini); 990 } 991 } 992 993 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr) 994 { 995 amdgpu_ctx_mgr_entity_fini(mgr); 996 idr_destroy(&mgr->ctx_handles); 997 mutex_destroy(&mgr->lock); 998 } 999 1000 void amdgpu_ctx_mgr_usage(struct amdgpu_ctx_mgr *mgr, 1001 ktime_t usage[AMDGPU_HW_IP_NUM]) 1002 { 1003 struct amdgpu_ctx *ctx; 1004 unsigned int hw_ip, i; 1005 uint32_t id; 1006 1007 /* 1008 * This is a little bit racy because it can be that a ctx or a fence are 1009 * destroyed just in the moment we try to account them. But that is ok 1010 * since exactly that case is explicitely allowed by the interface. 1011 */ 1012 mutex_lock(&mgr->lock); 1013 for (hw_ip = 0; hw_ip < AMDGPU_HW_IP_NUM; ++hw_ip) { 1014 uint64_t ns = atomic64_read(&mgr->time_spend[hw_ip]); 1015 1016 usage[hw_ip] = ns_to_ktime(ns); 1017 } 1018 1019 idr_for_each_entry(&mgr->ctx_handles, ctx, id) { 1020 for (hw_ip = 0; hw_ip < AMDGPU_HW_IP_NUM; ++hw_ip) { 1021 for (i = 0; i < amdgpu_ctx_num_entities[hw_ip]; ++i) { 1022 struct amdgpu_ctx_entity *centity; 1023 ktime_t spend; 1024 1025 centity = ctx->entities[hw_ip][i]; 1026 if (!centity) 1027 continue; 1028 spend = amdgpu_ctx_entity_time(ctx, centity); 1029 usage[hw_ip] = ktime_add(usage[hw_ip], spend); 1030 } 1031 } 1032 } 1033 mutex_unlock(&mgr->lock); 1034 } 1035