1 /* 2 * Copyright 2008 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Jerome Glisse <glisse@freedesktop.org> 26 */ 27 #include <linux/list_sort.h> 28 #include <drm/drmP.h> 29 #include <drm/amdgpu_drm.h> 30 #include "amdgpu.h" 31 #include "amdgpu_trace.h" 32 33 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 34 u32 ip_instance, u32 ring, 35 struct amdgpu_ring **out_ring) 36 { 37 /* Right now all IPs have only one instance - multiple rings. */ 38 if (ip_instance != 0) { 39 DRM_ERROR("invalid ip instance: %d\n", ip_instance); 40 return -EINVAL; 41 } 42 43 switch (ip_type) { 44 default: 45 DRM_ERROR("unknown ip type: %d\n", ip_type); 46 return -EINVAL; 47 case AMDGPU_HW_IP_GFX: 48 if (ring < adev->gfx.num_gfx_rings) { 49 *out_ring = &adev->gfx.gfx_ring[ring]; 50 } else { 51 DRM_ERROR("only %d gfx rings are supported now\n", 52 adev->gfx.num_gfx_rings); 53 return -EINVAL; 54 } 55 break; 56 case AMDGPU_HW_IP_COMPUTE: 57 if (ring < adev->gfx.num_compute_rings) { 58 *out_ring = &adev->gfx.compute_ring[ring]; 59 } else { 60 DRM_ERROR("only %d compute rings are supported now\n", 61 adev->gfx.num_compute_rings); 62 return -EINVAL; 63 } 64 break; 65 case AMDGPU_HW_IP_DMA: 66 if (ring < adev->sdma.num_instances) { 67 *out_ring = &adev->sdma.instance[ring].ring; 68 } else { 69 DRM_ERROR("only %d SDMA rings are supported\n", 70 adev->sdma.num_instances); 71 return -EINVAL; 72 } 73 break; 74 case AMDGPU_HW_IP_UVD: 75 *out_ring = &adev->uvd.ring; 76 break; 77 case AMDGPU_HW_IP_VCE: 78 if (ring < 2){ 79 *out_ring = &adev->vce.ring[ring]; 80 } else { 81 DRM_ERROR("only two VCE rings are supported\n"); 82 return -EINVAL; 83 } 84 break; 85 } 86 return 0; 87 } 88 89 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p, 90 struct drm_amdgpu_cs_chunk_fence *fence_data) 91 { 92 struct drm_gem_object *gobj; 93 uint32_t handle; 94 95 handle = fence_data->handle; 96 gobj = drm_gem_object_lookup(p->adev->ddev, p->filp, 97 fence_data->handle); 98 if (gobj == NULL) 99 return -EINVAL; 100 101 p->uf.bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj)); 102 p->uf.offset = fence_data->offset; 103 104 if (amdgpu_ttm_tt_has_userptr(p->uf.bo->tbo.ttm)) { 105 drm_gem_object_unreference_unlocked(gobj); 106 return -EINVAL; 107 } 108 109 p->uf_entry.robj = amdgpu_bo_ref(p->uf.bo); 110 p->uf_entry.priority = 0; 111 p->uf_entry.tv.bo = &p->uf_entry.robj->tbo; 112 p->uf_entry.tv.shared = true; 113 114 drm_gem_object_unreference_unlocked(gobj); 115 return 0; 116 } 117 118 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) 119 { 120 union drm_amdgpu_cs *cs = data; 121 uint64_t *chunk_array_user; 122 uint64_t *chunk_array; 123 struct amdgpu_fpriv *fpriv = p->filp->driver_priv; 124 unsigned size; 125 int i; 126 int ret; 127 128 if (cs->in.num_chunks == 0) 129 return 0; 130 131 chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL); 132 if (!chunk_array) 133 return -ENOMEM; 134 135 p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id); 136 if (!p->ctx) { 137 ret = -EINVAL; 138 goto free_chunk; 139 } 140 141 /* get chunks */ 142 chunk_array_user = (uint64_t __user *)(unsigned long)(cs->in.chunks); 143 if (copy_from_user(chunk_array, chunk_array_user, 144 sizeof(uint64_t)*cs->in.num_chunks)) { 145 ret = -EFAULT; 146 goto put_ctx; 147 } 148 149 p->nchunks = cs->in.num_chunks; 150 p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk), 151 GFP_KERNEL); 152 if (!p->chunks) { 153 ret = -ENOMEM; 154 goto put_ctx; 155 } 156 157 for (i = 0; i < p->nchunks; i++) { 158 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL; 159 struct drm_amdgpu_cs_chunk user_chunk; 160 uint32_t __user *cdata; 161 162 chunk_ptr = (void __user *)(unsigned long)chunk_array[i]; 163 if (copy_from_user(&user_chunk, chunk_ptr, 164 sizeof(struct drm_amdgpu_cs_chunk))) { 165 ret = -EFAULT; 166 i--; 167 goto free_partial_kdata; 168 } 169 p->chunks[i].chunk_id = user_chunk.chunk_id; 170 p->chunks[i].length_dw = user_chunk.length_dw; 171 172 size = p->chunks[i].length_dw; 173 cdata = (void __user *)(unsigned long)user_chunk.chunk_data; 174 175 p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t)); 176 if (p->chunks[i].kdata == NULL) { 177 ret = -ENOMEM; 178 i--; 179 goto free_partial_kdata; 180 } 181 size *= sizeof(uint32_t); 182 if (copy_from_user(p->chunks[i].kdata, cdata, size)) { 183 ret = -EFAULT; 184 goto free_partial_kdata; 185 } 186 187 switch (p->chunks[i].chunk_id) { 188 case AMDGPU_CHUNK_ID_IB: 189 p->num_ibs++; 190 break; 191 192 case AMDGPU_CHUNK_ID_FENCE: 193 size = sizeof(struct drm_amdgpu_cs_chunk_fence); 194 if (p->chunks[i].length_dw * sizeof(uint32_t) < size) { 195 ret = -EINVAL; 196 goto free_partial_kdata; 197 } 198 199 ret = amdgpu_cs_user_fence_chunk(p, (void *)p->chunks[i].kdata); 200 if (ret) 201 goto free_partial_kdata; 202 203 break; 204 205 case AMDGPU_CHUNK_ID_DEPENDENCIES: 206 break; 207 208 default: 209 ret = -EINVAL; 210 goto free_partial_kdata; 211 } 212 } 213 214 215 p->ibs = kcalloc(p->num_ibs, sizeof(struct amdgpu_ib), GFP_KERNEL); 216 if (!p->ibs) { 217 ret = -ENOMEM; 218 goto free_all_kdata; 219 } 220 221 kfree(chunk_array); 222 return 0; 223 224 free_all_kdata: 225 i = p->nchunks - 1; 226 free_partial_kdata: 227 for (; i >= 0; i--) 228 drm_free_large(p->chunks[i].kdata); 229 kfree(p->chunks); 230 put_ctx: 231 amdgpu_ctx_put(p->ctx); 232 free_chunk: 233 kfree(chunk_array); 234 235 return ret; 236 } 237 238 /* Returns how many bytes TTM can move per IB. 239 */ 240 static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev) 241 { 242 u64 real_vram_size = adev->mc.real_vram_size; 243 u64 vram_usage = atomic64_read(&adev->vram_usage); 244 245 /* This function is based on the current VRAM usage. 246 * 247 * - If all of VRAM is free, allow relocating the number of bytes that 248 * is equal to 1/4 of the size of VRAM for this IB. 249 250 * - If more than one half of VRAM is occupied, only allow relocating 251 * 1 MB of data for this IB. 252 * 253 * - From 0 to one half of used VRAM, the threshold decreases 254 * linearly. 255 * __________________ 256 * 1/4 of -|\ | 257 * VRAM | \ | 258 * | \ | 259 * | \ | 260 * | \ | 261 * | \ | 262 * | \ | 263 * | \________|1 MB 264 * |----------------| 265 * VRAM 0 % 100 % 266 * used used 267 * 268 * Note: It's a threshold, not a limit. The threshold must be crossed 269 * for buffer relocations to stop, so any buffer of an arbitrary size 270 * can be moved as long as the threshold isn't crossed before 271 * the relocation takes place. We don't want to disable buffer 272 * relocations completely. 273 * 274 * The idea is that buffers should be placed in VRAM at creation time 275 * and TTM should only do a minimum number of relocations during 276 * command submission. In practice, you need to submit at least 277 * a dozen IBs to move all buffers to VRAM if they are in GTT. 278 * 279 * Also, things can get pretty crazy under memory pressure and actual 280 * VRAM usage can change a lot, so playing safe even at 50% does 281 * consistently increase performance. 282 */ 283 284 u64 half_vram = real_vram_size >> 1; 285 u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage; 286 u64 bytes_moved_threshold = half_free_vram >> 1; 287 return max(bytes_moved_threshold, 1024*1024ull); 288 } 289 290 int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p, 291 struct list_head *validated) 292 { 293 struct amdgpu_bo_list_entry *lobj; 294 u64 initial_bytes_moved; 295 int r; 296 297 list_for_each_entry(lobj, validated, tv.head) { 298 struct amdgpu_bo *bo = lobj->robj; 299 uint32_t domain; 300 301 if (bo->pin_count) 302 continue; 303 304 /* Avoid moving this one if we have moved too many buffers 305 * for this IB already. 306 * 307 * Note that this allows moving at least one buffer of 308 * any size, because it doesn't take the current "bo" 309 * into account. We don't want to disallow buffer moves 310 * completely. 311 */ 312 if (p->bytes_moved <= p->bytes_moved_threshold) 313 domain = bo->prefered_domains; 314 else 315 domain = bo->allowed_domains; 316 317 retry: 318 amdgpu_ttm_placement_from_domain(bo, domain); 319 initial_bytes_moved = atomic64_read(&bo->adev->num_bytes_moved); 320 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); 321 p->bytes_moved += atomic64_read(&bo->adev->num_bytes_moved) - 322 initial_bytes_moved; 323 324 if (unlikely(r)) { 325 if (r != -ERESTARTSYS && domain != bo->allowed_domains) { 326 domain = bo->allowed_domains; 327 goto retry; 328 } 329 return r; 330 } 331 } 332 return 0; 333 } 334 335 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, 336 union drm_amdgpu_cs *cs) 337 { 338 struct amdgpu_fpriv *fpriv = p->filp->driver_priv; 339 struct list_head duplicates; 340 bool need_mmap_lock = false; 341 int r; 342 343 INIT_LIST_HEAD(&p->validated); 344 345 p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle); 346 if (p->bo_list) { 347 need_mmap_lock = p->bo_list->has_userptr; 348 amdgpu_bo_list_get_list(p->bo_list, &p->validated); 349 } 350 351 INIT_LIST_HEAD(&duplicates); 352 amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd); 353 354 if (p->uf.bo) 355 list_add(&p->uf_entry.tv.head, &p->validated); 356 357 if (need_mmap_lock) 358 down_read(¤t->mm->mmap_sem); 359 360 r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, &duplicates); 361 if (unlikely(r != 0)) 362 goto error_reserve; 363 364 amdgpu_vm_get_pt_bos(&fpriv->vm, &duplicates); 365 366 p->bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(p->adev); 367 p->bytes_moved = 0; 368 369 r = amdgpu_cs_list_validate(p, &duplicates); 370 if (r) 371 goto error_validate; 372 373 r = amdgpu_cs_list_validate(p, &p->validated); 374 if (r) 375 goto error_validate; 376 377 if (p->bo_list) { 378 struct amdgpu_vm *vm = &fpriv->vm; 379 unsigned i; 380 381 for (i = 0; i < p->bo_list->num_entries; i++) { 382 struct amdgpu_bo *bo = p->bo_list->array[i].robj; 383 384 p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo); 385 } 386 } 387 388 error_validate: 389 if (r) { 390 amdgpu_vm_move_pt_bos_in_lru(p->adev, &fpriv->vm); 391 ttm_eu_backoff_reservation(&p->ticket, &p->validated); 392 } 393 394 error_reserve: 395 if (need_mmap_lock) 396 up_read(¤t->mm->mmap_sem); 397 398 return r; 399 } 400 401 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p) 402 { 403 struct amdgpu_bo_list_entry *e; 404 int r; 405 406 list_for_each_entry(e, &p->validated, tv.head) { 407 struct reservation_object *resv = e->robj->tbo.resv; 408 r = amdgpu_sync_resv(p->adev, &p->ibs[0].sync, resv, p->filp); 409 410 if (r) 411 return r; 412 } 413 return 0; 414 } 415 416 static int cmp_size_smaller_first(void *priv, struct list_head *a, 417 struct list_head *b) 418 { 419 struct amdgpu_bo_list_entry *la = list_entry(a, struct amdgpu_bo_list_entry, tv.head); 420 struct amdgpu_bo_list_entry *lb = list_entry(b, struct amdgpu_bo_list_entry, tv.head); 421 422 /* Sort A before B if A is smaller. */ 423 return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages; 424 } 425 426 /** 427 * cs_parser_fini() - clean parser states 428 * @parser: parser structure holding parsing context. 429 * @error: error number 430 * 431 * If error is set than unvalidate buffer, otherwise just free memory 432 * used by parsing context. 433 **/ 434 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff) 435 { 436 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; 437 unsigned i; 438 439 if (!error) { 440 amdgpu_vm_move_pt_bos_in_lru(parser->adev, &fpriv->vm); 441 442 /* Sort the buffer list from the smallest to largest buffer, 443 * which affects the order of buffers in the LRU list. 444 * This assures that the smallest buffers are added first 445 * to the LRU list, so they are likely to be later evicted 446 * first, instead of large buffers whose eviction is more 447 * expensive. 448 * 449 * This slightly lowers the number of bytes moved by TTM 450 * per frame under memory pressure. 451 */ 452 list_sort(NULL, &parser->validated, cmp_size_smaller_first); 453 454 ttm_eu_fence_buffer_objects(&parser->ticket, 455 &parser->validated, 456 parser->fence); 457 } else if (backoff) { 458 ttm_eu_backoff_reservation(&parser->ticket, 459 &parser->validated); 460 } 461 fence_put(parser->fence); 462 463 if (parser->ctx) 464 amdgpu_ctx_put(parser->ctx); 465 if (parser->bo_list) 466 amdgpu_bo_list_put(parser->bo_list); 467 468 for (i = 0; i < parser->nchunks; i++) 469 drm_free_large(parser->chunks[i].kdata); 470 kfree(parser->chunks); 471 if (parser->ibs) 472 for (i = 0; i < parser->num_ibs; i++) 473 amdgpu_ib_free(parser->adev, &parser->ibs[i]); 474 kfree(parser->ibs); 475 amdgpu_bo_unref(&parser->uf.bo); 476 amdgpu_bo_unref(&parser->uf_entry.robj); 477 } 478 479 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p, 480 struct amdgpu_vm *vm) 481 { 482 struct amdgpu_device *adev = p->adev; 483 struct amdgpu_bo_va *bo_va; 484 struct amdgpu_bo *bo; 485 int i, r; 486 487 r = amdgpu_vm_update_page_directory(adev, vm); 488 if (r) 489 return r; 490 491 r = amdgpu_sync_fence(adev, &p->ibs[0].sync, vm->page_directory_fence); 492 if (r) 493 return r; 494 495 r = amdgpu_vm_clear_freed(adev, vm); 496 if (r) 497 return r; 498 499 if (p->bo_list) { 500 for (i = 0; i < p->bo_list->num_entries; i++) { 501 struct fence *f; 502 503 /* ignore duplicates */ 504 bo = p->bo_list->array[i].robj; 505 if (!bo) 506 continue; 507 508 bo_va = p->bo_list->array[i].bo_va; 509 if (bo_va == NULL) 510 continue; 511 512 r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem); 513 if (r) 514 return r; 515 516 f = bo_va->last_pt_update; 517 r = amdgpu_sync_fence(adev, &p->ibs[0].sync, f); 518 if (r) 519 return r; 520 } 521 522 } 523 524 r = amdgpu_vm_clear_invalids(adev, vm, &p->ibs[0].sync); 525 526 if (amdgpu_vm_debug && p->bo_list) { 527 /* Invalidate all BOs to test for userspace bugs */ 528 for (i = 0; i < p->bo_list->num_entries; i++) { 529 /* ignore duplicates */ 530 bo = p->bo_list->array[i].robj; 531 if (!bo) 532 continue; 533 534 amdgpu_vm_bo_invalidate(adev, bo); 535 } 536 } 537 538 return r; 539 } 540 541 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, 542 struct amdgpu_cs_parser *parser) 543 { 544 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; 545 struct amdgpu_vm *vm = &fpriv->vm; 546 struct amdgpu_ring *ring; 547 int i, r; 548 549 if (parser->num_ibs == 0) 550 return 0; 551 552 /* Only for UVD/VCE VM emulation */ 553 for (i = 0; i < parser->num_ibs; i++) { 554 ring = parser->ibs[i].ring; 555 if (ring->funcs->parse_cs) { 556 r = amdgpu_ring_parse_cs(ring, parser, i); 557 if (r) 558 return r; 559 } 560 } 561 562 r = amdgpu_bo_vm_update_pte(parser, vm); 563 if (!r) 564 amdgpu_cs_sync_rings(parser); 565 566 return r; 567 } 568 569 static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r) 570 { 571 if (r == -EDEADLK) { 572 r = amdgpu_gpu_reset(adev); 573 if (!r) 574 r = -EAGAIN; 575 } 576 return r; 577 } 578 579 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, 580 struct amdgpu_cs_parser *parser) 581 { 582 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; 583 struct amdgpu_vm *vm = &fpriv->vm; 584 int i, j; 585 int r; 586 587 for (i = 0, j = 0; i < parser->nchunks && j < parser->num_ibs; i++) { 588 struct amdgpu_cs_chunk *chunk; 589 struct amdgpu_ib *ib; 590 struct drm_amdgpu_cs_chunk_ib *chunk_ib; 591 struct amdgpu_ring *ring; 592 593 chunk = &parser->chunks[i]; 594 ib = &parser->ibs[j]; 595 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata; 596 597 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB) 598 continue; 599 600 r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type, 601 chunk_ib->ip_instance, chunk_ib->ring, 602 &ring); 603 if (r) 604 return r; 605 606 if (ring->funcs->parse_cs) { 607 struct amdgpu_bo_va_mapping *m; 608 struct amdgpu_bo *aobj = NULL; 609 uint64_t offset; 610 uint8_t *kptr; 611 612 m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start, 613 &aobj); 614 if (!aobj) { 615 DRM_ERROR("IB va_start is invalid\n"); 616 return -EINVAL; 617 } 618 619 if ((chunk_ib->va_start + chunk_ib->ib_bytes) > 620 (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) { 621 DRM_ERROR("IB va_start+ib_bytes is invalid\n"); 622 return -EINVAL; 623 } 624 625 /* the IB should be reserved at this point */ 626 r = amdgpu_bo_kmap(aobj, (void **)&kptr); 627 if (r) { 628 return r; 629 } 630 631 offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE; 632 kptr += chunk_ib->va_start - offset; 633 634 r = amdgpu_ib_get(ring, NULL, chunk_ib->ib_bytes, ib); 635 if (r) { 636 DRM_ERROR("Failed to get ib !\n"); 637 return r; 638 } 639 640 memcpy(ib->ptr, kptr, chunk_ib->ib_bytes); 641 amdgpu_bo_kunmap(aobj); 642 } else { 643 r = amdgpu_ib_get(ring, vm, 0, ib); 644 if (r) { 645 DRM_ERROR("Failed to get ib !\n"); 646 return r; 647 } 648 649 ib->gpu_addr = chunk_ib->va_start; 650 } 651 652 ib->length_dw = chunk_ib->ib_bytes / 4; 653 ib->flags = chunk_ib->flags; 654 ib->ctx = parser->ctx; 655 j++; 656 } 657 658 if (!parser->num_ibs) 659 return 0; 660 661 /* add GDS resources to first IB */ 662 if (parser->bo_list) { 663 struct amdgpu_bo *gds = parser->bo_list->gds_obj; 664 struct amdgpu_bo *gws = parser->bo_list->gws_obj; 665 struct amdgpu_bo *oa = parser->bo_list->oa_obj; 666 struct amdgpu_ib *ib = &parser->ibs[0]; 667 668 if (gds) { 669 ib->gds_base = amdgpu_bo_gpu_offset(gds); 670 ib->gds_size = amdgpu_bo_size(gds); 671 } 672 if (gws) { 673 ib->gws_base = amdgpu_bo_gpu_offset(gws); 674 ib->gws_size = amdgpu_bo_size(gws); 675 } 676 if (oa) { 677 ib->oa_base = amdgpu_bo_gpu_offset(oa); 678 ib->oa_size = amdgpu_bo_size(oa); 679 } 680 } 681 /* wrap the last IB with user fence */ 682 if (parser->uf.bo) { 683 struct amdgpu_ib *ib = &parser->ibs[parser->num_ibs - 1]; 684 685 /* UVD & VCE fw doesn't support user fences */ 686 if (ib->ring->type == AMDGPU_RING_TYPE_UVD || 687 ib->ring->type == AMDGPU_RING_TYPE_VCE) 688 return -EINVAL; 689 690 ib->user = &parser->uf; 691 } 692 693 return 0; 694 } 695 696 static int amdgpu_cs_dependencies(struct amdgpu_device *adev, 697 struct amdgpu_cs_parser *p) 698 { 699 struct amdgpu_fpriv *fpriv = p->filp->driver_priv; 700 struct amdgpu_ib *ib; 701 int i, j, r; 702 703 if (!p->num_ibs) 704 return 0; 705 706 /* Add dependencies to first IB */ 707 ib = &p->ibs[0]; 708 for (i = 0; i < p->nchunks; ++i) { 709 struct drm_amdgpu_cs_chunk_dep *deps; 710 struct amdgpu_cs_chunk *chunk; 711 unsigned num_deps; 712 713 chunk = &p->chunks[i]; 714 715 if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES) 716 continue; 717 718 deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata; 719 num_deps = chunk->length_dw * 4 / 720 sizeof(struct drm_amdgpu_cs_chunk_dep); 721 722 for (j = 0; j < num_deps; ++j) { 723 struct amdgpu_ring *ring; 724 struct amdgpu_ctx *ctx; 725 struct fence *fence; 726 727 r = amdgpu_cs_get_ring(adev, deps[j].ip_type, 728 deps[j].ip_instance, 729 deps[j].ring, &ring); 730 if (r) 731 return r; 732 733 ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id); 734 if (ctx == NULL) 735 return -EINVAL; 736 737 fence = amdgpu_ctx_get_fence(ctx, ring, 738 deps[j].handle); 739 if (IS_ERR(fence)) { 740 r = PTR_ERR(fence); 741 amdgpu_ctx_put(ctx); 742 return r; 743 744 } else if (fence) { 745 r = amdgpu_sync_fence(adev, &ib->sync, fence); 746 fence_put(fence); 747 amdgpu_ctx_put(ctx); 748 if (r) 749 return r; 750 } 751 } 752 } 753 754 return 0; 755 } 756 757 static int amdgpu_cs_free_job(struct amdgpu_job *job) 758 { 759 int i; 760 if (job->ibs) 761 for (i = 0; i < job->num_ibs; i++) 762 amdgpu_ib_free(job->adev, &job->ibs[i]); 763 kfree(job->ibs); 764 if (job->uf.bo) 765 amdgpu_bo_unref(&job->uf.bo); 766 return 0; 767 } 768 769 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 770 { 771 struct amdgpu_device *adev = dev->dev_private; 772 union drm_amdgpu_cs *cs = data; 773 struct amdgpu_cs_parser parser = {}; 774 bool reserved_buffers = false; 775 int i, r; 776 777 if (!adev->accel_working) 778 return -EBUSY; 779 780 parser.adev = adev; 781 parser.filp = filp; 782 783 r = amdgpu_cs_parser_init(&parser, data); 784 if (r) { 785 DRM_ERROR("Failed to initialize parser !\n"); 786 amdgpu_cs_parser_fini(&parser, r, false); 787 r = amdgpu_cs_handle_lockup(adev, r); 788 return r; 789 } 790 r = amdgpu_cs_parser_bos(&parser, data); 791 if (r == -ENOMEM) 792 DRM_ERROR("Not enough memory for command submission!\n"); 793 else if (r && r != -ERESTARTSYS) 794 DRM_ERROR("Failed to process the buffer list %d!\n", r); 795 else if (!r) { 796 reserved_buffers = true; 797 r = amdgpu_cs_ib_fill(adev, &parser); 798 } 799 800 if (!r) { 801 r = amdgpu_cs_dependencies(adev, &parser); 802 if (r) 803 DRM_ERROR("Failed in the dependencies handling %d!\n", r); 804 } 805 806 if (r) 807 goto out; 808 809 for (i = 0; i < parser.num_ibs; i++) 810 trace_amdgpu_cs(&parser, i); 811 812 r = amdgpu_cs_ib_vm_chunk(adev, &parser); 813 if (r) 814 goto out; 815 816 if (parser.num_ibs) { 817 struct amdgpu_ring * ring = parser.ibs->ring; 818 struct amd_sched_fence *fence; 819 struct amdgpu_job *job; 820 821 job = kzalloc(sizeof(struct amdgpu_job), GFP_KERNEL); 822 if (!job) { 823 r = -ENOMEM; 824 goto out; 825 } 826 827 job->base.sched = &ring->sched; 828 job->base.s_entity = &parser.ctx->rings[ring->idx].entity; 829 job->adev = parser.adev; 830 job->owner = parser.filp; 831 job->free_job = amdgpu_cs_free_job; 832 833 job->ibs = parser.ibs; 834 job->num_ibs = parser.num_ibs; 835 parser.ibs = NULL; 836 parser.num_ibs = 0; 837 838 if (job->ibs[job->num_ibs - 1].user) { 839 job->uf = parser.uf; 840 job->ibs[job->num_ibs - 1].user = &job->uf; 841 parser.uf.bo = NULL; 842 } 843 844 fence = amd_sched_fence_create(job->base.s_entity, 845 parser.filp); 846 if (!fence) { 847 r = -ENOMEM; 848 amdgpu_cs_free_job(job); 849 kfree(job); 850 goto out; 851 } 852 job->base.s_fence = fence; 853 parser.fence = fence_get(&fence->base); 854 855 cs->out.handle = amdgpu_ctx_add_fence(parser.ctx, ring, 856 &fence->base); 857 job->ibs[job->num_ibs - 1].sequence = cs->out.handle; 858 859 trace_amdgpu_cs_ioctl(job); 860 amd_sched_entity_push_job(&job->base); 861 } 862 863 out: 864 amdgpu_cs_parser_fini(&parser, r, reserved_buffers); 865 r = amdgpu_cs_handle_lockup(adev, r); 866 return r; 867 } 868 869 /** 870 * amdgpu_cs_wait_ioctl - wait for a command submission to finish 871 * 872 * @dev: drm device 873 * @data: data from userspace 874 * @filp: file private 875 * 876 * Wait for the command submission identified by handle to finish. 877 */ 878 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, 879 struct drm_file *filp) 880 { 881 union drm_amdgpu_wait_cs *wait = data; 882 struct amdgpu_device *adev = dev->dev_private; 883 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout); 884 struct amdgpu_ring *ring = NULL; 885 struct amdgpu_ctx *ctx; 886 struct fence *fence; 887 long r; 888 889 r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance, 890 wait->in.ring, &ring); 891 if (r) 892 return r; 893 894 ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id); 895 if (ctx == NULL) 896 return -EINVAL; 897 898 fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle); 899 if (IS_ERR(fence)) 900 r = PTR_ERR(fence); 901 else if (fence) { 902 r = fence_wait_timeout(fence, true, timeout); 903 fence_put(fence); 904 } else 905 r = 1; 906 907 amdgpu_ctx_put(ctx); 908 if (r < 0) 909 return r; 910 911 memset(wait, 0, sizeof(*wait)); 912 wait->out.status = (r == 0); 913 914 return 0; 915 } 916 917 /** 918 * amdgpu_cs_find_bo_va - find bo_va for VM address 919 * 920 * @parser: command submission parser context 921 * @addr: VM address 922 * @bo: resulting BO of the mapping found 923 * 924 * Search the buffer objects in the command submission context for a certain 925 * virtual memory address. Returns allocation structure when found, NULL 926 * otherwise. 927 */ 928 struct amdgpu_bo_va_mapping * 929 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 930 uint64_t addr, struct amdgpu_bo **bo) 931 { 932 struct amdgpu_bo_va_mapping *mapping; 933 unsigned i; 934 935 if (!parser->bo_list) 936 return NULL; 937 938 addr /= AMDGPU_GPU_PAGE_SIZE; 939 940 for (i = 0; i < parser->bo_list->num_entries; i++) { 941 struct amdgpu_bo_list_entry *lobj; 942 943 lobj = &parser->bo_list->array[i]; 944 if (!lobj->bo_va) 945 continue; 946 947 list_for_each_entry(mapping, &lobj->bo_va->valids, list) { 948 if (mapping->it.start > addr || 949 addr > mapping->it.last) 950 continue; 951 952 *bo = lobj->bo_va->bo; 953 return mapping; 954 } 955 956 list_for_each_entry(mapping, &lobj->bo_va->invalids, list) { 957 if (mapping->it.start > addr || 958 addr > mapping->it.last) 959 continue; 960 961 *bo = lobj->bo_va->bo; 962 return mapping; 963 } 964 } 965 966 return NULL; 967 } 968