1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2025 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 #include <linux/list.h> 25 #include "amdgpu.h" 26 27 static const guid_t MCE = CPER_NOTIFY_MCE; 28 static const guid_t CMC = CPER_NOTIFY_CMC; 29 static const guid_t BOOT = BOOT_TYPE; 30 31 static const guid_t CRASHDUMP = AMD_CRASHDUMP; 32 static const guid_t RUNTIME = AMD_GPU_NONSTANDARD_ERROR; 33 34 static void __inc_entry_length(struct cper_hdr *hdr, uint32_t size) 35 { 36 hdr->record_length += size; 37 } 38 39 static void amdgpu_cper_get_timestamp(struct cper_timestamp *timestamp) 40 { 41 struct tm tm; 42 time64_t now = ktime_get_real_seconds(); 43 44 time64_to_tm(now, 0, &tm); 45 timestamp->seconds = tm.tm_sec; 46 timestamp->minutes = tm.tm_min; 47 timestamp->hours = tm.tm_hour; 48 timestamp->flag = 0; 49 timestamp->day = tm.tm_mday; 50 timestamp->month = 1 + tm.tm_mon; 51 timestamp->year = (1900 + tm.tm_year) % 100; 52 timestamp->century = (1900 + tm.tm_year) / 100; 53 } 54 55 void amdgpu_cper_entry_fill_hdr(struct amdgpu_device *adev, 56 struct cper_hdr *hdr, 57 enum amdgpu_cper_type type, 58 enum cper_error_severity sev) 59 { 60 char record_id[16]; 61 62 hdr->signature[0] = 'C'; 63 hdr->signature[1] = 'P'; 64 hdr->signature[2] = 'E'; 65 hdr->signature[3] = 'R'; 66 hdr->revision = CPER_HDR_REV_1; 67 hdr->signature_end = 0xFFFFFFFF; 68 hdr->error_severity = sev; 69 70 hdr->valid_bits.platform_id = 1; 71 hdr->valid_bits.partition_id = 1; 72 hdr->valid_bits.timestamp = 1; 73 74 amdgpu_cper_get_timestamp(&hdr->timestamp); 75 76 snprintf(record_id, 9, "%d:%X", 77 (adev->smuio.funcs && adev->smuio.funcs->get_socket_id) ? 78 adev->smuio.funcs->get_socket_id(adev) : 79 0, 80 atomic_inc_return(&adev->cper.unique_id)); 81 memcpy(hdr->record_id, record_id, 8); 82 83 snprintf(hdr->platform_id, 16, "0x%04X:0x%04X", 84 adev->pdev->vendor, adev->pdev->device); 85 /* pmfw version should be part of creator_id according to CPER spec */ 86 snprintf(hdr->creator_id, 16, "%s", CPER_CREATOR_ID_AMDGPU); 87 88 switch (type) { 89 case AMDGPU_CPER_TYPE_BOOT: 90 hdr->notify_type = BOOT; 91 break; 92 case AMDGPU_CPER_TYPE_FATAL: 93 case AMDGPU_CPER_TYPE_BP_THRESHOLD: 94 hdr->notify_type = MCE; 95 break; 96 case AMDGPU_CPER_TYPE_RUNTIME: 97 if (sev == CPER_SEV_NON_FATAL_CORRECTED) 98 hdr->notify_type = CMC; 99 else 100 hdr->notify_type = MCE; 101 break; 102 default: 103 dev_err(adev->dev, "Unknown CPER Type\n"); 104 break; 105 } 106 107 __inc_entry_length(hdr, HDR_LEN); 108 } 109 110 static int amdgpu_cper_entry_fill_section_desc(struct amdgpu_device *adev, 111 struct cper_sec_desc *section_desc, 112 bool bp_threshold, 113 bool poison, 114 enum cper_error_severity sev, 115 guid_t sec_type, 116 uint32_t section_length, 117 uint32_t section_offset) 118 { 119 section_desc->revision_minor = CPER_SEC_MINOR_REV_1; 120 section_desc->revision_major = CPER_SEC_MAJOR_REV_22; 121 section_desc->sec_offset = section_offset; 122 section_desc->sec_length = section_length; 123 section_desc->valid_bits.fru_text = 1; 124 section_desc->flag_bits.primary = 1; 125 section_desc->severity = sev; 126 section_desc->sec_type = sec_type; 127 128 snprintf(section_desc->fru_text, 20, "OAM%d", 129 (adev->smuio.funcs && adev->smuio.funcs->get_socket_id) ? 130 adev->smuio.funcs->get_socket_id(adev) : 131 0); 132 133 if (bp_threshold) 134 section_desc->flag_bits.exceed_err_threshold = 1; 135 if (poison) 136 section_desc->flag_bits.latent_err = 1; 137 138 return 0; 139 } 140 141 int amdgpu_cper_entry_fill_fatal_section(struct amdgpu_device *adev, 142 struct cper_hdr *hdr, 143 uint32_t idx, 144 struct cper_sec_crashdump_reg_data reg_data) 145 { 146 struct cper_sec_desc *section_desc; 147 struct cper_sec_crashdump_fatal *section; 148 149 section_desc = (struct cper_sec_desc *)((uint8_t *)hdr + SEC_DESC_OFFSET(idx)); 150 section = (struct cper_sec_crashdump_fatal *)((uint8_t *)hdr + 151 FATAL_SEC_OFFSET(hdr->sec_cnt, idx)); 152 153 amdgpu_cper_entry_fill_section_desc(adev, section_desc, false, false, 154 CPER_SEV_FATAL, CRASHDUMP, FATAL_SEC_LEN, 155 FATAL_SEC_OFFSET(hdr->sec_cnt, idx)); 156 157 section->body.reg_ctx_type = CPER_CTX_TYPE_CRASH; 158 section->body.reg_arr_size = sizeof(reg_data); 159 section->body.data = reg_data; 160 161 __inc_entry_length(hdr, SEC_DESC_LEN + FATAL_SEC_LEN); 162 163 return 0; 164 } 165 166 int amdgpu_cper_entry_fill_runtime_section(struct amdgpu_device *adev, 167 struct cper_hdr *hdr, 168 uint32_t idx, 169 enum cper_error_severity sev, 170 uint32_t *reg_dump, 171 uint32_t reg_count) 172 { 173 struct cper_sec_desc *section_desc; 174 struct cper_sec_nonstd_err *section; 175 bool poison; 176 177 poison = (sev == CPER_SEV_NON_FATAL_CORRECTED) ? false : true; 178 section_desc = (struct cper_sec_desc *)((uint8_t *)hdr + SEC_DESC_OFFSET(idx)); 179 section = (struct cper_sec_nonstd_err *)((uint8_t *)hdr + 180 NONSTD_SEC_OFFSET(hdr->sec_cnt, idx)); 181 182 amdgpu_cper_entry_fill_section_desc(adev, section_desc, false, poison, 183 sev, RUNTIME, NONSTD_SEC_LEN, 184 NONSTD_SEC_OFFSET(hdr->sec_cnt, idx)); 185 186 reg_count = umin(reg_count, CPER_ACA_REG_COUNT); 187 188 section->hdr.valid_bits.err_info_cnt = 1; 189 section->hdr.valid_bits.err_context_cnt = 1; 190 191 section->info.error_type = RUNTIME; 192 section->info.ms_chk_bits.err_type_valid = 1; 193 section->ctx.reg_ctx_type = CPER_CTX_TYPE_CRASH; 194 section->ctx.reg_arr_size = sizeof(section->ctx.reg_dump); 195 196 memcpy(section->ctx.reg_dump, reg_dump, reg_count * sizeof(uint32_t)); 197 198 __inc_entry_length(hdr, SEC_DESC_LEN + NONSTD_SEC_LEN); 199 200 return 0; 201 } 202 203 int amdgpu_cper_entry_fill_bad_page_threshold_section(struct amdgpu_device *adev, 204 struct cper_hdr *hdr, 205 uint32_t idx) 206 { 207 struct cper_sec_desc *section_desc; 208 struct cper_sec_nonstd_err *section; 209 uint32_t socket_id; 210 211 section_desc = (struct cper_sec_desc *)((uint8_t *)hdr + SEC_DESC_OFFSET(idx)); 212 section = (struct cper_sec_nonstd_err *)((uint8_t *)hdr + 213 NONSTD_SEC_OFFSET(hdr->sec_cnt, idx)); 214 215 amdgpu_cper_entry_fill_section_desc(adev, section_desc, true, false, 216 CPER_SEV_FATAL, RUNTIME, NONSTD_SEC_LEN, 217 NONSTD_SEC_OFFSET(hdr->sec_cnt, idx)); 218 219 section->hdr.valid_bits.err_info_cnt = 1; 220 section->hdr.valid_bits.err_context_cnt = 1; 221 222 section->info.error_type = RUNTIME; 223 section->info.ms_chk_bits.err_type_valid = 1; 224 section->ctx.reg_ctx_type = CPER_CTX_TYPE_CRASH; 225 section->ctx.reg_arr_size = sizeof(section->ctx.reg_dump); 226 227 /* Hardcoded Reg dump for bad page threshold CPER */ 228 socket_id = (adev->smuio.funcs && adev->smuio.funcs->get_socket_id) ? 229 adev->smuio.funcs->get_socket_id(adev) : 230 0; 231 section->ctx.reg_dump[CPER_ACA_REG_CTL_LO] = 0x1; 232 section->ctx.reg_dump[CPER_ACA_REG_CTL_HI] = 0x0; 233 section->ctx.reg_dump[CPER_ACA_REG_STATUS_LO] = 0x137; 234 section->ctx.reg_dump[CPER_ACA_REG_STATUS_HI] = 0xB0000000; 235 section->ctx.reg_dump[CPER_ACA_REG_ADDR_LO] = 0x0; 236 section->ctx.reg_dump[CPER_ACA_REG_ADDR_HI] = 0x0; 237 section->ctx.reg_dump[CPER_ACA_REG_MISC0_LO] = 0x0; 238 section->ctx.reg_dump[CPER_ACA_REG_MISC0_HI] = 0x0; 239 section->ctx.reg_dump[CPER_ACA_REG_CONFIG_LO] = 0x2; 240 section->ctx.reg_dump[CPER_ACA_REG_CONFIG_HI] = 0x1ff; 241 section->ctx.reg_dump[CPER_ACA_REG_IPID_LO] = (socket_id / 4) & 0x01; 242 section->ctx.reg_dump[CPER_ACA_REG_IPID_HI] = 0x096 | (((socket_id % 4) & 0x3) << 12); 243 section->ctx.reg_dump[CPER_ACA_REG_SYND_LO] = 0x0; 244 section->ctx.reg_dump[CPER_ACA_REG_SYND_HI] = 0x0; 245 246 __inc_entry_length(hdr, SEC_DESC_LEN + NONSTD_SEC_LEN); 247 248 return 0; 249 } 250 251 struct cper_hdr *amdgpu_cper_alloc_entry(struct amdgpu_device *adev, 252 enum amdgpu_cper_type type, 253 uint16_t section_count) 254 { 255 struct cper_hdr *hdr; 256 uint32_t size = 0; 257 258 size += HDR_LEN; 259 size += (SEC_DESC_LEN * section_count); 260 261 switch (type) { 262 case AMDGPU_CPER_TYPE_RUNTIME: 263 case AMDGPU_CPER_TYPE_BP_THRESHOLD: 264 size += (NONSTD_SEC_LEN * section_count); 265 break; 266 case AMDGPU_CPER_TYPE_FATAL: 267 size += (FATAL_SEC_LEN * section_count); 268 break; 269 case AMDGPU_CPER_TYPE_BOOT: 270 size += (BOOT_SEC_LEN * section_count); 271 break; 272 default: 273 dev_err(adev->dev, "Unknown CPER Type!\n"); 274 return NULL; 275 } 276 277 hdr = kzalloc(size, GFP_KERNEL); 278 if (!hdr) 279 return NULL; 280 281 /* Save this early */ 282 hdr->sec_cnt = section_count; 283 284 return hdr; 285 } 286 287 int amdgpu_cper_generate_ue_record(struct amdgpu_device *adev, 288 struct aca_bank *bank) 289 { 290 struct cper_hdr *fatal = NULL; 291 struct cper_sec_crashdump_reg_data reg_data = { 0 }; 292 struct amdgpu_ring *ring = &adev->cper.ring_buf; 293 int ret; 294 295 fatal = amdgpu_cper_alloc_entry(adev, AMDGPU_CPER_TYPE_FATAL, 1); 296 if (!fatal) { 297 dev_err(adev->dev, "fail to alloc cper entry for ue record\n"); 298 return -ENOMEM; 299 } 300 301 reg_data.status_lo = lower_32_bits(bank->regs[ACA_REG_IDX_STATUS]); 302 reg_data.status_hi = upper_32_bits(bank->regs[ACA_REG_IDX_STATUS]); 303 reg_data.addr_lo = lower_32_bits(bank->regs[ACA_REG_IDX_ADDR]); 304 reg_data.addr_hi = upper_32_bits(bank->regs[ACA_REG_IDX_ADDR]); 305 reg_data.ipid_lo = lower_32_bits(bank->regs[ACA_REG_IDX_IPID]); 306 reg_data.ipid_hi = upper_32_bits(bank->regs[ACA_REG_IDX_IPID]); 307 reg_data.synd_lo = lower_32_bits(bank->regs[ACA_REG_IDX_SYND]); 308 reg_data.synd_hi = upper_32_bits(bank->regs[ACA_REG_IDX_SYND]); 309 310 amdgpu_cper_entry_fill_hdr(adev, fatal, AMDGPU_CPER_TYPE_FATAL, CPER_SEV_FATAL); 311 ret = amdgpu_cper_entry_fill_fatal_section(adev, fatal, 0, reg_data); 312 if (ret) 313 return ret; 314 315 amdgpu_cper_ring_write(ring, fatal, fatal->record_length); 316 kfree(fatal); 317 318 return 0; 319 } 320 321 int amdgpu_cper_generate_bp_threshold_record(struct amdgpu_device *adev) 322 { 323 struct cper_hdr *bp_threshold = NULL; 324 struct amdgpu_ring *ring = &adev->cper.ring_buf; 325 int ret; 326 327 bp_threshold = amdgpu_cper_alloc_entry(adev, AMDGPU_CPER_TYPE_BP_THRESHOLD, 1); 328 if (!bp_threshold) { 329 dev_err(adev->dev, "fail to alloc cper entry for bad page threshold record\n"); 330 return -ENOMEM; 331 } 332 333 amdgpu_cper_entry_fill_hdr(adev, bp_threshold, 334 AMDGPU_CPER_TYPE_BP_THRESHOLD, 335 CPER_SEV_FATAL); 336 ret = amdgpu_cper_entry_fill_bad_page_threshold_section(adev, bp_threshold, 0); 337 if (ret) 338 return ret; 339 340 amdgpu_cper_ring_write(ring, bp_threshold, bp_threshold->record_length); 341 kfree(bp_threshold); 342 343 return 0; 344 } 345 346 static enum cper_error_severity amdgpu_aca_err_type_to_cper_sev(struct amdgpu_device *adev, 347 enum aca_error_type aca_err_type) 348 { 349 switch (aca_err_type) { 350 case ACA_ERROR_TYPE_UE: 351 return CPER_SEV_FATAL; 352 case ACA_ERROR_TYPE_CE: 353 return CPER_SEV_NON_FATAL_CORRECTED; 354 case ACA_ERROR_TYPE_DEFERRED: 355 return CPER_SEV_NON_FATAL_UNCORRECTED; 356 default: 357 dev_err(adev->dev, "Unknown ACA error type!\n"); 358 return CPER_SEV_FATAL; 359 } 360 } 361 362 int amdgpu_cper_generate_ce_records(struct amdgpu_device *adev, 363 struct aca_banks *banks, 364 uint16_t bank_count) 365 { 366 struct cper_hdr *corrected = NULL; 367 enum cper_error_severity sev = CPER_SEV_NON_FATAL_CORRECTED; 368 struct amdgpu_ring *ring = &adev->cper.ring_buf; 369 uint32_t reg_data[CPER_ACA_REG_COUNT] = { 0 }; 370 struct aca_bank_node *node; 371 struct aca_bank *bank; 372 uint32_t i = 0; 373 int ret; 374 375 corrected = amdgpu_cper_alloc_entry(adev, AMDGPU_CPER_TYPE_RUNTIME, bank_count); 376 if (!corrected) { 377 dev_err(adev->dev, "fail to allocate cper entry for ce records\n"); 378 return -ENOMEM; 379 } 380 381 /* Raise severity if any DE is detected in the ACA bank list */ 382 list_for_each_entry(node, &banks->list, node) { 383 bank = &node->bank; 384 if (bank->aca_err_type == ACA_ERROR_TYPE_DEFERRED) { 385 sev = CPER_SEV_NON_FATAL_UNCORRECTED; 386 break; 387 } 388 } 389 390 amdgpu_cper_entry_fill_hdr(adev, corrected, AMDGPU_CPER_TYPE_RUNTIME, sev); 391 392 /* Combine CE and DE in cper record */ 393 list_for_each_entry(node, &banks->list, node) { 394 bank = &node->bank; 395 reg_data[CPER_ACA_REG_CTL_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_CTL]); 396 reg_data[CPER_ACA_REG_CTL_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_CTL]); 397 reg_data[CPER_ACA_REG_STATUS_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_STATUS]); 398 reg_data[CPER_ACA_REG_STATUS_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_STATUS]); 399 reg_data[CPER_ACA_REG_ADDR_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_ADDR]); 400 reg_data[CPER_ACA_REG_ADDR_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_ADDR]); 401 reg_data[CPER_ACA_REG_MISC0_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_MISC0]); 402 reg_data[CPER_ACA_REG_MISC0_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_MISC0]); 403 reg_data[CPER_ACA_REG_CONFIG_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_CONFIG]); 404 reg_data[CPER_ACA_REG_CONFIG_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_CONFIG]); 405 reg_data[CPER_ACA_REG_IPID_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_IPID]); 406 reg_data[CPER_ACA_REG_IPID_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_IPID]); 407 reg_data[CPER_ACA_REG_SYND_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_SYND]); 408 reg_data[CPER_ACA_REG_SYND_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_SYND]); 409 410 ret = amdgpu_cper_entry_fill_runtime_section(adev, corrected, i++, 411 amdgpu_aca_err_type_to_cper_sev(adev, bank->aca_err_type), 412 reg_data, CPER_ACA_REG_COUNT); 413 if (ret) 414 return ret; 415 } 416 417 amdgpu_cper_ring_write(ring, corrected, corrected->record_length); 418 kfree(corrected); 419 420 return 0; 421 } 422 423 static bool amdgpu_cper_is_hdr(struct amdgpu_ring *ring, u64 pos) 424 { 425 struct cper_hdr *chdr; 426 427 chdr = (struct cper_hdr *)&(ring->ring[pos]); 428 return strcmp(chdr->signature, "CPER") ? false : true; 429 } 430 431 static u32 amdgpu_cper_ring_get_ent_sz(struct amdgpu_ring *ring, u64 pos) 432 { 433 struct cper_hdr *chdr; 434 u64 p; 435 u32 chunk, rec_len = 0; 436 437 chdr = (struct cper_hdr *)&(ring->ring[pos]); 438 chunk = ring->ring_size - (pos << 2); 439 440 if (!strcmp(chdr->signature, "CPER")) { 441 rec_len = chdr->record_length; 442 goto calc; 443 } 444 445 /* ring buffer is not full, no cper data after ring->wptr */ 446 if (ring->count_dw) 447 goto calc; 448 449 for (p = pos + 1; p <= ring->buf_mask; p++) { 450 chdr = (struct cper_hdr *)&(ring->ring[p]); 451 if (!strcmp(chdr->signature, "CPER")) { 452 rec_len = (p - pos) << 2; 453 goto calc; 454 } 455 } 456 457 calc: 458 if (!rec_len) 459 return chunk; 460 else 461 return umin(rec_len, chunk); 462 } 463 464 void amdgpu_cper_ring_write(struct amdgpu_ring *ring, void *src, int count) 465 { 466 u64 pos, wptr_old, rptr; 467 int rec_cnt_dw = count >> 2; 468 u32 chunk, ent_sz; 469 u8 *s = (u8 *)src; 470 471 if (count >= ring->ring_size - 4) { 472 dev_err(ring->adev->dev, 473 "CPER data size(%d) is larger than ring size(%d)\n", 474 count, ring->ring_size - 4); 475 476 return; 477 } 478 479 mutex_lock(&ring->adev->cper.ring_lock); 480 481 wptr_old = ring->wptr; 482 rptr = *ring->rptr_cpu_addr & ring->ptr_mask; 483 484 while (count) { 485 ent_sz = amdgpu_cper_ring_get_ent_sz(ring, ring->wptr); 486 chunk = umin(ent_sz, count); 487 488 memcpy(&ring->ring[ring->wptr], s, chunk); 489 490 ring->wptr += (chunk >> 2); 491 ring->wptr &= ring->ptr_mask; 492 count -= chunk; 493 s += chunk; 494 } 495 496 if (ring->count_dw < rec_cnt_dw) 497 ring->count_dw = 0; 498 499 /* the buffer is overflow, adjust rptr */ 500 if (((wptr_old < rptr) && (rptr <= ring->wptr)) || 501 ((ring->wptr < wptr_old) && (wptr_old < rptr)) || 502 ((rptr <= ring->wptr) && (ring->wptr < wptr_old))) { 503 pos = (ring->wptr + 1) & ring->ptr_mask; 504 505 do { 506 ent_sz = amdgpu_cper_ring_get_ent_sz(ring, pos); 507 508 rptr += (ent_sz >> 2); 509 rptr &= ring->ptr_mask; 510 *ring->rptr_cpu_addr = rptr; 511 512 pos = rptr; 513 } while (!amdgpu_cper_is_hdr(ring, rptr)); 514 } 515 516 if (ring->count_dw >= rec_cnt_dw) 517 ring->count_dw -= rec_cnt_dw; 518 mutex_unlock(&ring->adev->cper.ring_lock); 519 } 520 521 static u64 amdgpu_cper_ring_get_rptr(struct amdgpu_ring *ring) 522 { 523 return *(ring->rptr_cpu_addr); 524 } 525 526 static u64 amdgpu_cper_ring_get_wptr(struct amdgpu_ring *ring) 527 { 528 return ring->wptr; 529 } 530 531 static const struct amdgpu_ring_funcs cper_ring_funcs = { 532 .type = AMDGPU_RING_TYPE_CPER, 533 .align_mask = 0xff, 534 .support_64bit_ptrs = false, 535 .get_rptr = amdgpu_cper_ring_get_rptr, 536 .get_wptr = amdgpu_cper_ring_get_wptr, 537 }; 538 539 static int amdgpu_cper_ring_init(struct amdgpu_device *adev) 540 { 541 struct amdgpu_ring *ring = &(adev->cper.ring_buf); 542 543 mutex_init(&adev->cper.ring_lock); 544 545 ring->adev = NULL; 546 ring->ring_obj = NULL; 547 ring->use_doorbell = false; 548 ring->no_scheduler = true; 549 ring->funcs = &cper_ring_funcs; 550 551 sprintf(ring->name, "cper"); 552 return amdgpu_ring_init(adev, ring, CPER_MAX_RING_SIZE, NULL, 0, 553 AMDGPU_RING_PRIO_DEFAULT, NULL); 554 } 555 556 int amdgpu_cper_init(struct amdgpu_device *adev) 557 { 558 int r; 559 560 if (!amdgpu_aca_is_enabled(adev) && !amdgpu_sriov_ras_cper_en(adev)) 561 return 0; 562 563 r = amdgpu_cper_ring_init(adev); 564 if (r) { 565 dev_err(adev->dev, "failed to initialize cper ring, r = %d\n", r); 566 return r; 567 } 568 569 mutex_init(&adev->cper.cper_lock); 570 571 adev->cper.enabled = true; 572 adev->cper.max_count = CPER_MAX_ALLOWED_COUNT; 573 574 return 0; 575 } 576 577 int amdgpu_cper_fini(struct amdgpu_device *adev) 578 { 579 if (!amdgpu_aca_is_enabled(adev) && !amdgpu_sriov_ras_cper_en(adev)) 580 return 0; 581 582 adev->cper.enabled = false; 583 584 amdgpu_ring_fini(&(adev->cper.ring_buf)); 585 adev->cper.count = 0; 586 adev->cper.wptr = 0; 587 588 return 0; 589 } 590