1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27 #include <drm/display/drm_dp_helper.h> 28 #include <drm/drm_crtc_helper.h> 29 #include <drm/drm_edid.h> 30 #include <drm/drm_modeset_helper_vtables.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/amdgpu_drm.h> 33 #include "amdgpu.h" 34 #include "atom.h" 35 #include "atombios_encoders.h" 36 #include "atombios_dp.h" 37 #include "amdgpu_connectors.h" 38 #include "amdgpu_i2c.h" 39 #include "amdgpu_display.h" 40 41 #include <linux/pm_runtime.h> 42 43 void amdgpu_connector_hotplug(struct drm_connector *connector) 44 { 45 struct drm_device *dev = connector->dev; 46 struct amdgpu_device *adev = drm_to_adev(dev); 47 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 48 49 /* bail if the connector does not have hpd pin, e.g., 50 * VGA, TV, etc. 51 */ 52 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) 53 return; 54 55 amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 56 57 /* if the connector is already off, don't turn it back on */ 58 if (connector->dpms != DRM_MODE_DPMS_ON) 59 return; 60 61 /* just deal with DP (not eDP) here. */ 62 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 63 struct amdgpu_connector_atom_dig *dig_connector = 64 amdgpu_connector->con_priv; 65 66 /* if existing sink type was not DP no need to retrain */ 67 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) 68 return; 69 70 /* first get sink type as it may be reset after (un)plug */ 71 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 72 /* don't do anything if sink is not display port, i.e., 73 * passive dp->(dvi|hdmi) adaptor 74 */ 75 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT && 76 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) && 77 amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 78 /* Don't start link training before we have the DPCD */ 79 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 80 return; 81 82 /* Turn the connector off and back on immediately, which 83 * will trigger link training 84 */ 85 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 86 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 87 } 88 } 89 } 90 91 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder) 92 { 93 struct drm_crtc *crtc = encoder->crtc; 94 95 if (crtc && crtc->enabled) { 96 drm_crtc_helper_set_mode(crtc, &crtc->mode, 97 crtc->x, crtc->y, crtc->primary->fb); 98 } 99 } 100 101 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) 102 { 103 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 104 struct amdgpu_connector_atom_dig *dig_connector; 105 int bpc = 8; 106 unsigned int mode_clock, max_tmds_clock; 107 108 switch (connector->connector_type) { 109 case DRM_MODE_CONNECTOR_DVII: 110 case DRM_MODE_CONNECTOR_HDMIB: 111 if (amdgpu_connector->use_digital) { 112 if (connector->display_info.is_hdmi) { 113 if (connector->display_info.bpc) 114 bpc = connector->display_info.bpc; 115 } 116 } 117 break; 118 case DRM_MODE_CONNECTOR_DVID: 119 case DRM_MODE_CONNECTOR_HDMIA: 120 if (connector->display_info.is_hdmi) { 121 if (connector->display_info.bpc) 122 bpc = connector->display_info.bpc; 123 } 124 break; 125 case DRM_MODE_CONNECTOR_DisplayPort: 126 dig_connector = amdgpu_connector->con_priv; 127 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 128 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || 129 connector->display_info.is_hdmi) { 130 if (connector->display_info.bpc) 131 bpc = connector->display_info.bpc; 132 } 133 break; 134 case DRM_MODE_CONNECTOR_eDP: 135 case DRM_MODE_CONNECTOR_LVDS: 136 if (connector->display_info.bpc) 137 bpc = connector->display_info.bpc; 138 else { 139 const struct drm_connector_helper_funcs *connector_funcs = 140 connector->helper_private; 141 struct drm_encoder *encoder = connector_funcs->best_encoder(connector); 142 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 143 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 144 145 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR) 146 bpc = 6; 147 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR) 148 bpc = 8; 149 } 150 break; 151 } 152 153 if (connector->display_info.is_hdmi) { 154 /* 155 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make 156 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at 157 * 12 bpc is always supported on hdmi deep color sinks, as this is 158 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. 159 */ 160 if (bpc > 12) { 161 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", 162 connector->name, bpc); 163 bpc = 12; 164 } 165 166 /* Any defined maximum tmds clock limit we must not exceed? */ 167 if (connector->display_info.max_tmds_clock > 0) { 168 /* mode_clock is clock in kHz for mode to be modeset on this connector */ 169 mode_clock = amdgpu_connector->pixelclock_for_modeset; 170 171 /* Maximum allowable input clock in kHz */ 172 max_tmds_clock = connector->display_info.max_tmds_clock; 173 174 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n", 175 connector->name, mode_clock, max_tmds_clock); 176 177 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ 178 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { 179 if ((connector->display_info.edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) && 180 (mode_clock * 5/4 <= max_tmds_clock)) 181 bpc = 10; 182 else 183 bpc = 8; 184 185 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", 186 connector->name, bpc); 187 } 188 189 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { 190 bpc = 8; 191 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", 192 connector->name, bpc); 193 } 194 } else if (bpc > 8) { 195 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ 196 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", 197 connector->name); 198 bpc = 8; 199 } 200 } 201 202 if ((amdgpu_deep_color == 0) && (bpc > 8)) { 203 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n", 204 connector->name); 205 bpc = 8; 206 } 207 208 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", 209 connector->name, connector->display_info.bpc, bpc); 210 211 return bpc; 212 } 213 214 static void 215 amdgpu_connector_update_scratch_regs(struct drm_connector *connector, 216 enum drm_connector_status status) 217 { 218 struct drm_encoder *best_encoder; 219 struct drm_encoder *encoder; 220 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 221 bool connected; 222 223 best_encoder = connector_funcs->best_encoder(connector); 224 225 drm_connector_for_each_possible_encoder(connector, encoder) { 226 if ((encoder == best_encoder) && (status == connector_status_connected)) 227 connected = true; 228 else 229 connected = false; 230 231 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected); 232 } 233 } 234 235 static struct drm_encoder * 236 amdgpu_connector_find_encoder(struct drm_connector *connector, 237 int encoder_type) 238 { 239 struct drm_encoder *encoder; 240 241 drm_connector_for_each_possible_encoder(connector, encoder) { 242 if (encoder->encoder_type == encoder_type) 243 return encoder; 244 } 245 246 return NULL; 247 } 248 249 static struct edid * 250 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) 251 { 252 return drm_edid_duplicate(drm_edid_raw(adev->mode_info.bios_hardcoded_edid)); 253 } 254 255 static void amdgpu_connector_get_edid(struct drm_connector *connector) 256 { 257 struct drm_device *dev = connector->dev; 258 struct amdgpu_device *adev = drm_to_adev(dev); 259 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 260 261 if (amdgpu_connector->edid) 262 return; 263 264 /* on hw with routers, select right port */ 265 if (amdgpu_connector->router.ddc_valid) 266 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 267 268 if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 269 ENCODER_OBJECT_ID_NONE) && 270 amdgpu_connector->ddc_bus->has_aux) { 271 amdgpu_connector->edid = drm_get_edid(connector, 272 &amdgpu_connector->ddc_bus->aux.ddc); 273 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 274 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 275 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; 276 277 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 278 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && 279 amdgpu_connector->ddc_bus->has_aux) 280 amdgpu_connector->edid = drm_get_edid(connector, 281 &amdgpu_connector->ddc_bus->aux.ddc); 282 else if (amdgpu_connector->ddc_bus) 283 amdgpu_connector->edid = drm_get_edid(connector, 284 &amdgpu_connector->ddc_bus->adapter); 285 } else if (amdgpu_connector->ddc_bus) { 286 amdgpu_connector->edid = drm_get_edid(connector, 287 &amdgpu_connector->ddc_bus->adapter); 288 } 289 290 if (!amdgpu_connector->edid) { 291 /* some laptops provide a hardcoded edid in rom for LCDs */ 292 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || 293 (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) { 294 amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev); 295 drm_connector_update_edid_property(connector, amdgpu_connector->edid); 296 } 297 } 298 } 299 300 static void amdgpu_connector_free_edid(struct drm_connector *connector) 301 { 302 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 303 304 kfree(amdgpu_connector->edid); 305 amdgpu_connector->edid = NULL; 306 } 307 308 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) 309 { 310 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 311 int ret; 312 313 if (amdgpu_connector->edid) { 314 drm_connector_update_edid_property(connector, amdgpu_connector->edid); 315 ret = drm_add_edid_modes(connector, amdgpu_connector->edid); 316 return ret; 317 } 318 drm_connector_update_edid_property(connector, NULL); 319 return 0; 320 } 321 322 static struct drm_encoder * 323 amdgpu_connector_best_single_encoder(struct drm_connector *connector) 324 { 325 struct drm_encoder *encoder; 326 327 /* pick the first one */ 328 drm_connector_for_each_possible_encoder(connector, encoder) 329 return encoder; 330 331 return NULL; 332 } 333 334 static void amdgpu_get_native_mode(struct drm_connector *connector) 335 { 336 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 337 struct amdgpu_encoder *amdgpu_encoder; 338 339 if (encoder == NULL) 340 return; 341 342 amdgpu_encoder = to_amdgpu_encoder(encoder); 343 344 if (!list_empty(&connector->probed_modes)) { 345 struct drm_display_mode *preferred_mode = 346 list_first_entry(&connector->probed_modes, 347 struct drm_display_mode, head); 348 349 amdgpu_encoder->native_mode = *preferred_mode; 350 } else { 351 amdgpu_encoder->native_mode.clock = 0; 352 } 353 } 354 355 static struct drm_display_mode * 356 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder) 357 { 358 struct drm_device *dev = encoder->dev; 359 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 360 struct drm_display_mode *mode = NULL; 361 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 362 363 if (native_mode->hdisplay != 0 && 364 native_mode->vdisplay != 0 && 365 native_mode->clock != 0) { 366 mode = drm_mode_duplicate(dev, native_mode); 367 if (!mode) 368 return NULL; 369 370 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 371 drm_mode_set_name(mode); 372 373 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); 374 } else if (native_mode->hdisplay != 0 && 375 native_mode->vdisplay != 0) { 376 /* mac laptops without an edid */ 377 /* Note that this is not necessarily the exact panel mode, 378 * but an approximation based on the cvt formula. For these 379 * systems we should ideally read the mode info out of the 380 * registers or add a mode table, but this works and is much 381 * simpler. 382 */ 383 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); 384 if (!mode) 385 return NULL; 386 387 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 388 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); 389 } 390 return mode; 391 } 392 393 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, 394 struct drm_connector *connector) 395 { 396 struct drm_device *dev = encoder->dev; 397 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 398 struct drm_display_mode *mode = NULL; 399 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 400 int i; 401 int n; 402 struct mode_size { 403 char name[DRM_DISPLAY_MODE_LEN]; 404 int w; 405 int h; 406 } common_modes[] = { 407 { "640x480", 640, 480}, 408 { "800x600", 800, 600}, 409 { "1024x768", 1024, 768}, 410 { "1280x720", 1280, 720}, 411 { "1280x800", 1280, 800}, 412 {"1280x1024", 1280, 1024}, 413 { "1440x900", 1440, 900}, 414 {"1680x1050", 1680, 1050}, 415 {"1600x1200", 1600, 1200}, 416 {"1920x1080", 1920, 1080}, 417 {"1920x1200", 1920, 1200} 418 }; 419 420 n = ARRAY_SIZE(common_modes); 421 422 for (i = 0; i < n; i++) { 423 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 424 if (common_modes[i].w > 1024 || 425 common_modes[i].h > 768) 426 continue; 427 } 428 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 429 if (common_modes[i].w > native_mode->hdisplay || 430 common_modes[i].h > native_mode->vdisplay || 431 (common_modes[i].w == native_mode->hdisplay && 432 common_modes[i].h == native_mode->vdisplay)) 433 continue; 434 } 435 436 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); 437 if (!mode) 438 return; 439 strscpy(mode->name, common_modes[i].name, DRM_DISPLAY_MODE_LEN); 440 441 drm_mode_probed_add(connector, mode); 442 } 443 } 444 445 static int amdgpu_connector_set_property(struct drm_connector *connector, 446 struct drm_property *property, 447 uint64_t val) 448 { 449 struct drm_device *dev = connector->dev; 450 struct amdgpu_device *adev = drm_to_adev(dev); 451 struct drm_encoder *encoder; 452 struct amdgpu_encoder *amdgpu_encoder; 453 454 if (property == adev->mode_info.coherent_mode_property) { 455 struct amdgpu_encoder_atom_dig *dig; 456 bool new_coherent_mode; 457 458 /* need to find digital encoder on connector */ 459 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 460 if (!encoder) 461 return 0; 462 463 amdgpu_encoder = to_amdgpu_encoder(encoder); 464 465 if (!amdgpu_encoder->enc_priv) 466 return 0; 467 468 dig = amdgpu_encoder->enc_priv; 469 new_coherent_mode = val ? true : false; 470 if (dig->coherent_mode != new_coherent_mode) { 471 dig->coherent_mode = new_coherent_mode; 472 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 473 } 474 } 475 476 if (property == adev->mode_info.audio_property) { 477 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 478 /* need to find digital encoder on connector */ 479 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 480 if (!encoder) 481 return 0; 482 483 amdgpu_encoder = to_amdgpu_encoder(encoder); 484 485 if (amdgpu_connector->audio != val) { 486 amdgpu_connector->audio = val; 487 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 488 } 489 } 490 491 if (property == adev->mode_info.dither_property) { 492 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 493 /* need to find digital encoder on connector */ 494 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 495 if (!encoder) 496 return 0; 497 498 amdgpu_encoder = to_amdgpu_encoder(encoder); 499 500 if (amdgpu_connector->dither != val) { 501 amdgpu_connector->dither = val; 502 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 503 } 504 } 505 506 if (property == adev->mode_info.underscan_property) { 507 /* need to find digital encoder on connector */ 508 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 509 if (!encoder) 510 return 0; 511 512 amdgpu_encoder = to_amdgpu_encoder(encoder); 513 514 if (amdgpu_encoder->underscan_type != val) { 515 amdgpu_encoder->underscan_type = val; 516 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 517 } 518 } 519 520 if (property == adev->mode_info.underscan_hborder_property) { 521 /* need to find digital encoder on connector */ 522 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 523 if (!encoder) 524 return 0; 525 526 amdgpu_encoder = to_amdgpu_encoder(encoder); 527 528 if (amdgpu_encoder->underscan_hborder != val) { 529 amdgpu_encoder->underscan_hborder = val; 530 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 531 } 532 } 533 534 if (property == adev->mode_info.underscan_vborder_property) { 535 /* need to find digital encoder on connector */ 536 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 537 if (!encoder) 538 return 0; 539 540 amdgpu_encoder = to_amdgpu_encoder(encoder); 541 542 if (amdgpu_encoder->underscan_vborder != val) { 543 amdgpu_encoder->underscan_vborder = val; 544 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 545 } 546 } 547 548 if (property == adev->mode_info.load_detect_property) { 549 struct amdgpu_connector *amdgpu_connector = 550 to_amdgpu_connector(connector); 551 552 if (val == 0) 553 amdgpu_connector->dac_load_detect = false; 554 else 555 amdgpu_connector->dac_load_detect = true; 556 } 557 558 if (property == dev->mode_config.scaling_mode_property) { 559 enum amdgpu_rmx_type rmx_type; 560 561 if (connector->encoder) { 562 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 563 } else { 564 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 565 566 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 567 } 568 569 switch (val) { 570 default: 571 case DRM_MODE_SCALE_NONE: 572 rmx_type = RMX_OFF; 573 break; 574 case DRM_MODE_SCALE_CENTER: 575 rmx_type = RMX_CENTER; 576 break; 577 case DRM_MODE_SCALE_ASPECT: 578 rmx_type = RMX_ASPECT; 579 break; 580 case DRM_MODE_SCALE_FULLSCREEN: 581 rmx_type = RMX_FULL; 582 break; 583 } 584 585 if (amdgpu_encoder->rmx_type == rmx_type) 586 return 0; 587 588 if ((rmx_type != DRM_MODE_SCALE_NONE) && 589 (amdgpu_encoder->native_mode.clock == 0)) 590 return 0; 591 592 amdgpu_encoder->rmx_type = rmx_type; 593 594 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 595 } 596 597 return 0; 598 } 599 600 static void 601 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder, 602 struct drm_connector *connector) 603 { 604 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 605 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 606 struct drm_display_mode *t, *mode; 607 608 /* If the EDID preferred mode doesn't match the native mode, use it */ 609 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 610 if (mode->type & DRM_MODE_TYPE_PREFERRED) { 611 if (mode->hdisplay != native_mode->hdisplay || 612 mode->vdisplay != native_mode->vdisplay) 613 drm_mode_copy(native_mode, mode); 614 } 615 } 616 617 /* Try to get native mode details from EDID if necessary */ 618 if (!native_mode->clock) { 619 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 620 if (mode->hdisplay == native_mode->hdisplay && 621 mode->vdisplay == native_mode->vdisplay) { 622 drm_mode_copy(native_mode, mode); 623 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); 624 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); 625 break; 626 } 627 } 628 } 629 630 if (!native_mode->clock) { 631 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n"); 632 amdgpu_encoder->rmx_type = RMX_OFF; 633 } 634 } 635 636 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) 637 { 638 struct drm_encoder *encoder; 639 int ret = 0; 640 struct drm_display_mode *mode; 641 642 amdgpu_connector_get_edid(connector); 643 ret = amdgpu_connector_ddc_get_modes(connector); 644 if (ret > 0) { 645 encoder = amdgpu_connector_best_single_encoder(connector); 646 if (encoder) { 647 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 648 /* add scaled modes */ 649 amdgpu_connector_add_common_modes(encoder, connector); 650 } 651 return ret; 652 } 653 654 encoder = amdgpu_connector_best_single_encoder(connector); 655 if (!encoder) 656 return 0; 657 658 /* we have no EDID modes */ 659 mode = amdgpu_connector_lcd_native_mode(encoder); 660 if (mode) { 661 ret = 1; 662 drm_mode_probed_add(connector, mode); 663 /* add the width/height from vbios tables if available */ 664 connector->display_info.width_mm = mode->width_mm; 665 connector->display_info.height_mm = mode->height_mm; 666 /* add scaled modes */ 667 amdgpu_connector_add_common_modes(encoder, connector); 668 } 669 670 return ret; 671 } 672 673 static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, 674 const struct drm_display_mode *mode) 675 { 676 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 677 678 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 679 return MODE_PANEL; 680 681 if (encoder) { 682 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 683 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 684 685 /* AVIVO hardware supports downscaling modes larger than the panel 686 * to the panel size, but I'm not sure this is desirable. 687 */ 688 if ((mode->hdisplay > native_mode->hdisplay) || 689 (mode->vdisplay > native_mode->vdisplay)) 690 return MODE_PANEL; 691 692 /* if scaling is disabled, block non-native modes */ 693 if (amdgpu_encoder->rmx_type == RMX_OFF) { 694 if ((mode->hdisplay != native_mode->hdisplay) || 695 (mode->vdisplay != native_mode->vdisplay)) 696 return MODE_PANEL; 697 } 698 } 699 700 return MODE_OK; 701 } 702 703 static enum drm_connector_status 704 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force) 705 { 706 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 707 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 708 enum drm_connector_status ret = connector_status_disconnected; 709 int r; 710 711 if (!drm_kms_helper_is_poll_worker()) { 712 r = pm_runtime_get_sync(connector->dev->dev); 713 if (r < 0) { 714 pm_runtime_put_autosuspend(connector->dev->dev); 715 return connector_status_disconnected; 716 } 717 } 718 719 if (encoder) { 720 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 721 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 722 723 /* check if panel is valid */ 724 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 725 ret = connector_status_connected; 726 727 } 728 729 /* check for edid as well */ 730 amdgpu_connector_get_edid(connector); 731 if (amdgpu_connector->edid) 732 ret = connector_status_connected; 733 /* check acpi lid status ??? */ 734 735 amdgpu_connector_update_scratch_regs(connector, ret); 736 737 if (!drm_kms_helper_is_poll_worker()) 738 pm_runtime_put_autosuspend(connector->dev->dev); 739 740 return ret; 741 } 742 743 static void amdgpu_connector_unregister(struct drm_connector *connector) 744 { 745 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 746 747 if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) { 748 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); 749 amdgpu_connector->ddc_bus->has_aux = false; 750 } 751 } 752 753 static void amdgpu_connector_destroy(struct drm_connector *connector) 754 { 755 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 756 757 amdgpu_connector_free_edid(connector); 758 kfree(amdgpu_connector->con_priv); 759 drm_connector_unregister(connector); 760 drm_connector_cleanup(connector); 761 kfree(connector); 762 } 763 764 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector, 765 struct drm_property *property, 766 uint64_t value) 767 { 768 struct drm_device *dev = connector->dev; 769 struct amdgpu_encoder *amdgpu_encoder; 770 enum amdgpu_rmx_type rmx_type; 771 772 DRM_DEBUG_KMS("\n"); 773 if (property != dev->mode_config.scaling_mode_property) 774 return 0; 775 776 if (connector->encoder) 777 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 778 else { 779 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 780 781 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 782 } 783 784 switch (value) { 785 case DRM_MODE_SCALE_NONE: 786 rmx_type = RMX_OFF; 787 break; 788 case DRM_MODE_SCALE_CENTER: 789 rmx_type = RMX_CENTER; 790 break; 791 case DRM_MODE_SCALE_ASPECT: 792 rmx_type = RMX_ASPECT; 793 break; 794 default: 795 case DRM_MODE_SCALE_FULLSCREEN: 796 rmx_type = RMX_FULL; 797 break; 798 } 799 800 if (amdgpu_encoder->rmx_type == rmx_type) 801 return 0; 802 803 amdgpu_encoder->rmx_type = rmx_type; 804 805 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 806 return 0; 807 } 808 809 810 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = { 811 .get_modes = amdgpu_connector_lvds_get_modes, 812 .mode_valid = amdgpu_connector_lvds_mode_valid, 813 .best_encoder = amdgpu_connector_best_single_encoder, 814 }; 815 816 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = { 817 .dpms = drm_helper_connector_dpms, 818 .detect = amdgpu_connector_lvds_detect, 819 .fill_modes = drm_helper_probe_single_connector_modes, 820 .early_unregister = amdgpu_connector_unregister, 821 .destroy = amdgpu_connector_destroy, 822 .set_property = amdgpu_connector_set_lcd_property, 823 }; 824 825 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) 826 { 827 int ret; 828 829 amdgpu_connector_get_edid(connector); 830 ret = amdgpu_connector_ddc_get_modes(connector); 831 amdgpu_get_native_mode(connector); 832 833 return ret; 834 } 835 836 static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector, 837 const struct drm_display_mode *mode) 838 { 839 struct drm_device *dev = connector->dev; 840 struct amdgpu_device *adev = drm_to_adev(dev); 841 842 /* XXX check mode bandwidth */ 843 844 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 845 return MODE_CLOCK_HIGH; 846 847 return MODE_OK; 848 } 849 850 static enum drm_connector_status 851 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) 852 { 853 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 854 struct drm_encoder *encoder; 855 const struct drm_encoder_helper_funcs *encoder_funcs; 856 bool dret = false; 857 enum drm_connector_status ret = connector_status_disconnected; 858 int r; 859 860 if (!drm_kms_helper_is_poll_worker()) { 861 r = pm_runtime_get_sync(connector->dev->dev); 862 if (r < 0) { 863 pm_runtime_put_autosuspend(connector->dev->dev); 864 return connector_status_disconnected; 865 } 866 } 867 868 encoder = amdgpu_connector_best_single_encoder(connector); 869 if (!encoder) 870 ret = connector_status_disconnected; 871 872 if (amdgpu_connector->ddc_bus) 873 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 874 if (dret) { 875 amdgpu_connector->detected_by_load = false; 876 amdgpu_connector_free_edid(connector); 877 amdgpu_connector_get_edid(connector); 878 879 if (!amdgpu_connector->edid) { 880 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 881 connector->name); 882 ret = connector_status_connected; 883 } else { 884 amdgpu_connector->use_digital = 885 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 886 887 /* some oems have boards with separate digital and analog connectors 888 * with a shared ddc line (often vga + hdmi) 889 */ 890 if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) { 891 amdgpu_connector_free_edid(connector); 892 ret = connector_status_disconnected; 893 } else { 894 ret = connector_status_connected; 895 } 896 } 897 } else { 898 899 /* if we aren't forcing don't do destructive polling */ 900 if (!force) { 901 /* only return the previous status if we last 902 * detected a monitor via load. 903 */ 904 if (amdgpu_connector->detected_by_load) 905 ret = connector->status; 906 goto out; 907 } 908 909 if (amdgpu_connector->dac_load_detect && encoder) { 910 encoder_funcs = encoder->helper_private; 911 ret = encoder_funcs->detect(encoder, connector); 912 if (ret != connector_status_disconnected) 913 amdgpu_connector->detected_by_load = true; 914 } 915 } 916 917 amdgpu_connector_update_scratch_regs(connector, ret); 918 919 out: 920 if (!drm_kms_helper_is_poll_worker()) 921 pm_runtime_put_autosuspend(connector->dev->dev); 922 923 return ret; 924 } 925 926 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = { 927 .get_modes = amdgpu_connector_vga_get_modes, 928 .mode_valid = amdgpu_connector_vga_mode_valid, 929 .best_encoder = amdgpu_connector_best_single_encoder, 930 }; 931 932 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = { 933 .dpms = drm_helper_connector_dpms, 934 .detect = amdgpu_connector_vga_detect, 935 .fill_modes = drm_helper_probe_single_connector_modes, 936 .early_unregister = amdgpu_connector_unregister, 937 .destroy = amdgpu_connector_destroy, 938 .set_property = amdgpu_connector_set_property, 939 }; 940 941 static bool 942 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector) 943 { 944 struct drm_device *dev = connector->dev; 945 struct amdgpu_device *adev = drm_to_adev(dev); 946 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 947 enum drm_connector_status status; 948 949 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) { 950 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) 951 status = connector_status_connected; 952 else 953 status = connector_status_disconnected; 954 if (connector->status == status) 955 return true; 956 } 957 958 return false; 959 } 960 961 static void amdgpu_connector_shared_ddc(enum drm_connector_status *status, 962 struct drm_connector *connector, 963 struct amdgpu_connector *amdgpu_connector) 964 { 965 struct drm_connector *list_connector; 966 struct drm_connector_list_iter iter; 967 struct amdgpu_connector *list_amdgpu_connector; 968 struct drm_device *dev = connector->dev; 969 struct amdgpu_device *adev = drm_to_adev(dev); 970 971 if (amdgpu_connector->shared_ddc && *status == connector_status_connected) { 972 drm_connector_list_iter_begin(dev, &iter); 973 drm_for_each_connector_iter(list_connector, 974 &iter) { 975 if (connector == list_connector) 976 continue; 977 list_amdgpu_connector = to_amdgpu_connector(list_connector); 978 if (list_amdgpu_connector->shared_ddc && 979 list_amdgpu_connector->ddc_bus->rec.i2c_id == 980 amdgpu_connector->ddc_bus->rec.i2c_id) { 981 /* cases where both connectors are digital */ 982 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { 983 /* hpd is our only option in this case */ 984 if (!amdgpu_display_hpd_sense(adev, 985 amdgpu_connector->hpd.hpd)) { 986 amdgpu_connector_free_edid(connector); 987 *status = connector_status_disconnected; 988 } 989 } 990 } 991 } 992 drm_connector_list_iter_end(&iter); 993 } 994 } 995 996 /* 997 * DVI is complicated 998 * Do a DDC probe, if DDC probe passes, get the full EDID so 999 * we can do analog/digital monitor detection at this point. 1000 * If the monitor is an analog monitor or we got no DDC, 1001 * we need to find the DAC encoder object for this connector. 1002 * If we got no DDC, we do load detection on the DAC encoder object. 1003 * If we got analog DDC or load detection passes on the DAC encoder 1004 * we have to check if this analog encoder is shared with anyone else (TV) 1005 * if its shared we have to set the other connector to disconnected. 1006 */ 1007 static enum drm_connector_status 1008 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) 1009 { 1010 struct drm_device *dev = connector->dev; 1011 struct amdgpu_device *adev = drm_to_adev(dev); 1012 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1013 const struct drm_encoder_helper_funcs *encoder_funcs; 1014 int r; 1015 enum drm_connector_status ret = connector_status_disconnected; 1016 bool dret = false, broken_edid = false; 1017 1018 if (!drm_kms_helper_is_poll_worker()) { 1019 r = pm_runtime_get_sync(connector->dev->dev); 1020 if (r < 0) { 1021 pm_runtime_put_autosuspend(connector->dev->dev); 1022 return connector_status_disconnected; 1023 } 1024 } 1025 1026 if (amdgpu_connector->detected_hpd_without_ddc) { 1027 force = true; 1028 amdgpu_connector->detected_hpd_without_ddc = false; 1029 } 1030 1031 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1032 ret = connector->status; 1033 goto exit; 1034 } 1035 1036 if (amdgpu_connector->ddc_bus) { 1037 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 1038 1039 /* Sometimes the pins required for the DDC probe on DVI 1040 * connectors don't make contact at the same time that the ones 1041 * for HPD do. If the DDC probe fails even though we had an HPD 1042 * signal, try again later 1043 */ 1044 if (!dret && !force && 1045 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1046 DRM_DEBUG_KMS("hpd detected without ddc, retrying in 1 second\n"); 1047 amdgpu_connector->detected_hpd_without_ddc = true; 1048 schedule_delayed_work(&adev->hotplug_work, 1049 msecs_to_jiffies(1000)); 1050 goto exit; 1051 } 1052 } 1053 if (dret) { 1054 amdgpu_connector->detected_by_load = false; 1055 amdgpu_connector_free_edid(connector); 1056 amdgpu_connector_get_edid(connector); 1057 1058 if (!amdgpu_connector->edid) { 1059 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 1060 connector->name); 1061 ret = connector_status_connected; 1062 broken_edid = true; /* defer use_digital to later */ 1063 } else { 1064 amdgpu_connector->use_digital = 1065 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 1066 1067 /* some oems have boards with separate digital and analog connectors 1068 * with a shared ddc line (often vga + hdmi) 1069 */ 1070 if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) { 1071 amdgpu_connector_free_edid(connector); 1072 ret = connector_status_disconnected; 1073 } else { 1074 ret = connector_status_connected; 1075 } 1076 1077 /* This gets complicated. We have boards with VGA + HDMI with a 1078 * shared DDC line and we have boards with DVI-D + HDMI with a shared 1079 * DDC line. The latter is more complex because with DVI<->HDMI adapters 1080 * you don't really know what's connected to which port as both are digital. 1081 */ 1082 amdgpu_connector_shared_ddc(&ret, connector, amdgpu_connector); 1083 } 1084 } 1085 1086 if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true)) 1087 goto out; 1088 1089 /* DVI-D and HDMI-A are digital only */ 1090 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) || 1091 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)) 1092 goto out; 1093 1094 /* if we aren't forcing don't do destructive polling */ 1095 if (!force) { 1096 /* only return the previous status if we last 1097 * detected a monitor via load. 1098 */ 1099 if (amdgpu_connector->detected_by_load) 1100 ret = connector->status; 1101 goto out; 1102 } 1103 1104 /* find analog encoder */ 1105 if (amdgpu_connector->dac_load_detect) { 1106 struct drm_encoder *encoder; 1107 1108 drm_connector_for_each_possible_encoder(connector, encoder) { 1109 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && 1110 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) 1111 continue; 1112 1113 encoder_funcs = encoder->helper_private; 1114 if (encoder_funcs->detect) { 1115 if (!broken_edid) { 1116 if (ret != connector_status_connected) { 1117 /* deal with analog monitors without DDC */ 1118 ret = encoder_funcs->detect(encoder, connector); 1119 if (ret == connector_status_connected) { 1120 amdgpu_connector->use_digital = false; 1121 } 1122 if (ret != connector_status_disconnected) 1123 amdgpu_connector->detected_by_load = true; 1124 } 1125 } else { 1126 enum drm_connector_status lret; 1127 /* assume digital unless load detected otherwise */ 1128 amdgpu_connector->use_digital = true; 1129 lret = encoder_funcs->detect(encoder, connector); 1130 DRM_DEBUG_KMS("load_detect %x returned: %x\n", 1131 encoder->encoder_type, lret); 1132 if (lret == connector_status_connected) 1133 amdgpu_connector->use_digital = false; 1134 } 1135 break; 1136 } 1137 } 1138 } 1139 1140 out: 1141 /* updated in get modes as well since we need to know if it's analog or digital */ 1142 amdgpu_connector_update_scratch_regs(connector, ret); 1143 1144 exit: 1145 if (!drm_kms_helper_is_poll_worker()) 1146 pm_runtime_put_autosuspend(connector->dev->dev); 1147 1148 return ret; 1149 } 1150 1151 /* okay need to be smart in here about which encoder to pick */ 1152 static struct drm_encoder * 1153 amdgpu_connector_dvi_encoder(struct drm_connector *connector) 1154 { 1155 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1156 struct drm_encoder *encoder; 1157 1158 drm_connector_for_each_possible_encoder(connector, encoder) { 1159 if (amdgpu_connector->use_digital == true) { 1160 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) 1161 return encoder; 1162 } else { 1163 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC || 1164 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1165 return encoder; 1166 } 1167 } 1168 1169 /* see if we have a default encoder TODO */ 1170 1171 /* then check use digitial */ 1172 /* pick the first one */ 1173 drm_connector_for_each_possible_encoder(connector, encoder) 1174 return encoder; 1175 1176 return NULL; 1177 } 1178 1179 static void amdgpu_connector_dvi_force(struct drm_connector *connector) 1180 { 1181 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1182 1183 if (connector->force == DRM_FORCE_ON) 1184 amdgpu_connector->use_digital = false; 1185 if (connector->force == DRM_FORCE_ON_DIGITAL) 1186 amdgpu_connector->use_digital = true; 1187 } 1188 1189 /** 1190 * amdgpu_max_hdmi_pixel_clock - Return max supported HDMI (TMDS) pixel clock 1191 * @adev: pointer to amdgpu_device 1192 * 1193 * Return: maximum supported HDMI (TMDS) pixel clock in KHz. 1194 */ 1195 static int amdgpu_max_hdmi_pixel_clock(const struct amdgpu_device *adev) 1196 { 1197 if (adev->asic_type >= CHIP_POLARIS10) 1198 return 600000; 1199 else if (adev->asic_type >= CHIP_TONGA) 1200 return 300000; 1201 else 1202 return 297000; 1203 } 1204 1205 /** 1206 * amdgpu_connector_dvi_mode_valid - Validate a mode on DVI/HDMI connectors 1207 * @connector: DRM connector to validate the mode on 1208 * @mode: display mode to validate 1209 * 1210 * Validate the given display mode on DVI and HDMI connectors, including 1211 * analog signals on DVI-I. 1212 * 1213 * Return: drm_mode_status indicating whether the mode is valid. 1214 */ 1215 static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, 1216 const struct drm_display_mode *mode) 1217 { 1218 struct drm_device *dev = connector->dev; 1219 struct amdgpu_device *adev = drm_to_adev(dev); 1220 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1221 const int max_hdmi_pixel_clock = amdgpu_max_hdmi_pixel_clock(adev); 1222 const int max_dvi_single_link_pixel_clock = 165000; 1223 int max_digital_pixel_clock_khz; 1224 1225 /* XXX check mode bandwidth */ 1226 1227 if (amdgpu_connector->use_digital) { 1228 switch (amdgpu_connector->connector_object_id) { 1229 case CONNECTOR_OBJECT_ID_HDMI_TYPE_A: 1230 max_digital_pixel_clock_khz = max_hdmi_pixel_clock; 1231 break; 1232 case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I: 1233 case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D: 1234 max_digital_pixel_clock_khz = max_dvi_single_link_pixel_clock; 1235 break; 1236 case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I: 1237 case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D: 1238 case CONNECTOR_OBJECT_ID_HDMI_TYPE_B: 1239 max_digital_pixel_clock_khz = max_dvi_single_link_pixel_clock * 2; 1240 break; 1241 } 1242 1243 /* When the display EDID claims that it's an HDMI display, 1244 * we use the HDMI encoder mode of the display HW, 1245 * so we should verify against the max HDMI clock here. 1246 */ 1247 if (connector->display_info.is_hdmi) 1248 max_digital_pixel_clock_khz = max_hdmi_pixel_clock; 1249 1250 if (mode->clock > max_digital_pixel_clock_khz) 1251 return MODE_CLOCK_HIGH; 1252 } 1253 1254 /* check against the max pixel clock */ 1255 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 1256 return MODE_CLOCK_HIGH; 1257 1258 return MODE_OK; 1259 } 1260 1261 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = { 1262 .get_modes = amdgpu_connector_vga_get_modes, 1263 .mode_valid = amdgpu_connector_dvi_mode_valid, 1264 .best_encoder = amdgpu_connector_dvi_encoder, 1265 }; 1266 1267 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = { 1268 .dpms = drm_helper_connector_dpms, 1269 .detect = amdgpu_connector_dvi_detect, 1270 .fill_modes = drm_helper_probe_single_connector_modes, 1271 .set_property = amdgpu_connector_set_property, 1272 .early_unregister = amdgpu_connector_unregister, 1273 .destroy = amdgpu_connector_destroy, 1274 .force = amdgpu_connector_dvi_force, 1275 }; 1276 1277 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) 1278 { 1279 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1280 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1281 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1282 int ret; 1283 1284 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1285 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1286 struct drm_display_mode *mode; 1287 1288 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1289 if (!amdgpu_dig_connector->edp_on) 1290 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1291 ATOM_TRANSMITTER_ACTION_POWER_ON); 1292 amdgpu_connector_get_edid(connector); 1293 ret = amdgpu_connector_ddc_get_modes(connector); 1294 if (!amdgpu_dig_connector->edp_on) 1295 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1296 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1297 } else { 1298 /* need to setup ddc on the bridge */ 1299 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1300 ENCODER_OBJECT_ID_NONE) { 1301 if (encoder) 1302 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1303 } 1304 amdgpu_connector_get_edid(connector); 1305 ret = amdgpu_connector_ddc_get_modes(connector); 1306 } 1307 1308 if (ret > 0) { 1309 if (encoder) { 1310 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 1311 /* add scaled modes */ 1312 amdgpu_connector_add_common_modes(encoder, connector); 1313 } 1314 return ret; 1315 } 1316 1317 if (!encoder) 1318 return 0; 1319 1320 /* we have no EDID modes */ 1321 mode = amdgpu_connector_lcd_native_mode(encoder); 1322 if (mode) { 1323 ret = 1; 1324 drm_mode_probed_add(connector, mode); 1325 /* add the width/height from vbios tables if available */ 1326 connector->display_info.width_mm = mode->width_mm; 1327 connector->display_info.height_mm = mode->height_mm; 1328 /* add scaled modes */ 1329 amdgpu_connector_add_common_modes(encoder, connector); 1330 } 1331 } else { 1332 /* need to setup ddc on the bridge */ 1333 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1334 ENCODER_OBJECT_ID_NONE) { 1335 if (encoder) 1336 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1337 } 1338 amdgpu_connector_get_edid(connector); 1339 ret = amdgpu_connector_ddc_get_modes(connector); 1340 1341 amdgpu_get_native_mode(connector); 1342 } 1343 1344 return ret; 1345 } 1346 1347 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) 1348 { 1349 struct drm_encoder *encoder; 1350 struct amdgpu_encoder *amdgpu_encoder; 1351 1352 drm_connector_for_each_possible_encoder(connector, encoder) { 1353 amdgpu_encoder = to_amdgpu_encoder(encoder); 1354 1355 switch (amdgpu_encoder->encoder_id) { 1356 case ENCODER_OBJECT_ID_TRAVIS: 1357 case ENCODER_OBJECT_ID_NUTMEG: 1358 return amdgpu_encoder->encoder_id; 1359 default: 1360 break; 1361 } 1362 } 1363 1364 return ENCODER_OBJECT_ID_NONE; 1365 } 1366 1367 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) 1368 { 1369 struct drm_encoder *encoder; 1370 struct amdgpu_encoder *amdgpu_encoder; 1371 bool found = false; 1372 1373 drm_connector_for_each_possible_encoder(connector, encoder) { 1374 amdgpu_encoder = to_amdgpu_encoder(encoder); 1375 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) 1376 found = true; 1377 } 1378 1379 return found; 1380 } 1381 1382 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector) 1383 { 1384 struct drm_device *dev = connector->dev; 1385 struct amdgpu_device *adev = drm_to_adev(dev); 1386 1387 if ((adev->clock.default_dispclk >= 53900) && 1388 amdgpu_connector_encoder_is_hbr2(connector)) { 1389 return true; 1390 } 1391 1392 return false; 1393 } 1394 1395 static enum drm_connector_status 1396 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) 1397 { 1398 struct drm_device *dev = connector->dev; 1399 struct amdgpu_device *adev = drm_to_adev(dev); 1400 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1401 enum drm_connector_status ret = connector_status_disconnected; 1402 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1403 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1404 int r; 1405 1406 if (!drm_kms_helper_is_poll_worker()) { 1407 r = pm_runtime_get_sync(connector->dev->dev); 1408 if (r < 0) { 1409 pm_runtime_put_autosuspend(connector->dev->dev); 1410 return connector_status_disconnected; 1411 } 1412 } 1413 1414 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1415 ret = connector->status; 1416 goto out; 1417 } 1418 1419 amdgpu_connector_free_edid(connector); 1420 1421 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1422 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1423 if (encoder) { 1424 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1425 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1426 1427 /* check if panel is valid */ 1428 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 1429 ret = connector_status_connected; 1430 } 1431 /* eDP is always DP */ 1432 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1433 if (!amdgpu_dig_connector->edp_on) 1434 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1435 ATOM_TRANSMITTER_ACTION_POWER_ON); 1436 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1437 ret = connector_status_connected; 1438 if (!amdgpu_dig_connector->edp_on) 1439 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1440 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1441 } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1442 ENCODER_OBJECT_ID_NONE) { 1443 /* DP bridges are always DP */ 1444 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1445 /* get the DPCD from the bridge */ 1446 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1447 1448 if (encoder) { 1449 /* setup ddc on the bridge */ 1450 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1451 /* bridge chips are always aux */ 1452 /* try DDC */ 1453 if (amdgpu_display_ddc_probe(amdgpu_connector, true)) 1454 ret = connector_status_connected; 1455 else if (amdgpu_connector->dac_load_detect) { /* try load detection */ 1456 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 1457 1458 ret = encoder_funcs->detect(encoder, connector); 1459 } 1460 } 1461 } else { 1462 amdgpu_dig_connector->dp_sink_type = 1463 amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 1464 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1465 ret = connector_status_connected; 1466 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) 1467 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1468 } else { 1469 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 1470 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1471 ret = connector_status_connected; 1472 } else { 1473 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ 1474 if (amdgpu_display_ddc_probe(amdgpu_connector, 1475 false)) 1476 ret = connector_status_connected; 1477 } 1478 } 1479 } 1480 1481 amdgpu_connector_update_scratch_regs(connector, ret); 1482 out: 1483 if (!drm_kms_helper_is_poll_worker()) 1484 pm_runtime_put_autosuspend(connector->dev->dev); 1485 1486 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 1487 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 1488 drm_dp_set_subconnector_property(&amdgpu_connector->base, 1489 ret, 1490 amdgpu_dig_connector->dpcd, 1491 amdgpu_dig_connector->downstream_ports); 1492 return ret; 1493 } 1494 1495 static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector, 1496 const struct drm_display_mode *mode) 1497 { 1498 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1499 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1500 1501 /* XXX check mode bandwidth */ 1502 1503 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1504 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1505 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1506 1507 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 1508 return MODE_PANEL; 1509 1510 if (encoder) { 1511 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1512 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1513 1514 /* AVIVO hardware supports downscaling modes larger than the panel 1515 * to the panel size, but I'm not sure this is desirable. 1516 */ 1517 if ((mode->hdisplay > native_mode->hdisplay) || 1518 (mode->vdisplay > native_mode->vdisplay)) 1519 return MODE_PANEL; 1520 1521 /* if scaling is disabled, block non-native modes */ 1522 if (amdgpu_encoder->rmx_type == RMX_OFF) { 1523 if ((mode->hdisplay != native_mode->hdisplay) || 1524 (mode->vdisplay != native_mode->vdisplay)) 1525 return MODE_PANEL; 1526 } 1527 } 1528 return MODE_OK; 1529 } else { 1530 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 1531 (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 1532 return amdgpu_atombios_dp_mode_valid_helper(connector, mode); 1533 } else { 1534 if (connector->display_info.is_hdmi) { 1535 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1536 if (mode->clock > 340000) 1537 return MODE_CLOCK_HIGH; 1538 } else { 1539 if (mode->clock > 165000) 1540 return MODE_CLOCK_HIGH; 1541 } 1542 } 1543 } 1544 1545 return MODE_OK; 1546 } 1547 1548 static int 1549 amdgpu_connector_late_register(struct drm_connector *connector) 1550 { 1551 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1552 int r = 0; 1553 1554 if (amdgpu_connector->ddc_bus->has_aux) { 1555 amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev; 1556 r = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux); 1557 } 1558 1559 return r; 1560 } 1561 1562 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = { 1563 .get_modes = amdgpu_connector_dp_get_modes, 1564 .mode_valid = amdgpu_connector_dp_mode_valid, 1565 .best_encoder = amdgpu_connector_dvi_encoder, 1566 }; 1567 1568 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = { 1569 .dpms = drm_helper_connector_dpms, 1570 .detect = amdgpu_connector_dp_detect, 1571 .fill_modes = drm_helper_probe_single_connector_modes, 1572 .set_property = amdgpu_connector_set_property, 1573 .early_unregister = amdgpu_connector_unregister, 1574 .destroy = amdgpu_connector_destroy, 1575 .force = amdgpu_connector_dvi_force, 1576 .late_register = amdgpu_connector_late_register, 1577 }; 1578 1579 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = { 1580 .dpms = drm_helper_connector_dpms, 1581 .detect = amdgpu_connector_dp_detect, 1582 .fill_modes = drm_helper_probe_single_connector_modes, 1583 .set_property = amdgpu_connector_set_lcd_property, 1584 .early_unregister = amdgpu_connector_unregister, 1585 .destroy = amdgpu_connector_destroy, 1586 .force = amdgpu_connector_dvi_force, 1587 .late_register = amdgpu_connector_late_register, 1588 }; 1589 1590 void 1591 amdgpu_connector_add(struct amdgpu_device *adev, 1592 uint32_t connector_id, 1593 uint32_t supported_device, 1594 int connector_type, 1595 struct amdgpu_i2c_bus_rec *i2c_bus, 1596 uint16_t connector_object_id, 1597 struct amdgpu_hpd *hpd, 1598 struct amdgpu_router *router) 1599 { 1600 struct drm_device *dev = adev_to_drm(adev); 1601 struct drm_connector *connector; 1602 struct drm_connector_list_iter iter; 1603 struct amdgpu_connector *amdgpu_connector; 1604 struct amdgpu_connector_atom_dig *amdgpu_dig_connector; 1605 struct drm_encoder *encoder; 1606 struct amdgpu_encoder *amdgpu_encoder; 1607 struct i2c_adapter *ddc = NULL; 1608 uint32_t subpixel_order = SubPixelNone; 1609 bool shared_ddc = false; 1610 bool is_dp_bridge = false; 1611 bool has_aux = false; 1612 1613 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1614 return; 1615 1616 /* see if we already added it */ 1617 drm_connector_list_iter_begin(dev, &iter); 1618 drm_for_each_connector_iter(connector, &iter) { 1619 amdgpu_connector = to_amdgpu_connector(connector); 1620 if (amdgpu_connector->connector_id == connector_id) { 1621 amdgpu_connector->devices |= supported_device; 1622 drm_connector_list_iter_end(&iter); 1623 return; 1624 } 1625 if (amdgpu_connector->ddc_bus && i2c_bus->valid) { 1626 if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) { 1627 amdgpu_connector->shared_ddc = true; 1628 shared_ddc = true; 1629 } 1630 if (amdgpu_connector->router_bus && router->ddc_valid && 1631 (amdgpu_connector->router.router_id == router->router_id)) { 1632 amdgpu_connector->shared_ddc = false; 1633 shared_ddc = false; 1634 } 1635 } 1636 } 1637 drm_connector_list_iter_end(&iter); 1638 1639 /* check if it's a dp bridge */ 1640 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1641 amdgpu_encoder = to_amdgpu_encoder(encoder); 1642 if (amdgpu_encoder->devices & supported_device) { 1643 switch (amdgpu_encoder->encoder_id) { 1644 case ENCODER_OBJECT_ID_TRAVIS: 1645 case ENCODER_OBJECT_ID_NUTMEG: 1646 is_dp_bridge = true; 1647 break; 1648 default: 1649 break; 1650 } 1651 } 1652 } 1653 1654 amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL); 1655 if (!amdgpu_connector) 1656 return; 1657 1658 connector = &amdgpu_connector->base; 1659 1660 amdgpu_connector->connector_id = connector_id; 1661 amdgpu_connector->devices = supported_device; 1662 amdgpu_connector->shared_ddc = shared_ddc; 1663 amdgpu_connector->connector_object_id = connector_object_id; 1664 amdgpu_connector->hpd = *hpd; 1665 1666 amdgpu_connector->router = *router; 1667 if (router->ddc_valid || router->cd_valid) { 1668 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info); 1669 if (!amdgpu_connector->router_bus) 1670 DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); 1671 } 1672 1673 if (is_dp_bridge) { 1674 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1675 if (!amdgpu_dig_connector) 1676 goto failed; 1677 amdgpu_connector->con_priv = amdgpu_dig_connector; 1678 if (i2c_bus->valid) { 1679 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1680 if (amdgpu_connector->ddc_bus) { 1681 has_aux = true; 1682 ddc = &amdgpu_connector->ddc_bus->adapter; 1683 } else { 1684 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1685 } 1686 } 1687 switch (connector_type) { 1688 case DRM_MODE_CONNECTOR_VGA: 1689 case DRM_MODE_CONNECTOR_DVIA: 1690 default: 1691 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1692 &amdgpu_connector_dp_funcs, 1693 connector_type, 1694 ddc); 1695 drm_connector_helper_add(&amdgpu_connector->base, 1696 &amdgpu_connector_dp_helper_funcs); 1697 connector->interlace_allowed = true; 1698 connector->doublescan_allowed = true; 1699 amdgpu_connector->dac_load_detect = true; 1700 drm_object_attach_property(&amdgpu_connector->base.base, 1701 adev->mode_info.load_detect_property, 1702 1); 1703 drm_object_attach_property(&amdgpu_connector->base.base, 1704 dev->mode_config.scaling_mode_property, 1705 DRM_MODE_SCALE_NONE); 1706 break; 1707 case DRM_MODE_CONNECTOR_DVII: 1708 case DRM_MODE_CONNECTOR_DVID: 1709 case DRM_MODE_CONNECTOR_HDMIA: 1710 case DRM_MODE_CONNECTOR_HDMIB: 1711 case DRM_MODE_CONNECTOR_DisplayPort: 1712 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1713 &amdgpu_connector_dp_funcs, 1714 connector_type, 1715 ddc); 1716 drm_connector_helper_add(&amdgpu_connector->base, 1717 &amdgpu_connector_dp_helper_funcs); 1718 drm_object_attach_property(&amdgpu_connector->base.base, 1719 adev->mode_info.underscan_property, 1720 UNDERSCAN_OFF); 1721 drm_object_attach_property(&amdgpu_connector->base.base, 1722 adev->mode_info.underscan_hborder_property, 1723 0); 1724 drm_object_attach_property(&amdgpu_connector->base.base, 1725 adev->mode_info.underscan_vborder_property, 1726 0); 1727 1728 drm_object_attach_property(&amdgpu_connector->base.base, 1729 dev->mode_config.scaling_mode_property, 1730 DRM_MODE_SCALE_NONE); 1731 1732 drm_object_attach_property(&amdgpu_connector->base.base, 1733 adev->mode_info.dither_property, 1734 AMDGPU_FMT_DITHER_DISABLE); 1735 1736 if (amdgpu_audio != 0) { 1737 drm_object_attach_property(&amdgpu_connector->base.base, 1738 adev->mode_info.audio_property, 1739 AMDGPU_AUDIO_AUTO); 1740 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1741 } 1742 1743 subpixel_order = SubPixelHorizontalRGB; 1744 connector->interlace_allowed = true; 1745 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1746 connector->doublescan_allowed = true; 1747 else 1748 connector->doublescan_allowed = false; 1749 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1750 amdgpu_connector->dac_load_detect = true; 1751 drm_object_attach_property(&amdgpu_connector->base.base, 1752 adev->mode_info.load_detect_property, 1753 1); 1754 } 1755 break; 1756 case DRM_MODE_CONNECTOR_LVDS: 1757 case DRM_MODE_CONNECTOR_eDP: 1758 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1759 &amdgpu_connector_edp_funcs, 1760 connector_type, 1761 ddc); 1762 drm_connector_helper_add(&amdgpu_connector->base, 1763 &amdgpu_connector_dp_helper_funcs); 1764 drm_object_attach_property(&amdgpu_connector->base.base, 1765 dev->mode_config.scaling_mode_property, 1766 DRM_MODE_SCALE_FULLSCREEN); 1767 subpixel_order = SubPixelHorizontalRGB; 1768 connector->interlace_allowed = false; 1769 connector->doublescan_allowed = false; 1770 break; 1771 } 1772 } else { 1773 switch (connector_type) { 1774 case DRM_MODE_CONNECTOR_VGA: 1775 if (i2c_bus->valid) { 1776 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1777 if (!amdgpu_connector->ddc_bus) 1778 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1779 else 1780 ddc = &amdgpu_connector->ddc_bus->adapter; 1781 } 1782 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1783 &amdgpu_connector_vga_funcs, 1784 connector_type, 1785 ddc); 1786 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1787 amdgpu_connector->dac_load_detect = true; 1788 drm_object_attach_property(&amdgpu_connector->base.base, 1789 adev->mode_info.load_detect_property, 1790 1); 1791 drm_object_attach_property(&amdgpu_connector->base.base, 1792 dev->mode_config.scaling_mode_property, 1793 DRM_MODE_SCALE_NONE); 1794 /* no HPD on analog connectors */ 1795 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1796 connector->interlace_allowed = true; 1797 connector->doublescan_allowed = true; 1798 break; 1799 case DRM_MODE_CONNECTOR_DVIA: 1800 if (i2c_bus->valid) { 1801 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1802 if (!amdgpu_connector->ddc_bus) 1803 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1804 else 1805 ddc = &amdgpu_connector->ddc_bus->adapter; 1806 } 1807 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1808 &amdgpu_connector_vga_funcs, 1809 connector_type, 1810 ddc); 1811 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1812 amdgpu_connector->dac_load_detect = true; 1813 drm_object_attach_property(&amdgpu_connector->base.base, 1814 adev->mode_info.load_detect_property, 1815 1); 1816 drm_object_attach_property(&amdgpu_connector->base.base, 1817 dev->mode_config.scaling_mode_property, 1818 DRM_MODE_SCALE_NONE); 1819 /* no HPD on analog connectors */ 1820 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1821 connector->interlace_allowed = true; 1822 connector->doublescan_allowed = true; 1823 break; 1824 case DRM_MODE_CONNECTOR_DVII: 1825 case DRM_MODE_CONNECTOR_DVID: 1826 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1827 if (!amdgpu_dig_connector) 1828 goto failed; 1829 amdgpu_connector->con_priv = amdgpu_dig_connector; 1830 if (i2c_bus->valid) { 1831 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1832 if (!amdgpu_connector->ddc_bus) 1833 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1834 else 1835 ddc = &amdgpu_connector->ddc_bus->adapter; 1836 } 1837 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1838 &amdgpu_connector_dvi_funcs, 1839 connector_type, 1840 ddc); 1841 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1842 subpixel_order = SubPixelHorizontalRGB; 1843 drm_object_attach_property(&amdgpu_connector->base.base, 1844 adev->mode_info.coherent_mode_property, 1845 1); 1846 drm_object_attach_property(&amdgpu_connector->base.base, 1847 adev->mode_info.underscan_property, 1848 UNDERSCAN_OFF); 1849 drm_object_attach_property(&amdgpu_connector->base.base, 1850 adev->mode_info.underscan_hborder_property, 1851 0); 1852 drm_object_attach_property(&amdgpu_connector->base.base, 1853 adev->mode_info.underscan_vborder_property, 1854 0); 1855 drm_object_attach_property(&amdgpu_connector->base.base, 1856 dev->mode_config.scaling_mode_property, 1857 DRM_MODE_SCALE_NONE); 1858 1859 if (amdgpu_audio != 0) { 1860 drm_object_attach_property(&amdgpu_connector->base.base, 1861 adev->mode_info.audio_property, 1862 AMDGPU_AUDIO_AUTO); 1863 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1864 } 1865 drm_object_attach_property(&amdgpu_connector->base.base, 1866 adev->mode_info.dither_property, 1867 AMDGPU_FMT_DITHER_DISABLE); 1868 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1869 amdgpu_connector->dac_load_detect = true; 1870 drm_object_attach_property(&amdgpu_connector->base.base, 1871 adev->mode_info.load_detect_property, 1872 1); 1873 } 1874 connector->interlace_allowed = true; 1875 if (connector_type == DRM_MODE_CONNECTOR_DVII) 1876 connector->doublescan_allowed = true; 1877 else 1878 connector->doublescan_allowed = false; 1879 break; 1880 case DRM_MODE_CONNECTOR_HDMIA: 1881 case DRM_MODE_CONNECTOR_HDMIB: 1882 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1883 if (!amdgpu_dig_connector) 1884 goto failed; 1885 amdgpu_connector->con_priv = amdgpu_dig_connector; 1886 if (i2c_bus->valid) { 1887 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1888 if (!amdgpu_connector->ddc_bus) 1889 DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1890 else 1891 ddc = &amdgpu_connector->ddc_bus->adapter; 1892 } 1893 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1894 &amdgpu_connector_dvi_funcs, 1895 connector_type, 1896 ddc); 1897 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1898 drm_object_attach_property(&amdgpu_connector->base.base, 1899 adev->mode_info.coherent_mode_property, 1900 1); 1901 drm_object_attach_property(&amdgpu_connector->base.base, 1902 adev->mode_info.underscan_property, 1903 UNDERSCAN_OFF); 1904 drm_object_attach_property(&amdgpu_connector->base.base, 1905 adev->mode_info.underscan_hborder_property, 1906 0); 1907 drm_object_attach_property(&amdgpu_connector->base.base, 1908 adev->mode_info.underscan_vborder_property, 1909 0); 1910 drm_object_attach_property(&amdgpu_connector->base.base, 1911 dev->mode_config.scaling_mode_property, 1912 DRM_MODE_SCALE_NONE); 1913 if (amdgpu_audio != 0) { 1914 drm_object_attach_property(&amdgpu_connector->base.base, 1915 adev->mode_info.audio_property, 1916 AMDGPU_AUDIO_AUTO); 1917 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1918 } 1919 drm_object_attach_property(&amdgpu_connector->base.base, 1920 adev->mode_info.dither_property, 1921 AMDGPU_FMT_DITHER_DISABLE); 1922 subpixel_order = SubPixelHorizontalRGB; 1923 connector->interlace_allowed = true; 1924 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1925 connector->doublescan_allowed = true; 1926 else 1927 connector->doublescan_allowed = false; 1928 break; 1929 case DRM_MODE_CONNECTOR_DisplayPort: 1930 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1931 if (!amdgpu_dig_connector) 1932 goto failed; 1933 amdgpu_connector->con_priv = amdgpu_dig_connector; 1934 if (i2c_bus->valid) { 1935 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1936 if (amdgpu_connector->ddc_bus) { 1937 has_aux = true; 1938 ddc = &amdgpu_connector->ddc_bus->adapter; 1939 } else { 1940 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1941 } 1942 } 1943 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1944 &amdgpu_connector_dp_funcs, 1945 connector_type, 1946 ddc); 1947 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1948 subpixel_order = SubPixelHorizontalRGB; 1949 drm_object_attach_property(&amdgpu_connector->base.base, 1950 adev->mode_info.coherent_mode_property, 1951 1); 1952 drm_object_attach_property(&amdgpu_connector->base.base, 1953 adev->mode_info.underscan_property, 1954 UNDERSCAN_OFF); 1955 drm_object_attach_property(&amdgpu_connector->base.base, 1956 adev->mode_info.underscan_hborder_property, 1957 0); 1958 drm_object_attach_property(&amdgpu_connector->base.base, 1959 adev->mode_info.underscan_vborder_property, 1960 0); 1961 drm_object_attach_property(&amdgpu_connector->base.base, 1962 dev->mode_config.scaling_mode_property, 1963 DRM_MODE_SCALE_NONE); 1964 if (amdgpu_audio != 0) { 1965 drm_object_attach_property(&amdgpu_connector->base.base, 1966 adev->mode_info.audio_property, 1967 AMDGPU_AUDIO_AUTO); 1968 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1969 } 1970 drm_object_attach_property(&amdgpu_connector->base.base, 1971 adev->mode_info.dither_property, 1972 AMDGPU_FMT_DITHER_DISABLE); 1973 connector->interlace_allowed = true; 1974 /* in theory with a DP to VGA converter... */ 1975 connector->doublescan_allowed = false; 1976 break; 1977 case DRM_MODE_CONNECTOR_eDP: 1978 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1979 if (!amdgpu_dig_connector) 1980 goto failed; 1981 amdgpu_connector->con_priv = amdgpu_dig_connector; 1982 if (i2c_bus->valid) { 1983 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1984 if (amdgpu_connector->ddc_bus) { 1985 has_aux = true; 1986 ddc = &amdgpu_connector->ddc_bus->adapter; 1987 } else { 1988 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1989 } 1990 } 1991 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1992 &amdgpu_connector_edp_funcs, 1993 connector_type, 1994 ddc); 1995 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1996 drm_object_attach_property(&amdgpu_connector->base.base, 1997 dev->mode_config.scaling_mode_property, 1998 DRM_MODE_SCALE_FULLSCREEN); 1999 subpixel_order = SubPixelHorizontalRGB; 2000 connector->interlace_allowed = false; 2001 connector->doublescan_allowed = false; 2002 break; 2003 case DRM_MODE_CONNECTOR_LVDS: 2004 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 2005 if (!amdgpu_dig_connector) 2006 goto failed; 2007 amdgpu_connector->con_priv = amdgpu_dig_connector; 2008 if (i2c_bus->valid) { 2009 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 2010 if (!amdgpu_connector->ddc_bus) 2011 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 2012 else 2013 ddc = &amdgpu_connector->ddc_bus->adapter; 2014 } 2015 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 2016 &amdgpu_connector_lvds_funcs, 2017 connector_type, 2018 ddc); 2019 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); 2020 drm_object_attach_property(&amdgpu_connector->base.base, 2021 dev->mode_config.scaling_mode_property, 2022 DRM_MODE_SCALE_FULLSCREEN); 2023 subpixel_order = SubPixelHorizontalRGB; 2024 connector->interlace_allowed = false; 2025 connector->doublescan_allowed = false; 2026 break; 2027 } 2028 } 2029 2030 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) { 2031 if (i2c_bus->valid) { 2032 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 2033 DRM_CONNECTOR_POLL_DISCONNECT; 2034 } 2035 } else 2036 connector->polled = DRM_CONNECTOR_POLL_HPD; 2037 2038 connector->display_info.subpixel_order = subpixel_order; 2039 2040 if (has_aux) 2041 amdgpu_atombios_dp_aux_init(amdgpu_connector); 2042 2043 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort || 2044 connector_type == DRM_MODE_CONNECTOR_eDP) { 2045 drm_connector_attach_dp_subconnector_property(&amdgpu_connector->base); 2046 } 2047 2048 return; 2049 2050 failed: 2051 drm_connector_cleanup(connector); 2052 kfree(connector); 2053 } 2054