1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27 #include <drm/display/drm_dp_helper.h> 28 #include <drm/drm_crtc_helper.h> 29 #include <drm/drm_edid.h> 30 #include <drm/drm_modeset_helper_vtables.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/amdgpu_drm.h> 33 #include "amdgpu.h" 34 #include "atom.h" 35 #include "atombios_encoders.h" 36 #include "atombios_dp.h" 37 #include "amdgpu_connectors.h" 38 #include "amdgpu_i2c.h" 39 #include "amdgpu_display.h" 40 41 #include <linux/pm_runtime.h> 42 43 void amdgpu_connector_hotplug(struct drm_connector *connector) 44 { 45 struct drm_device *dev = connector->dev; 46 struct amdgpu_device *adev = drm_to_adev(dev); 47 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 48 49 /* bail if the connector does not have hpd pin, e.g., 50 * VGA, TV, etc. 51 */ 52 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) 53 return; 54 55 amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 56 57 /* if the connector is already off, don't turn it back on */ 58 if (connector->dpms != DRM_MODE_DPMS_ON) 59 return; 60 61 /* just deal with DP (not eDP) here. */ 62 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 63 struct amdgpu_connector_atom_dig *dig_connector = 64 amdgpu_connector->con_priv; 65 66 /* if existing sink type was not DP no need to retrain */ 67 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) 68 return; 69 70 /* first get sink type as it may be reset after (un)plug */ 71 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 72 /* don't do anything if sink is not display port, i.e., 73 * passive dp->(dvi|hdmi) adaptor 74 */ 75 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT && 76 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) && 77 amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 78 /* Don't start link training before we have the DPCD */ 79 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 80 return; 81 82 /* Turn the connector off and back on immediately, which 83 * will trigger link training 84 */ 85 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 86 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 87 } 88 } 89 } 90 91 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder) 92 { 93 struct drm_crtc *crtc = encoder->crtc; 94 95 if (crtc && crtc->enabled) { 96 drm_crtc_helper_set_mode(crtc, &crtc->mode, 97 crtc->x, crtc->y, crtc->primary->fb); 98 } 99 } 100 101 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) 102 { 103 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 104 struct amdgpu_connector_atom_dig *dig_connector; 105 int bpc = 8; 106 unsigned int mode_clock, max_tmds_clock; 107 108 switch (connector->connector_type) { 109 case DRM_MODE_CONNECTOR_DVII: 110 case DRM_MODE_CONNECTOR_HDMIB: 111 if (amdgpu_connector->use_digital) { 112 if (connector->display_info.is_hdmi) { 113 if (connector->display_info.bpc) 114 bpc = connector->display_info.bpc; 115 } 116 } 117 break; 118 case DRM_MODE_CONNECTOR_DVID: 119 case DRM_MODE_CONNECTOR_HDMIA: 120 if (connector->display_info.is_hdmi) { 121 if (connector->display_info.bpc) 122 bpc = connector->display_info.bpc; 123 } 124 break; 125 case DRM_MODE_CONNECTOR_DisplayPort: 126 dig_connector = amdgpu_connector->con_priv; 127 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 128 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || 129 connector->display_info.is_hdmi) { 130 if (connector->display_info.bpc) 131 bpc = connector->display_info.bpc; 132 } 133 break; 134 case DRM_MODE_CONNECTOR_eDP: 135 case DRM_MODE_CONNECTOR_LVDS: 136 if (connector->display_info.bpc) 137 bpc = connector->display_info.bpc; 138 else { 139 const struct drm_connector_helper_funcs *connector_funcs = 140 connector->helper_private; 141 struct drm_encoder *encoder = connector_funcs->best_encoder(connector); 142 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 143 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 144 145 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR) 146 bpc = 6; 147 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR) 148 bpc = 8; 149 } 150 break; 151 } 152 153 if (connector->display_info.is_hdmi) { 154 /* 155 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make 156 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at 157 * 12 bpc is always supported on hdmi deep color sinks, as this is 158 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. 159 */ 160 if (bpc > 12) { 161 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", 162 connector->name, bpc); 163 bpc = 12; 164 } 165 166 /* Any defined maximum tmds clock limit we must not exceed? */ 167 if (connector->display_info.max_tmds_clock > 0) { 168 /* mode_clock is clock in kHz for mode to be modeset on this connector */ 169 mode_clock = amdgpu_connector->pixelclock_for_modeset; 170 171 /* Maximum allowable input clock in kHz */ 172 max_tmds_clock = connector->display_info.max_tmds_clock; 173 174 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n", 175 connector->name, mode_clock, max_tmds_clock); 176 177 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ 178 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { 179 if ((connector->display_info.edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) && 180 (mode_clock * 5/4 <= max_tmds_clock)) 181 bpc = 10; 182 else 183 bpc = 8; 184 185 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", 186 connector->name, bpc); 187 } 188 189 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { 190 bpc = 8; 191 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", 192 connector->name, bpc); 193 } 194 } else if (bpc > 8) { 195 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ 196 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", 197 connector->name); 198 bpc = 8; 199 } 200 } 201 202 if ((amdgpu_deep_color == 0) && (bpc > 8)) { 203 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n", 204 connector->name); 205 bpc = 8; 206 } 207 208 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", 209 connector->name, connector->display_info.bpc, bpc); 210 211 return bpc; 212 } 213 214 static void 215 amdgpu_connector_update_scratch_regs(struct drm_connector *connector, 216 enum drm_connector_status status) 217 { 218 struct drm_encoder *best_encoder; 219 struct drm_encoder *encoder; 220 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 221 bool connected; 222 223 best_encoder = connector_funcs->best_encoder(connector); 224 225 drm_connector_for_each_possible_encoder(connector, encoder) { 226 if ((encoder == best_encoder) && (status == connector_status_connected)) 227 connected = true; 228 else 229 connected = false; 230 231 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected); 232 } 233 } 234 235 static struct drm_encoder * 236 amdgpu_connector_find_encoder(struct drm_connector *connector, 237 int encoder_type) 238 { 239 struct drm_encoder *encoder; 240 241 drm_connector_for_each_possible_encoder(connector, encoder) { 242 if (encoder->encoder_type == encoder_type) 243 return encoder; 244 } 245 246 return NULL; 247 } 248 249 static const struct drm_edid * 250 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) 251 { 252 return drm_edid_dup(adev->mode_info.bios_hardcoded_edid); 253 } 254 255 static void amdgpu_connector_get_edid(struct drm_connector *connector) 256 { 257 struct drm_device *dev = connector->dev; 258 struct amdgpu_device *adev = drm_to_adev(dev); 259 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 260 261 if (amdgpu_connector->edid) 262 return; 263 264 /* on hw with routers, select right port */ 265 if (amdgpu_connector->router.ddc_valid) 266 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 267 268 if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 269 ENCODER_OBJECT_ID_NONE) && 270 amdgpu_connector->ddc_bus->has_aux) { 271 amdgpu_connector->edid = drm_edid_read_ddc(connector, 272 &amdgpu_connector->ddc_bus->aux.ddc); 273 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 274 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 275 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; 276 277 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 278 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && 279 amdgpu_connector->ddc_bus->has_aux) 280 amdgpu_connector->edid = drm_edid_read_ddc(connector, 281 &amdgpu_connector->ddc_bus->aux.ddc); 282 else if (amdgpu_connector->ddc_bus) 283 amdgpu_connector->edid = drm_edid_read_ddc(connector, 284 &amdgpu_connector->ddc_bus->adapter); 285 } else if (amdgpu_connector->ddc_bus) { 286 amdgpu_connector->edid = drm_edid_read_ddc(connector, 287 &amdgpu_connector->ddc_bus->adapter); 288 } 289 290 if (!amdgpu_connector->edid) { 291 /* some laptops provide a hardcoded edid in rom for LCDs */ 292 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || 293 (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) { 294 amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev); 295 drm_edid_connector_update(connector, amdgpu_connector->edid); 296 } 297 } 298 } 299 300 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) 301 { 302 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 303 int ret; 304 305 if (amdgpu_connector->edid) { 306 drm_edid_connector_update(connector, amdgpu_connector->edid); 307 ret = drm_edid_connector_add_modes(connector); 308 return ret; 309 } 310 drm_edid_connector_update(connector, NULL); 311 return 0; 312 } 313 314 static struct drm_encoder * 315 amdgpu_connector_best_single_encoder(struct drm_connector *connector) 316 { 317 struct drm_encoder *encoder; 318 319 /* pick the first one */ 320 drm_connector_for_each_possible_encoder(connector, encoder) 321 return encoder; 322 323 return NULL; 324 } 325 326 static void amdgpu_get_native_mode(struct drm_connector *connector) 327 { 328 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 329 struct amdgpu_encoder *amdgpu_encoder; 330 331 if (encoder == NULL) 332 return; 333 334 amdgpu_encoder = to_amdgpu_encoder(encoder); 335 336 if (!list_empty(&connector->probed_modes)) { 337 struct drm_display_mode *preferred_mode = 338 list_first_entry(&connector->probed_modes, 339 struct drm_display_mode, head); 340 341 amdgpu_encoder->native_mode = *preferred_mode; 342 } else { 343 amdgpu_encoder->native_mode.clock = 0; 344 } 345 } 346 347 static struct drm_display_mode * 348 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder) 349 { 350 struct drm_device *dev = encoder->dev; 351 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 352 struct drm_display_mode *mode = NULL; 353 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 354 355 if (native_mode->hdisplay != 0 && 356 native_mode->vdisplay != 0 && 357 native_mode->clock != 0) { 358 mode = drm_mode_duplicate(dev, native_mode); 359 if (!mode) 360 return NULL; 361 362 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 363 drm_mode_set_name(mode); 364 365 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); 366 } else if (native_mode->hdisplay != 0 && 367 native_mode->vdisplay != 0) { 368 /* mac laptops without an edid */ 369 /* Note that this is not necessarily the exact panel mode, 370 * but an approximation based on the cvt formula. For these 371 * systems we should ideally read the mode info out of the 372 * registers or add a mode table, but this works and is much 373 * simpler. 374 */ 375 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); 376 if (!mode) 377 return NULL; 378 379 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 380 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); 381 } 382 return mode; 383 } 384 385 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, 386 struct drm_connector *connector) 387 { 388 struct drm_device *dev = encoder->dev; 389 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 390 struct drm_display_mode *mode = NULL; 391 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 392 int i; 393 int n; 394 struct mode_size { 395 char name[DRM_DISPLAY_MODE_LEN]; 396 int w; 397 int h; 398 } common_modes[] = { 399 { "640x480", 640, 480}, 400 { "800x600", 800, 600}, 401 { "1024x768", 1024, 768}, 402 { "1280x720", 1280, 720}, 403 { "1280x800", 1280, 800}, 404 {"1280x1024", 1280, 1024}, 405 { "1440x900", 1440, 900}, 406 {"1680x1050", 1680, 1050}, 407 {"1600x1200", 1600, 1200}, 408 {"1920x1080", 1920, 1080}, 409 {"1920x1200", 1920, 1200} 410 }; 411 412 n = ARRAY_SIZE(common_modes); 413 414 for (i = 0; i < n; i++) { 415 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 416 if (common_modes[i].w > 1024 || 417 common_modes[i].h > 768) 418 continue; 419 } 420 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 421 if (common_modes[i].w > native_mode->hdisplay || 422 common_modes[i].h > native_mode->vdisplay || 423 (common_modes[i].w == native_mode->hdisplay && 424 common_modes[i].h == native_mode->vdisplay)) 425 continue; 426 } 427 428 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); 429 if (!mode) 430 return; 431 strscpy(mode->name, common_modes[i].name, DRM_DISPLAY_MODE_LEN); 432 433 drm_mode_probed_add(connector, mode); 434 } 435 } 436 437 static int amdgpu_connector_set_property(struct drm_connector *connector, 438 struct drm_property *property, 439 uint64_t val) 440 { 441 struct drm_device *dev = connector->dev; 442 struct amdgpu_device *adev = drm_to_adev(dev); 443 struct drm_encoder *encoder; 444 struct amdgpu_encoder *amdgpu_encoder; 445 446 if (property == adev->mode_info.coherent_mode_property) { 447 struct amdgpu_encoder_atom_dig *dig; 448 bool new_coherent_mode; 449 450 /* need to find digital encoder on connector */ 451 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 452 if (!encoder) 453 return 0; 454 455 amdgpu_encoder = to_amdgpu_encoder(encoder); 456 457 if (!amdgpu_encoder->enc_priv) 458 return 0; 459 460 dig = amdgpu_encoder->enc_priv; 461 new_coherent_mode = val ? true : false; 462 if (dig->coherent_mode != new_coherent_mode) { 463 dig->coherent_mode = new_coherent_mode; 464 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 465 } 466 } 467 468 if (property == adev->mode_info.audio_property) { 469 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 470 /* need to find digital encoder on connector */ 471 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 472 if (!encoder) 473 return 0; 474 475 amdgpu_encoder = to_amdgpu_encoder(encoder); 476 477 if (amdgpu_connector->audio != val) { 478 amdgpu_connector->audio = val; 479 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 480 } 481 } 482 483 if (property == adev->mode_info.dither_property) { 484 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 485 /* need to find digital encoder on connector */ 486 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 487 if (!encoder) 488 return 0; 489 490 amdgpu_encoder = to_amdgpu_encoder(encoder); 491 492 if (amdgpu_connector->dither != val) { 493 amdgpu_connector->dither = val; 494 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 495 } 496 } 497 498 if (property == adev->mode_info.underscan_property) { 499 /* need to find digital encoder on connector */ 500 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 501 if (!encoder) 502 return 0; 503 504 amdgpu_encoder = to_amdgpu_encoder(encoder); 505 506 if (amdgpu_encoder->underscan_type != val) { 507 amdgpu_encoder->underscan_type = val; 508 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 509 } 510 } 511 512 if (property == adev->mode_info.underscan_hborder_property) { 513 /* need to find digital encoder on connector */ 514 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 515 if (!encoder) 516 return 0; 517 518 amdgpu_encoder = to_amdgpu_encoder(encoder); 519 520 if (amdgpu_encoder->underscan_hborder != val) { 521 amdgpu_encoder->underscan_hborder = val; 522 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 523 } 524 } 525 526 if (property == adev->mode_info.underscan_vborder_property) { 527 /* need to find digital encoder on connector */ 528 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 529 if (!encoder) 530 return 0; 531 532 amdgpu_encoder = to_amdgpu_encoder(encoder); 533 534 if (amdgpu_encoder->underscan_vborder != val) { 535 amdgpu_encoder->underscan_vborder = val; 536 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 537 } 538 } 539 540 if (property == adev->mode_info.load_detect_property) { 541 struct amdgpu_connector *amdgpu_connector = 542 to_amdgpu_connector(connector); 543 544 if (val == 0) 545 amdgpu_connector->dac_load_detect = false; 546 else 547 amdgpu_connector->dac_load_detect = true; 548 } 549 550 if (property == dev->mode_config.scaling_mode_property) { 551 enum amdgpu_rmx_type rmx_type; 552 553 if (connector->encoder) { 554 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 555 } else { 556 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 557 558 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 559 } 560 561 switch (val) { 562 default: 563 case DRM_MODE_SCALE_NONE: 564 rmx_type = RMX_OFF; 565 break; 566 case DRM_MODE_SCALE_CENTER: 567 rmx_type = RMX_CENTER; 568 break; 569 case DRM_MODE_SCALE_ASPECT: 570 rmx_type = RMX_ASPECT; 571 break; 572 case DRM_MODE_SCALE_FULLSCREEN: 573 rmx_type = RMX_FULL; 574 break; 575 } 576 577 if (amdgpu_encoder->rmx_type == rmx_type) 578 return 0; 579 580 if ((rmx_type != DRM_MODE_SCALE_NONE) && 581 (amdgpu_encoder->native_mode.clock == 0)) 582 return 0; 583 584 amdgpu_encoder->rmx_type = rmx_type; 585 586 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 587 } 588 589 return 0; 590 } 591 592 static void 593 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder, 594 struct drm_connector *connector) 595 { 596 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 597 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 598 struct drm_display_mode *t, *mode; 599 600 /* If the EDID preferred mode doesn't match the native mode, use it */ 601 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 602 if (mode->type & DRM_MODE_TYPE_PREFERRED) { 603 if (mode->hdisplay != native_mode->hdisplay || 604 mode->vdisplay != native_mode->vdisplay) 605 drm_mode_copy(native_mode, mode); 606 } 607 } 608 609 /* Try to get native mode details from EDID if necessary */ 610 if (!native_mode->clock) { 611 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 612 if (mode->hdisplay == native_mode->hdisplay && 613 mode->vdisplay == native_mode->vdisplay) { 614 drm_mode_copy(native_mode, mode); 615 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); 616 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); 617 break; 618 } 619 } 620 } 621 622 if (!native_mode->clock) { 623 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n"); 624 amdgpu_encoder->rmx_type = RMX_OFF; 625 } 626 } 627 628 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) 629 { 630 struct drm_encoder *encoder; 631 int ret = 0; 632 struct drm_display_mode *mode; 633 634 amdgpu_connector_get_edid(connector); 635 ret = amdgpu_connector_ddc_get_modes(connector); 636 if (ret > 0) { 637 encoder = amdgpu_connector_best_single_encoder(connector); 638 if (encoder) { 639 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 640 /* add scaled modes */ 641 amdgpu_connector_add_common_modes(encoder, connector); 642 } 643 return ret; 644 } 645 646 encoder = amdgpu_connector_best_single_encoder(connector); 647 if (!encoder) 648 return 0; 649 650 /* we have no EDID modes */ 651 mode = amdgpu_connector_lcd_native_mode(encoder); 652 if (mode) { 653 ret = 1; 654 drm_mode_probed_add(connector, mode); 655 /* add the width/height from vbios tables if available */ 656 connector->display_info.width_mm = mode->width_mm; 657 connector->display_info.height_mm = mode->height_mm; 658 /* add scaled modes */ 659 amdgpu_connector_add_common_modes(encoder, connector); 660 } 661 662 return ret; 663 } 664 665 static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, 666 const struct drm_display_mode *mode) 667 { 668 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 669 670 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 671 return MODE_PANEL; 672 673 if (encoder) { 674 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 675 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 676 677 /* AVIVO hardware supports downscaling modes larger than the panel 678 * to the panel size, but I'm not sure this is desirable. 679 */ 680 if ((mode->hdisplay > native_mode->hdisplay) || 681 (mode->vdisplay > native_mode->vdisplay)) 682 return MODE_PANEL; 683 684 /* if scaling is disabled, block non-native modes */ 685 if (amdgpu_encoder->rmx_type == RMX_OFF) { 686 if ((mode->hdisplay != native_mode->hdisplay) || 687 (mode->vdisplay != native_mode->vdisplay)) 688 return MODE_PANEL; 689 } 690 } 691 692 return MODE_OK; 693 } 694 695 static enum drm_connector_status 696 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force) 697 { 698 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 699 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 700 enum drm_connector_status ret = connector_status_disconnected; 701 int r; 702 703 if (!drm_kms_helper_is_poll_worker()) { 704 r = pm_runtime_get_sync(connector->dev->dev); 705 if (r < 0) { 706 pm_runtime_put_autosuspend(connector->dev->dev); 707 return connector_status_disconnected; 708 } 709 } 710 711 if (encoder) { 712 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 713 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 714 715 /* check if panel is valid */ 716 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 717 ret = connector_status_connected; 718 719 } 720 721 /* check for edid as well */ 722 amdgpu_connector_get_edid(connector); 723 if (amdgpu_connector->edid) 724 ret = connector_status_connected; 725 /* check acpi lid status ??? */ 726 727 amdgpu_connector_update_scratch_regs(connector, ret); 728 729 if (!drm_kms_helper_is_poll_worker()) 730 pm_runtime_put_autosuspend(connector->dev->dev); 731 732 return ret; 733 } 734 735 static void amdgpu_connector_unregister(struct drm_connector *connector) 736 { 737 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 738 739 if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) { 740 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); 741 amdgpu_connector->ddc_bus->has_aux = false; 742 } 743 } 744 745 static void amdgpu_connector_destroy(struct drm_connector *connector) 746 { 747 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 748 749 drm_edid_free(amdgpu_connector->edid); 750 kfree(amdgpu_connector->con_priv); 751 drm_connector_unregister(connector); 752 drm_connector_cleanup(connector); 753 kfree(connector); 754 } 755 756 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector, 757 struct drm_property *property, 758 uint64_t value) 759 { 760 struct drm_device *dev = connector->dev; 761 struct amdgpu_encoder *amdgpu_encoder; 762 enum amdgpu_rmx_type rmx_type; 763 764 DRM_DEBUG_KMS("\n"); 765 if (property != dev->mode_config.scaling_mode_property) 766 return 0; 767 768 if (connector->encoder) 769 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 770 else { 771 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 772 773 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 774 } 775 776 switch (value) { 777 case DRM_MODE_SCALE_NONE: 778 rmx_type = RMX_OFF; 779 break; 780 case DRM_MODE_SCALE_CENTER: 781 rmx_type = RMX_CENTER; 782 break; 783 case DRM_MODE_SCALE_ASPECT: 784 rmx_type = RMX_ASPECT; 785 break; 786 default: 787 case DRM_MODE_SCALE_FULLSCREEN: 788 rmx_type = RMX_FULL; 789 break; 790 } 791 792 if (amdgpu_encoder->rmx_type == rmx_type) 793 return 0; 794 795 amdgpu_encoder->rmx_type = rmx_type; 796 797 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 798 return 0; 799 } 800 801 802 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = { 803 .get_modes = amdgpu_connector_lvds_get_modes, 804 .mode_valid = amdgpu_connector_lvds_mode_valid, 805 .best_encoder = amdgpu_connector_best_single_encoder, 806 }; 807 808 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = { 809 .dpms = drm_helper_connector_dpms, 810 .detect = amdgpu_connector_lvds_detect, 811 .fill_modes = drm_helper_probe_single_connector_modes, 812 .early_unregister = amdgpu_connector_unregister, 813 .destroy = amdgpu_connector_destroy, 814 .set_property = amdgpu_connector_set_lcd_property, 815 }; 816 817 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) 818 { 819 int ret; 820 821 amdgpu_connector_get_edid(connector); 822 ret = amdgpu_connector_ddc_get_modes(connector); 823 amdgpu_get_native_mode(connector); 824 825 return ret; 826 } 827 828 static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector, 829 const struct drm_display_mode *mode) 830 { 831 struct drm_device *dev = connector->dev; 832 struct amdgpu_device *adev = drm_to_adev(dev); 833 834 /* XXX check mode bandwidth */ 835 836 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 837 return MODE_CLOCK_HIGH; 838 839 return MODE_OK; 840 } 841 842 static enum drm_connector_status 843 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) 844 { 845 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 846 struct drm_encoder *encoder; 847 const struct drm_encoder_helper_funcs *encoder_funcs; 848 bool dret = false; 849 enum drm_connector_status ret = connector_status_disconnected; 850 int r; 851 852 if (!drm_kms_helper_is_poll_worker()) { 853 r = pm_runtime_get_sync(connector->dev->dev); 854 if (r < 0) { 855 pm_runtime_put_autosuspend(connector->dev->dev); 856 return connector_status_disconnected; 857 } 858 } 859 860 encoder = amdgpu_connector_best_single_encoder(connector); 861 if (!encoder) 862 ret = connector_status_disconnected; 863 864 if (amdgpu_connector->ddc_bus) 865 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 866 if (dret) { 867 amdgpu_connector->detected_by_load = false; 868 drm_edid_free(amdgpu_connector->edid); 869 amdgpu_connector_get_edid(connector); 870 871 if (!amdgpu_connector->edid) { 872 drm_err(connector->dev, 873 "%s: probed a monitor but no|invalid EDID\n", 874 connector->name); 875 ret = connector_status_connected; 876 } else { 877 amdgpu_connector->use_digital = 878 drm_edid_is_digital(amdgpu_connector->edid); 879 880 /* some oems have boards with separate digital and analog connectors 881 * with a shared ddc line (often vga + hdmi) 882 */ 883 if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) { 884 drm_edid_free(amdgpu_connector->edid); 885 ret = connector_status_disconnected; 886 } else { 887 ret = connector_status_connected; 888 } 889 } 890 } else { 891 892 /* if we aren't forcing don't do destructive polling */ 893 if (!force) { 894 /* only return the previous status if we last 895 * detected a monitor via load. 896 */ 897 if (amdgpu_connector->detected_by_load) 898 ret = connector->status; 899 goto out; 900 } 901 902 if (amdgpu_connector->dac_load_detect && encoder) { 903 encoder_funcs = encoder->helper_private; 904 ret = encoder_funcs->detect(encoder, connector); 905 if (ret != connector_status_disconnected) 906 amdgpu_connector->detected_by_load = true; 907 } 908 } 909 910 amdgpu_connector_update_scratch_regs(connector, ret); 911 912 out: 913 if (!drm_kms_helper_is_poll_worker()) 914 pm_runtime_put_autosuspend(connector->dev->dev); 915 916 return ret; 917 } 918 919 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = { 920 .get_modes = amdgpu_connector_vga_get_modes, 921 .mode_valid = amdgpu_connector_vga_mode_valid, 922 .best_encoder = amdgpu_connector_best_single_encoder, 923 }; 924 925 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = { 926 .dpms = drm_helper_connector_dpms, 927 .detect = amdgpu_connector_vga_detect, 928 .fill_modes = drm_helper_probe_single_connector_modes, 929 .early_unregister = amdgpu_connector_unregister, 930 .destroy = amdgpu_connector_destroy, 931 .set_property = amdgpu_connector_set_property, 932 }; 933 934 static bool 935 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector) 936 { 937 struct drm_device *dev = connector->dev; 938 struct amdgpu_device *adev = drm_to_adev(dev); 939 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 940 enum drm_connector_status status; 941 942 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) { 943 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) 944 status = connector_status_connected; 945 else 946 status = connector_status_disconnected; 947 if (connector->status == status) 948 return true; 949 } 950 951 return false; 952 } 953 954 static void amdgpu_connector_shared_ddc(enum drm_connector_status *status, 955 struct drm_connector *connector, 956 struct amdgpu_connector *amdgpu_connector) 957 { 958 struct drm_connector *list_connector; 959 struct drm_connector_list_iter iter; 960 struct amdgpu_connector *list_amdgpu_connector; 961 struct drm_device *dev = connector->dev; 962 struct amdgpu_device *adev = drm_to_adev(dev); 963 964 if (amdgpu_connector->shared_ddc && *status == connector_status_connected) { 965 drm_connector_list_iter_begin(dev, &iter); 966 drm_for_each_connector_iter(list_connector, 967 &iter) { 968 if (connector == list_connector) 969 continue; 970 list_amdgpu_connector = to_amdgpu_connector(list_connector); 971 if (list_amdgpu_connector->shared_ddc && 972 list_amdgpu_connector->ddc_bus->rec.i2c_id == 973 amdgpu_connector->ddc_bus->rec.i2c_id) { 974 /* cases where both connectors are digital */ 975 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { 976 /* hpd is our only option in this case */ 977 if (!amdgpu_display_hpd_sense(adev, 978 amdgpu_connector->hpd.hpd)) { 979 drm_edid_free(amdgpu_connector->edid); 980 *status = connector_status_disconnected; 981 } 982 } 983 } 984 } 985 drm_connector_list_iter_end(&iter); 986 } 987 } 988 989 /* 990 * DVI is complicated 991 * Do a DDC probe, if DDC probe passes, get the full EDID so 992 * we can do analog/digital monitor detection at this point. 993 * If the monitor is an analog monitor or we got no DDC, 994 * we need to find the DAC encoder object for this connector. 995 * If we got no DDC, we do load detection on the DAC encoder object. 996 * If we got analog DDC or load detection passes on the DAC encoder 997 * we have to check if this analog encoder is shared with anyone else (TV) 998 * if its shared we have to set the other connector to disconnected. 999 */ 1000 static enum drm_connector_status 1001 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) 1002 { 1003 struct drm_device *dev = connector->dev; 1004 struct amdgpu_device *adev = drm_to_adev(dev); 1005 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1006 const struct drm_encoder_helper_funcs *encoder_funcs; 1007 int r; 1008 enum drm_connector_status ret = connector_status_disconnected; 1009 bool dret = false, broken_edid = false; 1010 1011 if (!drm_kms_helper_is_poll_worker()) { 1012 r = pm_runtime_get_sync(connector->dev->dev); 1013 if (r < 0) { 1014 pm_runtime_put_autosuspend(connector->dev->dev); 1015 return connector_status_disconnected; 1016 } 1017 } 1018 1019 if (amdgpu_connector->detected_hpd_without_ddc) { 1020 force = true; 1021 amdgpu_connector->detected_hpd_without_ddc = false; 1022 } 1023 1024 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1025 ret = connector->status; 1026 goto exit; 1027 } 1028 1029 if (amdgpu_connector->ddc_bus) { 1030 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 1031 1032 /* Sometimes the pins required for the DDC probe on DVI 1033 * connectors don't make contact at the same time that the ones 1034 * for HPD do. If the DDC probe fails even though we had an HPD 1035 * signal, try again later 1036 */ 1037 if (!dret && !force && 1038 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1039 DRM_DEBUG_KMS("hpd detected without ddc, retrying in 1 second\n"); 1040 amdgpu_connector->detected_hpd_without_ddc = true; 1041 schedule_delayed_work(&adev->hotplug_work, 1042 msecs_to_jiffies(1000)); 1043 goto exit; 1044 } 1045 } 1046 if (dret) { 1047 amdgpu_connector->detected_by_load = false; 1048 drm_edid_free(amdgpu_connector->edid); 1049 amdgpu_connector_get_edid(connector); 1050 1051 if (!amdgpu_connector->edid) { 1052 drm_err(adev_to_drm(adev), "%s: probed a monitor but no|invalid EDID\n", 1053 connector->name); 1054 ret = connector_status_connected; 1055 broken_edid = true; /* defer use_digital to later */ 1056 } else { 1057 amdgpu_connector->use_digital = 1058 drm_edid_is_digital(amdgpu_connector->edid); 1059 1060 /* some oems have boards with separate digital and analog connectors 1061 * with a shared ddc line (often vga + hdmi) 1062 */ 1063 if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) { 1064 drm_edid_free(amdgpu_connector->edid); 1065 ret = connector_status_disconnected; 1066 } else { 1067 ret = connector_status_connected; 1068 } 1069 1070 /* This gets complicated. We have boards with VGA + HDMI with a 1071 * shared DDC line and we have boards with DVI-D + HDMI with a shared 1072 * DDC line. The latter is more complex because with DVI<->HDMI adapters 1073 * you don't really know what's connected to which port as both are digital. 1074 */ 1075 amdgpu_connector_shared_ddc(&ret, connector, amdgpu_connector); 1076 } 1077 } 1078 1079 if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true)) 1080 goto out; 1081 1082 /* DVI-D and HDMI-A are digital only */ 1083 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) || 1084 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)) 1085 goto out; 1086 1087 /* if we aren't forcing don't do destructive polling */ 1088 if (!force) { 1089 /* only return the previous status if we last 1090 * detected a monitor via load. 1091 */ 1092 if (amdgpu_connector->detected_by_load) 1093 ret = connector->status; 1094 goto out; 1095 } 1096 1097 /* find analog encoder */ 1098 if (amdgpu_connector->dac_load_detect) { 1099 struct drm_encoder *encoder; 1100 1101 drm_connector_for_each_possible_encoder(connector, encoder) { 1102 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && 1103 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) 1104 continue; 1105 1106 encoder_funcs = encoder->helper_private; 1107 if (encoder_funcs->detect) { 1108 if (!broken_edid) { 1109 if (ret != connector_status_connected) { 1110 /* deal with analog monitors without DDC */ 1111 ret = encoder_funcs->detect(encoder, connector); 1112 if (ret == connector_status_connected) { 1113 amdgpu_connector->use_digital = false; 1114 } 1115 if (ret != connector_status_disconnected) 1116 amdgpu_connector->detected_by_load = true; 1117 } 1118 } else { 1119 enum drm_connector_status lret; 1120 /* assume digital unless load detected otherwise */ 1121 amdgpu_connector->use_digital = true; 1122 lret = encoder_funcs->detect(encoder, connector); 1123 DRM_DEBUG_KMS("load_detect %x returned: %x\n", 1124 encoder->encoder_type, lret); 1125 if (lret == connector_status_connected) 1126 amdgpu_connector->use_digital = false; 1127 } 1128 break; 1129 } 1130 } 1131 } 1132 1133 out: 1134 /* updated in get modes as well since we need to know if it's analog or digital */ 1135 amdgpu_connector_update_scratch_regs(connector, ret); 1136 1137 exit: 1138 if (!drm_kms_helper_is_poll_worker()) 1139 pm_runtime_put_autosuspend(connector->dev->dev); 1140 1141 return ret; 1142 } 1143 1144 /* okay need to be smart in here about which encoder to pick */ 1145 static struct drm_encoder * 1146 amdgpu_connector_dvi_encoder(struct drm_connector *connector) 1147 { 1148 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1149 struct drm_encoder *encoder; 1150 1151 drm_connector_for_each_possible_encoder(connector, encoder) { 1152 if (amdgpu_connector->use_digital == true) { 1153 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) 1154 return encoder; 1155 } else { 1156 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC || 1157 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1158 return encoder; 1159 } 1160 } 1161 1162 /* see if we have a default encoder TODO */ 1163 1164 /* then check use digitial */ 1165 /* pick the first one */ 1166 drm_connector_for_each_possible_encoder(connector, encoder) 1167 return encoder; 1168 1169 return NULL; 1170 } 1171 1172 static void amdgpu_connector_dvi_force(struct drm_connector *connector) 1173 { 1174 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1175 1176 if (connector->force == DRM_FORCE_ON) 1177 amdgpu_connector->use_digital = false; 1178 if (connector->force == DRM_FORCE_ON_DIGITAL) 1179 amdgpu_connector->use_digital = true; 1180 } 1181 1182 /** 1183 * amdgpu_max_hdmi_pixel_clock - Return max supported HDMI (TMDS) pixel clock 1184 * @adev: pointer to amdgpu_device 1185 * 1186 * Return: maximum supported HDMI (TMDS) pixel clock in KHz. 1187 */ 1188 static int amdgpu_max_hdmi_pixel_clock(const struct amdgpu_device *adev) 1189 { 1190 if (adev->asic_type >= CHIP_POLARIS10) 1191 return 600000; 1192 else if (adev->asic_type >= CHIP_TONGA) 1193 return 300000; 1194 else 1195 return 297000; 1196 } 1197 1198 /** 1199 * amdgpu_connector_dvi_mode_valid - Validate a mode on DVI/HDMI connectors 1200 * @connector: DRM connector to validate the mode on 1201 * @mode: display mode to validate 1202 * 1203 * Validate the given display mode on DVI and HDMI connectors, including 1204 * analog signals on DVI-I. 1205 * 1206 * Return: drm_mode_status indicating whether the mode is valid. 1207 */ 1208 static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, 1209 const struct drm_display_mode *mode) 1210 { 1211 struct drm_device *dev = connector->dev; 1212 struct amdgpu_device *adev = drm_to_adev(dev); 1213 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1214 const int max_hdmi_pixel_clock = amdgpu_max_hdmi_pixel_clock(adev); 1215 const int max_dvi_single_link_pixel_clock = 165000; 1216 int max_digital_pixel_clock_khz; 1217 1218 /* XXX check mode bandwidth */ 1219 1220 if (amdgpu_connector->use_digital) { 1221 switch (amdgpu_connector->connector_object_id) { 1222 case CONNECTOR_OBJECT_ID_HDMI_TYPE_A: 1223 max_digital_pixel_clock_khz = max_hdmi_pixel_clock; 1224 break; 1225 case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I: 1226 case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D: 1227 max_digital_pixel_clock_khz = max_dvi_single_link_pixel_clock; 1228 break; 1229 case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I: 1230 case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D: 1231 case CONNECTOR_OBJECT_ID_HDMI_TYPE_B: 1232 max_digital_pixel_clock_khz = max_dvi_single_link_pixel_clock * 2; 1233 break; 1234 } 1235 1236 /* When the display EDID claims that it's an HDMI display, 1237 * we use the HDMI encoder mode of the display HW, 1238 * so we should verify against the max HDMI clock here. 1239 */ 1240 if (connector->display_info.is_hdmi) 1241 max_digital_pixel_clock_khz = max_hdmi_pixel_clock; 1242 1243 if (mode->clock > max_digital_pixel_clock_khz) 1244 return MODE_CLOCK_HIGH; 1245 } 1246 1247 /* check against the max pixel clock */ 1248 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 1249 return MODE_CLOCK_HIGH; 1250 1251 return MODE_OK; 1252 } 1253 1254 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = { 1255 .get_modes = amdgpu_connector_vga_get_modes, 1256 .mode_valid = amdgpu_connector_dvi_mode_valid, 1257 .best_encoder = amdgpu_connector_dvi_encoder, 1258 }; 1259 1260 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = { 1261 .dpms = drm_helper_connector_dpms, 1262 .detect = amdgpu_connector_dvi_detect, 1263 .fill_modes = drm_helper_probe_single_connector_modes, 1264 .set_property = amdgpu_connector_set_property, 1265 .early_unregister = amdgpu_connector_unregister, 1266 .destroy = amdgpu_connector_destroy, 1267 .force = amdgpu_connector_dvi_force, 1268 }; 1269 1270 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) 1271 { 1272 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1273 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1274 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1275 int ret; 1276 1277 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1278 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1279 struct drm_display_mode *mode; 1280 1281 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1282 if (!amdgpu_dig_connector->edp_on) 1283 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1284 ATOM_TRANSMITTER_ACTION_POWER_ON); 1285 amdgpu_connector_get_edid(connector); 1286 ret = amdgpu_connector_ddc_get_modes(connector); 1287 if (!amdgpu_dig_connector->edp_on) 1288 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1289 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1290 } else { 1291 /* need to setup ddc on the bridge */ 1292 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1293 ENCODER_OBJECT_ID_NONE) { 1294 if (encoder) 1295 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1296 } 1297 amdgpu_connector_get_edid(connector); 1298 ret = amdgpu_connector_ddc_get_modes(connector); 1299 } 1300 1301 if (ret > 0) { 1302 if (encoder) { 1303 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 1304 /* add scaled modes */ 1305 amdgpu_connector_add_common_modes(encoder, connector); 1306 } 1307 return ret; 1308 } 1309 1310 if (!encoder) 1311 return 0; 1312 1313 /* we have no EDID modes */ 1314 mode = amdgpu_connector_lcd_native_mode(encoder); 1315 if (mode) { 1316 ret = 1; 1317 drm_mode_probed_add(connector, mode); 1318 /* add the width/height from vbios tables if available */ 1319 connector->display_info.width_mm = mode->width_mm; 1320 connector->display_info.height_mm = mode->height_mm; 1321 /* add scaled modes */ 1322 amdgpu_connector_add_common_modes(encoder, connector); 1323 } 1324 } else { 1325 /* need to setup ddc on the bridge */ 1326 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1327 ENCODER_OBJECT_ID_NONE) { 1328 if (encoder) 1329 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1330 } 1331 amdgpu_connector_get_edid(connector); 1332 ret = amdgpu_connector_ddc_get_modes(connector); 1333 1334 amdgpu_get_native_mode(connector); 1335 } 1336 1337 return ret; 1338 } 1339 1340 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) 1341 { 1342 struct drm_encoder *encoder; 1343 struct amdgpu_encoder *amdgpu_encoder; 1344 1345 drm_connector_for_each_possible_encoder(connector, encoder) { 1346 amdgpu_encoder = to_amdgpu_encoder(encoder); 1347 1348 switch (amdgpu_encoder->encoder_id) { 1349 case ENCODER_OBJECT_ID_TRAVIS: 1350 case ENCODER_OBJECT_ID_NUTMEG: 1351 return amdgpu_encoder->encoder_id; 1352 default: 1353 break; 1354 } 1355 } 1356 1357 return ENCODER_OBJECT_ID_NONE; 1358 } 1359 1360 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) 1361 { 1362 struct drm_encoder *encoder; 1363 struct amdgpu_encoder *amdgpu_encoder; 1364 bool found = false; 1365 1366 drm_connector_for_each_possible_encoder(connector, encoder) { 1367 amdgpu_encoder = to_amdgpu_encoder(encoder); 1368 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) 1369 found = true; 1370 } 1371 1372 return found; 1373 } 1374 1375 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector) 1376 { 1377 struct drm_device *dev = connector->dev; 1378 struct amdgpu_device *adev = drm_to_adev(dev); 1379 1380 if ((adev->clock.default_dispclk >= 53900) && 1381 amdgpu_connector_encoder_is_hbr2(connector)) { 1382 return true; 1383 } 1384 1385 return false; 1386 } 1387 1388 static enum drm_connector_status 1389 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) 1390 { 1391 struct drm_device *dev = connector->dev; 1392 struct amdgpu_device *adev = drm_to_adev(dev); 1393 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1394 enum drm_connector_status ret = connector_status_disconnected; 1395 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1396 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1397 int r; 1398 1399 if (!drm_kms_helper_is_poll_worker()) { 1400 r = pm_runtime_get_sync(connector->dev->dev); 1401 if (r < 0) { 1402 pm_runtime_put_autosuspend(connector->dev->dev); 1403 return connector_status_disconnected; 1404 } 1405 } 1406 1407 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1408 ret = connector->status; 1409 goto out; 1410 } 1411 1412 drm_edid_free(amdgpu_connector->edid); 1413 1414 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1415 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1416 if (encoder) { 1417 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1418 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1419 1420 /* check if panel is valid */ 1421 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 1422 ret = connector_status_connected; 1423 } 1424 /* eDP is always DP */ 1425 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1426 if (!amdgpu_dig_connector->edp_on) 1427 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1428 ATOM_TRANSMITTER_ACTION_POWER_ON); 1429 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1430 ret = connector_status_connected; 1431 if (!amdgpu_dig_connector->edp_on) 1432 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1433 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1434 } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1435 ENCODER_OBJECT_ID_NONE) { 1436 /* DP bridges are always DP */ 1437 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1438 /* get the DPCD from the bridge */ 1439 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1440 1441 if (encoder) { 1442 /* setup ddc on the bridge */ 1443 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1444 /* bridge chips are always aux */ 1445 /* try DDC */ 1446 if (amdgpu_display_ddc_probe(amdgpu_connector, true)) 1447 ret = connector_status_connected; 1448 else if (amdgpu_connector->dac_load_detect) { /* try load detection */ 1449 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 1450 1451 ret = encoder_funcs->detect(encoder, connector); 1452 } 1453 } 1454 } else { 1455 amdgpu_dig_connector->dp_sink_type = 1456 amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 1457 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1458 ret = connector_status_connected; 1459 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) 1460 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1461 } else { 1462 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 1463 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1464 ret = connector_status_connected; 1465 } else { 1466 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ 1467 if (amdgpu_display_ddc_probe(amdgpu_connector, 1468 false)) 1469 ret = connector_status_connected; 1470 } 1471 } 1472 } 1473 1474 amdgpu_connector_update_scratch_regs(connector, ret); 1475 out: 1476 if (!drm_kms_helper_is_poll_worker()) 1477 pm_runtime_put_autosuspend(connector->dev->dev); 1478 1479 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 1480 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 1481 drm_dp_set_subconnector_property(&amdgpu_connector->base, 1482 ret, 1483 amdgpu_dig_connector->dpcd, 1484 amdgpu_dig_connector->downstream_ports); 1485 return ret; 1486 } 1487 1488 static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector, 1489 const struct drm_display_mode *mode) 1490 { 1491 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1492 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1493 1494 /* XXX check mode bandwidth */ 1495 1496 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1497 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1498 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1499 1500 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 1501 return MODE_PANEL; 1502 1503 if (encoder) { 1504 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1505 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1506 1507 /* AVIVO hardware supports downscaling modes larger than the panel 1508 * to the panel size, but I'm not sure this is desirable. 1509 */ 1510 if ((mode->hdisplay > native_mode->hdisplay) || 1511 (mode->vdisplay > native_mode->vdisplay)) 1512 return MODE_PANEL; 1513 1514 /* if scaling is disabled, block non-native modes */ 1515 if (amdgpu_encoder->rmx_type == RMX_OFF) { 1516 if ((mode->hdisplay != native_mode->hdisplay) || 1517 (mode->vdisplay != native_mode->vdisplay)) 1518 return MODE_PANEL; 1519 } 1520 } 1521 return MODE_OK; 1522 } else { 1523 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 1524 (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 1525 return amdgpu_atombios_dp_mode_valid_helper(connector, mode); 1526 } else { 1527 if (connector->display_info.is_hdmi) { 1528 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1529 if (mode->clock > 340000) 1530 return MODE_CLOCK_HIGH; 1531 } else { 1532 if (mode->clock > 165000) 1533 return MODE_CLOCK_HIGH; 1534 } 1535 } 1536 } 1537 1538 return MODE_OK; 1539 } 1540 1541 static int 1542 amdgpu_connector_late_register(struct drm_connector *connector) 1543 { 1544 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1545 int r = 0; 1546 1547 if (amdgpu_connector->ddc_bus->has_aux) { 1548 amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev; 1549 r = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux); 1550 } 1551 1552 return r; 1553 } 1554 1555 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = { 1556 .get_modes = amdgpu_connector_dp_get_modes, 1557 .mode_valid = amdgpu_connector_dp_mode_valid, 1558 .best_encoder = amdgpu_connector_dvi_encoder, 1559 }; 1560 1561 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = { 1562 .dpms = drm_helper_connector_dpms, 1563 .detect = amdgpu_connector_dp_detect, 1564 .fill_modes = drm_helper_probe_single_connector_modes, 1565 .set_property = amdgpu_connector_set_property, 1566 .early_unregister = amdgpu_connector_unregister, 1567 .destroy = amdgpu_connector_destroy, 1568 .force = amdgpu_connector_dvi_force, 1569 .late_register = amdgpu_connector_late_register, 1570 }; 1571 1572 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = { 1573 .dpms = drm_helper_connector_dpms, 1574 .detect = amdgpu_connector_dp_detect, 1575 .fill_modes = drm_helper_probe_single_connector_modes, 1576 .set_property = amdgpu_connector_set_lcd_property, 1577 .early_unregister = amdgpu_connector_unregister, 1578 .destroy = amdgpu_connector_destroy, 1579 .force = amdgpu_connector_dvi_force, 1580 .late_register = amdgpu_connector_late_register, 1581 }; 1582 1583 void 1584 amdgpu_connector_add(struct amdgpu_device *adev, 1585 uint32_t connector_id, 1586 uint32_t supported_device, 1587 int connector_type, 1588 struct amdgpu_i2c_bus_rec *i2c_bus, 1589 uint16_t connector_object_id, 1590 struct amdgpu_hpd *hpd, 1591 struct amdgpu_router *router) 1592 { 1593 struct drm_device *dev = adev_to_drm(adev); 1594 struct drm_connector *connector; 1595 struct drm_connector_list_iter iter; 1596 struct amdgpu_connector *amdgpu_connector; 1597 struct amdgpu_connector_atom_dig *amdgpu_dig_connector; 1598 struct drm_encoder *encoder; 1599 struct amdgpu_encoder *amdgpu_encoder; 1600 struct i2c_adapter *ddc = NULL; 1601 uint32_t subpixel_order = SubPixelNone; 1602 bool shared_ddc = false; 1603 bool is_dp_bridge = false; 1604 bool has_aux = false; 1605 1606 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1607 return; 1608 1609 /* see if we already added it */ 1610 drm_connector_list_iter_begin(dev, &iter); 1611 drm_for_each_connector_iter(connector, &iter) { 1612 amdgpu_connector = to_amdgpu_connector(connector); 1613 if (amdgpu_connector->connector_id == connector_id) { 1614 amdgpu_connector->devices |= supported_device; 1615 drm_connector_list_iter_end(&iter); 1616 return; 1617 } 1618 if (amdgpu_connector->ddc_bus && i2c_bus->valid) { 1619 if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) { 1620 amdgpu_connector->shared_ddc = true; 1621 shared_ddc = true; 1622 } 1623 if (amdgpu_connector->router_bus && router->ddc_valid && 1624 (amdgpu_connector->router.router_id == router->router_id)) { 1625 amdgpu_connector->shared_ddc = false; 1626 shared_ddc = false; 1627 } 1628 } 1629 } 1630 drm_connector_list_iter_end(&iter); 1631 1632 /* check if it's a dp bridge */ 1633 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1634 amdgpu_encoder = to_amdgpu_encoder(encoder); 1635 if (amdgpu_encoder->devices & supported_device) { 1636 switch (amdgpu_encoder->encoder_id) { 1637 case ENCODER_OBJECT_ID_TRAVIS: 1638 case ENCODER_OBJECT_ID_NUTMEG: 1639 is_dp_bridge = true; 1640 break; 1641 default: 1642 break; 1643 } 1644 } 1645 } 1646 1647 amdgpu_connector = kzalloc_obj(struct amdgpu_connector); 1648 if (!amdgpu_connector) 1649 return; 1650 1651 connector = &amdgpu_connector->base; 1652 1653 amdgpu_connector->connector_id = connector_id; 1654 amdgpu_connector->devices = supported_device; 1655 amdgpu_connector->shared_ddc = shared_ddc; 1656 amdgpu_connector->connector_object_id = connector_object_id; 1657 amdgpu_connector->hpd = *hpd; 1658 1659 amdgpu_connector->router = *router; 1660 if (router->ddc_valid || router->cd_valid) { 1661 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info); 1662 if (!amdgpu_connector->router_bus) 1663 drm_err(adev_to_drm(adev), 1664 "Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); 1665 } 1666 1667 if (is_dp_bridge) { 1668 amdgpu_dig_connector = kzalloc_obj(struct amdgpu_connector_atom_dig); 1669 if (!amdgpu_dig_connector) 1670 goto failed; 1671 amdgpu_connector->con_priv = amdgpu_dig_connector; 1672 if (i2c_bus->valid) { 1673 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1674 if (amdgpu_connector->ddc_bus) { 1675 has_aux = true; 1676 ddc = &amdgpu_connector->ddc_bus->adapter; 1677 } else { 1678 drm_err(adev_to_drm(adev), 1679 "DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1680 } 1681 } 1682 switch (connector_type) { 1683 case DRM_MODE_CONNECTOR_VGA: 1684 case DRM_MODE_CONNECTOR_DVIA: 1685 default: 1686 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1687 &amdgpu_connector_dp_funcs, 1688 connector_type, 1689 ddc); 1690 drm_connector_helper_add(&amdgpu_connector->base, 1691 &amdgpu_connector_dp_helper_funcs); 1692 connector->interlace_allowed = true; 1693 connector->doublescan_allowed = true; 1694 amdgpu_connector->dac_load_detect = true; 1695 drm_object_attach_property(&amdgpu_connector->base.base, 1696 adev->mode_info.load_detect_property, 1697 1); 1698 drm_object_attach_property(&amdgpu_connector->base.base, 1699 dev->mode_config.scaling_mode_property, 1700 DRM_MODE_SCALE_NONE); 1701 break; 1702 case DRM_MODE_CONNECTOR_DVII: 1703 case DRM_MODE_CONNECTOR_DVID: 1704 case DRM_MODE_CONNECTOR_HDMIA: 1705 case DRM_MODE_CONNECTOR_HDMIB: 1706 case DRM_MODE_CONNECTOR_DisplayPort: 1707 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1708 &amdgpu_connector_dp_funcs, 1709 connector_type, 1710 ddc); 1711 drm_connector_helper_add(&amdgpu_connector->base, 1712 &amdgpu_connector_dp_helper_funcs); 1713 drm_object_attach_property(&amdgpu_connector->base.base, 1714 adev->mode_info.underscan_property, 1715 UNDERSCAN_OFF); 1716 drm_object_attach_property(&amdgpu_connector->base.base, 1717 adev->mode_info.underscan_hborder_property, 1718 0); 1719 drm_object_attach_property(&amdgpu_connector->base.base, 1720 adev->mode_info.underscan_vborder_property, 1721 0); 1722 1723 drm_object_attach_property(&amdgpu_connector->base.base, 1724 dev->mode_config.scaling_mode_property, 1725 DRM_MODE_SCALE_NONE); 1726 1727 drm_object_attach_property(&amdgpu_connector->base.base, 1728 adev->mode_info.dither_property, 1729 AMDGPU_FMT_DITHER_DISABLE); 1730 1731 if (amdgpu_audio != 0) { 1732 drm_object_attach_property(&amdgpu_connector->base.base, 1733 adev->mode_info.audio_property, 1734 AMDGPU_AUDIO_AUTO); 1735 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1736 } 1737 1738 subpixel_order = SubPixelHorizontalRGB; 1739 connector->interlace_allowed = true; 1740 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1741 connector->doublescan_allowed = true; 1742 else 1743 connector->doublescan_allowed = false; 1744 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1745 amdgpu_connector->dac_load_detect = true; 1746 drm_object_attach_property(&amdgpu_connector->base.base, 1747 adev->mode_info.load_detect_property, 1748 1); 1749 } 1750 break; 1751 case DRM_MODE_CONNECTOR_LVDS: 1752 case DRM_MODE_CONNECTOR_eDP: 1753 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1754 &amdgpu_connector_edp_funcs, 1755 connector_type, 1756 ddc); 1757 drm_connector_helper_add(&amdgpu_connector->base, 1758 &amdgpu_connector_dp_helper_funcs); 1759 drm_object_attach_property(&amdgpu_connector->base.base, 1760 dev->mode_config.scaling_mode_property, 1761 DRM_MODE_SCALE_FULLSCREEN); 1762 subpixel_order = SubPixelHorizontalRGB; 1763 connector->interlace_allowed = false; 1764 connector->doublescan_allowed = false; 1765 break; 1766 } 1767 } else { 1768 switch (connector_type) { 1769 case DRM_MODE_CONNECTOR_VGA: 1770 if (i2c_bus->valid) { 1771 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1772 if (!amdgpu_connector->ddc_bus) 1773 drm_err(adev_to_drm(adev), 1774 "VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1775 else 1776 ddc = &amdgpu_connector->ddc_bus->adapter; 1777 } 1778 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1779 &amdgpu_connector_vga_funcs, 1780 connector_type, 1781 ddc); 1782 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1783 amdgpu_connector->dac_load_detect = true; 1784 drm_object_attach_property(&amdgpu_connector->base.base, 1785 adev->mode_info.load_detect_property, 1786 1); 1787 drm_object_attach_property(&amdgpu_connector->base.base, 1788 dev->mode_config.scaling_mode_property, 1789 DRM_MODE_SCALE_NONE); 1790 /* no HPD on analog connectors */ 1791 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1792 connector->interlace_allowed = true; 1793 connector->doublescan_allowed = true; 1794 break; 1795 case DRM_MODE_CONNECTOR_DVIA: 1796 if (i2c_bus->valid) { 1797 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1798 if (!amdgpu_connector->ddc_bus) 1799 drm_err(adev_to_drm(adev), 1800 "DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1801 else 1802 ddc = &amdgpu_connector->ddc_bus->adapter; 1803 } 1804 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1805 &amdgpu_connector_vga_funcs, 1806 connector_type, 1807 ddc); 1808 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1809 amdgpu_connector->dac_load_detect = true; 1810 drm_object_attach_property(&amdgpu_connector->base.base, 1811 adev->mode_info.load_detect_property, 1812 1); 1813 drm_object_attach_property(&amdgpu_connector->base.base, 1814 dev->mode_config.scaling_mode_property, 1815 DRM_MODE_SCALE_NONE); 1816 /* no HPD on analog connectors */ 1817 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1818 connector->interlace_allowed = true; 1819 connector->doublescan_allowed = true; 1820 break; 1821 case DRM_MODE_CONNECTOR_DVII: 1822 case DRM_MODE_CONNECTOR_DVID: 1823 amdgpu_dig_connector = kzalloc_obj(struct amdgpu_connector_atom_dig); 1824 if (!amdgpu_dig_connector) 1825 goto failed; 1826 amdgpu_connector->con_priv = amdgpu_dig_connector; 1827 if (i2c_bus->valid) { 1828 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1829 if (!amdgpu_connector->ddc_bus) 1830 drm_err(adev_to_drm(adev), 1831 "DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1832 else 1833 ddc = &amdgpu_connector->ddc_bus->adapter; 1834 } 1835 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1836 &amdgpu_connector_dvi_funcs, 1837 connector_type, 1838 ddc); 1839 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1840 subpixel_order = SubPixelHorizontalRGB; 1841 drm_object_attach_property(&amdgpu_connector->base.base, 1842 adev->mode_info.coherent_mode_property, 1843 1); 1844 drm_object_attach_property(&amdgpu_connector->base.base, 1845 adev->mode_info.underscan_property, 1846 UNDERSCAN_OFF); 1847 drm_object_attach_property(&amdgpu_connector->base.base, 1848 adev->mode_info.underscan_hborder_property, 1849 0); 1850 drm_object_attach_property(&amdgpu_connector->base.base, 1851 adev->mode_info.underscan_vborder_property, 1852 0); 1853 drm_object_attach_property(&amdgpu_connector->base.base, 1854 dev->mode_config.scaling_mode_property, 1855 DRM_MODE_SCALE_NONE); 1856 1857 if (amdgpu_audio != 0) { 1858 drm_object_attach_property(&amdgpu_connector->base.base, 1859 adev->mode_info.audio_property, 1860 AMDGPU_AUDIO_AUTO); 1861 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1862 } 1863 drm_object_attach_property(&amdgpu_connector->base.base, 1864 adev->mode_info.dither_property, 1865 AMDGPU_FMT_DITHER_DISABLE); 1866 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1867 amdgpu_connector->dac_load_detect = true; 1868 drm_object_attach_property(&amdgpu_connector->base.base, 1869 adev->mode_info.load_detect_property, 1870 1); 1871 } 1872 connector->interlace_allowed = true; 1873 if (connector_type == DRM_MODE_CONNECTOR_DVII) 1874 connector->doublescan_allowed = true; 1875 else 1876 connector->doublescan_allowed = false; 1877 break; 1878 case DRM_MODE_CONNECTOR_HDMIA: 1879 case DRM_MODE_CONNECTOR_HDMIB: 1880 amdgpu_dig_connector = kzalloc_obj(struct amdgpu_connector_atom_dig); 1881 if (!amdgpu_dig_connector) 1882 goto failed; 1883 amdgpu_connector->con_priv = amdgpu_dig_connector; 1884 if (i2c_bus->valid) { 1885 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1886 if (!amdgpu_connector->ddc_bus) 1887 drm_err(adev_to_drm(adev), 1888 "HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1889 else 1890 ddc = &amdgpu_connector->ddc_bus->adapter; 1891 } 1892 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1893 &amdgpu_connector_dvi_funcs, 1894 connector_type, 1895 ddc); 1896 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1897 drm_object_attach_property(&amdgpu_connector->base.base, 1898 adev->mode_info.coherent_mode_property, 1899 1); 1900 drm_object_attach_property(&amdgpu_connector->base.base, 1901 adev->mode_info.underscan_property, 1902 UNDERSCAN_OFF); 1903 drm_object_attach_property(&amdgpu_connector->base.base, 1904 adev->mode_info.underscan_hborder_property, 1905 0); 1906 drm_object_attach_property(&amdgpu_connector->base.base, 1907 adev->mode_info.underscan_vborder_property, 1908 0); 1909 drm_object_attach_property(&amdgpu_connector->base.base, 1910 dev->mode_config.scaling_mode_property, 1911 DRM_MODE_SCALE_NONE); 1912 if (amdgpu_audio != 0) { 1913 drm_object_attach_property(&amdgpu_connector->base.base, 1914 adev->mode_info.audio_property, 1915 AMDGPU_AUDIO_AUTO); 1916 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1917 } 1918 drm_object_attach_property(&amdgpu_connector->base.base, 1919 adev->mode_info.dither_property, 1920 AMDGPU_FMT_DITHER_DISABLE); 1921 subpixel_order = SubPixelHorizontalRGB; 1922 connector->interlace_allowed = true; 1923 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1924 connector->doublescan_allowed = true; 1925 else 1926 connector->doublescan_allowed = false; 1927 break; 1928 case DRM_MODE_CONNECTOR_DisplayPort: 1929 amdgpu_dig_connector = kzalloc_obj(struct amdgpu_connector_atom_dig); 1930 if (!amdgpu_dig_connector) 1931 goto failed; 1932 amdgpu_connector->con_priv = amdgpu_dig_connector; 1933 if (i2c_bus->valid) { 1934 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1935 if (amdgpu_connector->ddc_bus) { 1936 has_aux = true; 1937 ddc = &amdgpu_connector->ddc_bus->adapter; 1938 } else { 1939 drm_err(adev_to_drm(adev), 1940 "DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1941 } 1942 } 1943 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1944 &amdgpu_connector_dp_funcs, 1945 connector_type, 1946 ddc); 1947 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1948 subpixel_order = SubPixelHorizontalRGB; 1949 drm_object_attach_property(&amdgpu_connector->base.base, 1950 adev->mode_info.coherent_mode_property, 1951 1); 1952 drm_object_attach_property(&amdgpu_connector->base.base, 1953 adev->mode_info.underscan_property, 1954 UNDERSCAN_OFF); 1955 drm_object_attach_property(&amdgpu_connector->base.base, 1956 adev->mode_info.underscan_hborder_property, 1957 0); 1958 drm_object_attach_property(&amdgpu_connector->base.base, 1959 adev->mode_info.underscan_vborder_property, 1960 0); 1961 drm_object_attach_property(&amdgpu_connector->base.base, 1962 dev->mode_config.scaling_mode_property, 1963 DRM_MODE_SCALE_NONE); 1964 if (amdgpu_audio != 0) { 1965 drm_object_attach_property(&amdgpu_connector->base.base, 1966 adev->mode_info.audio_property, 1967 AMDGPU_AUDIO_AUTO); 1968 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1969 } 1970 drm_object_attach_property(&amdgpu_connector->base.base, 1971 adev->mode_info.dither_property, 1972 AMDGPU_FMT_DITHER_DISABLE); 1973 connector->interlace_allowed = true; 1974 /* in theory with a DP to VGA converter... */ 1975 connector->doublescan_allowed = false; 1976 break; 1977 case DRM_MODE_CONNECTOR_eDP: 1978 amdgpu_dig_connector = kzalloc_obj(struct amdgpu_connector_atom_dig); 1979 if (!amdgpu_dig_connector) 1980 goto failed; 1981 amdgpu_connector->con_priv = amdgpu_dig_connector; 1982 if (i2c_bus->valid) { 1983 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1984 if (amdgpu_connector->ddc_bus) { 1985 has_aux = true; 1986 ddc = &amdgpu_connector->ddc_bus->adapter; 1987 } else { 1988 drm_err(adev_to_drm(adev), 1989 "eDP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1990 } 1991 } 1992 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1993 &amdgpu_connector_edp_funcs, 1994 connector_type, 1995 ddc); 1996 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1997 drm_object_attach_property(&amdgpu_connector->base.base, 1998 dev->mode_config.scaling_mode_property, 1999 DRM_MODE_SCALE_FULLSCREEN); 2000 subpixel_order = SubPixelHorizontalRGB; 2001 connector->interlace_allowed = false; 2002 connector->doublescan_allowed = false; 2003 break; 2004 case DRM_MODE_CONNECTOR_LVDS: 2005 amdgpu_dig_connector = kzalloc_obj(struct amdgpu_connector_atom_dig); 2006 if (!amdgpu_dig_connector) 2007 goto failed; 2008 amdgpu_connector->con_priv = amdgpu_dig_connector; 2009 if (i2c_bus->valid) { 2010 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 2011 if (!amdgpu_connector->ddc_bus) 2012 drm_err(adev_to_drm(adev), 2013 "LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 2014 else 2015 ddc = &amdgpu_connector->ddc_bus->adapter; 2016 } 2017 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 2018 &amdgpu_connector_lvds_funcs, 2019 connector_type, 2020 ddc); 2021 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); 2022 drm_object_attach_property(&amdgpu_connector->base.base, 2023 dev->mode_config.scaling_mode_property, 2024 DRM_MODE_SCALE_FULLSCREEN); 2025 subpixel_order = SubPixelHorizontalRGB; 2026 connector->interlace_allowed = false; 2027 connector->doublescan_allowed = false; 2028 break; 2029 } 2030 } 2031 2032 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) { 2033 if (i2c_bus->valid) { 2034 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 2035 DRM_CONNECTOR_POLL_DISCONNECT; 2036 } 2037 } else 2038 connector->polled = DRM_CONNECTOR_POLL_HPD; 2039 2040 connector->display_info.subpixel_order = subpixel_order; 2041 2042 if (has_aux) 2043 amdgpu_atombios_dp_aux_init(amdgpu_connector); 2044 2045 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort || 2046 connector_type == DRM_MODE_CONNECTOR_eDP) { 2047 drm_connector_attach_dp_subconnector_property(&amdgpu_connector->base); 2048 } 2049 2050 return; 2051 2052 failed: 2053 drm_connector_cleanup(connector); 2054 kfree(connector); 2055 } 2056