1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27 #include <drm/display/drm_dp_helper.h> 28 #include <drm/drm_crtc_helper.h> 29 #include <drm/drm_edid.h> 30 #include <drm/drm_modeset_helper_vtables.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/amdgpu_drm.h> 33 #include "amdgpu.h" 34 #include "atom.h" 35 #include "atombios_encoders.h" 36 #include "atombios_dp.h" 37 #include "amdgpu_connectors.h" 38 #include "amdgpu_i2c.h" 39 #include "amdgpu_display.h" 40 41 #include <linux/pm_runtime.h> 42 43 void amdgpu_connector_hotplug(struct drm_connector *connector) 44 { 45 struct drm_device *dev = connector->dev; 46 struct amdgpu_device *adev = drm_to_adev(dev); 47 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 48 49 /* bail if the connector does not have hpd pin, e.g., 50 * VGA, TV, etc. 51 */ 52 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) 53 return; 54 55 amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 56 57 /* if the connector is already off, don't turn it back on */ 58 if (connector->dpms != DRM_MODE_DPMS_ON) 59 return; 60 61 /* just deal with DP (not eDP) here. */ 62 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 63 struct amdgpu_connector_atom_dig *dig_connector = 64 amdgpu_connector->con_priv; 65 66 /* if existing sink type was not DP no need to retrain */ 67 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) 68 return; 69 70 /* first get sink type as it may be reset after (un)plug */ 71 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 72 /* don't do anything if sink is not display port, i.e., 73 * passive dp->(dvi|hdmi) adaptor 74 */ 75 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT && 76 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) && 77 amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 78 /* Don't start link training before we have the DPCD */ 79 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 80 return; 81 82 /* Turn the connector off and back on immediately, which 83 * will trigger link training 84 */ 85 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 86 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 87 } 88 } 89 } 90 91 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder) 92 { 93 struct drm_crtc *crtc = encoder->crtc; 94 95 if (crtc && crtc->enabled) { 96 drm_crtc_helper_set_mode(crtc, &crtc->mode, 97 crtc->x, crtc->y, crtc->primary->fb); 98 } 99 } 100 101 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) 102 { 103 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 104 struct amdgpu_connector_atom_dig *dig_connector; 105 int bpc = 8; 106 unsigned int mode_clock, max_tmds_clock; 107 108 switch (connector->connector_type) { 109 case DRM_MODE_CONNECTOR_DVII: 110 case DRM_MODE_CONNECTOR_HDMIB: 111 if (amdgpu_connector->use_digital) { 112 if (connector->display_info.is_hdmi) { 113 if (connector->display_info.bpc) 114 bpc = connector->display_info.bpc; 115 } 116 } 117 break; 118 case DRM_MODE_CONNECTOR_DVID: 119 case DRM_MODE_CONNECTOR_HDMIA: 120 if (connector->display_info.is_hdmi) { 121 if (connector->display_info.bpc) 122 bpc = connector->display_info.bpc; 123 } 124 break; 125 case DRM_MODE_CONNECTOR_DisplayPort: 126 dig_connector = amdgpu_connector->con_priv; 127 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 128 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || 129 connector->display_info.is_hdmi) { 130 if (connector->display_info.bpc) 131 bpc = connector->display_info.bpc; 132 } 133 break; 134 case DRM_MODE_CONNECTOR_eDP: 135 case DRM_MODE_CONNECTOR_LVDS: 136 if (connector->display_info.bpc) 137 bpc = connector->display_info.bpc; 138 else { 139 const struct drm_connector_helper_funcs *connector_funcs = 140 connector->helper_private; 141 struct drm_encoder *encoder = connector_funcs->best_encoder(connector); 142 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 143 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 144 145 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR) 146 bpc = 6; 147 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR) 148 bpc = 8; 149 } 150 break; 151 } 152 153 if (connector->display_info.is_hdmi) { 154 /* 155 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make 156 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at 157 * 12 bpc is always supported on hdmi deep color sinks, as this is 158 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. 159 */ 160 if (bpc > 12) { 161 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", 162 connector->name, bpc); 163 bpc = 12; 164 } 165 166 /* Any defined maximum tmds clock limit we must not exceed? */ 167 if (connector->display_info.max_tmds_clock > 0) { 168 /* mode_clock is clock in kHz for mode to be modeset on this connector */ 169 mode_clock = amdgpu_connector->pixelclock_for_modeset; 170 171 /* Maximum allowable input clock in kHz */ 172 max_tmds_clock = connector->display_info.max_tmds_clock; 173 174 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n", 175 connector->name, mode_clock, max_tmds_clock); 176 177 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ 178 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { 179 if ((connector->display_info.edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) && 180 (mode_clock * 5/4 <= max_tmds_clock)) 181 bpc = 10; 182 else 183 bpc = 8; 184 185 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", 186 connector->name, bpc); 187 } 188 189 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { 190 bpc = 8; 191 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", 192 connector->name, bpc); 193 } 194 } else if (bpc > 8) { 195 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ 196 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", 197 connector->name); 198 bpc = 8; 199 } 200 } 201 202 if ((amdgpu_deep_color == 0) && (bpc > 8)) { 203 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n", 204 connector->name); 205 bpc = 8; 206 } 207 208 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", 209 connector->name, connector->display_info.bpc, bpc); 210 211 return bpc; 212 } 213 214 static void 215 amdgpu_connector_update_scratch_regs(struct drm_connector *connector, 216 enum drm_connector_status status) 217 { 218 struct drm_encoder *best_encoder; 219 struct drm_encoder *encoder; 220 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 221 bool connected; 222 223 best_encoder = connector_funcs->best_encoder(connector); 224 225 drm_connector_for_each_possible_encoder(connector, encoder) { 226 if ((encoder == best_encoder) && (status == connector_status_connected)) 227 connected = true; 228 else 229 connected = false; 230 231 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected); 232 } 233 } 234 235 static struct drm_encoder * 236 amdgpu_connector_find_encoder(struct drm_connector *connector, 237 int encoder_type) 238 { 239 struct drm_encoder *encoder; 240 241 drm_connector_for_each_possible_encoder(connector, encoder) { 242 if (encoder->encoder_type == encoder_type) 243 return encoder; 244 } 245 246 return NULL; 247 } 248 249 static struct edid * 250 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) 251 { 252 if (adev->mode_info.bios_hardcoded_edid) { 253 return kmemdup((unsigned char *)adev->mode_info.bios_hardcoded_edid, 254 adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); 255 } 256 return NULL; 257 } 258 259 static void amdgpu_connector_get_edid(struct drm_connector *connector) 260 { 261 struct drm_device *dev = connector->dev; 262 struct amdgpu_device *adev = drm_to_adev(dev); 263 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 264 265 if (amdgpu_connector->edid) 266 return; 267 268 /* on hw with routers, select right port */ 269 if (amdgpu_connector->router.ddc_valid) 270 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 271 272 if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 273 ENCODER_OBJECT_ID_NONE) && 274 amdgpu_connector->ddc_bus->has_aux) { 275 amdgpu_connector->edid = drm_get_edid(connector, 276 &amdgpu_connector->ddc_bus->aux.ddc); 277 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 278 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 279 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; 280 281 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 282 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && 283 amdgpu_connector->ddc_bus->has_aux) 284 amdgpu_connector->edid = drm_get_edid(connector, 285 &amdgpu_connector->ddc_bus->aux.ddc); 286 else if (amdgpu_connector->ddc_bus) 287 amdgpu_connector->edid = drm_get_edid(connector, 288 &amdgpu_connector->ddc_bus->adapter); 289 } else if (amdgpu_connector->ddc_bus) { 290 amdgpu_connector->edid = drm_get_edid(connector, 291 &amdgpu_connector->ddc_bus->adapter); 292 } 293 294 if (!amdgpu_connector->edid) { 295 /* some laptops provide a hardcoded edid in rom for LCDs */ 296 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || 297 (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) { 298 amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev); 299 drm_connector_update_edid_property(connector, amdgpu_connector->edid); 300 } 301 } 302 } 303 304 static void amdgpu_connector_free_edid(struct drm_connector *connector) 305 { 306 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 307 308 kfree(amdgpu_connector->edid); 309 amdgpu_connector->edid = NULL; 310 } 311 312 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) 313 { 314 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 315 int ret; 316 317 if (amdgpu_connector->edid) { 318 drm_connector_update_edid_property(connector, amdgpu_connector->edid); 319 ret = drm_add_edid_modes(connector, amdgpu_connector->edid); 320 return ret; 321 } 322 drm_connector_update_edid_property(connector, NULL); 323 return 0; 324 } 325 326 static struct drm_encoder * 327 amdgpu_connector_best_single_encoder(struct drm_connector *connector) 328 { 329 struct drm_encoder *encoder; 330 331 /* pick the first one */ 332 drm_connector_for_each_possible_encoder(connector, encoder) 333 return encoder; 334 335 return NULL; 336 } 337 338 static void amdgpu_get_native_mode(struct drm_connector *connector) 339 { 340 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 341 struct amdgpu_encoder *amdgpu_encoder; 342 343 if (encoder == NULL) 344 return; 345 346 amdgpu_encoder = to_amdgpu_encoder(encoder); 347 348 if (!list_empty(&connector->probed_modes)) { 349 struct drm_display_mode *preferred_mode = 350 list_first_entry(&connector->probed_modes, 351 struct drm_display_mode, head); 352 353 amdgpu_encoder->native_mode = *preferred_mode; 354 } else { 355 amdgpu_encoder->native_mode.clock = 0; 356 } 357 } 358 359 static struct drm_display_mode * 360 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder) 361 { 362 struct drm_device *dev = encoder->dev; 363 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 364 struct drm_display_mode *mode = NULL; 365 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 366 367 if (native_mode->hdisplay != 0 && 368 native_mode->vdisplay != 0 && 369 native_mode->clock != 0) { 370 mode = drm_mode_duplicate(dev, native_mode); 371 if (!mode) 372 return NULL; 373 374 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 375 drm_mode_set_name(mode); 376 377 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); 378 } else if (native_mode->hdisplay != 0 && 379 native_mode->vdisplay != 0) { 380 /* mac laptops without an edid */ 381 /* Note that this is not necessarily the exact panel mode, 382 * but an approximation based on the cvt formula. For these 383 * systems we should ideally read the mode info out of the 384 * registers or add a mode table, but this works and is much 385 * simpler. 386 */ 387 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); 388 if (!mode) 389 return NULL; 390 391 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 392 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); 393 } 394 return mode; 395 } 396 397 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, 398 struct drm_connector *connector) 399 { 400 struct drm_device *dev = encoder->dev; 401 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 402 struct drm_display_mode *mode = NULL; 403 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 404 int i; 405 static const struct mode_size { 406 int w; 407 int h; 408 } common_modes[17] = { 409 { 640, 480}, 410 { 720, 480}, 411 { 800, 600}, 412 { 848, 480}, 413 {1024, 768}, 414 {1152, 768}, 415 {1280, 720}, 416 {1280, 800}, 417 {1280, 854}, 418 {1280, 960}, 419 {1280, 1024}, 420 {1440, 900}, 421 {1400, 1050}, 422 {1680, 1050}, 423 {1600, 1200}, 424 {1920, 1080}, 425 {1920, 1200} 426 }; 427 428 for (i = 0; i < 17; i++) { 429 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 430 if (common_modes[i].w > 1024 || 431 common_modes[i].h > 768) 432 continue; 433 } 434 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 435 if (common_modes[i].w > native_mode->hdisplay || 436 common_modes[i].h > native_mode->vdisplay || 437 (common_modes[i].w == native_mode->hdisplay && 438 common_modes[i].h == native_mode->vdisplay)) 439 continue; 440 } 441 if (common_modes[i].w < 320 || common_modes[i].h < 200) 442 continue; 443 444 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); 445 if (!mode) 446 return; 447 448 drm_mode_probed_add(connector, mode); 449 } 450 } 451 452 static int amdgpu_connector_set_property(struct drm_connector *connector, 453 struct drm_property *property, 454 uint64_t val) 455 { 456 struct drm_device *dev = connector->dev; 457 struct amdgpu_device *adev = drm_to_adev(dev); 458 struct drm_encoder *encoder; 459 struct amdgpu_encoder *amdgpu_encoder; 460 461 if (property == adev->mode_info.coherent_mode_property) { 462 struct amdgpu_encoder_atom_dig *dig; 463 bool new_coherent_mode; 464 465 /* need to find digital encoder on connector */ 466 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 467 if (!encoder) 468 return 0; 469 470 amdgpu_encoder = to_amdgpu_encoder(encoder); 471 472 if (!amdgpu_encoder->enc_priv) 473 return 0; 474 475 dig = amdgpu_encoder->enc_priv; 476 new_coherent_mode = val ? true : false; 477 if (dig->coherent_mode != new_coherent_mode) { 478 dig->coherent_mode = new_coherent_mode; 479 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 480 } 481 } 482 483 if (property == adev->mode_info.audio_property) { 484 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 485 /* need to find digital encoder on connector */ 486 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 487 if (!encoder) 488 return 0; 489 490 amdgpu_encoder = to_amdgpu_encoder(encoder); 491 492 if (amdgpu_connector->audio != val) { 493 amdgpu_connector->audio = val; 494 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 495 } 496 } 497 498 if (property == adev->mode_info.dither_property) { 499 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 500 /* need to find digital encoder on connector */ 501 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 502 if (!encoder) 503 return 0; 504 505 amdgpu_encoder = to_amdgpu_encoder(encoder); 506 507 if (amdgpu_connector->dither != val) { 508 amdgpu_connector->dither = val; 509 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 510 } 511 } 512 513 if (property == adev->mode_info.underscan_property) { 514 /* need to find digital encoder on connector */ 515 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 516 if (!encoder) 517 return 0; 518 519 amdgpu_encoder = to_amdgpu_encoder(encoder); 520 521 if (amdgpu_encoder->underscan_type != val) { 522 amdgpu_encoder->underscan_type = val; 523 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 524 } 525 } 526 527 if (property == adev->mode_info.underscan_hborder_property) { 528 /* need to find digital encoder on connector */ 529 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 530 if (!encoder) 531 return 0; 532 533 amdgpu_encoder = to_amdgpu_encoder(encoder); 534 535 if (amdgpu_encoder->underscan_hborder != val) { 536 amdgpu_encoder->underscan_hborder = val; 537 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 538 } 539 } 540 541 if (property == adev->mode_info.underscan_vborder_property) { 542 /* need to find digital encoder on connector */ 543 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 544 if (!encoder) 545 return 0; 546 547 amdgpu_encoder = to_amdgpu_encoder(encoder); 548 549 if (amdgpu_encoder->underscan_vborder != val) { 550 amdgpu_encoder->underscan_vborder = val; 551 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 552 } 553 } 554 555 if (property == adev->mode_info.load_detect_property) { 556 struct amdgpu_connector *amdgpu_connector = 557 to_amdgpu_connector(connector); 558 559 if (val == 0) 560 amdgpu_connector->dac_load_detect = false; 561 else 562 amdgpu_connector->dac_load_detect = true; 563 } 564 565 if (property == dev->mode_config.scaling_mode_property) { 566 enum amdgpu_rmx_type rmx_type; 567 568 if (connector->encoder) { 569 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 570 } else { 571 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 572 573 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 574 } 575 576 switch (val) { 577 default: 578 case DRM_MODE_SCALE_NONE: 579 rmx_type = RMX_OFF; 580 break; 581 case DRM_MODE_SCALE_CENTER: 582 rmx_type = RMX_CENTER; 583 break; 584 case DRM_MODE_SCALE_ASPECT: 585 rmx_type = RMX_ASPECT; 586 break; 587 case DRM_MODE_SCALE_FULLSCREEN: 588 rmx_type = RMX_FULL; 589 break; 590 } 591 592 if (amdgpu_encoder->rmx_type == rmx_type) 593 return 0; 594 595 if ((rmx_type != DRM_MODE_SCALE_NONE) && 596 (amdgpu_encoder->native_mode.clock == 0)) 597 return 0; 598 599 amdgpu_encoder->rmx_type = rmx_type; 600 601 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 602 } 603 604 return 0; 605 } 606 607 static void 608 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder, 609 struct drm_connector *connector) 610 { 611 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 612 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 613 struct drm_display_mode *t, *mode; 614 615 /* If the EDID preferred mode doesn't match the native mode, use it */ 616 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 617 if (mode->type & DRM_MODE_TYPE_PREFERRED) { 618 if (mode->hdisplay != native_mode->hdisplay || 619 mode->vdisplay != native_mode->vdisplay) 620 drm_mode_copy(native_mode, mode); 621 } 622 } 623 624 /* Try to get native mode details from EDID if necessary */ 625 if (!native_mode->clock) { 626 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 627 if (mode->hdisplay == native_mode->hdisplay && 628 mode->vdisplay == native_mode->vdisplay) { 629 drm_mode_copy(native_mode, mode); 630 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); 631 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); 632 break; 633 } 634 } 635 } 636 637 if (!native_mode->clock) { 638 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n"); 639 amdgpu_encoder->rmx_type = RMX_OFF; 640 } 641 } 642 643 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) 644 { 645 struct drm_encoder *encoder; 646 int ret = 0; 647 struct drm_display_mode *mode; 648 649 amdgpu_connector_get_edid(connector); 650 ret = amdgpu_connector_ddc_get_modes(connector); 651 if (ret > 0) { 652 encoder = amdgpu_connector_best_single_encoder(connector); 653 if (encoder) { 654 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 655 /* add scaled modes */ 656 amdgpu_connector_add_common_modes(encoder, connector); 657 } 658 return ret; 659 } 660 661 encoder = amdgpu_connector_best_single_encoder(connector); 662 if (!encoder) 663 return 0; 664 665 /* we have no EDID modes */ 666 mode = amdgpu_connector_lcd_native_mode(encoder); 667 if (mode) { 668 ret = 1; 669 drm_mode_probed_add(connector, mode); 670 /* add the width/height from vbios tables if available */ 671 connector->display_info.width_mm = mode->width_mm; 672 connector->display_info.height_mm = mode->height_mm; 673 /* add scaled modes */ 674 amdgpu_connector_add_common_modes(encoder, connector); 675 } 676 677 return ret; 678 } 679 680 static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, 681 struct drm_display_mode *mode) 682 { 683 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 684 685 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 686 return MODE_PANEL; 687 688 if (encoder) { 689 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 690 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 691 692 /* AVIVO hardware supports downscaling modes larger than the panel 693 * to the panel size, but I'm not sure this is desirable. 694 */ 695 if ((mode->hdisplay > native_mode->hdisplay) || 696 (mode->vdisplay > native_mode->vdisplay)) 697 return MODE_PANEL; 698 699 /* if scaling is disabled, block non-native modes */ 700 if (amdgpu_encoder->rmx_type == RMX_OFF) { 701 if ((mode->hdisplay != native_mode->hdisplay) || 702 (mode->vdisplay != native_mode->vdisplay)) 703 return MODE_PANEL; 704 } 705 } 706 707 return MODE_OK; 708 } 709 710 static enum drm_connector_status 711 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force) 712 { 713 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 714 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 715 enum drm_connector_status ret = connector_status_disconnected; 716 int r; 717 718 if (!drm_kms_helper_is_poll_worker()) { 719 r = pm_runtime_get_sync(connector->dev->dev); 720 if (r < 0) { 721 pm_runtime_put_autosuspend(connector->dev->dev); 722 return connector_status_disconnected; 723 } 724 } 725 726 if (encoder) { 727 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 728 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 729 730 /* check if panel is valid */ 731 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 732 ret = connector_status_connected; 733 734 } 735 736 /* check for edid as well */ 737 amdgpu_connector_get_edid(connector); 738 if (amdgpu_connector->edid) 739 ret = connector_status_connected; 740 /* check acpi lid status ??? */ 741 742 amdgpu_connector_update_scratch_regs(connector, ret); 743 744 if (!drm_kms_helper_is_poll_worker()) { 745 pm_runtime_mark_last_busy(connector->dev->dev); 746 pm_runtime_put_autosuspend(connector->dev->dev); 747 } 748 749 return ret; 750 } 751 752 static void amdgpu_connector_unregister(struct drm_connector *connector) 753 { 754 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 755 756 if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) { 757 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); 758 amdgpu_connector->ddc_bus->has_aux = false; 759 } 760 } 761 762 static void amdgpu_connector_destroy(struct drm_connector *connector) 763 { 764 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 765 766 amdgpu_connector_free_edid(connector); 767 kfree(amdgpu_connector->con_priv); 768 drm_connector_unregister(connector); 769 drm_connector_cleanup(connector); 770 kfree(connector); 771 } 772 773 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector, 774 struct drm_property *property, 775 uint64_t value) 776 { 777 struct drm_device *dev = connector->dev; 778 struct amdgpu_encoder *amdgpu_encoder; 779 enum amdgpu_rmx_type rmx_type; 780 781 DRM_DEBUG_KMS("\n"); 782 if (property != dev->mode_config.scaling_mode_property) 783 return 0; 784 785 if (connector->encoder) 786 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 787 else { 788 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 789 790 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 791 } 792 793 switch (value) { 794 case DRM_MODE_SCALE_NONE: 795 rmx_type = RMX_OFF; 796 break; 797 case DRM_MODE_SCALE_CENTER: 798 rmx_type = RMX_CENTER; 799 break; 800 case DRM_MODE_SCALE_ASPECT: 801 rmx_type = RMX_ASPECT; 802 break; 803 default: 804 case DRM_MODE_SCALE_FULLSCREEN: 805 rmx_type = RMX_FULL; 806 break; 807 } 808 809 if (amdgpu_encoder->rmx_type == rmx_type) 810 return 0; 811 812 amdgpu_encoder->rmx_type = rmx_type; 813 814 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 815 return 0; 816 } 817 818 819 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = { 820 .get_modes = amdgpu_connector_lvds_get_modes, 821 .mode_valid = amdgpu_connector_lvds_mode_valid, 822 .best_encoder = amdgpu_connector_best_single_encoder, 823 }; 824 825 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = { 826 .dpms = drm_helper_connector_dpms, 827 .detect = amdgpu_connector_lvds_detect, 828 .fill_modes = drm_helper_probe_single_connector_modes, 829 .early_unregister = amdgpu_connector_unregister, 830 .destroy = amdgpu_connector_destroy, 831 .set_property = amdgpu_connector_set_lcd_property, 832 }; 833 834 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) 835 { 836 int ret; 837 838 amdgpu_connector_get_edid(connector); 839 ret = amdgpu_connector_ddc_get_modes(connector); 840 amdgpu_get_native_mode(connector); 841 842 return ret; 843 } 844 845 static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector, 846 struct drm_display_mode *mode) 847 { 848 struct drm_device *dev = connector->dev; 849 struct amdgpu_device *adev = drm_to_adev(dev); 850 851 /* XXX check mode bandwidth */ 852 853 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 854 return MODE_CLOCK_HIGH; 855 856 return MODE_OK; 857 } 858 859 static enum drm_connector_status 860 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) 861 { 862 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 863 struct drm_encoder *encoder; 864 const struct drm_encoder_helper_funcs *encoder_funcs; 865 bool dret = false; 866 enum drm_connector_status ret = connector_status_disconnected; 867 int r; 868 869 if (!drm_kms_helper_is_poll_worker()) { 870 r = pm_runtime_get_sync(connector->dev->dev); 871 if (r < 0) { 872 pm_runtime_put_autosuspend(connector->dev->dev); 873 return connector_status_disconnected; 874 } 875 } 876 877 encoder = amdgpu_connector_best_single_encoder(connector); 878 if (!encoder) 879 ret = connector_status_disconnected; 880 881 if (amdgpu_connector->ddc_bus) 882 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 883 if (dret) { 884 amdgpu_connector->detected_by_load = false; 885 amdgpu_connector_free_edid(connector); 886 amdgpu_connector_get_edid(connector); 887 888 if (!amdgpu_connector->edid) { 889 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 890 connector->name); 891 ret = connector_status_connected; 892 } else { 893 amdgpu_connector->use_digital = 894 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 895 896 /* some oems have boards with separate digital and analog connectors 897 * with a shared ddc line (often vga + hdmi) 898 */ 899 if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) { 900 amdgpu_connector_free_edid(connector); 901 ret = connector_status_disconnected; 902 } else { 903 ret = connector_status_connected; 904 } 905 } 906 } else { 907 908 /* if we aren't forcing don't do destructive polling */ 909 if (!force) { 910 /* only return the previous status if we last 911 * detected a monitor via load. 912 */ 913 if (amdgpu_connector->detected_by_load) 914 ret = connector->status; 915 goto out; 916 } 917 918 if (amdgpu_connector->dac_load_detect && encoder) { 919 encoder_funcs = encoder->helper_private; 920 ret = encoder_funcs->detect(encoder, connector); 921 if (ret != connector_status_disconnected) 922 amdgpu_connector->detected_by_load = true; 923 } 924 } 925 926 amdgpu_connector_update_scratch_regs(connector, ret); 927 928 out: 929 if (!drm_kms_helper_is_poll_worker()) { 930 pm_runtime_mark_last_busy(connector->dev->dev); 931 pm_runtime_put_autosuspend(connector->dev->dev); 932 } 933 934 return ret; 935 } 936 937 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = { 938 .get_modes = amdgpu_connector_vga_get_modes, 939 .mode_valid = amdgpu_connector_vga_mode_valid, 940 .best_encoder = amdgpu_connector_best_single_encoder, 941 }; 942 943 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = { 944 .dpms = drm_helper_connector_dpms, 945 .detect = amdgpu_connector_vga_detect, 946 .fill_modes = drm_helper_probe_single_connector_modes, 947 .early_unregister = amdgpu_connector_unregister, 948 .destroy = amdgpu_connector_destroy, 949 .set_property = amdgpu_connector_set_property, 950 }; 951 952 static bool 953 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector) 954 { 955 struct drm_device *dev = connector->dev; 956 struct amdgpu_device *adev = drm_to_adev(dev); 957 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 958 enum drm_connector_status status; 959 960 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) { 961 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) 962 status = connector_status_connected; 963 else 964 status = connector_status_disconnected; 965 if (connector->status == status) 966 return true; 967 } 968 969 return false; 970 } 971 972 static void amdgpu_connector_shared_ddc(enum drm_connector_status *status, 973 struct drm_connector *connector, 974 struct amdgpu_connector *amdgpu_connector) 975 { 976 struct drm_connector *list_connector; 977 struct drm_connector_list_iter iter; 978 struct amdgpu_connector *list_amdgpu_connector; 979 struct drm_device *dev = connector->dev; 980 struct amdgpu_device *adev = drm_to_adev(dev); 981 982 if (amdgpu_connector->shared_ddc && *status == connector_status_connected) { 983 drm_connector_list_iter_begin(dev, &iter); 984 drm_for_each_connector_iter(list_connector, 985 &iter) { 986 if (connector == list_connector) 987 continue; 988 list_amdgpu_connector = to_amdgpu_connector(list_connector); 989 if (list_amdgpu_connector->shared_ddc && 990 list_amdgpu_connector->ddc_bus->rec.i2c_id == 991 amdgpu_connector->ddc_bus->rec.i2c_id) { 992 /* cases where both connectors are digital */ 993 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { 994 /* hpd is our only option in this case */ 995 if (!amdgpu_display_hpd_sense(adev, 996 amdgpu_connector->hpd.hpd)) { 997 amdgpu_connector_free_edid(connector); 998 *status = connector_status_disconnected; 999 } 1000 } 1001 } 1002 } 1003 drm_connector_list_iter_end(&iter); 1004 } 1005 } 1006 1007 /* 1008 * DVI is complicated 1009 * Do a DDC probe, if DDC probe passes, get the full EDID so 1010 * we can do analog/digital monitor detection at this point. 1011 * If the monitor is an analog monitor or we got no DDC, 1012 * we need to find the DAC encoder object for this connector. 1013 * If we got no DDC, we do load detection on the DAC encoder object. 1014 * If we got analog DDC or load detection passes on the DAC encoder 1015 * we have to check if this analog encoder is shared with anyone else (TV) 1016 * if its shared we have to set the other connector to disconnected. 1017 */ 1018 static enum drm_connector_status 1019 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) 1020 { 1021 struct drm_device *dev = connector->dev; 1022 struct amdgpu_device *adev = drm_to_adev(dev); 1023 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1024 const struct drm_encoder_helper_funcs *encoder_funcs; 1025 int r; 1026 enum drm_connector_status ret = connector_status_disconnected; 1027 bool dret = false, broken_edid = false; 1028 1029 if (!drm_kms_helper_is_poll_worker()) { 1030 r = pm_runtime_get_sync(connector->dev->dev); 1031 if (r < 0) { 1032 pm_runtime_put_autosuspend(connector->dev->dev); 1033 return connector_status_disconnected; 1034 } 1035 } 1036 1037 if (amdgpu_connector->detected_hpd_without_ddc) { 1038 force = true; 1039 amdgpu_connector->detected_hpd_without_ddc = false; 1040 } 1041 1042 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1043 ret = connector->status; 1044 goto exit; 1045 } 1046 1047 if (amdgpu_connector->ddc_bus) { 1048 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 1049 1050 /* Sometimes the pins required for the DDC probe on DVI 1051 * connectors don't make contact at the same time that the ones 1052 * for HPD do. If the DDC probe fails even though we had an HPD 1053 * signal, try again later 1054 */ 1055 if (!dret && !force && 1056 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1057 DRM_DEBUG_KMS("hpd detected without ddc, retrying in 1 second\n"); 1058 amdgpu_connector->detected_hpd_without_ddc = true; 1059 schedule_delayed_work(&adev->hotplug_work, 1060 msecs_to_jiffies(1000)); 1061 goto exit; 1062 } 1063 } 1064 if (dret) { 1065 amdgpu_connector->detected_by_load = false; 1066 amdgpu_connector_free_edid(connector); 1067 amdgpu_connector_get_edid(connector); 1068 1069 if (!amdgpu_connector->edid) { 1070 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 1071 connector->name); 1072 ret = connector_status_connected; 1073 broken_edid = true; /* defer use_digital to later */ 1074 } else { 1075 amdgpu_connector->use_digital = 1076 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 1077 1078 /* some oems have boards with separate digital and analog connectors 1079 * with a shared ddc line (often vga + hdmi) 1080 */ 1081 if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) { 1082 amdgpu_connector_free_edid(connector); 1083 ret = connector_status_disconnected; 1084 } else { 1085 ret = connector_status_connected; 1086 } 1087 1088 /* This gets complicated. We have boards with VGA + HDMI with a 1089 * shared DDC line and we have boards with DVI-D + HDMI with a shared 1090 * DDC line. The latter is more complex because with DVI<->HDMI adapters 1091 * you don't really know what's connected to which port as both are digital. 1092 */ 1093 amdgpu_connector_shared_ddc(&ret, connector, amdgpu_connector); 1094 } 1095 } 1096 1097 if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true)) 1098 goto out; 1099 1100 /* DVI-D and HDMI-A are digital only */ 1101 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) || 1102 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)) 1103 goto out; 1104 1105 /* if we aren't forcing don't do destructive polling */ 1106 if (!force) { 1107 /* only return the previous status if we last 1108 * detected a monitor via load. 1109 */ 1110 if (amdgpu_connector->detected_by_load) 1111 ret = connector->status; 1112 goto out; 1113 } 1114 1115 /* find analog encoder */ 1116 if (amdgpu_connector->dac_load_detect) { 1117 struct drm_encoder *encoder; 1118 1119 drm_connector_for_each_possible_encoder(connector, encoder) { 1120 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && 1121 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) 1122 continue; 1123 1124 encoder_funcs = encoder->helper_private; 1125 if (encoder_funcs->detect) { 1126 if (!broken_edid) { 1127 if (ret != connector_status_connected) { 1128 /* deal with analog monitors without DDC */ 1129 ret = encoder_funcs->detect(encoder, connector); 1130 if (ret == connector_status_connected) { 1131 amdgpu_connector->use_digital = false; 1132 } 1133 if (ret != connector_status_disconnected) 1134 amdgpu_connector->detected_by_load = true; 1135 } 1136 } else { 1137 enum drm_connector_status lret; 1138 /* assume digital unless load detected otherwise */ 1139 amdgpu_connector->use_digital = true; 1140 lret = encoder_funcs->detect(encoder, connector); 1141 DRM_DEBUG_KMS("load_detect %x returned: %x\n", 1142 encoder->encoder_type, lret); 1143 if (lret == connector_status_connected) 1144 amdgpu_connector->use_digital = false; 1145 } 1146 break; 1147 } 1148 } 1149 } 1150 1151 out: 1152 /* updated in get modes as well since we need to know if it's analog or digital */ 1153 amdgpu_connector_update_scratch_regs(connector, ret); 1154 1155 exit: 1156 if (!drm_kms_helper_is_poll_worker()) { 1157 pm_runtime_mark_last_busy(connector->dev->dev); 1158 pm_runtime_put_autosuspend(connector->dev->dev); 1159 } 1160 1161 return ret; 1162 } 1163 1164 /* okay need to be smart in here about which encoder to pick */ 1165 static struct drm_encoder * 1166 amdgpu_connector_dvi_encoder(struct drm_connector *connector) 1167 { 1168 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1169 struct drm_encoder *encoder; 1170 1171 drm_connector_for_each_possible_encoder(connector, encoder) { 1172 if (amdgpu_connector->use_digital == true) { 1173 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) 1174 return encoder; 1175 } else { 1176 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC || 1177 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1178 return encoder; 1179 } 1180 } 1181 1182 /* see if we have a default encoder TODO */ 1183 1184 /* then check use digitial */ 1185 /* pick the first one */ 1186 drm_connector_for_each_possible_encoder(connector, encoder) 1187 return encoder; 1188 1189 return NULL; 1190 } 1191 1192 static void amdgpu_connector_dvi_force(struct drm_connector *connector) 1193 { 1194 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1195 1196 if (connector->force == DRM_FORCE_ON) 1197 amdgpu_connector->use_digital = false; 1198 if (connector->force == DRM_FORCE_ON_DIGITAL) 1199 amdgpu_connector->use_digital = true; 1200 } 1201 1202 static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, 1203 struct drm_display_mode *mode) 1204 { 1205 struct drm_device *dev = connector->dev; 1206 struct amdgpu_device *adev = drm_to_adev(dev); 1207 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1208 1209 /* XXX check mode bandwidth */ 1210 1211 if (amdgpu_connector->use_digital && (mode->clock > 165000)) { 1212 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) || 1213 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || 1214 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) { 1215 return MODE_OK; 1216 } else if (connector->display_info.is_hdmi) { 1217 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1218 if (mode->clock > 340000) 1219 return MODE_CLOCK_HIGH; 1220 else 1221 return MODE_OK; 1222 } else { 1223 return MODE_CLOCK_HIGH; 1224 } 1225 } 1226 1227 /* check against the max pixel clock */ 1228 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 1229 return MODE_CLOCK_HIGH; 1230 1231 return MODE_OK; 1232 } 1233 1234 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = { 1235 .get_modes = amdgpu_connector_vga_get_modes, 1236 .mode_valid = amdgpu_connector_dvi_mode_valid, 1237 .best_encoder = amdgpu_connector_dvi_encoder, 1238 }; 1239 1240 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = { 1241 .dpms = drm_helper_connector_dpms, 1242 .detect = amdgpu_connector_dvi_detect, 1243 .fill_modes = drm_helper_probe_single_connector_modes, 1244 .set_property = amdgpu_connector_set_property, 1245 .early_unregister = amdgpu_connector_unregister, 1246 .destroy = amdgpu_connector_destroy, 1247 .force = amdgpu_connector_dvi_force, 1248 }; 1249 1250 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) 1251 { 1252 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1253 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1254 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1255 int ret; 1256 1257 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1258 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1259 struct drm_display_mode *mode; 1260 1261 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1262 if (!amdgpu_dig_connector->edp_on) 1263 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1264 ATOM_TRANSMITTER_ACTION_POWER_ON); 1265 amdgpu_connector_get_edid(connector); 1266 ret = amdgpu_connector_ddc_get_modes(connector); 1267 if (!amdgpu_dig_connector->edp_on) 1268 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1269 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1270 } else { 1271 /* need to setup ddc on the bridge */ 1272 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1273 ENCODER_OBJECT_ID_NONE) { 1274 if (encoder) 1275 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1276 } 1277 amdgpu_connector_get_edid(connector); 1278 ret = amdgpu_connector_ddc_get_modes(connector); 1279 } 1280 1281 if (ret > 0) { 1282 if (encoder) { 1283 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 1284 /* add scaled modes */ 1285 amdgpu_connector_add_common_modes(encoder, connector); 1286 } 1287 return ret; 1288 } 1289 1290 if (!encoder) 1291 return 0; 1292 1293 /* we have no EDID modes */ 1294 mode = amdgpu_connector_lcd_native_mode(encoder); 1295 if (mode) { 1296 ret = 1; 1297 drm_mode_probed_add(connector, mode); 1298 /* add the width/height from vbios tables if available */ 1299 connector->display_info.width_mm = mode->width_mm; 1300 connector->display_info.height_mm = mode->height_mm; 1301 /* add scaled modes */ 1302 amdgpu_connector_add_common_modes(encoder, connector); 1303 } 1304 } else { 1305 /* need to setup ddc on the bridge */ 1306 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1307 ENCODER_OBJECT_ID_NONE) { 1308 if (encoder) 1309 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1310 } 1311 amdgpu_connector_get_edid(connector); 1312 ret = amdgpu_connector_ddc_get_modes(connector); 1313 1314 amdgpu_get_native_mode(connector); 1315 } 1316 1317 return ret; 1318 } 1319 1320 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) 1321 { 1322 struct drm_encoder *encoder; 1323 struct amdgpu_encoder *amdgpu_encoder; 1324 1325 drm_connector_for_each_possible_encoder(connector, encoder) { 1326 amdgpu_encoder = to_amdgpu_encoder(encoder); 1327 1328 switch (amdgpu_encoder->encoder_id) { 1329 case ENCODER_OBJECT_ID_TRAVIS: 1330 case ENCODER_OBJECT_ID_NUTMEG: 1331 return amdgpu_encoder->encoder_id; 1332 default: 1333 break; 1334 } 1335 } 1336 1337 return ENCODER_OBJECT_ID_NONE; 1338 } 1339 1340 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) 1341 { 1342 struct drm_encoder *encoder; 1343 struct amdgpu_encoder *amdgpu_encoder; 1344 bool found = false; 1345 1346 drm_connector_for_each_possible_encoder(connector, encoder) { 1347 amdgpu_encoder = to_amdgpu_encoder(encoder); 1348 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) 1349 found = true; 1350 } 1351 1352 return found; 1353 } 1354 1355 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector) 1356 { 1357 struct drm_device *dev = connector->dev; 1358 struct amdgpu_device *adev = drm_to_adev(dev); 1359 1360 if ((adev->clock.default_dispclk >= 53900) && 1361 amdgpu_connector_encoder_is_hbr2(connector)) { 1362 return true; 1363 } 1364 1365 return false; 1366 } 1367 1368 static enum drm_connector_status 1369 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) 1370 { 1371 struct drm_device *dev = connector->dev; 1372 struct amdgpu_device *adev = drm_to_adev(dev); 1373 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1374 enum drm_connector_status ret = connector_status_disconnected; 1375 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1376 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1377 int r; 1378 1379 if (!drm_kms_helper_is_poll_worker()) { 1380 r = pm_runtime_get_sync(connector->dev->dev); 1381 if (r < 0) { 1382 pm_runtime_put_autosuspend(connector->dev->dev); 1383 return connector_status_disconnected; 1384 } 1385 } 1386 1387 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1388 ret = connector->status; 1389 goto out; 1390 } 1391 1392 amdgpu_connector_free_edid(connector); 1393 1394 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1395 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1396 if (encoder) { 1397 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1398 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1399 1400 /* check if panel is valid */ 1401 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 1402 ret = connector_status_connected; 1403 } 1404 /* eDP is always DP */ 1405 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1406 if (!amdgpu_dig_connector->edp_on) 1407 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1408 ATOM_TRANSMITTER_ACTION_POWER_ON); 1409 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1410 ret = connector_status_connected; 1411 if (!amdgpu_dig_connector->edp_on) 1412 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1413 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1414 } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1415 ENCODER_OBJECT_ID_NONE) { 1416 /* DP bridges are always DP */ 1417 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1418 /* get the DPCD from the bridge */ 1419 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1420 1421 if (encoder) { 1422 /* setup ddc on the bridge */ 1423 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1424 /* bridge chips are always aux */ 1425 /* try DDC */ 1426 if (amdgpu_display_ddc_probe(amdgpu_connector, true)) 1427 ret = connector_status_connected; 1428 else if (amdgpu_connector->dac_load_detect) { /* try load detection */ 1429 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 1430 1431 ret = encoder_funcs->detect(encoder, connector); 1432 } 1433 } 1434 } else { 1435 amdgpu_dig_connector->dp_sink_type = 1436 amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 1437 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1438 ret = connector_status_connected; 1439 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) 1440 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1441 } else { 1442 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 1443 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1444 ret = connector_status_connected; 1445 } else { 1446 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ 1447 if (amdgpu_display_ddc_probe(amdgpu_connector, 1448 false)) 1449 ret = connector_status_connected; 1450 } 1451 } 1452 } 1453 1454 amdgpu_connector_update_scratch_regs(connector, ret); 1455 out: 1456 if (!drm_kms_helper_is_poll_worker()) { 1457 pm_runtime_mark_last_busy(connector->dev->dev); 1458 pm_runtime_put_autosuspend(connector->dev->dev); 1459 } 1460 1461 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 1462 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 1463 drm_dp_set_subconnector_property(&amdgpu_connector->base, 1464 ret, 1465 amdgpu_dig_connector->dpcd, 1466 amdgpu_dig_connector->downstream_ports); 1467 return ret; 1468 } 1469 1470 static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector, 1471 struct drm_display_mode *mode) 1472 { 1473 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1474 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1475 1476 /* XXX check mode bandwidth */ 1477 1478 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1479 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1480 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1481 1482 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 1483 return MODE_PANEL; 1484 1485 if (encoder) { 1486 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1487 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1488 1489 /* AVIVO hardware supports downscaling modes larger than the panel 1490 * to the panel size, but I'm not sure this is desirable. 1491 */ 1492 if ((mode->hdisplay > native_mode->hdisplay) || 1493 (mode->vdisplay > native_mode->vdisplay)) 1494 return MODE_PANEL; 1495 1496 /* if scaling is disabled, block non-native modes */ 1497 if (amdgpu_encoder->rmx_type == RMX_OFF) { 1498 if ((mode->hdisplay != native_mode->hdisplay) || 1499 (mode->vdisplay != native_mode->vdisplay)) 1500 return MODE_PANEL; 1501 } 1502 } 1503 return MODE_OK; 1504 } else { 1505 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 1506 (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 1507 return amdgpu_atombios_dp_mode_valid_helper(connector, mode); 1508 } else { 1509 if (connector->display_info.is_hdmi) { 1510 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1511 if (mode->clock > 340000) 1512 return MODE_CLOCK_HIGH; 1513 } else { 1514 if (mode->clock > 165000) 1515 return MODE_CLOCK_HIGH; 1516 } 1517 } 1518 } 1519 1520 return MODE_OK; 1521 } 1522 1523 static int 1524 amdgpu_connector_late_register(struct drm_connector *connector) 1525 { 1526 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1527 int r = 0; 1528 1529 if (amdgpu_connector->ddc_bus->has_aux) { 1530 amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev; 1531 r = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux); 1532 } 1533 1534 return r; 1535 } 1536 1537 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = { 1538 .get_modes = amdgpu_connector_dp_get_modes, 1539 .mode_valid = amdgpu_connector_dp_mode_valid, 1540 .best_encoder = amdgpu_connector_dvi_encoder, 1541 }; 1542 1543 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = { 1544 .dpms = drm_helper_connector_dpms, 1545 .detect = amdgpu_connector_dp_detect, 1546 .fill_modes = drm_helper_probe_single_connector_modes, 1547 .set_property = amdgpu_connector_set_property, 1548 .early_unregister = amdgpu_connector_unregister, 1549 .destroy = amdgpu_connector_destroy, 1550 .force = amdgpu_connector_dvi_force, 1551 .late_register = amdgpu_connector_late_register, 1552 }; 1553 1554 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = { 1555 .dpms = drm_helper_connector_dpms, 1556 .detect = amdgpu_connector_dp_detect, 1557 .fill_modes = drm_helper_probe_single_connector_modes, 1558 .set_property = amdgpu_connector_set_lcd_property, 1559 .early_unregister = amdgpu_connector_unregister, 1560 .destroy = amdgpu_connector_destroy, 1561 .force = amdgpu_connector_dvi_force, 1562 .late_register = amdgpu_connector_late_register, 1563 }; 1564 1565 void 1566 amdgpu_connector_add(struct amdgpu_device *adev, 1567 uint32_t connector_id, 1568 uint32_t supported_device, 1569 int connector_type, 1570 struct amdgpu_i2c_bus_rec *i2c_bus, 1571 uint16_t connector_object_id, 1572 struct amdgpu_hpd *hpd, 1573 struct amdgpu_router *router) 1574 { 1575 struct drm_device *dev = adev_to_drm(adev); 1576 struct drm_connector *connector; 1577 struct drm_connector_list_iter iter; 1578 struct amdgpu_connector *amdgpu_connector; 1579 struct amdgpu_connector_atom_dig *amdgpu_dig_connector; 1580 struct drm_encoder *encoder; 1581 struct amdgpu_encoder *amdgpu_encoder; 1582 struct i2c_adapter *ddc = NULL; 1583 uint32_t subpixel_order = SubPixelNone; 1584 bool shared_ddc = false; 1585 bool is_dp_bridge = false; 1586 bool has_aux = false; 1587 1588 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1589 return; 1590 1591 /* see if we already added it */ 1592 drm_connector_list_iter_begin(dev, &iter); 1593 drm_for_each_connector_iter(connector, &iter) { 1594 amdgpu_connector = to_amdgpu_connector(connector); 1595 if (amdgpu_connector->connector_id == connector_id) { 1596 amdgpu_connector->devices |= supported_device; 1597 drm_connector_list_iter_end(&iter); 1598 return; 1599 } 1600 if (amdgpu_connector->ddc_bus && i2c_bus->valid) { 1601 if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) { 1602 amdgpu_connector->shared_ddc = true; 1603 shared_ddc = true; 1604 } 1605 if (amdgpu_connector->router_bus && router->ddc_valid && 1606 (amdgpu_connector->router.router_id == router->router_id)) { 1607 amdgpu_connector->shared_ddc = false; 1608 shared_ddc = false; 1609 } 1610 } 1611 } 1612 drm_connector_list_iter_end(&iter); 1613 1614 /* check if it's a dp bridge */ 1615 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1616 amdgpu_encoder = to_amdgpu_encoder(encoder); 1617 if (amdgpu_encoder->devices & supported_device) { 1618 switch (amdgpu_encoder->encoder_id) { 1619 case ENCODER_OBJECT_ID_TRAVIS: 1620 case ENCODER_OBJECT_ID_NUTMEG: 1621 is_dp_bridge = true; 1622 break; 1623 default: 1624 break; 1625 } 1626 } 1627 } 1628 1629 amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL); 1630 if (!amdgpu_connector) 1631 return; 1632 1633 connector = &amdgpu_connector->base; 1634 1635 amdgpu_connector->connector_id = connector_id; 1636 amdgpu_connector->devices = supported_device; 1637 amdgpu_connector->shared_ddc = shared_ddc; 1638 amdgpu_connector->connector_object_id = connector_object_id; 1639 amdgpu_connector->hpd = *hpd; 1640 1641 amdgpu_connector->router = *router; 1642 if (router->ddc_valid || router->cd_valid) { 1643 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info); 1644 if (!amdgpu_connector->router_bus) 1645 DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); 1646 } 1647 1648 if (is_dp_bridge) { 1649 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1650 if (!amdgpu_dig_connector) 1651 goto failed; 1652 amdgpu_connector->con_priv = amdgpu_dig_connector; 1653 if (i2c_bus->valid) { 1654 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1655 if (amdgpu_connector->ddc_bus) { 1656 has_aux = true; 1657 ddc = &amdgpu_connector->ddc_bus->adapter; 1658 } else { 1659 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1660 } 1661 } 1662 switch (connector_type) { 1663 case DRM_MODE_CONNECTOR_VGA: 1664 case DRM_MODE_CONNECTOR_DVIA: 1665 default: 1666 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1667 &amdgpu_connector_dp_funcs, 1668 connector_type, 1669 ddc); 1670 drm_connector_helper_add(&amdgpu_connector->base, 1671 &amdgpu_connector_dp_helper_funcs); 1672 connector->interlace_allowed = true; 1673 connector->doublescan_allowed = true; 1674 amdgpu_connector->dac_load_detect = true; 1675 drm_object_attach_property(&amdgpu_connector->base.base, 1676 adev->mode_info.load_detect_property, 1677 1); 1678 drm_object_attach_property(&amdgpu_connector->base.base, 1679 dev->mode_config.scaling_mode_property, 1680 DRM_MODE_SCALE_NONE); 1681 break; 1682 case DRM_MODE_CONNECTOR_DVII: 1683 case DRM_MODE_CONNECTOR_DVID: 1684 case DRM_MODE_CONNECTOR_HDMIA: 1685 case DRM_MODE_CONNECTOR_HDMIB: 1686 case DRM_MODE_CONNECTOR_DisplayPort: 1687 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1688 &amdgpu_connector_dp_funcs, 1689 connector_type, 1690 ddc); 1691 drm_connector_helper_add(&amdgpu_connector->base, 1692 &amdgpu_connector_dp_helper_funcs); 1693 drm_object_attach_property(&amdgpu_connector->base.base, 1694 adev->mode_info.underscan_property, 1695 UNDERSCAN_OFF); 1696 drm_object_attach_property(&amdgpu_connector->base.base, 1697 adev->mode_info.underscan_hborder_property, 1698 0); 1699 drm_object_attach_property(&amdgpu_connector->base.base, 1700 adev->mode_info.underscan_vborder_property, 1701 0); 1702 1703 drm_object_attach_property(&amdgpu_connector->base.base, 1704 dev->mode_config.scaling_mode_property, 1705 DRM_MODE_SCALE_NONE); 1706 1707 drm_object_attach_property(&amdgpu_connector->base.base, 1708 adev->mode_info.dither_property, 1709 AMDGPU_FMT_DITHER_DISABLE); 1710 1711 if (amdgpu_audio != 0) { 1712 drm_object_attach_property(&amdgpu_connector->base.base, 1713 adev->mode_info.audio_property, 1714 AMDGPU_AUDIO_AUTO); 1715 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1716 } 1717 1718 subpixel_order = SubPixelHorizontalRGB; 1719 connector->interlace_allowed = true; 1720 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1721 connector->doublescan_allowed = true; 1722 else 1723 connector->doublescan_allowed = false; 1724 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1725 amdgpu_connector->dac_load_detect = true; 1726 drm_object_attach_property(&amdgpu_connector->base.base, 1727 adev->mode_info.load_detect_property, 1728 1); 1729 } 1730 break; 1731 case DRM_MODE_CONNECTOR_LVDS: 1732 case DRM_MODE_CONNECTOR_eDP: 1733 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1734 &amdgpu_connector_edp_funcs, 1735 connector_type, 1736 ddc); 1737 drm_connector_helper_add(&amdgpu_connector->base, 1738 &amdgpu_connector_dp_helper_funcs); 1739 drm_object_attach_property(&amdgpu_connector->base.base, 1740 dev->mode_config.scaling_mode_property, 1741 DRM_MODE_SCALE_FULLSCREEN); 1742 subpixel_order = SubPixelHorizontalRGB; 1743 connector->interlace_allowed = false; 1744 connector->doublescan_allowed = false; 1745 break; 1746 } 1747 } else { 1748 switch (connector_type) { 1749 case DRM_MODE_CONNECTOR_VGA: 1750 if (i2c_bus->valid) { 1751 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1752 if (!amdgpu_connector->ddc_bus) 1753 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1754 else 1755 ddc = &amdgpu_connector->ddc_bus->adapter; 1756 } 1757 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1758 &amdgpu_connector_vga_funcs, 1759 connector_type, 1760 ddc); 1761 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1762 amdgpu_connector->dac_load_detect = true; 1763 drm_object_attach_property(&amdgpu_connector->base.base, 1764 adev->mode_info.load_detect_property, 1765 1); 1766 drm_object_attach_property(&amdgpu_connector->base.base, 1767 dev->mode_config.scaling_mode_property, 1768 DRM_MODE_SCALE_NONE); 1769 /* no HPD on analog connectors */ 1770 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1771 connector->interlace_allowed = true; 1772 connector->doublescan_allowed = true; 1773 break; 1774 case DRM_MODE_CONNECTOR_DVIA: 1775 if (i2c_bus->valid) { 1776 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1777 if (!amdgpu_connector->ddc_bus) 1778 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1779 else 1780 ddc = &amdgpu_connector->ddc_bus->adapter; 1781 } 1782 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1783 &amdgpu_connector_vga_funcs, 1784 connector_type, 1785 ddc); 1786 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1787 amdgpu_connector->dac_load_detect = true; 1788 drm_object_attach_property(&amdgpu_connector->base.base, 1789 adev->mode_info.load_detect_property, 1790 1); 1791 drm_object_attach_property(&amdgpu_connector->base.base, 1792 dev->mode_config.scaling_mode_property, 1793 DRM_MODE_SCALE_NONE); 1794 /* no HPD on analog connectors */ 1795 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1796 connector->interlace_allowed = true; 1797 connector->doublescan_allowed = true; 1798 break; 1799 case DRM_MODE_CONNECTOR_DVII: 1800 case DRM_MODE_CONNECTOR_DVID: 1801 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1802 if (!amdgpu_dig_connector) 1803 goto failed; 1804 amdgpu_connector->con_priv = amdgpu_dig_connector; 1805 if (i2c_bus->valid) { 1806 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1807 if (!amdgpu_connector->ddc_bus) 1808 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1809 else 1810 ddc = &amdgpu_connector->ddc_bus->adapter; 1811 } 1812 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1813 &amdgpu_connector_dvi_funcs, 1814 connector_type, 1815 ddc); 1816 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1817 subpixel_order = SubPixelHorizontalRGB; 1818 drm_object_attach_property(&amdgpu_connector->base.base, 1819 adev->mode_info.coherent_mode_property, 1820 1); 1821 drm_object_attach_property(&amdgpu_connector->base.base, 1822 adev->mode_info.underscan_property, 1823 UNDERSCAN_OFF); 1824 drm_object_attach_property(&amdgpu_connector->base.base, 1825 adev->mode_info.underscan_hborder_property, 1826 0); 1827 drm_object_attach_property(&amdgpu_connector->base.base, 1828 adev->mode_info.underscan_vborder_property, 1829 0); 1830 drm_object_attach_property(&amdgpu_connector->base.base, 1831 dev->mode_config.scaling_mode_property, 1832 DRM_MODE_SCALE_NONE); 1833 1834 if (amdgpu_audio != 0) { 1835 drm_object_attach_property(&amdgpu_connector->base.base, 1836 adev->mode_info.audio_property, 1837 AMDGPU_AUDIO_AUTO); 1838 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1839 } 1840 drm_object_attach_property(&amdgpu_connector->base.base, 1841 adev->mode_info.dither_property, 1842 AMDGPU_FMT_DITHER_DISABLE); 1843 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1844 amdgpu_connector->dac_load_detect = true; 1845 drm_object_attach_property(&amdgpu_connector->base.base, 1846 adev->mode_info.load_detect_property, 1847 1); 1848 } 1849 connector->interlace_allowed = true; 1850 if (connector_type == DRM_MODE_CONNECTOR_DVII) 1851 connector->doublescan_allowed = true; 1852 else 1853 connector->doublescan_allowed = false; 1854 break; 1855 case DRM_MODE_CONNECTOR_HDMIA: 1856 case DRM_MODE_CONNECTOR_HDMIB: 1857 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1858 if (!amdgpu_dig_connector) 1859 goto failed; 1860 amdgpu_connector->con_priv = amdgpu_dig_connector; 1861 if (i2c_bus->valid) { 1862 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1863 if (!amdgpu_connector->ddc_bus) 1864 DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1865 else 1866 ddc = &amdgpu_connector->ddc_bus->adapter; 1867 } 1868 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1869 &amdgpu_connector_dvi_funcs, 1870 connector_type, 1871 ddc); 1872 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1873 drm_object_attach_property(&amdgpu_connector->base.base, 1874 adev->mode_info.coherent_mode_property, 1875 1); 1876 drm_object_attach_property(&amdgpu_connector->base.base, 1877 adev->mode_info.underscan_property, 1878 UNDERSCAN_OFF); 1879 drm_object_attach_property(&amdgpu_connector->base.base, 1880 adev->mode_info.underscan_hborder_property, 1881 0); 1882 drm_object_attach_property(&amdgpu_connector->base.base, 1883 adev->mode_info.underscan_vborder_property, 1884 0); 1885 drm_object_attach_property(&amdgpu_connector->base.base, 1886 dev->mode_config.scaling_mode_property, 1887 DRM_MODE_SCALE_NONE); 1888 if (amdgpu_audio != 0) { 1889 drm_object_attach_property(&amdgpu_connector->base.base, 1890 adev->mode_info.audio_property, 1891 AMDGPU_AUDIO_AUTO); 1892 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1893 } 1894 drm_object_attach_property(&amdgpu_connector->base.base, 1895 adev->mode_info.dither_property, 1896 AMDGPU_FMT_DITHER_DISABLE); 1897 subpixel_order = SubPixelHorizontalRGB; 1898 connector->interlace_allowed = true; 1899 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1900 connector->doublescan_allowed = true; 1901 else 1902 connector->doublescan_allowed = false; 1903 break; 1904 case DRM_MODE_CONNECTOR_DisplayPort: 1905 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1906 if (!amdgpu_dig_connector) 1907 goto failed; 1908 amdgpu_connector->con_priv = amdgpu_dig_connector; 1909 if (i2c_bus->valid) { 1910 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1911 if (amdgpu_connector->ddc_bus) { 1912 has_aux = true; 1913 ddc = &amdgpu_connector->ddc_bus->adapter; 1914 } else { 1915 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1916 } 1917 } 1918 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1919 &amdgpu_connector_dp_funcs, 1920 connector_type, 1921 ddc); 1922 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1923 subpixel_order = SubPixelHorizontalRGB; 1924 drm_object_attach_property(&amdgpu_connector->base.base, 1925 adev->mode_info.coherent_mode_property, 1926 1); 1927 drm_object_attach_property(&amdgpu_connector->base.base, 1928 adev->mode_info.underscan_property, 1929 UNDERSCAN_OFF); 1930 drm_object_attach_property(&amdgpu_connector->base.base, 1931 adev->mode_info.underscan_hborder_property, 1932 0); 1933 drm_object_attach_property(&amdgpu_connector->base.base, 1934 adev->mode_info.underscan_vborder_property, 1935 0); 1936 drm_object_attach_property(&amdgpu_connector->base.base, 1937 dev->mode_config.scaling_mode_property, 1938 DRM_MODE_SCALE_NONE); 1939 if (amdgpu_audio != 0) { 1940 drm_object_attach_property(&amdgpu_connector->base.base, 1941 adev->mode_info.audio_property, 1942 AMDGPU_AUDIO_AUTO); 1943 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1944 } 1945 drm_object_attach_property(&amdgpu_connector->base.base, 1946 adev->mode_info.dither_property, 1947 AMDGPU_FMT_DITHER_DISABLE); 1948 connector->interlace_allowed = true; 1949 /* in theory with a DP to VGA converter... */ 1950 connector->doublescan_allowed = false; 1951 break; 1952 case DRM_MODE_CONNECTOR_eDP: 1953 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1954 if (!amdgpu_dig_connector) 1955 goto failed; 1956 amdgpu_connector->con_priv = amdgpu_dig_connector; 1957 if (i2c_bus->valid) { 1958 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1959 if (amdgpu_connector->ddc_bus) { 1960 has_aux = true; 1961 ddc = &amdgpu_connector->ddc_bus->adapter; 1962 } else { 1963 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1964 } 1965 } 1966 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1967 &amdgpu_connector_edp_funcs, 1968 connector_type, 1969 ddc); 1970 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1971 drm_object_attach_property(&amdgpu_connector->base.base, 1972 dev->mode_config.scaling_mode_property, 1973 DRM_MODE_SCALE_FULLSCREEN); 1974 subpixel_order = SubPixelHorizontalRGB; 1975 connector->interlace_allowed = false; 1976 connector->doublescan_allowed = false; 1977 break; 1978 case DRM_MODE_CONNECTOR_LVDS: 1979 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1980 if (!amdgpu_dig_connector) 1981 goto failed; 1982 amdgpu_connector->con_priv = amdgpu_dig_connector; 1983 if (i2c_bus->valid) { 1984 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1985 if (!amdgpu_connector->ddc_bus) 1986 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1987 else 1988 ddc = &amdgpu_connector->ddc_bus->adapter; 1989 } 1990 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1991 &amdgpu_connector_lvds_funcs, 1992 connector_type, 1993 ddc); 1994 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); 1995 drm_object_attach_property(&amdgpu_connector->base.base, 1996 dev->mode_config.scaling_mode_property, 1997 DRM_MODE_SCALE_FULLSCREEN); 1998 subpixel_order = SubPixelHorizontalRGB; 1999 connector->interlace_allowed = false; 2000 connector->doublescan_allowed = false; 2001 break; 2002 } 2003 } 2004 2005 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) { 2006 if (i2c_bus->valid) { 2007 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 2008 DRM_CONNECTOR_POLL_DISCONNECT; 2009 } 2010 } else 2011 connector->polled = DRM_CONNECTOR_POLL_HPD; 2012 2013 connector->display_info.subpixel_order = subpixel_order; 2014 2015 if (has_aux) 2016 amdgpu_atombios_dp_aux_init(amdgpu_connector); 2017 2018 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort || 2019 connector_type == DRM_MODE_CONNECTOR_eDP) { 2020 drm_connector_attach_dp_subconnector_property(&amdgpu_connector->base); 2021 } 2022 2023 return; 2024 2025 failed: 2026 drm_connector_cleanup(connector); 2027 kfree(connector); 2028 } 2029