1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27 #include <drm/display/drm_dp_helper.h> 28 #include <drm/drm_crtc_helper.h> 29 #include <drm/drm_edid.h> 30 #include <drm/drm_modeset_helper_vtables.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/amdgpu_drm.h> 33 #include "amdgpu.h" 34 #include "atom.h" 35 #include "atombios_encoders.h" 36 #include "atombios_dp.h" 37 #include "amdgpu_connectors.h" 38 #include "amdgpu_i2c.h" 39 #include "amdgpu_display.h" 40 41 #include <linux/pm_runtime.h> 42 43 void amdgpu_connector_hotplug(struct drm_connector *connector) 44 { 45 struct drm_device *dev = connector->dev; 46 struct amdgpu_device *adev = drm_to_adev(dev); 47 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 48 49 /* bail if the connector does not have hpd pin, e.g., 50 * VGA, TV, etc. 51 */ 52 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) 53 return; 54 55 amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 56 57 /* if the connector is already off, don't turn it back on */ 58 if (connector->dpms != DRM_MODE_DPMS_ON) 59 return; 60 61 /* just deal with DP (not eDP) here. */ 62 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 63 struct amdgpu_connector_atom_dig *dig_connector = 64 amdgpu_connector->con_priv; 65 66 /* if existing sink type was not DP no need to retrain */ 67 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) 68 return; 69 70 /* first get sink type as it may be reset after (un)plug */ 71 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 72 /* don't do anything if sink is not display port, i.e., 73 * passive dp->(dvi|hdmi) adaptor 74 */ 75 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT && 76 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) && 77 amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 78 /* Don't start link training before we have the DPCD */ 79 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 80 return; 81 82 /* Turn the connector off and back on immediately, which 83 * will trigger link training 84 */ 85 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 86 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 87 } 88 } 89 } 90 91 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder) 92 { 93 struct drm_crtc *crtc = encoder->crtc; 94 95 if (crtc && crtc->enabled) { 96 drm_crtc_helper_set_mode(crtc, &crtc->mode, 97 crtc->x, crtc->y, crtc->primary->fb); 98 } 99 } 100 101 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) 102 { 103 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 104 struct amdgpu_connector_atom_dig *dig_connector; 105 int bpc = 8; 106 unsigned int mode_clock, max_tmds_clock; 107 108 switch (connector->connector_type) { 109 case DRM_MODE_CONNECTOR_DVII: 110 case DRM_MODE_CONNECTOR_HDMIB: 111 if (amdgpu_connector->use_digital) { 112 if (connector->display_info.is_hdmi) { 113 if (connector->display_info.bpc) 114 bpc = connector->display_info.bpc; 115 } 116 } 117 break; 118 case DRM_MODE_CONNECTOR_DVID: 119 case DRM_MODE_CONNECTOR_HDMIA: 120 if (connector->display_info.is_hdmi) { 121 if (connector->display_info.bpc) 122 bpc = connector->display_info.bpc; 123 } 124 break; 125 case DRM_MODE_CONNECTOR_DisplayPort: 126 dig_connector = amdgpu_connector->con_priv; 127 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 128 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || 129 connector->display_info.is_hdmi) { 130 if (connector->display_info.bpc) 131 bpc = connector->display_info.bpc; 132 } 133 break; 134 case DRM_MODE_CONNECTOR_eDP: 135 case DRM_MODE_CONNECTOR_LVDS: 136 if (connector->display_info.bpc) 137 bpc = connector->display_info.bpc; 138 else { 139 const struct drm_connector_helper_funcs *connector_funcs = 140 connector->helper_private; 141 struct drm_encoder *encoder = connector_funcs->best_encoder(connector); 142 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 143 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 144 145 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR) 146 bpc = 6; 147 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR) 148 bpc = 8; 149 } 150 break; 151 } 152 153 if (connector->display_info.is_hdmi) { 154 /* 155 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make 156 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at 157 * 12 bpc is always supported on hdmi deep color sinks, as this is 158 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. 159 */ 160 if (bpc > 12) { 161 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", 162 connector->name, bpc); 163 bpc = 12; 164 } 165 166 /* Any defined maximum tmds clock limit we must not exceed? */ 167 if (connector->display_info.max_tmds_clock > 0) { 168 /* mode_clock is clock in kHz for mode to be modeset on this connector */ 169 mode_clock = amdgpu_connector->pixelclock_for_modeset; 170 171 /* Maximum allowable input clock in kHz */ 172 max_tmds_clock = connector->display_info.max_tmds_clock; 173 174 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n", 175 connector->name, mode_clock, max_tmds_clock); 176 177 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ 178 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { 179 if ((connector->display_info.edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) && 180 (mode_clock * 5/4 <= max_tmds_clock)) 181 bpc = 10; 182 else 183 bpc = 8; 184 185 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", 186 connector->name, bpc); 187 } 188 189 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { 190 bpc = 8; 191 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", 192 connector->name, bpc); 193 } 194 } else if (bpc > 8) { 195 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ 196 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", 197 connector->name); 198 bpc = 8; 199 } 200 } 201 202 if ((amdgpu_deep_color == 0) && (bpc > 8)) { 203 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n", 204 connector->name); 205 bpc = 8; 206 } 207 208 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", 209 connector->name, connector->display_info.bpc, bpc); 210 211 return bpc; 212 } 213 214 static void 215 amdgpu_connector_update_scratch_regs(struct drm_connector *connector, 216 enum drm_connector_status status) 217 { 218 struct drm_encoder *best_encoder; 219 struct drm_encoder *encoder; 220 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 221 bool connected; 222 223 best_encoder = connector_funcs->best_encoder(connector); 224 225 drm_connector_for_each_possible_encoder(connector, encoder) { 226 if ((encoder == best_encoder) && (status == connector_status_connected)) 227 connected = true; 228 else 229 connected = false; 230 231 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected); 232 } 233 } 234 235 static struct drm_encoder * 236 amdgpu_connector_find_encoder(struct drm_connector *connector, 237 int encoder_type) 238 { 239 struct drm_encoder *encoder; 240 241 drm_connector_for_each_possible_encoder(connector, encoder) { 242 if (encoder->encoder_type == encoder_type) 243 return encoder; 244 } 245 246 return NULL; 247 } 248 249 static struct edid * 250 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) 251 { 252 return drm_edid_duplicate(drm_edid_raw(adev->mode_info.bios_hardcoded_edid)); 253 } 254 255 static void amdgpu_connector_get_edid(struct drm_connector *connector) 256 { 257 struct drm_device *dev = connector->dev; 258 struct amdgpu_device *adev = drm_to_adev(dev); 259 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 260 261 if (amdgpu_connector->edid) 262 return; 263 264 /* on hw with routers, select right port */ 265 if (amdgpu_connector->router.ddc_valid) 266 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 267 268 if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 269 ENCODER_OBJECT_ID_NONE) && 270 amdgpu_connector->ddc_bus->has_aux) { 271 amdgpu_connector->edid = drm_get_edid(connector, 272 &amdgpu_connector->ddc_bus->aux.ddc); 273 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 274 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 275 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; 276 277 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 278 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && 279 amdgpu_connector->ddc_bus->has_aux) 280 amdgpu_connector->edid = drm_get_edid(connector, 281 &amdgpu_connector->ddc_bus->aux.ddc); 282 else if (amdgpu_connector->ddc_bus) 283 amdgpu_connector->edid = drm_get_edid(connector, 284 &amdgpu_connector->ddc_bus->adapter); 285 } else if (amdgpu_connector->ddc_bus) { 286 amdgpu_connector->edid = drm_get_edid(connector, 287 &amdgpu_connector->ddc_bus->adapter); 288 } 289 290 if (!amdgpu_connector->edid) { 291 /* some laptops provide a hardcoded edid in rom for LCDs */ 292 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || 293 (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) { 294 amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev); 295 drm_connector_update_edid_property(connector, amdgpu_connector->edid); 296 } 297 } 298 } 299 300 static void amdgpu_connector_free_edid(struct drm_connector *connector) 301 { 302 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 303 304 kfree(amdgpu_connector->edid); 305 amdgpu_connector->edid = NULL; 306 } 307 308 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) 309 { 310 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 311 int ret; 312 313 if (amdgpu_connector->edid) { 314 drm_connector_update_edid_property(connector, amdgpu_connector->edid); 315 ret = drm_add_edid_modes(connector, amdgpu_connector->edid); 316 return ret; 317 } 318 drm_connector_update_edid_property(connector, NULL); 319 return 0; 320 } 321 322 static struct drm_encoder * 323 amdgpu_connector_best_single_encoder(struct drm_connector *connector) 324 { 325 struct drm_encoder *encoder; 326 327 /* pick the first one */ 328 drm_connector_for_each_possible_encoder(connector, encoder) 329 return encoder; 330 331 return NULL; 332 } 333 334 static void amdgpu_get_native_mode(struct drm_connector *connector) 335 { 336 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 337 struct amdgpu_encoder *amdgpu_encoder; 338 339 if (encoder == NULL) 340 return; 341 342 amdgpu_encoder = to_amdgpu_encoder(encoder); 343 344 if (!list_empty(&connector->probed_modes)) { 345 struct drm_display_mode *preferred_mode = 346 list_first_entry(&connector->probed_modes, 347 struct drm_display_mode, head); 348 349 amdgpu_encoder->native_mode = *preferred_mode; 350 } else { 351 amdgpu_encoder->native_mode.clock = 0; 352 } 353 } 354 355 static struct drm_display_mode * 356 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder) 357 { 358 struct drm_device *dev = encoder->dev; 359 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 360 struct drm_display_mode *mode = NULL; 361 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 362 363 if (native_mode->hdisplay != 0 && 364 native_mode->vdisplay != 0 && 365 native_mode->clock != 0) { 366 mode = drm_mode_duplicate(dev, native_mode); 367 if (!mode) 368 return NULL; 369 370 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 371 drm_mode_set_name(mode); 372 373 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); 374 } else if (native_mode->hdisplay != 0 && 375 native_mode->vdisplay != 0) { 376 /* mac laptops without an edid */ 377 /* Note that this is not necessarily the exact panel mode, 378 * but an approximation based on the cvt formula. For these 379 * systems we should ideally read the mode info out of the 380 * registers or add a mode table, but this works and is much 381 * simpler. 382 */ 383 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); 384 if (!mode) 385 return NULL; 386 387 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 388 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); 389 } 390 return mode; 391 } 392 393 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, 394 struct drm_connector *connector) 395 { 396 struct drm_device *dev = encoder->dev; 397 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 398 struct drm_display_mode *mode = NULL; 399 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 400 int i; 401 int n; 402 struct mode_size { 403 char name[DRM_DISPLAY_MODE_LEN]; 404 int w; 405 int h; 406 } common_modes[] = { 407 { "640x480", 640, 480}, 408 { "800x600", 800, 600}, 409 { "1024x768", 1024, 768}, 410 { "1280x720", 1280, 720}, 411 { "1280x800", 1280, 800}, 412 {"1280x1024", 1280, 1024}, 413 { "1440x900", 1440, 900}, 414 {"1680x1050", 1680, 1050}, 415 {"1600x1200", 1600, 1200}, 416 {"1920x1080", 1920, 1080}, 417 {"1920x1200", 1920, 1200} 418 }; 419 420 n = ARRAY_SIZE(common_modes); 421 422 for (i = 0; i < n; i++) { 423 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 424 if (common_modes[i].w > 1024 || 425 common_modes[i].h > 768) 426 continue; 427 } 428 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 429 if (common_modes[i].w > native_mode->hdisplay || 430 common_modes[i].h > native_mode->vdisplay || 431 (common_modes[i].w == native_mode->hdisplay && 432 common_modes[i].h == native_mode->vdisplay)) 433 continue; 434 } 435 436 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); 437 if (!mode) 438 return; 439 strscpy(mode->name, common_modes[i].name, DRM_DISPLAY_MODE_LEN); 440 441 drm_mode_probed_add(connector, mode); 442 } 443 } 444 445 static int amdgpu_connector_set_property(struct drm_connector *connector, 446 struct drm_property *property, 447 uint64_t val) 448 { 449 struct drm_device *dev = connector->dev; 450 struct amdgpu_device *adev = drm_to_adev(dev); 451 struct drm_encoder *encoder; 452 struct amdgpu_encoder *amdgpu_encoder; 453 454 if (property == adev->mode_info.coherent_mode_property) { 455 struct amdgpu_encoder_atom_dig *dig; 456 bool new_coherent_mode; 457 458 /* need to find digital encoder on connector */ 459 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 460 if (!encoder) 461 return 0; 462 463 amdgpu_encoder = to_amdgpu_encoder(encoder); 464 465 if (!amdgpu_encoder->enc_priv) 466 return 0; 467 468 dig = amdgpu_encoder->enc_priv; 469 new_coherent_mode = val ? true : false; 470 if (dig->coherent_mode != new_coherent_mode) { 471 dig->coherent_mode = new_coherent_mode; 472 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 473 } 474 } 475 476 if (property == adev->mode_info.audio_property) { 477 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 478 /* need to find digital encoder on connector */ 479 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 480 if (!encoder) 481 return 0; 482 483 amdgpu_encoder = to_amdgpu_encoder(encoder); 484 485 if (amdgpu_connector->audio != val) { 486 amdgpu_connector->audio = val; 487 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 488 } 489 } 490 491 if (property == adev->mode_info.dither_property) { 492 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 493 /* need to find digital encoder on connector */ 494 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 495 if (!encoder) 496 return 0; 497 498 amdgpu_encoder = to_amdgpu_encoder(encoder); 499 500 if (amdgpu_connector->dither != val) { 501 amdgpu_connector->dither = val; 502 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 503 } 504 } 505 506 if (property == adev->mode_info.underscan_property) { 507 /* need to find digital encoder on connector */ 508 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 509 if (!encoder) 510 return 0; 511 512 amdgpu_encoder = to_amdgpu_encoder(encoder); 513 514 if (amdgpu_encoder->underscan_type != val) { 515 amdgpu_encoder->underscan_type = val; 516 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 517 } 518 } 519 520 if (property == adev->mode_info.underscan_hborder_property) { 521 /* need to find digital encoder on connector */ 522 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 523 if (!encoder) 524 return 0; 525 526 amdgpu_encoder = to_amdgpu_encoder(encoder); 527 528 if (amdgpu_encoder->underscan_hborder != val) { 529 amdgpu_encoder->underscan_hborder = val; 530 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 531 } 532 } 533 534 if (property == adev->mode_info.underscan_vborder_property) { 535 /* need to find digital encoder on connector */ 536 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 537 if (!encoder) 538 return 0; 539 540 amdgpu_encoder = to_amdgpu_encoder(encoder); 541 542 if (amdgpu_encoder->underscan_vborder != val) { 543 amdgpu_encoder->underscan_vborder = val; 544 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 545 } 546 } 547 548 if (property == adev->mode_info.load_detect_property) { 549 struct amdgpu_connector *amdgpu_connector = 550 to_amdgpu_connector(connector); 551 552 if (val == 0) 553 amdgpu_connector->dac_load_detect = false; 554 else 555 amdgpu_connector->dac_load_detect = true; 556 } 557 558 if (property == dev->mode_config.scaling_mode_property) { 559 enum amdgpu_rmx_type rmx_type; 560 561 if (connector->encoder) { 562 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 563 } else { 564 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 565 566 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 567 } 568 569 switch (val) { 570 default: 571 case DRM_MODE_SCALE_NONE: 572 rmx_type = RMX_OFF; 573 break; 574 case DRM_MODE_SCALE_CENTER: 575 rmx_type = RMX_CENTER; 576 break; 577 case DRM_MODE_SCALE_ASPECT: 578 rmx_type = RMX_ASPECT; 579 break; 580 case DRM_MODE_SCALE_FULLSCREEN: 581 rmx_type = RMX_FULL; 582 break; 583 } 584 585 if (amdgpu_encoder->rmx_type == rmx_type) 586 return 0; 587 588 if ((rmx_type != DRM_MODE_SCALE_NONE) && 589 (amdgpu_encoder->native_mode.clock == 0)) 590 return 0; 591 592 amdgpu_encoder->rmx_type = rmx_type; 593 594 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 595 } 596 597 return 0; 598 } 599 600 static void 601 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder, 602 struct drm_connector *connector) 603 { 604 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 605 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 606 struct drm_display_mode *t, *mode; 607 608 /* If the EDID preferred mode doesn't match the native mode, use it */ 609 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 610 if (mode->type & DRM_MODE_TYPE_PREFERRED) { 611 if (mode->hdisplay != native_mode->hdisplay || 612 mode->vdisplay != native_mode->vdisplay) 613 drm_mode_copy(native_mode, mode); 614 } 615 } 616 617 /* Try to get native mode details from EDID if necessary */ 618 if (!native_mode->clock) { 619 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 620 if (mode->hdisplay == native_mode->hdisplay && 621 mode->vdisplay == native_mode->vdisplay) { 622 drm_mode_copy(native_mode, mode); 623 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); 624 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); 625 break; 626 } 627 } 628 } 629 630 if (!native_mode->clock) { 631 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n"); 632 amdgpu_encoder->rmx_type = RMX_OFF; 633 } 634 } 635 636 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) 637 { 638 struct drm_encoder *encoder; 639 int ret = 0; 640 struct drm_display_mode *mode; 641 642 amdgpu_connector_get_edid(connector); 643 ret = amdgpu_connector_ddc_get_modes(connector); 644 if (ret > 0) { 645 encoder = amdgpu_connector_best_single_encoder(connector); 646 if (encoder) { 647 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 648 /* add scaled modes */ 649 amdgpu_connector_add_common_modes(encoder, connector); 650 } 651 return ret; 652 } 653 654 encoder = amdgpu_connector_best_single_encoder(connector); 655 if (!encoder) 656 return 0; 657 658 /* we have no EDID modes */ 659 mode = amdgpu_connector_lcd_native_mode(encoder); 660 if (mode) { 661 ret = 1; 662 drm_mode_probed_add(connector, mode); 663 /* add the width/height from vbios tables if available */ 664 connector->display_info.width_mm = mode->width_mm; 665 connector->display_info.height_mm = mode->height_mm; 666 /* add scaled modes */ 667 amdgpu_connector_add_common_modes(encoder, connector); 668 } 669 670 return ret; 671 } 672 673 static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, 674 const struct drm_display_mode *mode) 675 { 676 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 677 678 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 679 return MODE_PANEL; 680 681 if (encoder) { 682 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 683 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 684 685 /* AVIVO hardware supports downscaling modes larger than the panel 686 * to the panel size, but I'm not sure this is desirable. 687 */ 688 if ((mode->hdisplay > native_mode->hdisplay) || 689 (mode->vdisplay > native_mode->vdisplay)) 690 return MODE_PANEL; 691 692 /* if scaling is disabled, block non-native modes */ 693 if (amdgpu_encoder->rmx_type == RMX_OFF) { 694 if ((mode->hdisplay != native_mode->hdisplay) || 695 (mode->vdisplay != native_mode->vdisplay)) 696 return MODE_PANEL; 697 } 698 } 699 700 return MODE_OK; 701 } 702 703 static enum drm_connector_status 704 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force) 705 { 706 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 707 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 708 enum drm_connector_status ret = connector_status_disconnected; 709 int r; 710 711 if (!drm_kms_helper_is_poll_worker()) { 712 r = pm_runtime_get_sync(connector->dev->dev); 713 if (r < 0) { 714 pm_runtime_put_autosuspend(connector->dev->dev); 715 return connector_status_disconnected; 716 } 717 } 718 719 if (encoder) { 720 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 721 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 722 723 /* check if panel is valid */ 724 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 725 ret = connector_status_connected; 726 727 } 728 729 /* check for edid as well */ 730 amdgpu_connector_get_edid(connector); 731 if (amdgpu_connector->edid) 732 ret = connector_status_connected; 733 /* check acpi lid status ??? */ 734 735 amdgpu_connector_update_scratch_regs(connector, ret); 736 737 if (!drm_kms_helper_is_poll_worker()) 738 pm_runtime_put_autosuspend(connector->dev->dev); 739 740 return ret; 741 } 742 743 static void amdgpu_connector_unregister(struct drm_connector *connector) 744 { 745 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 746 747 if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) { 748 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); 749 amdgpu_connector->ddc_bus->has_aux = false; 750 } 751 } 752 753 static void amdgpu_connector_destroy(struct drm_connector *connector) 754 { 755 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 756 757 amdgpu_connector_free_edid(connector); 758 kfree(amdgpu_connector->con_priv); 759 drm_connector_unregister(connector); 760 drm_connector_cleanup(connector); 761 kfree(connector); 762 } 763 764 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector, 765 struct drm_property *property, 766 uint64_t value) 767 { 768 struct drm_device *dev = connector->dev; 769 struct amdgpu_encoder *amdgpu_encoder; 770 enum amdgpu_rmx_type rmx_type; 771 772 DRM_DEBUG_KMS("\n"); 773 if (property != dev->mode_config.scaling_mode_property) 774 return 0; 775 776 if (connector->encoder) 777 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 778 else { 779 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 780 781 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 782 } 783 784 switch (value) { 785 case DRM_MODE_SCALE_NONE: 786 rmx_type = RMX_OFF; 787 break; 788 case DRM_MODE_SCALE_CENTER: 789 rmx_type = RMX_CENTER; 790 break; 791 case DRM_MODE_SCALE_ASPECT: 792 rmx_type = RMX_ASPECT; 793 break; 794 default: 795 case DRM_MODE_SCALE_FULLSCREEN: 796 rmx_type = RMX_FULL; 797 break; 798 } 799 800 if (amdgpu_encoder->rmx_type == rmx_type) 801 return 0; 802 803 amdgpu_encoder->rmx_type = rmx_type; 804 805 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 806 return 0; 807 } 808 809 810 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = { 811 .get_modes = amdgpu_connector_lvds_get_modes, 812 .mode_valid = amdgpu_connector_lvds_mode_valid, 813 .best_encoder = amdgpu_connector_best_single_encoder, 814 }; 815 816 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = { 817 .dpms = drm_helper_connector_dpms, 818 .detect = amdgpu_connector_lvds_detect, 819 .fill_modes = drm_helper_probe_single_connector_modes, 820 .early_unregister = amdgpu_connector_unregister, 821 .destroy = amdgpu_connector_destroy, 822 .set_property = amdgpu_connector_set_lcd_property, 823 }; 824 825 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) 826 { 827 int ret; 828 829 amdgpu_connector_get_edid(connector); 830 ret = amdgpu_connector_ddc_get_modes(connector); 831 amdgpu_get_native_mode(connector); 832 833 return ret; 834 } 835 836 static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector, 837 const struct drm_display_mode *mode) 838 { 839 struct drm_device *dev = connector->dev; 840 struct amdgpu_device *adev = drm_to_adev(dev); 841 842 /* XXX check mode bandwidth */ 843 844 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 845 return MODE_CLOCK_HIGH; 846 847 return MODE_OK; 848 } 849 850 static enum drm_connector_status 851 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) 852 { 853 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 854 struct drm_encoder *encoder; 855 const struct drm_encoder_helper_funcs *encoder_funcs; 856 bool dret = false; 857 enum drm_connector_status ret = connector_status_disconnected; 858 int r; 859 860 if (!drm_kms_helper_is_poll_worker()) { 861 r = pm_runtime_get_sync(connector->dev->dev); 862 if (r < 0) { 863 pm_runtime_put_autosuspend(connector->dev->dev); 864 return connector_status_disconnected; 865 } 866 } 867 868 encoder = amdgpu_connector_best_single_encoder(connector); 869 if (!encoder) 870 ret = connector_status_disconnected; 871 872 if (amdgpu_connector->ddc_bus) 873 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 874 if (dret) { 875 amdgpu_connector->detected_by_load = false; 876 amdgpu_connector_free_edid(connector); 877 amdgpu_connector_get_edid(connector); 878 879 if (!amdgpu_connector->edid) { 880 drm_err(connector->dev, 881 "%s: probed a monitor but no|invalid EDID\n", 882 connector->name); 883 ret = connector_status_connected; 884 } else { 885 amdgpu_connector->use_digital = 886 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 887 888 /* some oems have boards with separate digital and analog connectors 889 * with a shared ddc line (often vga + hdmi) 890 */ 891 if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) { 892 amdgpu_connector_free_edid(connector); 893 ret = connector_status_disconnected; 894 } else { 895 ret = connector_status_connected; 896 } 897 } 898 } else { 899 900 /* if we aren't forcing don't do destructive polling */ 901 if (!force) { 902 /* only return the previous status if we last 903 * detected a monitor via load. 904 */ 905 if (amdgpu_connector->detected_by_load) 906 ret = connector->status; 907 goto out; 908 } 909 910 if (amdgpu_connector->dac_load_detect && encoder) { 911 encoder_funcs = encoder->helper_private; 912 ret = encoder_funcs->detect(encoder, connector); 913 if (ret != connector_status_disconnected) 914 amdgpu_connector->detected_by_load = true; 915 } 916 } 917 918 amdgpu_connector_update_scratch_regs(connector, ret); 919 920 out: 921 if (!drm_kms_helper_is_poll_worker()) 922 pm_runtime_put_autosuspend(connector->dev->dev); 923 924 return ret; 925 } 926 927 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = { 928 .get_modes = amdgpu_connector_vga_get_modes, 929 .mode_valid = amdgpu_connector_vga_mode_valid, 930 .best_encoder = amdgpu_connector_best_single_encoder, 931 }; 932 933 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = { 934 .dpms = drm_helper_connector_dpms, 935 .detect = amdgpu_connector_vga_detect, 936 .fill_modes = drm_helper_probe_single_connector_modes, 937 .early_unregister = amdgpu_connector_unregister, 938 .destroy = amdgpu_connector_destroy, 939 .set_property = amdgpu_connector_set_property, 940 }; 941 942 static bool 943 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector) 944 { 945 struct drm_device *dev = connector->dev; 946 struct amdgpu_device *adev = drm_to_adev(dev); 947 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 948 enum drm_connector_status status; 949 950 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) { 951 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) 952 status = connector_status_connected; 953 else 954 status = connector_status_disconnected; 955 if (connector->status == status) 956 return true; 957 } 958 959 return false; 960 } 961 962 static void amdgpu_connector_shared_ddc(enum drm_connector_status *status, 963 struct drm_connector *connector, 964 struct amdgpu_connector *amdgpu_connector) 965 { 966 struct drm_connector *list_connector; 967 struct drm_connector_list_iter iter; 968 struct amdgpu_connector *list_amdgpu_connector; 969 struct drm_device *dev = connector->dev; 970 struct amdgpu_device *adev = drm_to_adev(dev); 971 972 if (amdgpu_connector->shared_ddc && *status == connector_status_connected) { 973 drm_connector_list_iter_begin(dev, &iter); 974 drm_for_each_connector_iter(list_connector, 975 &iter) { 976 if (connector == list_connector) 977 continue; 978 list_amdgpu_connector = to_amdgpu_connector(list_connector); 979 if (list_amdgpu_connector->shared_ddc && 980 list_amdgpu_connector->ddc_bus->rec.i2c_id == 981 amdgpu_connector->ddc_bus->rec.i2c_id) { 982 /* cases where both connectors are digital */ 983 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { 984 /* hpd is our only option in this case */ 985 if (!amdgpu_display_hpd_sense(adev, 986 amdgpu_connector->hpd.hpd)) { 987 amdgpu_connector_free_edid(connector); 988 *status = connector_status_disconnected; 989 } 990 } 991 } 992 } 993 drm_connector_list_iter_end(&iter); 994 } 995 } 996 997 /* 998 * DVI is complicated 999 * Do a DDC probe, if DDC probe passes, get the full EDID so 1000 * we can do analog/digital monitor detection at this point. 1001 * If the monitor is an analog monitor or we got no DDC, 1002 * we need to find the DAC encoder object for this connector. 1003 * If we got no DDC, we do load detection on the DAC encoder object. 1004 * If we got analog DDC or load detection passes on the DAC encoder 1005 * we have to check if this analog encoder is shared with anyone else (TV) 1006 * if its shared we have to set the other connector to disconnected. 1007 */ 1008 static enum drm_connector_status 1009 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) 1010 { 1011 struct drm_device *dev = connector->dev; 1012 struct amdgpu_device *adev = drm_to_adev(dev); 1013 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1014 const struct drm_encoder_helper_funcs *encoder_funcs; 1015 int r; 1016 enum drm_connector_status ret = connector_status_disconnected; 1017 bool dret = false, broken_edid = false; 1018 1019 if (!drm_kms_helper_is_poll_worker()) { 1020 r = pm_runtime_get_sync(connector->dev->dev); 1021 if (r < 0) { 1022 pm_runtime_put_autosuspend(connector->dev->dev); 1023 return connector_status_disconnected; 1024 } 1025 } 1026 1027 if (amdgpu_connector->detected_hpd_without_ddc) { 1028 force = true; 1029 amdgpu_connector->detected_hpd_without_ddc = false; 1030 } 1031 1032 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1033 ret = connector->status; 1034 goto exit; 1035 } 1036 1037 if (amdgpu_connector->ddc_bus) { 1038 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 1039 1040 /* Sometimes the pins required for the DDC probe on DVI 1041 * connectors don't make contact at the same time that the ones 1042 * for HPD do. If the DDC probe fails even though we had an HPD 1043 * signal, try again later 1044 */ 1045 if (!dret && !force && 1046 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1047 DRM_DEBUG_KMS("hpd detected without ddc, retrying in 1 second\n"); 1048 amdgpu_connector->detected_hpd_without_ddc = true; 1049 schedule_delayed_work(&adev->hotplug_work, 1050 msecs_to_jiffies(1000)); 1051 goto exit; 1052 } 1053 } 1054 if (dret) { 1055 amdgpu_connector->detected_by_load = false; 1056 amdgpu_connector_free_edid(connector); 1057 amdgpu_connector_get_edid(connector); 1058 1059 if (!amdgpu_connector->edid) { 1060 drm_err(adev_to_drm(adev), "%s: probed a monitor but no|invalid EDID\n", 1061 connector->name); 1062 ret = connector_status_connected; 1063 broken_edid = true; /* defer use_digital to later */ 1064 } else { 1065 amdgpu_connector->use_digital = 1066 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 1067 1068 /* some oems have boards with separate digital and analog connectors 1069 * with a shared ddc line (often vga + hdmi) 1070 */ 1071 if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) { 1072 amdgpu_connector_free_edid(connector); 1073 ret = connector_status_disconnected; 1074 } else { 1075 ret = connector_status_connected; 1076 } 1077 1078 /* This gets complicated. We have boards with VGA + HDMI with a 1079 * shared DDC line and we have boards with DVI-D + HDMI with a shared 1080 * DDC line. The latter is more complex because with DVI<->HDMI adapters 1081 * you don't really know what's connected to which port as both are digital. 1082 */ 1083 amdgpu_connector_shared_ddc(&ret, connector, amdgpu_connector); 1084 } 1085 } 1086 1087 if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true)) 1088 goto out; 1089 1090 /* DVI-D and HDMI-A are digital only */ 1091 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) || 1092 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)) 1093 goto out; 1094 1095 /* if we aren't forcing don't do destructive polling */ 1096 if (!force) { 1097 /* only return the previous status if we last 1098 * detected a monitor via load. 1099 */ 1100 if (amdgpu_connector->detected_by_load) 1101 ret = connector->status; 1102 goto out; 1103 } 1104 1105 /* find analog encoder */ 1106 if (amdgpu_connector->dac_load_detect) { 1107 struct drm_encoder *encoder; 1108 1109 drm_connector_for_each_possible_encoder(connector, encoder) { 1110 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && 1111 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) 1112 continue; 1113 1114 encoder_funcs = encoder->helper_private; 1115 if (encoder_funcs->detect) { 1116 if (!broken_edid) { 1117 if (ret != connector_status_connected) { 1118 /* deal with analog monitors without DDC */ 1119 ret = encoder_funcs->detect(encoder, connector); 1120 if (ret == connector_status_connected) { 1121 amdgpu_connector->use_digital = false; 1122 } 1123 if (ret != connector_status_disconnected) 1124 amdgpu_connector->detected_by_load = true; 1125 } 1126 } else { 1127 enum drm_connector_status lret; 1128 /* assume digital unless load detected otherwise */ 1129 amdgpu_connector->use_digital = true; 1130 lret = encoder_funcs->detect(encoder, connector); 1131 DRM_DEBUG_KMS("load_detect %x returned: %x\n", 1132 encoder->encoder_type, lret); 1133 if (lret == connector_status_connected) 1134 amdgpu_connector->use_digital = false; 1135 } 1136 break; 1137 } 1138 } 1139 } 1140 1141 out: 1142 /* updated in get modes as well since we need to know if it's analog or digital */ 1143 amdgpu_connector_update_scratch_regs(connector, ret); 1144 1145 exit: 1146 if (!drm_kms_helper_is_poll_worker()) 1147 pm_runtime_put_autosuspend(connector->dev->dev); 1148 1149 return ret; 1150 } 1151 1152 /* okay need to be smart in here about which encoder to pick */ 1153 static struct drm_encoder * 1154 amdgpu_connector_dvi_encoder(struct drm_connector *connector) 1155 { 1156 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1157 struct drm_encoder *encoder; 1158 1159 drm_connector_for_each_possible_encoder(connector, encoder) { 1160 if (amdgpu_connector->use_digital == true) { 1161 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) 1162 return encoder; 1163 } else { 1164 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC || 1165 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1166 return encoder; 1167 } 1168 } 1169 1170 /* see if we have a default encoder TODO */ 1171 1172 /* then check use digitial */ 1173 /* pick the first one */ 1174 drm_connector_for_each_possible_encoder(connector, encoder) 1175 return encoder; 1176 1177 return NULL; 1178 } 1179 1180 static void amdgpu_connector_dvi_force(struct drm_connector *connector) 1181 { 1182 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1183 1184 if (connector->force == DRM_FORCE_ON) 1185 amdgpu_connector->use_digital = false; 1186 if (connector->force == DRM_FORCE_ON_DIGITAL) 1187 amdgpu_connector->use_digital = true; 1188 } 1189 1190 /** 1191 * amdgpu_max_hdmi_pixel_clock - Return max supported HDMI (TMDS) pixel clock 1192 * @adev: pointer to amdgpu_device 1193 * 1194 * Return: maximum supported HDMI (TMDS) pixel clock in KHz. 1195 */ 1196 static int amdgpu_max_hdmi_pixel_clock(const struct amdgpu_device *adev) 1197 { 1198 if (adev->asic_type >= CHIP_POLARIS10) 1199 return 600000; 1200 else if (adev->asic_type >= CHIP_TONGA) 1201 return 300000; 1202 else 1203 return 297000; 1204 } 1205 1206 /** 1207 * amdgpu_connector_dvi_mode_valid - Validate a mode on DVI/HDMI connectors 1208 * @connector: DRM connector to validate the mode on 1209 * @mode: display mode to validate 1210 * 1211 * Validate the given display mode on DVI and HDMI connectors, including 1212 * analog signals on DVI-I. 1213 * 1214 * Return: drm_mode_status indicating whether the mode is valid. 1215 */ 1216 static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, 1217 const struct drm_display_mode *mode) 1218 { 1219 struct drm_device *dev = connector->dev; 1220 struct amdgpu_device *adev = drm_to_adev(dev); 1221 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1222 const int max_hdmi_pixel_clock = amdgpu_max_hdmi_pixel_clock(adev); 1223 const int max_dvi_single_link_pixel_clock = 165000; 1224 int max_digital_pixel_clock_khz; 1225 1226 /* XXX check mode bandwidth */ 1227 1228 if (amdgpu_connector->use_digital) { 1229 switch (amdgpu_connector->connector_object_id) { 1230 case CONNECTOR_OBJECT_ID_HDMI_TYPE_A: 1231 max_digital_pixel_clock_khz = max_hdmi_pixel_clock; 1232 break; 1233 case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I: 1234 case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D: 1235 max_digital_pixel_clock_khz = max_dvi_single_link_pixel_clock; 1236 break; 1237 case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I: 1238 case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D: 1239 case CONNECTOR_OBJECT_ID_HDMI_TYPE_B: 1240 max_digital_pixel_clock_khz = max_dvi_single_link_pixel_clock * 2; 1241 break; 1242 } 1243 1244 /* When the display EDID claims that it's an HDMI display, 1245 * we use the HDMI encoder mode of the display HW, 1246 * so we should verify against the max HDMI clock here. 1247 */ 1248 if (connector->display_info.is_hdmi) 1249 max_digital_pixel_clock_khz = max_hdmi_pixel_clock; 1250 1251 if (mode->clock > max_digital_pixel_clock_khz) 1252 return MODE_CLOCK_HIGH; 1253 } 1254 1255 /* check against the max pixel clock */ 1256 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 1257 return MODE_CLOCK_HIGH; 1258 1259 return MODE_OK; 1260 } 1261 1262 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = { 1263 .get_modes = amdgpu_connector_vga_get_modes, 1264 .mode_valid = amdgpu_connector_dvi_mode_valid, 1265 .best_encoder = amdgpu_connector_dvi_encoder, 1266 }; 1267 1268 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = { 1269 .dpms = drm_helper_connector_dpms, 1270 .detect = amdgpu_connector_dvi_detect, 1271 .fill_modes = drm_helper_probe_single_connector_modes, 1272 .set_property = amdgpu_connector_set_property, 1273 .early_unregister = amdgpu_connector_unregister, 1274 .destroy = amdgpu_connector_destroy, 1275 .force = amdgpu_connector_dvi_force, 1276 }; 1277 1278 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) 1279 { 1280 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1281 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1282 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1283 int ret; 1284 1285 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1286 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1287 struct drm_display_mode *mode; 1288 1289 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1290 if (!amdgpu_dig_connector->edp_on) 1291 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1292 ATOM_TRANSMITTER_ACTION_POWER_ON); 1293 amdgpu_connector_get_edid(connector); 1294 ret = amdgpu_connector_ddc_get_modes(connector); 1295 if (!amdgpu_dig_connector->edp_on) 1296 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1297 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1298 } else { 1299 /* need to setup ddc on the bridge */ 1300 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1301 ENCODER_OBJECT_ID_NONE) { 1302 if (encoder) 1303 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1304 } 1305 amdgpu_connector_get_edid(connector); 1306 ret = amdgpu_connector_ddc_get_modes(connector); 1307 } 1308 1309 if (ret > 0) { 1310 if (encoder) { 1311 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 1312 /* add scaled modes */ 1313 amdgpu_connector_add_common_modes(encoder, connector); 1314 } 1315 return ret; 1316 } 1317 1318 if (!encoder) 1319 return 0; 1320 1321 /* we have no EDID modes */ 1322 mode = amdgpu_connector_lcd_native_mode(encoder); 1323 if (mode) { 1324 ret = 1; 1325 drm_mode_probed_add(connector, mode); 1326 /* add the width/height from vbios tables if available */ 1327 connector->display_info.width_mm = mode->width_mm; 1328 connector->display_info.height_mm = mode->height_mm; 1329 /* add scaled modes */ 1330 amdgpu_connector_add_common_modes(encoder, connector); 1331 } 1332 } else { 1333 /* need to setup ddc on the bridge */ 1334 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1335 ENCODER_OBJECT_ID_NONE) { 1336 if (encoder) 1337 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1338 } 1339 amdgpu_connector_get_edid(connector); 1340 ret = amdgpu_connector_ddc_get_modes(connector); 1341 1342 amdgpu_get_native_mode(connector); 1343 } 1344 1345 return ret; 1346 } 1347 1348 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) 1349 { 1350 struct drm_encoder *encoder; 1351 struct amdgpu_encoder *amdgpu_encoder; 1352 1353 drm_connector_for_each_possible_encoder(connector, encoder) { 1354 amdgpu_encoder = to_amdgpu_encoder(encoder); 1355 1356 switch (amdgpu_encoder->encoder_id) { 1357 case ENCODER_OBJECT_ID_TRAVIS: 1358 case ENCODER_OBJECT_ID_NUTMEG: 1359 return amdgpu_encoder->encoder_id; 1360 default: 1361 break; 1362 } 1363 } 1364 1365 return ENCODER_OBJECT_ID_NONE; 1366 } 1367 1368 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) 1369 { 1370 struct drm_encoder *encoder; 1371 struct amdgpu_encoder *amdgpu_encoder; 1372 bool found = false; 1373 1374 drm_connector_for_each_possible_encoder(connector, encoder) { 1375 amdgpu_encoder = to_amdgpu_encoder(encoder); 1376 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) 1377 found = true; 1378 } 1379 1380 return found; 1381 } 1382 1383 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector) 1384 { 1385 struct drm_device *dev = connector->dev; 1386 struct amdgpu_device *adev = drm_to_adev(dev); 1387 1388 if ((adev->clock.default_dispclk >= 53900) && 1389 amdgpu_connector_encoder_is_hbr2(connector)) { 1390 return true; 1391 } 1392 1393 return false; 1394 } 1395 1396 static enum drm_connector_status 1397 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) 1398 { 1399 struct drm_device *dev = connector->dev; 1400 struct amdgpu_device *adev = drm_to_adev(dev); 1401 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1402 enum drm_connector_status ret = connector_status_disconnected; 1403 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1404 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1405 int r; 1406 1407 if (!drm_kms_helper_is_poll_worker()) { 1408 r = pm_runtime_get_sync(connector->dev->dev); 1409 if (r < 0) { 1410 pm_runtime_put_autosuspend(connector->dev->dev); 1411 return connector_status_disconnected; 1412 } 1413 } 1414 1415 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1416 ret = connector->status; 1417 goto out; 1418 } 1419 1420 amdgpu_connector_free_edid(connector); 1421 1422 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1423 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1424 if (encoder) { 1425 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1426 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1427 1428 /* check if panel is valid */ 1429 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 1430 ret = connector_status_connected; 1431 } 1432 /* eDP is always DP */ 1433 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1434 if (!amdgpu_dig_connector->edp_on) 1435 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1436 ATOM_TRANSMITTER_ACTION_POWER_ON); 1437 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1438 ret = connector_status_connected; 1439 if (!amdgpu_dig_connector->edp_on) 1440 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1441 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1442 } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1443 ENCODER_OBJECT_ID_NONE) { 1444 /* DP bridges are always DP */ 1445 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1446 /* get the DPCD from the bridge */ 1447 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1448 1449 if (encoder) { 1450 /* setup ddc on the bridge */ 1451 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1452 /* bridge chips are always aux */ 1453 /* try DDC */ 1454 if (amdgpu_display_ddc_probe(amdgpu_connector, true)) 1455 ret = connector_status_connected; 1456 else if (amdgpu_connector->dac_load_detect) { /* try load detection */ 1457 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 1458 1459 ret = encoder_funcs->detect(encoder, connector); 1460 } 1461 } 1462 } else { 1463 amdgpu_dig_connector->dp_sink_type = 1464 amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 1465 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1466 ret = connector_status_connected; 1467 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) 1468 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1469 } else { 1470 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 1471 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1472 ret = connector_status_connected; 1473 } else { 1474 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ 1475 if (amdgpu_display_ddc_probe(amdgpu_connector, 1476 false)) 1477 ret = connector_status_connected; 1478 } 1479 } 1480 } 1481 1482 amdgpu_connector_update_scratch_regs(connector, ret); 1483 out: 1484 if (!drm_kms_helper_is_poll_worker()) 1485 pm_runtime_put_autosuspend(connector->dev->dev); 1486 1487 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 1488 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 1489 drm_dp_set_subconnector_property(&amdgpu_connector->base, 1490 ret, 1491 amdgpu_dig_connector->dpcd, 1492 amdgpu_dig_connector->downstream_ports); 1493 return ret; 1494 } 1495 1496 static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector, 1497 const struct drm_display_mode *mode) 1498 { 1499 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1500 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1501 1502 /* XXX check mode bandwidth */ 1503 1504 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1505 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1506 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1507 1508 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 1509 return MODE_PANEL; 1510 1511 if (encoder) { 1512 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1513 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1514 1515 /* AVIVO hardware supports downscaling modes larger than the panel 1516 * to the panel size, but I'm not sure this is desirable. 1517 */ 1518 if ((mode->hdisplay > native_mode->hdisplay) || 1519 (mode->vdisplay > native_mode->vdisplay)) 1520 return MODE_PANEL; 1521 1522 /* if scaling is disabled, block non-native modes */ 1523 if (amdgpu_encoder->rmx_type == RMX_OFF) { 1524 if ((mode->hdisplay != native_mode->hdisplay) || 1525 (mode->vdisplay != native_mode->vdisplay)) 1526 return MODE_PANEL; 1527 } 1528 } 1529 return MODE_OK; 1530 } else { 1531 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 1532 (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 1533 return amdgpu_atombios_dp_mode_valid_helper(connector, mode); 1534 } else { 1535 if (connector->display_info.is_hdmi) { 1536 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1537 if (mode->clock > 340000) 1538 return MODE_CLOCK_HIGH; 1539 } else { 1540 if (mode->clock > 165000) 1541 return MODE_CLOCK_HIGH; 1542 } 1543 } 1544 } 1545 1546 return MODE_OK; 1547 } 1548 1549 static int 1550 amdgpu_connector_late_register(struct drm_connector *connector) 1551 { 1552 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1553 int r = 0; 1554 1555 if (amdgpu_connector->ddc_bus->has_aux) { 1556 amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev; 1557 r = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux); 1558 } 1559 1560 return r; 1561 } 1562 1563 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = { 1564 .get_modes = amdgpu_connector_dp_get_modes, 1565 .mode_valid = amdgpu_connector_dp_mode_valid, 1566 .best_encoder = amdgpu_connector_dvi_encoder, 1567 }; 1568 1569 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = { 1570 .dpms = drm_helper_connector_dpms, 1571 .detect = amdgpu_connector_dp_detect, 1572 .fill_modes = drm_helper_probe_single_connector_modes, 1573 .set_property = amdgpu_connector_set_property, 1574 .early_unregister = amdgpu_connector_unregister, 1575 .destroy = amdgpu_connector_destroy, 1576 .force = amdgpu_connector_dvi_force, 1577 .late_register = amdgpu_connector_late_register, 1578 }; 1579 1580 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = { 1581 .dpms = drm_helper_connector_dpms, 1582 .detect = amdgpu_connector_dp_detect, 1583 .fill_modes = drm_helper_probe_single_connector_modes, 1584 .set_property = amdgpu_connector_set_lcd_property, 1585 .early_unregister = amdgpu_connector_unregister, 1586 .destroy = amdgpu_connector_destroy, 1587 .force = amdgpu_connector_dvi_force, 1588 .late_register = amdgpu_connector_late_register, 1589 }; 1590 1591 void 1592 amdgpu_connector_add(struct amdgpu_device *adev, 1593 uint32_t connector_id, 1594 uint32_t supported_device, 1595 int connector_type, 1596 struct amdgpu_i2c_bus_rec *i2c_bus, 1597 uint16_t connector_object_id, 1598 struct amdgpu_hpd *hpd, 1599 struct amdgpu_router *router) 1600 { 1601 struct drm_device *dev = adev_to_drm(adev); 1602 struct drm_connector *connector; 1603 struct drm_connector_list_iter iter; 1604 struct amdgpu_connector *amdgpu_connector; 1605 struct amdgpu_connector_atom_dig *amdgpu_dig_connector; 1606 struct drm_encoder *encoder; 1607 struct amdgpu_encoder *amdgpu_encoder; 1608 struct i2c_adapter *ddc = NULL; 1609 uint32_t subpixel_order = SubPixelNone; 1610 bool shared_ddc = false; 1611 bool is_dp_bridge = false; 1612 bool has_aux = false; 1613 1614 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1615 return; 1616 1617 /* see if we already added it */ 1618 drm_connector_list_iter_begin(dev, &iter); 1619 drm_for_each_connector_iter(connector, &iter) { 1620 amdgpu_connector = to_amdgpu_connector(connector); 1621 if (amdgpu_connector->connector_id == connector_id) { 1622 amdgpu_connector->devices |= supported_device; 1623 drm_connector_list_iter_end(&iter); 1624 return; 1625 } 1626 if (amdgpu_connector->ddc_bus && i2c_bus->valid) { 1627 if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) { 1628 amdgpu_connector->shared_ddc = true; 1629 shared_ddc = true; 1630 } 1631 if (amdgpu_connector->router_bus && router->ddc_valid && 1632 (amdgpu_connector->router.router_id == router->router_id)) { 1633 amdgpu_connector->shared_ddc = false; 1634 shared_ddc = false; 1635 } 1636 } 1637 } 1638 drm_connector_list_iter_end(&iter); 1639 1640 /* check if it's a dp bridge */ 1641 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1642 amdgpu_encoder = to_amdgpu_encoder(encoder); 1643 if (amdgpu_encoder->devices & supported_device) { 1644 switch (amdgpu_encoder->encoder_id) { 1645 case ENCODER_OBJECT_ID_TRAVIS: 1646 case ENCODER_OBJECT_ID_NUTMEG: 1647 is_dp_bridge = true; 1648 break; 1649 default: 1650 break; 1651 } 1652 } 1653 } 1654 1655 amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL); 1656 if (!amdgpu_connector) 1657 return; 1658 1659 connector = &amdgpu_connector->base; 1660 1661 amdgpu_connector->connector_id = connector_id; 1662 amdgpu_connector->devices = supported_device; 1663 amdgpu_connector->shared_ddc = shared_ddc; 1664 amdgpu_connector->connector_object_id = connector_object_id; 1665 amdgpu_connector->hpd = *hpd; 1666 1667 amdgpu_connector->router = *router; 1668 if (router->ddc_valid || router->cd_valid) { 1669 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info); 1670 if (!amdgpu_connector->router_bus) 1671 drm_err(adev_to_drm(adev), 1672 "Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); 1673 } 1674 1675 if (is_dp_bridge) { 1676 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1677 if (!amdgpu_dig_connector) 1678 goto failed; 1679 amdgpu_connector->con_priv = amdgpu_dig_connector; 1680 if (i2c_bus->valid) { 1681 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1682 if (amdgpu_connector->ddc_bus) { 1683 has_aux = true; 1684 ddc = &amdgpu_connector->ddc_bus->adapter; 1685 } else { 1686 drm_err(adev_to_drm(adev), 1687 "DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1688 } 1689 } 1690 switch (connector_type) { 1691 case DRM_MODE_CONNECTOR_VGA: 1692 case DRM_MODE_CONNECTOR_DVIA: 1693 default: 1694 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1695 &amdgpu_connector_dp_funcs, 1696 connector_type, 1697 ddc); 1698 drm_connector_helper_add(&amdgpu_connector->base, 1699 &amdgpu_connector_dp_helper_funcs); 1700 connector->interlace_allowed = true; 1701 connector->doublescan_allowed = true; 1702 amdgpu_connector->dac_load_detect = true; 1703 drm_object_attach_property(&amdgpu_connector->base.base, 1704 adev->mode_info.load_detect_property, 1705 1); 1706 drm_object_attach_property(&amdgpu_connector->base.base, 1707 dev->mode_config.scaling_mode_property, 1708 DRM_MODE_SCALE_NONE); 1709 break; 1710 case DRM_MODE_CONNECTOR_DVII: 1711 case DRM_MODE_CONNECTOR_DVID: 1712 case DRM_MODE_CONNECTOR_HDMIA: 1713 case DRM_MODE_CONNECTOR_HDMIB: 1714 case DRM_MODE_CONNECTOR_DisplayPort: 1715 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1716 &amdgpu_connector_dp_funcs, 1717 connector_type, 1718 ddc); 1719 drm_connector_helper_add(&amdgpu_connector->base, 1720 &amdgpu_connector_dp_helper_funcs); 1721 drm_object_attach_property(&amdgpu_connector->base.base, 1722 adev->mode_info.underscan_property, 1723 UNDERSCAN_OFF); 1724 drm_object_attach_property(&amdgpu_connector->base.base, 1725 adev->mode_info.underscan_hborder_property, 1726 0); 1727 drm_object_attach_property(&amdgpu_connector->base.base, 1728 adev->mode_info.underscan_vborder_property, 1729 0); 1730 1731 drm_object_attach_property(&amdgpu_connector->base.base, 1732 dev->mode_config.scaling_mode_property, 1733 DRM_MODE_SCALE_NONE); 1734 1735 drm_object_attach_property(&amdgpu_connector->base.base, 1736 adev->mode_info.dither_property, 1737 AMDGPU_FMT_DITHER_DISABLE); 1738 1739 if (amdgpu_audio != 0) { 1740 drm_object_attach_property(&amdgpu_connector->base.base, 1741 adev->mode_info.audio_property, 1742 AMDGPU_AUDIO_AUTO); 1743 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1744 } 1745 1746 subpixel_order = SubPixelHorizontalRGB; 1747 connector->interlace_allowed = true; 1748 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1749 connector->doublescan_allowed = true; 1750 else 1751 connector->doublescan_allowed = false; 1752 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1753 amdgpu_connector->dac_load_detect = true; 1754 drm_object_attach_property(&amdgpu_connector->base.base, 1755 adev->mode_info.load_detect_property, 1756 1); 1757 } 1758 break; 1759 case DRM_MODE_CONNECTOR_LVDS: 1760 case DRM_MODE_CONNECTOR_eDP: 1761 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1762 &amdgpu_connector_edp_funcs, 1763 connector_type, 1764 ddc); 1765 drm_connector_helper_add(&amdgpu_connector->base, 1766 &amdgpu_connector_dp_helper_funcs); 1767 drm_object_attach_property(&amdgpu_connector->base.base, 1768 dev->mode_config.scaling_mode_property, 1769 DRM_MODE_SCALE_FULLSCREEN); 1770 subpixel_order = SubPixelHorizontalRGB; 1771 connector->interlace_allowed = false; 1772 connector->doublescan_allowed = false; 1773 break; 1774 } 1775 } else { 1776 switch (connector_type) { 1777 case DRM_MODE_CONNECTOR_VGA: 1778 if (i2c_bus->valid) { 1779 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1780 if (!amdgpu_connector->ddc_bus) 1781 drm_err(adev_to_drm(adev), 1782 "VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1783 else 1784 ddc = &amdgpu_connector->ddc_bus->adapter; 1785 } 1786 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1787 &amdgpu_connector_vga_funcs, 1788 connector_type, 1789 ddc); 1790 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1791 amdgpu_connector->dac_load_detect = true; 1792 drm_object_attach_property(&amdgpu_connector->base.base, 1793 adev->mode_info.load_detect_property, 1794 1); 1795 drm_object_attach_property(&amdgpu_connector->base.base, 1796 dev->mode_config.scaling_mode_property, 1797 DRM_MODE_SCALE_NONE); 1798 /* no HPD on analog connectors */ 1799 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1800 connector->interlace_allowed = true; 1801 connector->doublescan_allowed = true; 1802 break; 1803 case DRM_MODE_CONNECTOR_DVIA: 1804 if (i2c_bus->valid) { 1805 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1806 if (!amdgpu_connector->ddc_bus) 1807 drm_err(adev_to_drm(adev), 1808 "DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1809 else 1810 ddc = &amdgpu_connector->ddc_bus->adapter; 1811 } 1812 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1813 &amdgpu_connector_vga_funcs, 1814 connector_type, 1815 ddc); 1816 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1817 amdgpu_connector->dac_load_detect = true; 1818 drm_object_attach_property(&amdgpu_connector->base.base, 1819 adev->mode_info.load_detect_property, 1820 1); 1821 drm_object_attach_property(&amdgpu_connector->base.base, 1822 dev->mode_config.scaling_mode_property, 1823 DRM_MODE_SCALE_NONE); 1824 /* no HPD on analog connectors */ 1825 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1826 connector->interlace_allowed = true; 1827 connector->doublescan_allowed = true; 1828 break; 1829 case DRM_MODE_CONNECTOR_DVII: 1830 case DRM_MODE_CONNECTOR_DVID: 1831 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1832 if (!amdgpu_dig_connector) 1833 goto failed; 1834 amdgpu_connector->con_priv = amdgpu_dig_connector; 1835 if (i2c_bus->valid) { 1836 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1837 if (!amdgpu_connector->ddc_bus) 1838 drm_err(adev_to_drm(adev), 1839 "DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1840 else 1841 ddc = &amdgpu_connector->ddc_bus->adapter; 1842 } 1843 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1844 &amdgpu_connector_dvi_funcs, 1845 connector_type, 1846 ddc); 1847 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1848 subpixel_order = SubPixelHorizontalRGB; 1849 drm_object_attach_property(&amdgpu_connector->base.base, 1850 adev->mode_info.coherent_mode_property, 1851 1); 1852 drm_object_attach_property(&amdgpu_connector->base.base, 1853 adev->mode_info.underscan_property, 1854 UNDERSCAN_OFF); 1855 drm_object_attach_property(&amdgpu_connector->base.base, 1856 adev->mode_info.underscan_hborder_property, 1857 0); 1858 drm_object_attach_property(&amdgpu_connector->base.base, 1859 adev->mode_info.underscan_vborder_property, 1860 0); 1861 drm_object_attach_property(&amdgpu_connector->base.base, 1862 dev->mode_config.scaling_mode_property, 1863 DRM_MODE_SCALE_NONE); 1864 1865 if (amdgpu_audio != 0) { 1866 drm_object_attach_property(&amdgpu_connector->base.base, 1867 adev->mode_info.audio_property, 1868 AMDGPU_AUDIO_AUTO); 1869 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1870 } 1871 drm_object_attach_property(&amdgpu_connector->base.base, 1872 adev->mode_info.dither_property, 1873 AMDGPU_FMT_DITHER_DISABLE); 1874 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1875 amdgpu_connector->dac_load_detect = true; 1876 drm_object_attach_property(&amdgpu_connector->base.base, 1877 adev->mode_info.load_detect_property, 1878 1); 1879 } 1880 connector->interlace_allowed = true; 1881 if (connector_type == DRM_MODE_CONNECTOR_DVII) 1882 connector->doublescan_allowed = true; 1883 else 1884 connector->doublescan_allowed = false; 1885 break; 1886 case DRM_MODE_CONNECTOR_HDMIA: 1887 case DRM_MODE_CONNECTOR_HDMIB: 1888 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1889 if (!amdgpu_dig_connector) 1890 goto failed; 1891 amdgpu_connector->con_priv = amdgpu_dig_connector; 1892 if (i2c_bus->valid) { 1893 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1894 if (!amdgpu_connector->ddc_bus) 1895 drm_err(adev_to_drm(adev), 1896 "HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1897 else 1898 ddc = &amdgpu_connector->ddc_bus->adapter; 1899 } 1900 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1901 &amdgpu_connector_dvi_funcs, 1902 connector_type, 1903 ddc); 1904 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1905 drm_object_attach_property(&amdgpu_connector->base.base, 1906 adev->mode_info.coherent_mode_property, 1907 1); 1908 drm_object_attach_property(&amdgpu_connector->base.base, 1909 adev->mode_info.underscan_property, 1910 UNDERSCAN_OFF); 1911 drm_object_attach_property(&amdgpu_connector->base.base, 1912 adev->mode_info.underscan_hborder_property, 1913 0); 1914 drm_object_attach_property(&amdgpu_connector->base.base, 1915 adev->mode_info.underscan_vborder_property, 1916 0); 1917 drm_object_attach_property(&amdgpu_connector->base.base, 1918 dev->mode_config.scaling_mode_property, 1919 DRM_MODE_SCALE_NONE); 1920 if (amdgpu_audio != 0) { 1921 drm_object_attach_property(&amdgpu_connector->base.base, 1922 adev->mode_info.audio_property, 1923 AMDGPU_AUDIO_AUTO); 1924 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1925 } 1926 drm_object_attach_property(&amdgpu_connector->base.base, 1927 adev->mode_info.dither_property, 1928 AMDGPU_FMT_DITHER_DISABLE); 1929 subpixel_order = SubPixelHorizontalRGB; 1930 connector->interlace_allowed = true; 1931 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1932 connector->doublescan_allowed = true; 1933 else 1934 connector->doublescan_allowed = false; 1935 break; 1936 case DRM_MODE_CONNECTOR_DisplayPort: 1937 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1938 if (!amdgpu_dig_connector) 1939 goto failed; 1940 amdgpu_connector->con_priv = amdgpu_dig_connector; 1941 if (i2c_bus->valid) { 1942 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1943 if (amdgpu_connector->ddc_bus) { 1944 has_aux = true; 1945 ddc = &amdgpu_connector->ddc_bus->adapter; 1946 } else { 1947 drm_err(adev_to_drm(adev), 1948 "DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1949 } 1950 } 1951 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1952 &amdgpu_connector_dp_funcs, 1953 connector_type, 1954 ddc); 1955 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1956 subpixel_order = SubPixelHorizontalRGB; 1957 drm_object_attach_property(&amdgpu_connector->base.base, 1958 adev->mode_info.coherent_mode_property, 1959 1); 1960 drm_object_attach_property(&amdgpu_connector->base.base, 1961 adev->mode_info.underscan_property, 1962 UNDERSCAN_OFF); 1963 drm_object_attach_property(&amdgpu_connector->base.base, 1964 adev->mode_info.underscan_hborder_property, 1965 0); 1966 drm_object_attach_property(&amdgpu_connector->base.base, 1967 adev->mode_info.underscan_vborder_property, 1968 0); 1969 drm_object_attach_property(&amdgpu_connector->base.base, 1970 dev->mode_config.scaling_mode_property, 1971 DRM_MODE_SCALE_NONE); 1972 if (amdgpu_audio != 0) { 1973 drm_object_attach_property(&amdgpu_connector->base.base, 1974 adev->mode_info.audio_property, 1975 AMDGPU_AUDIO_AUTO); 1976 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1977 } 1978 drm_object_attach_property(&amdgpu_connector->base.base, 1979 adev->mode_info.dither_property, 1980 AMDGPU_FMT_DITHER_DISABLE); 1981 connector->interlace_allowed = true; 1982 /* in theory with a DP to VGA converter... */ 1983 connector->doublescan_allowed = false; 1984 break; 1985 case DRM_MODE_CONNECTOR_eDP: 1986 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1987 if (!amdgpu_dig_connector) 1988 goto failed; 1989 amdgpu_connector->con_priv = amdgpu_dig_connector; 1990 if (i2c_bus->valid) { 1991 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1992 if (amdgpu_connector->ddc_bus) { 1993 has_aux = true; 1994 ddc = &amdgpu_connector->ddc_bus->adapter; 1995 } else { 1996 drm_err(adev_to_drm(adev), 1997 "eDP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1998 } 1999 } 2000 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 2001 &amdgpu_connector_edp_funcs, 2002 connector_type, 2003 ddc); 2004 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 2005 drm_object_attach_property(&amdgpu_connector->base.base, 2006 dev->mode_config.scaling_mode_property, 2007 DRM_MODE_SCALE_FULLSCREEN); 2008 subpixel_order = SubPixelHorizontalRGB; 2009 connector->interlace_allowed = false; 2010 connector->doublescan_allowed = false; 2011 break; 2012 case DRM_MODE_CONNECTOR_LVDS: 2013 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 2014 if (!amdgpu_dig_connector) 2015 goto failed; 2016 amdgpu_connector->con_priv = amdgpu_dig_connector; 2017 if (i2c_bus->valid) { 2018 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 2019 if (!amdgpu_connector->ddc_bus) 2020 drm_err(adev_to_drm(adev), 2021 "LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 2022 else 2023 ddc = &amdgpu_connector->ddc_bus->adapter; 2024 } 2025 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 2026 &amdgpu_connector_lvds_funcs, 2027 connector_type, 2028 ddc); 2029 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); 2030 drm_object_attach_property(&amdgpu_connector->base.base, 2031 dev->mode_config.scaling_mode_property, 2032 DRM_MODE_SCALE_FULLSCREEN); 2033 subpixel_order = SubPixelHorizontalRGB; 2034 connector->interlace_allowed = false; 2035 connector->doublescan_allowed = false; 2036 break; 2037 } 2038 } 2039 2040 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) { 2041 if (i2c_bus->valid) { 2042 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 2043 DRM_CONNECTOR_POLL_DISCONNECT; 2044 } 2045 } else 2046 connector->polled = DRM_CONNECTOR_POLL_HPD; 2047 2048 connector->display_info.subpixel_order = subpixel_order; 2049 2050 if (has_aux) 2051 amdgpu_atombios_dp_aux_init(amdgpu_connector); 2052 2053 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort || 2054 connector_type == DRM_MODE_CONNECTOR_eDP) { 2055 drm_connector_attach_dp_subconnector_property(&amdgpu_connector->base); 2056 } 2057 2058 return; 2059 2060 failed: 2061 drm_connector_cleanup(connector); 2062 kfree(connector); 2063 } 2064