1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27 #include <drm/display/drm_dp_helper.h> 28 #include <drm/drm_crtc_helper.h> 29 #include <drm/drm_edid.h> 30 #include <drm/drm_modeset_helper_vtables.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/amdgpu_drm.h> 33 #include "amdgpu.h" 34 #include "atom.h" 35 #include "atombios_encoders.h" 36 #include "atombios_dp.h" 37 #include "amdgpu_connectors.h" 38 #include "amdgpu_i2c.h" 39 #include "amdgpu_display.h" 40 41 #include <linux/pm_runtime.h> 42 43 void amdgpu_connector_hotplug(struct drm_connector *connector) 44 { 45 struct drm_device *dev = connector->dev; 46 struct amdgpu_device *adev = drm_to_adev(dev); 47 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 48 49 /* bail if the connector does not have hpd pin, e.g., 50 * VGA, TV, etc. 51 */ 52 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) 53 return; 54 55 amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 56 57 /* if the connector is already off, don't turn it back on */ 58 if (connector->dpms != DRM_MODE_DPMS_ON) 59 return; 60 61 /* just deal with DP (not eDP) here. */ 62 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 63 struct amdgpu_connector_atom_dig *dig_connector = 64 amdgpu_connector->con_priv; 65 66 /* if existing sink type was not DP no need to retrain */ 67 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) 68 return; 69 70 /* first get sink type as it may be reset after (un)plug */ 71 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 72 /* don't do anything if sink is not display port, i.e., 73 * passive dp->(dvi|hdmi) adaptor 74 */ 75 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT && 76 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) && 77 amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 78 /* Don't start link training before we have the DPCD */ 79 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 80 return; 81 82 /* Turn the connector off and back on immediately, which 83 * will trigger link training 84 */ 85 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 86 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 87 } 88 } 89 } 90 91 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder) 92 { 93 struct drm_crtc *crtc = encoder->crtc; 94 95 if (crtc && crtc->enabled) { 96 drm_crtc_helper_set_mode(crtc, &crtc->mode, 97 crtc->x, crtc->y, crtc->primary->fb); 98 } 99 } 100 101 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) 102 { 103 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 104 struct amdgpu_connector_atom_dig *dig_connector; 105 int bpc = 8; 106 unsigned int mode_clock, max_tmds_clock; 107 108 switch (connector->connector_type) { 109 case DRM_MODE_CONNECTOR_DVII: 110 case DRM_MODE_CONNECTOR_HDMIB: 111 if (amdgpu_connector->use_digital) { 112 if (connector->display_info.is_hdmi) { 113 if (connector->display_info.bpc) 114 bpc = connector->display_info.bpc; 115 } 116 } 117 break; 118 case DRM_MODE_CONNECTOR_DVID: 119 case DRM_MODE_CONNECTOR_HDMIA: 120 if (connector->display_info.is_hdmi) { 121 if (connector->display_info.bpc) 122 bpc = connector->display_info.bpc; 123 } 124 break; 125 case DRM_MODE_CONNECTOR_DisplayPort: 126 dig_connector = amdgpu_connector->con_priv; 127 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 128 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || 129 connector->display_info.is_hdmi) { 130 if (connector->display_info.bpc) 131 bpc = connector->display_info.bpc; 132 } 133 break; 134 case DRM_MODE_CONNECTOR_eDP: 135 case DRM_MODE_CONNECTOR_LVDS: 136 if (connector->display_info.bpc) 137 bpc = connector->display_info.bpc; 138 else { 139 const struct drm_connector_helper_funcs *connector_funcs = 140 connector->helper_private; 141 struct drm_encoder *encoder = connector_funcs->best_encoder(connector); 142 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 143 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 144 145 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR) 146 bpc = 6; 147 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR) 148 bpc = 8; 149 } 150 break; 151 } 152 153 if (connector->display_info.is_hdmi) { 154 /* 155 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make 156 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at 157 * 12 bpc is always supported on hdmi deep color sinks, as this is 158 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. 159 */ 160 if (bpc > 12) { 161 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", 162 connector->name, bpc); 163 bpc = 12; 164 } 165 166 /* Any defined maximum tmds clock limit we must not exceed? */ 167 if (connector->display_info.max_tmds_clock > 0) { 168 /* mode_clock is clock in kHz for mode to be modeset on this connector */ 169 mode_clock = amdgpu_connector->pixelclock_for_modeset; 170 171 /* Maximum allowable input clock in kHz */ 172 max_tmds_clock = connector->display_info.max_tmds_clock; 173 174 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n", 175 connector->name, mode_clock, max_tmds_clock); 176 177 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ 178 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { 179 if ((connector->display_info.edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) && 180 (mode_clock * 5/4 <= max_tmds_clock)) 181 bpc = 10; 182 else 183 bpc = 8; 184 185 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", 186 connector->name, bpc); 187 } 188 189 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { 190 bpc = 8; 191 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", 192 connector->name, bpc); 193 } 194 } else if (bpc > 8) { 195 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ 196 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", 197 connector->name); 198 bpc = 8; 199 } 200 } 201 202 if ((amdgpu_deep_color == 0) && (bpc > 8)) { 203 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n", 204 connector->name); 205 bpc = 8; 206 } 207 208 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", 209 connector->name, connector->display_info.bpc, bpc); 210 211 return bpc; 212 } 213 214 static void 215 amdgpu_connector_update_scratch_regs(struct drm_connector *connector, 216 enum drm_connector_status status) 217 { 218 struct drm_encoder *best_encoder; 219 struct drm_encoder *encoder; 220 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 221 bool connected; 222 223 best_encoder = connector_funcs->best_encoder(connector); 224 225 drm_connector_for_each_possible_encoder(connector, encoder) { 226 if ((encoder == best_encoder) && (status == connector_status_connected)) 227 connected = true; 228 else 229 connected = false; 230 231 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected); 232 } 233 } 234 235 static struct drm_encoder * 236 amdgpu_connector_find_encoder(struct drm_connector *connector, 237 int encoder_type) 238 { 239 struct drm_encoder *encoder; 240 241 drm_connector_for_each_possible_encoder(connector, encoder) { 242 if (encoder->encoder_type == encoder_type) 243 return encoder; 244 } 245 246 return NULL; 247 } 248 249 static struct edid * 250 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) 251 { 252 return drm_edid_duplicate(drm_edid_raw(adev->mode_info.bios_hardcoded_edid)); 253 } 254 255 static void amdgpu_connector_get_edid(struct drm_connector *connector) 256 { 257 struct drm_device *dev = connector->dev; 258 struct amdgpu_device *adev = drm_to_adev(dev); 259 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 260 261 if (amdgpu_connector->edid) 262 return; 263 264 /* on hw with routers, select right port */ 265 if (amdgpu_connector->router.ddc_valid) 266 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 267 268 if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 269 ENCODER_OBJECT_ID_NONE) && 270 amdgpu_connector->ddc_bus->has_aux) { 271 amdgpu_connector->edid = drm_get_edid(connector, 272 &amdgpu_connector->ddc_bus->aux.ddc); 273 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 274 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 275 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; 276 277 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 278 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && 279 amdgpu_connector->ddc_bus->has_aux) 280 amdgpu_connector->edid = drm_get_edid(connector, 281 &amdgpu_connector->ddc_bus->aux.ddc); 282 else if (amdgpu_connector->ddc_bus) 283 amdgpu_connector->edid = drm_get_edid(connector, 284 &amdgpu_connector->ddc_bus->adapter); 285 } else if (amdgpu_connector->ddc_bus) { 286 amdgpu_connector->edid = drm_get_edid(connector, 287 &amdgpu_connector->ddc_bus->adapter); 288 } 289 290 if (!amdgpu_connector->edid) { 291 /* some laptops provide a hardcoded edid in rom for LCDs */ 292 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || 293 (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) { 294 amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev); 295 drm_connector_update_edid_property(connector, amdgpu_connector->edid); 296 } 297 } 298 } 299 300 static void amdgpu_connector_free_edid(struct drm_connector *connector) 301 { 302 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 303 304 kfree(amdgpu_connector->edid); 305 amdgpu_connector->edid = NULL; 306 } 307 308 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) 309 { 310 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 311 int ret; 312 313 if (amdgpu_connector->edid) { 314 drm_connector_update_edid_property(connector, amdgpu_connector->edid); 315 ret = drm_add_edid_modes(connector, amdgpu_connector->edid); 316 return ret; 317 } 318 drm_connector_update_edid_property(connector, NULL); 319 return 0; 320 } 321 322 static struct drm_encoder * 323 amdgpu_connector_best_single_encoder(struct drm_connector *connector) 324 { 325 struct drm_encoder *encoder; 326 327 /* pick the first one */ 328 drm_connector_for_each_possible_encoder(connector, encoder) 329 return encoder; 330 331 return NULL; 332 } 333 334 static void amdgpu_get_native_mode(struct drm_connector *connector) 335 { 336 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 337 struct amdgpu_encoder *amdgpu_encoder; 338 339 if (encoder == NULL) 340 return; 341 342 amdgpu_encoder = to_amdgpu_encoder(encoder); 343 344 if (!list_empty(&connector->probed_modes)) { 345 struct drm_display_mode *preferred_mode = 346 list_first_entry(&connector->probed_modes, 347 struct drm_display_mode, head); 348 349 amdgpu_encoder->native_mode = *preferred_mode; 350 } else { 351 amdgpu_encoder->native_mode.clock = 0; 352 } 353 } 354 355 static struct drm_display_mode * 356 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder) 357 { 358 struct drm_device *dev = encoder->dev; 359 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 360 struct drm_display_mode *mode = NULL; 361 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 362 363 if (native_mode->hdisplay != 0 && 364 native_mode->vdisplay != 0 && 365 native_mode->clock != 0) { 366 mode = drm_mode_duplicate(dev, native_mode); 367 if (!mode) 368 return NULL; 369 370 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 371 drm_mode_set_name(mode); 372 373 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); 374 } else if (native_mode->hdisplay != 0 && 375 native_mode->vdisplay != 0) { 376 /* mac laptops without an edid */ 377 /* Note that this is not necessarily the exact panel mode, 378 * but an approximation based on the cvt formula. For these 379 * systems we should ideally read the mode info out of the 380 * registers or add a mode table, but this works and is much 381 * simpler. 382 */ 383 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); 384 if (!mode) 385 return NULL; 386 387 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 388 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); 389 } 390 return mode; 391 } 392 393 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, 394 struct drm_connector *connector) 395 { 396 struct drm_device *dev = encoder->dev; 397 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 398 struct drm_display_mode *mode = NULL; 399 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 400 int i; 401 int n; 402 struct mode_size { 403 char name[DRM_DISPLAY_MODE_LEN]; 404 int w; 405 int h; 406 } common_modes[] = { 407 { "640x480", 640, 480}, 408 { "800x600", 800, 600}, 409 { "1024x768", 1024, 768}, 410 { "1280x720", 1280, 720}, 411 { "1280x800", 1280, 800}, 412 {"1280x1024", 1280, 1024}, 413 { "1440x900", 1440, 900}, 414 {"1680x1050", 1680, 1050}, 415 {"1600x1200", 1600, 1200}, 416 {"1920x1080", 1920, 1080}, 417 {"1920x1200", 1920, 1200} 418 }; 419 420 n = ARRAY_SIZE(common_modes); 421 422 for (i = 0; i < n; i++) { 423 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 424 if (common_modes[i].w > 1024 || 425 common_modes[i].h > 768) 426 continue; 427 } 428 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 429 if (common_modes[i].w > native_mode->hdisplay || 430 common_modes[i].h > native_mode->vdisplay || 431 (common_modes[i].w == native_mode->hdisplay && 432 common_modes[i].h == native_mode->vdisplay)) 433 continue; 434 } 435 436 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); 437 if (!mode) 438 return; 439 strscpy(mode->name, common_modes[i].name, DRM_DISPLAY_MODE_LEN); 440 441 drm_mode_probed_add(connector, mode); 442 } 443 } 444 445 static int amdgpu_connector_set_property(struct drm_connector *connector, 446 struct drm_property *property, 447 uint64_t val) 448 { 449 struct drm_device *dev = connector->dev; 450 struct amdgpu_device *adev = drm_to_adev(dev); 451 struct drm_encoder *encoder; 452 struct amdgpu_encoder *amdgpu_encoder; 453 454 if (property == adev->mode_info.coherent_mode_property) { 455 struct amdgpu_encoder_atom_dig *dig; 456 bool new_coherent_mode; 457 458 /* need to find digital encoder on connector */ 459 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 460 if (!encoder) 461 return 0; 462 463 amdgpu_encoder = to_amdgpu_encoder(encoder); 464 465 if (!amdgpu_encoder->enc_priv) 466 return 0; 467 468 dig = amdgpu_encoder->enc_priv; 469 new_coherent_mode = val ? true : false; 470 if (dig->coherent_mode != new_coherent_mode) { 471 dig->coherent_mode = new_coherent_mode; 472 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 473 } 474 } 475 476 if (property == adev->mode_info.audio_property) { 477 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 478 /* need to find digital encoder on connector */ 479 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 480 if (!encoder) 481 return 0; 482 483 amdgpu_encoder = to_amdgpu_encoder(encoder); 484 485 if (amdgpu_connector->audio != val) { 486 amdgpu_connector->audio = val; 487 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 488 } 489 } 490 491 if (property == adev->mode_info.dither_property) { 492 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 493 /* need to find digital encoder on connector */ 494 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 495 if (!encoder) 496 return 0; 497 498 amdgpu_encoder = to_amdgpu_encoder(encoder); 499 500 if (amdgpu_connector->dither != val) { 501 amdgpu_connector->dither = val; 502 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 503 } 504 } 505 506 if (property == adev->mode_info.underscan_property) { 507 /* need to find digital encoder on connector */ 508 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 509 if (!encoder) 510 return 0; 511 512 amdgpu_encoder = to_amdgpu_encoder(encoder); 513 514 if (amdgpu_encoder->underscan_type != val) { 515 amdgpu_encoder->underscan_type = val; 516 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 517 } 518 } 519 520 if (property == adev->mode_info.underscan_hborder_property) { 521 /* need to find digital encoder on connector */ 522 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 523 if (!encoder) 524 return 0; 525 526 amdgpu_encoder = to_amdgpu_encoder(encoder); 527 528 if (amdgpu_encoder->underscan_hborder != val) { 529 amdgpu_encoder->underscan_hborder = val; 530 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 531 } 532 } 533 534 if (property == adev->mode_info.underscan_vborder_property) { 535 /* need to find digital encoder on connector */ 536 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 537 if (!encoder) 538 return 0; 539 540 amdgpu_encoder = to_amdgpu_encoder(encoder); 541 542 if (amdgpu_encoder->underscan_vborder != val) { 543 amdgpu_encoder->underscan_vborder = val; 544 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 545 } 546 } 547 548 if (property == adev->mode_info.load_detect_property) { 549 struct amdgpu_connector *amdgpu_connector = 550 to_amdgpu_connector(connector); 551 552 if (val == 0) 553 amdgpu_connector->dac_load_detect = false; 554 else 555 amdgpu_connector->dac_load_detect = true; 556 } 557 558 if (property == dev->mode_config.scaling_mode_property) { 559 enum amdgpu_rmx_type rmx_type; 560 561 if (connector->encoder) { 562 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 563 } else { 564 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 565 566 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 567 } 568 569 switch (val) { 570 default: 571 case DRM_MODE_SCALE_NONE: 572 rmx_type = RMX_OFF; 573 break; 574 case DRM_MODE_SCALE_CENTER: 575 rmx_type = RMX_CENTER; 576 break; 577 case DRM_MODE_SCALE_ASPECT: 578 rmx_type = RMX_ASPECT; 579 break; 580 case DRM_MODE_SCALE_FULLSCREEN: 581 rmx_type = RMX_FULL; 582 break; 583 } 584 585 if (amdgpu_encoder->rmx_type == rmx_type) 586 return 0; 587 588 if ((rmx_type != DRM_MODE_SCALE_NONE) && 589 (amdgpu_encoder->native_mode.clock == 0)) 590 return 0; 591 592 amdgpu_encoder->rmx_type = rmx_type; 593 594 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 595 } 596 597 return 0; 598 } 599 600 static void 601 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder, 602 struct drm_connector *connector) 603 { 604 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 605 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 606 struct drm_display_mode *t, *mode; 607 608 /* If the EDID preferred mode doesn't match the native mode, use it */ 609 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 610 if (mode->type & DRM_MODE_TYPE_PREFERRED) { 611 if (mode->hdisplay != native_mode->hdisplay || 612 mode->vdisplay != native_mode->vdisplay) 613 drm_mode_copy(native_mode, mode); 614 } 615 } 616 617 /* Try to get native mode details from EDID if necessary */ 618 if (!native_mode->clock) { 619 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 620 if (mode->hdisplay == native_mode->hdisplay && 621 mode->vdisplay == native_mode->vdisplay) { 622 drm_mode_copy(native_mode, mode); 623 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); 624 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); 625 break; 626 } 627 } 628 } 629 630 if (!native_mode->clock) { 631 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n"); 632 amdgpu_encoder->rmx_type = RMX_OFF; 633 } 634 } 635 636 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) 637 { 638 struct drm_encoder *encoder; 639 int ret = 0; 640 struct drm_display_mode *mode; 641 642 amdgpu_connector_get_edid(connector); 643 ret = amdgpu_connector_ddc_get_modes(connector); 644 if (ret > 0) { 645 encoder = amdgpu_connector_best_single_encoder(connector); 646 if (encoder) { 647 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 648 /* add scaled modes */ 649 amdgpu_connector_add_common_modes(encoder, connector); 650 } 651 return ret; 652 } 653 654 encoder = amdgpu_connector_best_single_encoder(connector); 655 if (!encoder) 656 return 0; 657 658 /* we have no EDID modes */ 659 mode = amdgpu_connector_lcd_native_mode(encoder); 660 if (mode) { 661 ret = 1; 662 drm_mode_probed_add(connector, mode); 663 /* add the width/height from vbios tables if available */ 664 connector->display_info.width_mm = mode->width_mm; 665 connector->display_info.height_mm = mode->height_mm; 666 /* add scaled modes */ 667 amdgpu_connector_add_common_modes(encoder, connector); 668 } 669 670 return ret; 671 } 672 673 static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, 674 const struct drm_display_mode *mode) 675 { 676 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 677 678 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 679 return MODE_PANEL; 680 681 if (encoder) { 682 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 683 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 684 685 /* AVIVO hardware supports downscaling modes larger than the panel 686 * to the panel size, but I'm not sure this is desirable. 687 */ 688 if ((mode->hdisplay > native_mode->hdisplay) || 689 (mode->vdisplay > native_mode->vdisplay)) 690 return MODE_PANEL; 691 692 /* if scaling is disabled, block non-native modes */ 693 if (amdgpu_encoder->rmx_type == RMX_OFF) { 694 if ((mode->hdisplay != native_mode->hdisplay) || 695 (mode->vdisplay != native_mode->vdisplay)) 696 return MODE_PANEL; 697 } 698 } 699 700 return MODE_OK; 701 } 702 703 static enum drm_connector_status 704 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force) 705 { 706 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 707 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 708 enum drm_connector_status ret = connector_status_disconnected; 709 int r; 710 711 if (!drm_kms_helper_is_poll_worker()) { 712 r = pm_runtime_get_sync(connector->dev->dev); 713 if (r < 0) { 714 pm_runtime_put_autosuspend(connector->dev->dev); 715 return connector_status_disconnected; 716 } 717 } 718 719 if (encoder) { 720 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 721 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 722 723 /* check if panel is valid */ 724 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 725 ret = connector_status_connected; 726 727 } 728 729 /* check for edid as well */ 730 amdgpu_connector_get_edid(connector); 731 if (amdgpu_connector->edid) 732 ret = connector_status_connected; 733 /* check acpi lid status ??? */ 734 735 amdgpu_connector_update_scratch_regs(connector, ret); 736 737 if (!drm_kms_helper_is_poll_worker()) { 738 pm_runtime_mark_last_busy(connector->dev->dev); 739 pm_runtime_put_autosuspend(connector->dev->dev); 740 } 741 742 return ret; 743 } 744 745 static void amdgpu_connector_unregister(struct drm_connector *connector) 746 { 747 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 748 749 if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) { 750 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); 751 amdgpu_connector->ddc_bus->has_aux = false; 752 } 753 } 754 755 static void amdgpu_connector_destroy(struct drm_connector *connector) 756 { 757 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 758 759 amdgpu_connector_free_edid(connector); 760 kfree(amdgpu_connector->con_priv); 761 drm_connector_unregister(connector); 762 drm_connector_cleanup(connector); 763 kfree(connector); 764 } 765 766 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector, 767 struct drm_property *property, 768 uint64_t value) 769 { 770 struct drm_device *dev = connector->dev; 771 struct amdgpu_encoder *amdgpu_encoder; 772 enum amdgpu_rmx_type rmx_type; 773 774 DRM_DEBUG_KMS("\n"); 775 if (property != dev->mode_config.scaling_mode_property) 776 return 0; 777 778 if (connector->encoder) 779 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 780 else { 781 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 782 783 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 784 } 785 786 switch (value) { 787 case DRM_MODE_SCALE_NONE: 788 rmx_type = RMX_OFF; 789 break; 790 case DRM_MODE_SCALE_CENTER: 791 rmx_type = RMX_CENTER; 792 break; 793 case DRM_MODE_SCALE_ASPECT: 794 rmx_type = RMX_ASPECT; 795 break; 796 default: 797 case DRM_MODE_SCALE_FULLSCREEN: 798 rmx_type = RMX_FULL; 799 break; 800 } 801 802 if (amdgpu_encoder->rmx_type == rmx_type) 803 return 0; 804 805 amdgpu_encoder->rmx_type = rmx_type; 806 807 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 808 return 0; 809 } 810 811 812 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = { 813 .get_modes = amdgpu_connector_lvds_get_modes, 814 .mode_valid = amdgpu_connector_lvds_mode_valid, 815 .best_encoder = amdgpu_connector_best_single_encoder, 816 }; 817 818 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = { 819 .dpms = drm_helper_connector_dpms, 820 .detect = amdgpu_connector_lvds_detect, 821 .fill_modes = drm_helper_probe_single_connector_modes, 822 .early_unregister = amdgpu_connector_unregister, 823 .destroy = amdgpu_connector_destroy, 824 .set_property = amdgpu_connector_set_lcd_property, 825 }; 826 827 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) 828 { 829 int ret; 830 831 amdgpu_connector_get_edid(connector); 832 ret = amdgpu_connector_ddc_get_modes(connector); 833 amdgpu_get_native_mode(connector); 834 835 return ret; 836 } 837 838 static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector, 839 const struct drm_display_mode *mode) 840 { 841 struct drm_device *dev = connector->dev; 842 struct amdgpu_device *adev = drm_to_adev(dev); 843 844 /* XXX check mode bandwidth */ 845 846 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 847 return MODE_CLOCK_HIGH; 848 849 return MODE_OK; 850 } 851 852 static enum drm_connector_status 853 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) 854 { 855 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 856 struct drm_encoder *encoder; 857 const struct drm_encoder_helper_funcs *encoder_funcs; 858 bool dret = false; 859 enum drm_connector_status ret = connector_status_disconnected; 860 int r; 861 862 if (!drm_kms_helper_is_poll_worker()) { 863 r = pm_runtime_get_sync(connector->dev->dev); 864 if (r < 0) { 865 pm_runtime_put_autosuspend(connector->dev->dev); 866 return connector_status_disconnected; 867 } 868 } 869 870 encoder = amdgpu_connector_best_single_encoder(connector); 871 if (!encoder) 872 ret = connector_status_disconnected; 873 874 if (amdgpu_connector->ddc_bus) 875 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 876 if (dret) { 877 amdgpu_connector->detected_by_load = false; 878 amdgpu_connector_free_edid(connector); 879 amdgpu_connector_get_edid(connector); 880 881 if (!amdgpu_connector->edid) { 882 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 883 connector->name); 884 ret = connector_status_connected; 885 } else { 886 amdgpu_connector->use_digital = 887 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 888 889 /* some oems have boards with separate digital and analog connectors 890 * with a shared ddc line (often vga + hdmi) 891 */ 892 if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) { 893 amdgpu_connector_free_edid(connector); 894 ret = connector_status_disconnected; 895 } else { 896 ret = connector_status_connected; 897 } 898 } 899 } else { 900 901 /* if we aren't forcing don't do destructive polling */ 902 if (!force) { 903 /* only return the previous status if we last 904 * detected a monitor via load. 905 */ 906 if (amdgpu_connector->detected_by_load) 907 ret = connector->status; 908 goto out; 909 } 910 911 if (amdgpu_connector->dac_load_detect && encoder) { 912 encoder_funcs = encoder->helper_private; 913 ret = encoder_funcs->detect(encoder, connector); 914 if (ret != connector_status_disconnected) 915 amdgpu_connector->detected_by_load = true; 916 } 917 } 918 919 amdgpu_connector_update_scratch_regs(connector, ret); 920 921 out: 922 if (!drm_kms_helper_is_poll_worker()) { 923 pm_runtime_mark_last_busy(connector->dev->dev); 924 pm_runtime_put_autosuspend(connector->dev->dev); 925 } 926 927 return ret; 928 } 929 930 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = { 931 .get_modes = amdgpu_connector_vga_get_modes, 932 .mode_valid = amdgpu_connector_vga_mode_valid, 933 .best_encoder = amdgpu_connector_best_single_encoder, 934 }; 935 936 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = { 937 .dpms = drm_helper_connector_dpms, 938 .detect = amdgpu_connector_vga_detect, 939 .fill_modes = drm_helper_probe_single_connector_modes, 940 .early_unregister = amdgpu_connector_unregister, 941 .destroy = amdgpu_connector_destroy, 942 .set_property = amdgpu_connector_set_property, 943 }; 944 945 static bool 946 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector) 947 { 948 struct drm_device *dev = connector->dev; 949 struct amdgpu_device *adev = drm_to_adev(dev); 950 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 951 enum drm_connector_status status; 952 953 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) { 954 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) 955 status = connector_status_connected; 956 else 957 status = connector_status_disconnected; 958 if (connector->status == status) 959 return true; 960 } 961 962 return false; 963 } 964 965 static void amdgpu_connector_shared_ddc(enum drm_connector_status *status, 966 struct drm_connector *connector, 967 struct amdgpu_connector *amdgpu_connector) 968 { 969 struct drm_connector *list_connector; 970 struct drm_connector_list_iter iter; 971 struct amdgpu_connector *list_amdgpu_connector; 972 struct drm_device *dev = connector->dev; 973 struct amdgpu_device *adev = drm_to_adev(dev); 974 975 if (amdgpu_connector->shared_ddc && *status == connector_status_connected) { 976 drm_connector_list_iter_begin(dev, &iter); 977 drm_for_each_connector_iter(list_connector, 978 &iter) { 979 if (connector == list_connector) 980 continue; 981 list_amdgpu_connector = to_amdgpu_connector(list_connector); 982 if (list_amdgpu_connector->shared_ddc && 983 list_amdgpu_connector->ddc_bus->rec.i2c_id == 984 amdgpu_connector->ddc_bus->rec.i2c_id) { 985 /* cases where both connectors are digital */ 986 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { 987 /* hpd is our only option in this case */ 988 if (!amdgpu_display_hpd_sense(adev, 989 amdgpu_connector->hpd.hpd)) { 990 amdgpu_connector_free_edid(connector); 991 *status = connector_status_disconnected; 992 } 993 } 994 } 995 } 996 drm_connector_list_iter_end(&iter); 997 } 998 } 999 1000 /* 1001 * DVI is complicated 1002 * Do a DDC probe, if DDC probe passes, get the full EDID so 1003 * we can do analog/digital monitor detection at this point. 1004 * If the monitor is an analog monitor or we got no DDC, 1005 * we need to find the DAC encoder object for this connector. 1006 * If we got no DDC, we do load detection on the DAC encoder object. 1007 * If we got analog DDC or load detection passes on the DAC encoder 1008 * we have to check if this analog encoder is shared with anyone else (TV) 1009 * if its shared we have to set the other connector to disconnected. 1010 */ 1011 static enum drm_connector_status 1012 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) 1013 { 1014 struct drm_device *dev = connector->dev; 1015 struct amdgpu_device *adev = drm_to_adev(dev); 1016 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1017 const struct drm_encoder_helper_funcs *encoder_funcs; 1018 int r; 1019 enum drm_connector_status ret = connector_status_disconnected; 1020 bool dret = false, broken_edid = false; 1021 1022 if (!drm_kms_helper_is_poll_worker()) { 1023 r = pm_runtime_get_sync(connector->dev->dev); 1024 if (r < 0) { 1025 pm_runtime_put_autosuspend(connector->dev->dev); 1026 return connector_status_disconnected; 1027 } 1028 } 1029 1030 if (amdgpu_connector->detected_hpd_without_ddc) { 1031 force = true; 1032 amdgpu_connector->detected_hpd_without_ddc = false; 1033 } 1034 1035 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1036 ret = connector->status; 1037 goto exit; 1038 } 1039 1040 if (amdgpu_connector->ddc_bus) { 1041 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 1042 1043 /* Sometimes the pins required for the DDC probe on DVI 1044 * connectors don't make contact at the same time that the ones 1045 * for HPD do. If the DDC probe fails even though we had an HPD 1046 * signal, try again later 1047 */ 1048 if (!dret && !force && 1049 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1050 DRM_DEBUG_KMS("hpd detected without ddc, retrying in 1 second\n"); 1051 amdgpu_connector->detected_hpd_without_ddc = true; 1052 schedule_delayed_work(&adev->hotplug_work, 1053 msecs_to_jiffies(1000)); 1054 goto exit; 1055 } 1056 } 1057 if (dret) { 1058 amdgpu_connector->detected_by_load = false; 1059 amdgpu_connector_free_edid(connector); 1060 amdgpu_connector_get_edid(connector); 1061 1062 if (!amdgpu_connector->edid) { 1063 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 1064 connector->name); 1065 ret = connector_status_connected; 1066 broken_edid = true; /* defer use_digital to later */ 1067 } else { 1068 amdgpu_connector->use_digital = 1069 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 1070 1071 /* some oems have boards with separate digital and analog connectors 1072 * with a shared ddc line (often vga + hdmi) 1073 */ 1074 if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) { 1075 amdgpu_connector_free_edid(connector); 1076 ret = connector_status_disconnected; 1077 } else { 1078 ret = connector_status_connected; 1079 } 1080 1081 /* This gets complicated. We have boards with VGA + HDMI with a 1082 * shared DDC line and we have boards with DVI-D + HDMI with a shared 1083 * DDC line. The latter is more complex because with DVI<->HDMI adapters 1084 * you don't really know what's connected to which port as both are digital. 1085 */ 1086 amdgpu_connector_shared_ddc(&ret, connector, amdgpu_connector); 1087 } 1088 } 1089 1090 if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true)) 1091 goto out; 1092 1093 /* DVI-D and HDMI-A are digital only */ 1094 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) || 1095 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)) 1096 goto out; 1097 1098 /* if we aren't forcing don't do destructive polling */ 1099 if (!force) { 1100 /* only return the previous status if we last 1101 * detected a monitor via load. 1102 */ 1103 if (amdgpu_connector->detected_by_load) 1104 ret = connector->status; 1105 goto out; 1106 } 1107 1108 /* find analog encoder */ 1109 if (amdgpu_connector->dac_load_detect) { 1110 struct drm_encoder *encoder; 1111 1112 drm_connector_for_each_possible_encoder(connector, encoder) { 1113 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && 1114 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) 1115 continue; 1116 1117 encoder_funcs = encoder->helper_private; 1118 if (encoder_funcs->detect) { 1119 if (!broken_edid) { 1120 if (ret != connector_status_connected) { 1121 /* deal with analog monitors without DDC */ 1122 ret = encoder_funcs->detect(encoder, connector); 1123 if (ret == connector_status_connected) { 1124 amdgpu_connector->use_digital = false; 1125 } 1126 if (ret != connector_status_disconnected) 1127 amdgpu_connector->detected_by_load = true; 1128 } 1129 } else { 1130 enum drm_connector_status lret; 1131 /* assume digital unless load detected otherwise */ 1132 amdgpu_connector->use_digital = true; 1133 lret = encoder_funcs->detect(encoder, connector); 1134 DRM_DEBUG_KMS("load_detect %x returned: %x\n", 1135 encoder->encoder_type, lret); 1136 if (lret == connector_status_connected) 1137 amdgpu_connector->use_digital = false; 1138 } 1139 break; 1140 } 1141 } 1142 } 1143 1144 out: 1145 /* updated in get modes as well since we need to know if it's analog or digital */ 1146 amdgpu_connector_update_scratch_regs(connector, ret); 1147 1148 exit: 1149 if (!drm_kms_helper_is_poll_worker()) { 1150 pm_runtime_mark_last_busy(connector->dev->dev); 1151 pm_runtime_put_autosuspend(connector->dev->dev); 1152 } 1153 1154 return ret; 1155 } 1156 1157 /* okay need to be smart in here about which encoder to pick */ 1158 static struct drm_encoder * 1159 amdgpu_connector_dvi_encoder(struct drm_connector *connector) 1160 { 1161 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1162 struct drm_encoder *encoder; 1163 1164 drm_connector_for_each_possible_encoder(connector, encoder) { 1165 if (amdgpu_connector->use_digital == true) { 1166 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) 1167 return encoder; 1168 } else { 1169 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC || 1170 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1171 return encoder; 1172 } 1173 } 1174 1175 /* see if we have a default encoder TODO */ 1176 1177 /* then check use digitial */ 1178 /* pick the first one */ 1179 drm_connector_for_each_possible_encoder(connector, encoder) 1180 return encoder; 1181 1182 return NULL; 1183 } 1184 1185 static void amdgpu_connector_dvi_force(struct drm_connector *connector) 1186 { 1187 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1188 1189 if (connector->force == DRM_FORCE_ON) 1190 amdgpu_connector->use_digital = false; 1191 if (connector->force == DRM_FORCE_ON_DIGITAL) 1192 amdgpu_connector->use_digital = true; 1193 } 1194 1195 /** 1196 * amdgpu_max_hdmi_pixel_clock - Return max supported HDMI (TMDS) pixel clock 1197 * @adev: pointer to amdgpu_device 1198 * 1199 * Return: maximum supported HDMI (TMDS) pixel clock in KHz. 1200 */ 1201 static int amdgpu_max_hdmi_pixel_clock(const struct amdgpu_device *adev) 1202 { 1203 if (adev->asic_type >= CHIP_POLARIS10) 1204 return 600000; 1205 else if (adev->asic_type >= CHIP_TONGA) 1206 return 300000; 1207 else 1208 return 297000; 1209 } 1210 1211 /** 1212 * amdgpu_connector_dvi_mode_valid - Validate a mode on DVI/HDMI connectors 1213 * @connector: DRM connector to validate the mode on 1214 * @mode: display mode to validate 1215 * 1216 * Validate the given display mode on DVI and HDMI connectors, including 1217 * analog signals on DVI-I. 1218 * 1219 * Return: drm_mode_status indicating whether the mode is valid. 1220 */ 1221 static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, 1222 const struct drm_display_mode *mode) 1223 { 1224 struct drm_device *dev = connector->dev; 1225 struct amdgpu_device *adev = drm_to_adev(dev); 1226 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1227 const int max_hdmi_pixel_clock = amdgpu_max_hdmi_pixel_clock(adev); 1228 const int max_dvi_single_link_pixel_clock = 165000; 1229 int max_digital_pixel_clock_khz; 1230 1231 /* XXX check mode bandwidth */ 1232 1233 if (amdgpu_connector->use_digital) { 1234 switch (amdgpu_connector->connector_object_id) { 1235 case CONNECTOR_OBJECT_ID_HDMI_TYPE_A: 1236 max_digital_pixel_clock_khz = max_hdmi_pixel_clock; 1237 break; 1238 case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I: 1239 case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D: 1240 max_digital_pixel_clock_khz = max_dvi_single_link_pixel_clock; 1241 break; 1242 case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I: 1243 case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D: 1244 case CONNECTOR_OBJECT_ID_HDMI_TYPE_B: 1245 max_digital_pixel_clock_khz = max_dvi_single_link_pixel_clock * 2; 1246 break; 1247 } 1248 1249 /* When the display EDID claims that it's an HDMI display, 1250 * we use the HDMI encoder mode of the display HW, 1251 * so we should verify against the max HDMI clock here. 1252 */ 1253 if (connector->display_info.is_hdmi) 1254 max_digital_pixel_clock_khz = max_hdmi_pixel_clock; 1255 1256 if (mode->clock > max_digital_pixel_clock_khz) 1257 return MODE_CLOCK_HIGH; 1258 } 1259 1260 /* check against the max pixel clock */ 1261 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 1262 return MODE_CLOCK_HIGH; 1263 1264 return MODE_OK; 1265 } 1266 1267 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = { 1268 .get_modes = amdgpu_connector_vga_get_modes, 1269 .mode_valid = amdgpu_connector_dvi_mode_valid, 1270 .best_encoder = amdgpu_connector_dvi_encoder, 1271 }; 1272 1273 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = { 1274 .dpms = drm_helper_connector_dpms, 1275 .detect = amdgpu_connector_dvi_detect, 1276 .fill_modes = drm_helper_probe_single_connector_modes, 1277 .set_property = amdgpu_connector_set_property, 1278 .early_unregister = amdgpu_connector_unregister, 1279 .destroy = amdgpu_connector_destroy, 1280 .force = amdgpu_connector_dvi_force, 1281 }; 1282 1283 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) 1284 { 1285 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1286 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1287 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1288 int ret; 1289 1290 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1291 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1292 struct drm_display_mode *mode; 1293 1294 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1295 if (!amdgpu_dig_connector->edp_on) 1296 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1297 ATOM_TRANSMITTER_ACTION_POWER_ON); 1298 amdgpu_connector_get_edid(connector); 1299 ret = amdgpu_connector_ddc_get_modes(connector); 1300 if (!amdgpu_dig_connector->edp_on) 1301 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1302 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1303 } else { 1304 /* need to setup ddc on the bridge */ 1305 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1306 ENCODER_OBJECT_ID_NONE) { 1307 if (encoder) 1308 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1309 } 1310 amdgpu_connector_get_edid(connector); 1311 ret = amdgpu_connector_ddc_get_modes(connector); 1312 } 1313 1314 if (ret > 0) { 1315 if (encoder) { 1316 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 1317 /* add scaled modes */ 1318 amdgpu_connector_add_common_modes(encoder, connector); 1319 } 1320 return ret; 1321 } 1322 1323 if (!encoder) 1324 return 0; 1325 1326 /* we have no EDID modes */ 1327 mode = amdgpu_connector_lcd_native_mode(encoder); 1328 if (mode) { 1329 ret = 1; 1330 drm_mode_probed_add(connector, mode); 1331 /* add the width/height from vbios tables if available */ 1332 connector->display_info.width_mm = mode->width_mm; 1333 connector->display_info.height_mm = mode->height_mm; 1334 /* add scaled modes */ 1335 amdgpu_connector_add_common_modes(encoder, connector); 1336 } 1337 } else { 1338 /* need to setup ddc on the bridge */ 1339 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1340 ENCODER_OBJECT_ID_NONE) { 1341 if (encoder) 1342 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1343 } 1344 amdgpu_connector_get_edid(connector); 1345 ret = amdgpu_connector_ddc_get_modes(connector); 1346 1347 amdgpu_get_native_mode(connector); 1348 } 1349 1350 return ret; 1351 } 1352 1353 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) 1354 { 1355 struct drm_encoder *encoder; 1356 struct amdgpu_encoder *amdgpu_encoder; 1357 1358 drm_connector_for_each_possible_encoder(connector, encoder) { 1359 amdgpu_encoder = to_amdgpu_encoder(encoder); 1360 1361 switch (amdgpu_encoder->encoder_id) { 1362 case ENCODER_OBJECT_ID_TRAVIS: 1363 case ENCODER_OBJECT_ID_NUTMEG: 1364 return amdgpu_encoder->encoder_id; 1365 default: 1366 break; 1367 } 1368 } 1369 1370 return ENCODER_OBJECT_ID_NONE; 1371 } 1372 1373 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) 1374 { 1375 struct drm_encoder *encoder; 1376 struct amdgpu_encoder *amdgpu_encoder; 1377 bool found = false; 1378 1379 drm_connector_for_each_possible_encoder(connector, encoder) { 1380 amdgpu_encoder = to_amdgpu_encoder(encoder); 1381 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) 1382 found = true; 1383 } 1384 1385 return found; 1386 } 1387 1388 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector) 1389 { 1390 struct drm_device *dev = connector->dev; 1391 struct amdgpu_device *adev = drm_to_adev(dev); 1392 1393 if ((adev->clock.default_dispclk >= 53900) && 1394 amdgpu_connector_encoder_is_hbr2(connector)) { 1395 return true; 1396 } 1397 1398 return false; 1399 } 1400 1401 static enum drm_connector_status 1402 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) 1403 { 1404 struct drm_device *dev = connector->dev; 1405 struct amdgpu_device *adev = drm_to_adev(dev); 1406 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1407 enum drm_connector_status ret = connector_status_disconnected; 1408 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1409 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1410 int r; 1411 1412 if (!drm_kms_helper_is_poll_worker()) { 1413 r = pm_runtime_get_sync(connector->dev->dev); 1414 if (r < 0) { 1415 pm_runtime_put_autosuspend(connector->dev->dev); 1416 return connector_status_disconnected; 1417 } 1418 } 1419 1420 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1421 ret = connector->status; 1422 goto out; 1423 } 1424 1425 amdgpu_connector_free_edid(connector); 1426 1427 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1428 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1429 if (encoder) { 1430 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1431 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1432 1433 /* check if panel is valid */ 1434 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 1435 ret = connector_status_connected; 1436 } 1437 /* eDP is always DP */ 1438 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1439 if (!amdgpu_dig_connector->edp_on) 1440 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1441 ATOM_TRANSMITTER_ACTION_POWER_ON); 1442 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1443 ret = connector_status_connected; 1444 if (!amdgpu_dig_connector->edp_on) 1445 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1446 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1447 } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1448 ENCODER_OBJECT_ID_NONE) { 1449 /* DP bridges are always DP */ 1450 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1451 /* get the DPCD from the bridge */ 1452 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1453 1454 if (encoder) { 1455 /* setup ddc on the bridge */ 1456 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1457 /* bridge chips are always aux */ 1458 /* try DDC */ 1459 if (amdgpu_display_ddc_probe(amdgpu_connector, true)) 1460 ret = connector_status_connected; 1461 else if (amdgpu_connector->dac_load_detect) { /* try load detection */ 1462 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 1463 1464 ret = encoder_funcs->detect(encoder, connector); 1465 } 1466 } 1467 } else { 1468 amdgpu_dig_connector->dp_sink_type = 1469 amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 1470 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1471 ret = connector_status_connected; 1472 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) 1473 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1474 } else { 1475 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 1476 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1477 ret = connector_status_connected; 1478 } else { 1479 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ 1480 if (amdgpu_display_ddc_probe(amdgpu_connector, 1481 false)) 1482 ret = connector_status_connected; 1483 } 1484 } 1485 } 1486 1487 amdgpu_connector_update_scratch_regs(connector, ret); 1488 out: 1489 if (!drm_kms_helper_is_poll_worker()) { 1490 pm_runtime_mark_last_busy(connector->dev->dev); 1491 pm_runtime_put_autosuspend(connector->dev->dev); 1492 } 1493 1494 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 1495 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 1496 drm_dp_set_subconnector_property(&amdgpu_connector->base, 1497 ret, 1498 amdgpu_dig_connector->dpcd, 1499 amdgpu_dig_connector->downstream_ports); 1500 return ret; 1501 } 1502 1503 static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector, 1504 const struct drm_display_mode *mode) 1505 { 1506 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1507 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1508 1509 /* XXX check mode bandwidth */ 1510 1511 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1512 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1513 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1514 1515 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 1516 return MODE_PANEL; 1517 1518 if (encoder) { 1519 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1520 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1521 1522 /* AVIVO hardware supports downscaling modes larger than the panel 1523 * to the panel size, but I'm not sure this is desirable. 1524 */ 1525 if ((mode->hdisplay > native_mode->hdisplay) || 1526 (mode->vdisplay > native_mode->vdisplay)) 1527 return MODE_PANEL; 1528 1529 /* if scaling is disabled, block non-native modes */ 1530 if (amdgpu_encoder->rmx_type == RMX_OFF) { 1531 if ((mode->hdisplay != native_mode->hdisplay) || 1532 (mode->vdisplay != native_mode->vdisplay)) 1533 return MODE_PANEL; 1534 } 1535 } 1536 return MODE_OK; 1537 } else { 1538 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 1539 (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 1540 return amdgpu_atombios_dp_mode_valid_helper(connector, mode); 1541 } else { 1542 if (connector->display_info.is_hdmi) { 1543 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1544 if (mode->clock > 340000) 1545 return MODE_CLOCK_HIGH; 1546 } else { 1547 if (mode->clock > 165000) 1548 return MODE_CLOCK_HIGH; 1549 } 1550 } 1551 } 1552 1553 return MODE_OK; 1554 } 1555 1556 static int 1557 amdgpu_connector_late_register(struct drm_connector *connector) 1558 { 1559 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1560 int r = 0; 1561 1562 if (amdgpu_connector->ddc_bus->has_aux) { 1563 amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev; 1564 r = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux); 1565 } 1566 1567 return r; 1568 } 1569 1570 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = { 1571 .get_modes = amdgpu_connector_dp_get_modes, 1572 .mode_valid = amdgpu_connector_dp_mode_valid, 1573 .best_encoder = amdgpu_connector_dvi_encoder, 1574 }; 1575 1576 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = { 1577 .dpms = drm_helper_connector_dpms, 1578 .detect = amdgpu_connector_dp_detect, 1579 .fill_modes = drm_helper_probe_single_connector_modes, 1580 .set_property = amdgpu_connector_set_property, 1581 .early_unregister = amdgpu_connector_unregister, 1582 .destroy = amdgpu_connector_destroy, 1583 .force = amdgpu_connector_dvi_force, 1584 .late_register = amdgpu_connector_late_register, 1585 }; 1586 1587 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = { 1588 .dpms = drm_helper_connector_dpms, 1589 .detect = amdgpu_connector_dp_detect, 1590 .fill_modes = drm_helper_probe_single_connector_modes, 1591 .set_property = amdgpu_connector_set_lcd_property, 1592 .early_unregister = amdgpu_connector_unregister, 1593 .destroy = amdgpu_connector_destroy, 1594 .force = amdgpu_connector_dvi_force, 1595 .late_register = amdgpu_connector_late_register, 1596 }; 1597 1598 void 1599 amdgpu_connector_add(struct amdgpu_device *adev, 1600 uint32_t connector_id, 1601 uint32_t supported_device, 1602 int connector_type, 1603 struct amdgpu_i2c_bus_rec *i2c_bus, 1604 uint16_t connector_object_id, 1605 struct amdgpu_hpd *hpd, 1606 struct amdgpu_router *router) 1607 { 1608 struct drm_device *dev = adev_to_drm(adev); 1609 struct drm_connector *connector; 1610 struct drm_connector_list_iter iter; 1611 struct amdgpu_connector *amdgpu_connector; 1612 struct amdgpu_connector_atom_dig *amdgpu_dig_connector; 1613 struct drm_encoder *encoder; 1614 struct amdgpu_encoder *amdgpu_encoder; 1615 struct i2c_adapter *ddc = NULL; 1616 uint32_t subpixel_order = SubPixelNone; 1617 bool shared_ddc = false; 1618 bool is_dp_bridge = false; 1619 bool has_aux = false; 1620 1621 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1622 return; 1623 1624 /* see if we already added it */ 1625 drm_connector_list_iter_begin(dev, &iter); 1626 drm_for_each_connector_iter(connector, &iter) { 1627 amdgpu_connector = to_amdgpu_connector(connector); 1628 if (amdgpu_connector->connector_id == connector_id) { 1629 amdgpu_connector->devices |= supported_device; 1630 drm_connector_list_iter_end(&iter); 1631 return; 1632 } 1633 if (amdgpu_connector->ddc_bus && i2c_bus->valid) { 1634 if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) { 1635 amdgpu_connector->shared_ddc = true; 1636 shared_ddc = true; 1637 } 1638 if (amdgpu_connector->router_bus && router->ddc_valid && 1639 (amdgpu_connector->router.router_id == router->router_id)) { 1640 amdgpu_connector->shared_ddc = false; 1641 shared_ddc = false; 1642 } 1643 } 1644 } 1645 drm_connector_list_iter_end(&iter); 1646 1647 /* check if it's a dp bridge */ 1648 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1649 amdgpu_encoder = to_amdgpu_encoder(encoder); 1650 if (amdgpu_encoder->devices & supported_device) { 1651 switch (amdgpu_encoder->encoder_id) { 1652 case ENCODER_OBJECT_ID_TRAVIS: 1653 case ENCODER_OBJECT_ID_NUTMEG: 1654 is_dp_bridge = true; 1655 break; 1656 default: 1657 break; 1658 } 1659 } 1660 } 1661 1662 amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL); 1663 if (!amdgpu_connector) 1664 return; 1665 1666 connector = &amdgpu_connector->base; 1667 1668 amdgpu_connector->connector_id = connector_id; 1669 amdgpu_connector->devices = supported_device; 1670 amdgpu_connector->shared_ddc = shared_ddc; 1671 amdgpu_connector->connector_object_id = connector_object_id; 1672 amdgpu_connector->hpd = *hpd; 1673 1674 amdgpu_connector->router = *router; 1675 if (router->ddc_valid || router->cd_valid) { 1676 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info); 1677 if (!amdgpu_connector->router_bus) 1678 DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); 1679 } 1680 1681 if (is_dp_bridge) { 1682 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1683 if (!amdgpu_dig_connector) 1684 goto failed; 1685 amdgpu_connector->con_priv = amdgpu_dig_connector; 1686 if (i2c_bus->valid) { 1687 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1688 if (amdgpu_connector->ddc_bus) { 1689 has_aux = true; 1690 ddc = &amdgpu_connector->ddc_bus->adapter; 1691 } else { 1692 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1693 } 1694 } 1695 switch (connector_type) { 1696 case DRM_MODE_CONNECTOR_VGA: 1697 case DRM_MODE_CONNECTOR_DVIA: 1698 default: 1699 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1700 &amdgpu_connector_dp_funcs, 1701 connector_type, 1702 ddc); 1703 drm_connector_helper_add(&amdgpu_connector->base, 1704 &amdgpu_connector_dp_helper_funcs); 1705 connector->interlace_allowed = true; 1706 connector->doublescan_allowed = true; 1707 amdgpu_connector->dac_load_detect = true; 1708 drm_object_attach_property(&amdgpu_connector->base.base, 1709 adev->mode_info.load_detect_property, 1710 1); 1711 drm_object_attach_property(&amdgpu_connector->base.base, 1712 dev->mode_config.scaling_mode_property, 1713 DRM_MODE_SCALE_NONE); 1714 break; 1715 case DRM_MODE_CONNECTOR_DVII: 1716 case DRM_MODE_CONNECTOR_DVID: 1717 case DRM_MODE_CONNECTOR_HDMIA: 1718 case DRM_MODE_CONNECTOR_HDMIB: 1719 case DRM_MODE_CONNECTOR_DisplayPort: 1720 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1721 &amdgpu_connector_dp_funcs, 1722 connector_type, 1723 ddc); 1724 drm_connector_helper_add(&amdgpu_connector->base, 1725 &amdgpu_connector_dp_helper_funcs); 1726 drm_object_attach_property(&amdgpu_connector->base.base, 1727 adev->mode_info.underscan_property, 1728 UNDERSCAN_OFF); 1729 drm_object_attach_property(&amdgpu_connector->base.base, 1730 adev->mode_info.underscan_hborder_property, 1731 0); 1732 drm_object_attach_property(&amdgpu_connector->base.base, 1733 adev->mode_info.underscan_vborder_property, 1734 0); 1735 1736 drm_object_attach_property(&amdgpu_connector->base.base, 1737 dev->mode_config.scaling_mode_property, 1738 DRM_MODE_SCALE_NONE); 1739 1740 drm_object_attach_property(&amdgpu_connector->base.base, 1741 adev->mode_info.dither_property, 1742 AMDGPU_FMT_DITHER_DISABLE); 1743 1744 if (amdgpu_audio != 0) { 1745 drm_object_attach_property(&amdgpu_connector->base.base, 1746 adev->mode_info.audio_property, 1747 AMDGPU_AUDIO_AUTO); 1748 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1749 } 1750 1751 subpixel_order = SubPixelHorizontalRGB; 1752 connector->interlace_allowed = true; 1753 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1754 connector->doublescan_allowed = true; 1755 else 1756 connector->doublescan_allowed = false; 1757 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1758 amdgpu_connector->dac_load_detect = true; 1759 drm_object_attach_property(&amdgpu_connector->base.base, 1760 adev->mode_info.load_detect_property, 1761 1); 1762 } 1763 break; 1764 case DRM_MODE_CONNECTOR_LVDS: 1765 case DRM_MODE_CONNECTOR_eDP: 1766 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1767 &amdgpu_connector_edp_funcs, 1768 connector_type, 1769 ddc); 1770 drm_connector_helper_add(&amdgpu_connector->base, 1771 &amdgpu_connector_dp_helper_funcs); 1772 drm_object_attach_property(&amdgpu_connector->base.base, 1773 dev->mode_config.scaling_mode_property, 1774 DRM_MODE_SCALE_FULLSCREEN); 1775 subpixel_order = SubPixelHorizontalRGB; 1776 connector->interlace_allowed = false; 1777 connector->doublescan_allowed = false; 1778 break; 1779 } 1780 } else { 1781 switch (connector_type) { 1782 case DRM_MODE_CONNECTOR_VGA: 1783 if (i2c_bus->valid) { 1784 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1785 if (!amdgpu_connector->ddc_bus) 1786 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1787 else 1788 ddc = &amdgpu_connector->ddc_bus->adapter; 1789 } 1790 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1791 &amdgpu_connector_vga_funcs, 1792 connector_type, 1793 ddc); 1794 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1795 amdgpu_connector->dac_load_detect = true; 1796 drm_object_attach_property(&amdgpu_connector->base.base, 1797 adev->mode_info.load_detect_property, 1798 1); 1799 drm_object_attach_property(&amdgpu_connector->base.base, 1800 dev->mode_config.scaling_mode_property, 1801 DRM_MODE_SCALE_NONE); 1802 /* no HPD on analog connectors */ 1803 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1804 connector->interlace_allowed = true; 1805 connector->doublescan_allowed = true; 1806 break; 1807 case DRM_MODE_CONNECTOR_DVIA: 1808 if (i2c_bus->valid) { 1809 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1810 if (!amdgpu_connector->ddc_bus) 1811 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1812 else 1813 ddc = &amdgpu_connector->ddc_bus->adapter; 1814 } 1815 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1816 &amdgpu_connector_vga_funcs, 1817 connector_type, 1818 ddc); 1819 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1820 amdgpu_connector->dac_load_detect = true; 1821 drm_object_attach_property(&amdgpu_connector->base.base, 1822 adev->mode_info.load_detect_property, 1823 1); 1824 drm_object_attach_property(&amdgpu_connector->base.base, 1825 dev->mode_config.scaling_mode_property, 1826 DRM_MODE_SCALE_NONE); 1827 /* no HPD on analog connectors */ 1828 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1829 connector->interlace_allowed = true; 1830 connector->doublescan_allowed = true; 1831 break; 1832 case DRM_MODE_CONNECTOR_DVII: 1833 case DRM_MODE_CONNECTOR_DVID: 1834 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1835 if (!amdgpu_dig_connector) 1836 goto failed; 1837 amdgpu_connector->con_priv = amdgpu_dig_connector; 1838 if (i2c_bus->valid) { 1839 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1840 if (!amdgpu_connector->ddc_bus) 1841 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1842 else 1843 ddc = &amdgpu_connector->ddc_bus->adapter; 1844 } 1845 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1846 &amdgpu_connector_dvi_funcs, 1847 connector_type, 1848 ddc); 1849 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1850 subpixel_order = SubPixelHorizontalRGB; 1851 drm_object_attach_property(&amdgpu_connector->base.base, 1852 adev->mode_info.coherent_mode_property, 1853 1); 1854 drm_object_attach_property(&amdgpu_connector->base.base, 1855 adev->mode_info.underscan_property, 1856 UNDERSCAN_OFF); 1857 drm_object_attach_property(&amdgpu_connector->base.base, 1858 adev->mode_info.underscan_hborder_property, 1859 0); 1860 drm_object_attach_property(&amdgpu_connector->base.base, 1861 adev->mode_info.underscan_vborder_property, 1862 0); 1863 drm_object_attach_property(&amdgpu_connector->base.base, 1864 dev->mode_config.scaling_mode_property, 1865 DRM_MODE_SCALE_NONE); 1866 1867 if (amdgpu_audio != 0) { 1868 drm_object_attach_property(&amdgpu_connector->base.base, 1869 adev->mode_info.audio_property, 1870 AMDGPU_AUDIO_AUTO); 1871 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1872 } 1873 drm_object_attach_property(&amdgpu_connector->base.base, 1874 adev->mode_info.dither_property, 1875 AMDGPU_FMT_DITHER_DISABLE); 1876 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1877 amdgpu_connector->dac_load_detect = true; 1878 drm_object_attach_property(&amdgpu_connector->base.base, 1879 adev->mode_info.load_detect_property, 1880 1); 1881 } 1882 connector->interlace_allowed = true; 1883 if (connector_type == DRM_MODE_CONNECTOR_DVII) 1884 connector->doublescan_allowed = true; 1885 else 1886 connector->doublescan_allowed = false; 1887 break; 1888 case DRM_MODE_CONNECTOR_HDMIA: 1889 case DRM_MODE_CONNECTOR_HDMIB: 1890 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1891 if (!amdgpu_dig_connector) 1892 goto failed; 1893 amdgpu_connector->con_priv = amdgpu_dig_connector; 1894 if (i2c_bus->valid) { 1895 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1896 if (!amdgpu_connector->ddc_bus) 1897 DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1898 else 1899 ddc = &amdgpu_connector->ddc_bus->adapter; 1900 } 1901 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1902 &amdgpu_connector_dvi_funcs, 1903 connector_type, 1904 ddc); 1905 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1906 drm_object_attach_property(&amdgpu_connector->base.base, 1907 adev->mode_info.coherent_mode_property, 1908 1); 1909 drm_object_attach_property(&amdgpu_connector->base.base, 1910 adev->mode_info.underscan_property, 1911 UNDERSCAN_OFF); 1912 drm_object_attach_property(&amdgpu_connector->base.base, 1913 adev->mode_info.underscan_hborder_property, 1914 0); 1915 drm_object_attach_property(&amdgpu_connector->base.base, 1916 adev->mode_info.underscan_vborder_property, 1917 0); 1918 drm_object_attach_property(&amdgpu_connector->base.base, 1919 dev->mode_config.scaling_mode_property, 1920 DRM_MODE_SCALE_NONE); 1921 if (amdgpu_audio != 0) { 1922 drm_object_attach_property(&amdgpu_connector->base.base, 1923 adev->mode_info.audio_property, 1924 AMDGPU_AUDIO_AUTO); 1925 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1926 } 1927 drm_object_attach_property(&amdgpu_connector->base.base, 1928 adev->mode_info.dither_property, 1929 AMDGPU_FMT_DITHER_DISABLE); 1930 subpixel_order = SubPixelHorizontalRGB; 1931 connector->interlace_allowed = true; 1932 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1933 connector->doublescan_allowed = true; 1934 else 1935 connector->doublescan_allowed = false; 1936 break; 1937 case DRM_MODE_CONNECTOR_DisplayPort: 1938 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1939 if (!amdgpu_dig_connector) 1940 goto failed; 1941 amdgpu_connector->con_priv = amdgpu_dig_connector; 1942 if (i2c_bus->valid) { 1943 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1944 if (amdgpu_connector->ddc_bus) { 1945 has_aux = true; 1946 ddc = &amdgpu_connector->ddc_bus->adapter; 1947 } else { 1948 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1949 } 1950 } 1951 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1952 &amdgpu_connector_dp_funcs, 1953 connector_type, 1954 ddc); 1955 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1956 subpixel_order = SubPixelHorizontalRGB; 1957 drm_object_attach_property(&amdgpu_connector->base.base, 1958 adev->mode_info.coherent_mode_property, 1959 1); 1960 drm_object_attach_property(&amdgpu_connector->base.base, 1961 adev->mode_info.underscan_property, 1962 UNDERSCAN_OFF); 1963 drm_object_attach_property(&amdgpu_connector->base.base, 1964 adev->mode_info.underscan_hborder_property, 1965 0); 1966 drm_object_attach_property(&amdgpu_connector->base.base, 1967 adev->mode_info.underscan_vborder_property, 1968 0); 1969 drm_object_attach_property(&amdgpu_connector->base.base, 1970 dev->mode_config.scaling_mode_property, 1971 DRM_MODE_SCALE_NONE); 1972 if (amdgpu_audio != 0) { 1973 drm_object_attach_property(&amdgpu_connector->base.base, 1974 adev->mode_info.audio_property, 1975 AMDGPU_AUDIO_AUTO); 1976 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1977 } 1978 drm_object_attach_property(&amdgpu_connector->base.base, 1979 adev->mode_info.dither_property, 1980 AMDGPU_FMT_DITHER_DISABLE); 1981 connector->interlace_allowed = true; 1982 /* in theory with a DP to VGA converter... */ 1983 connector->doublescan_allowed = false; 1984 break; 1985 case DRM_MODE_CONNECTOR_eDP: 1986 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1987 if (!amdgpu_dig_connector) 1988 goto failed; 1989 amdgpu_connector->con_priv = amdgpu_dig_connector; 1990 if (i2c_bus->valid) { 1991 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1992 if (amdgpu_connector->ddc_bus) { 1993 has_aux = true; 1994 ddc = &amdgpu_connector->ddc_bus->adapter; 1995 } else { 1996 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1997 } 1998 } 1999 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 2000 &amdgpu_connector_edp_funcs, 2001 connector_type, 2002 ddc); 2003 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 2004 drm_object_attach_property(&amdgpu_connector->base.base, 2005 dev->mode_config.scaling_mode_property, 2006 DRM_MODE_SCALE_FULLSCREEN); 2007 subpixel_order = SubPixelHorizontalRGB; 2008 connector->interlace_allowed = false; 2009 connector->doublescan_allowed = false; 2010 break; 2011 case DRM_MODE_CONNECTOR_LVDS: 2012 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 2013 if (!amdgpu_dig_connector) 2014 goto failed; 2015 amdgpu_connector->con_priv = amdgpu_dig_connector; 2016 if (i2c_bus->valid) { 2017 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 2018 if (!amdgpu_connector->ddc_bus) 2019 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 2020 else 2021 ddc = &amdgpu_connector->ddc_bus->adapter; 2022 } 2023 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 2024 &amdgpu_connector_lvds_funcs, 2025 connector_type, 2026 ddc); 2027 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); 2028 drm_object_attach_property(&amdgpu_connector->base.base, 2029 dev->mode_config.scaling_mode_property, 2030 DRM_MODE_SCALE_FULLSCREEN); 2031 subpixel_order = SubPixelHorizontalRGB; 2032 connector->interlace_allowed = false; 2033 connector->doublescan_allowed = false; 2034 break; 2035 } 2036 } 2037 2038 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) { 2039 if (i2c_bus->valid) { 2040 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 2041 DRM_CONNECTOR_POLL_DISCONNECT; 2042 } 2043 } else 2044 connector->polled = DRM_CONNECTOR_POLL_HPD; 2045 2046 connector->display_info.subpixel_order = subpixel_order; 2047 2048 if (has_aux) 2049 amdgpu_atombios_dp_aux_init(amdgpu_connector); 2050 2051 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort || 2052 connector_type == DRM_MODE_CONNECTOR_eDP) { 2053 drm_connector_attach_dp_subconnector_property(&amdgpu_connector->base); 2054 } 2055 2056 return; 2057 2058 failed: 2059 drm_connector_cleanup(connector); 2060 kfree(connector); 2061 } 2062