1d38ceaf9SAlex Deucher /* 2d38ceaf9SAlex Deucher * Copyright 2007-8 Advanced Micro Devices, Inc. 3d38ceaf9SAlex Deucher * Copyright 2008 Red Hat Inc. 4d38ceaf9SAlex Deucher * 5d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 6d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the "Software"), 7d38ceaf9SAlex Deucher * to deal in the Software without restriction, including without limitation 8d38ceaf9SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9d38ceaf9SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 10d38ceaf9SAlex Deucher * Software is furnished to do so, subject to the following conditions: 11d38ceaf9SAlex Deucher * 12d38ceaf9SAlex Deucher * The above copyright notice and this permission notice shall be included in 13d38ceaf9SAlex Deucher * all copies or substantial portions of the Software. 14d38ceaf9SAlex Deucher * 15d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19d38ceaf9SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20d38ceaf9SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21d38ceaf9SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 22d38ceaf9SAlex Deucher * 23d38ceaf9SAlex Deucher * Authors: Dave Airlie 24d38ceaf9SAlex Deucher * Alex Deucher 25d38ceaf9SAlex Deucher */ 26fdf2f6c5SSam Ravnborg 27da68386dSThomas Zimmermann #include <drm/display/drm_dp_helper.h> 28973ad627SThomas Zimmermann #include <drm/drm_crtc_helper.h> 29d38ceaf9SAlex Deucher #include <drm/drm_edid.h> 30973ad627SThomas Zimmermann #include <drm/drm_modeset_helper_vtables.h> 31fcd70cd3SDaniel Vetter #include <drm/drm_probe_helper.h> 32d38ceaf9SAlex Deucher #include <drm/amdgpu_drm.h> 33d38ceaf9SAlex Deucher #include "amdgpu.h" 34d38ceaf9SAlex Deucher #include "atom.h" 35d38ceaf9SAlex Deucher #include "atombios_encoders.h" 36d38ceaf9SAlex Deucher #include "atombios_dp.h" 37d38ceaf9SAlex Deucher #include "amdgpu_connectors.h" 38d38ceaf9SAlex Deucher #include "amdgpu_i2c.h" 395df58525SHuang Rui #include "amdgpu_display.h" 40d38ceaf9SAlex Deucher 41d38ceaf9SAlex Deucher #include <linux/pm_runtime.h> 42d38ceaf9SAlex Deucher 43d38ceaf9SAlex Deucher void amdgpu_connector_hotplug(struct drm_connector *connector) 44d38ceaf9SAlex Deucher { 45d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 461348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev); 47d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 48d38ceaf9SAlex Deucher 49d38ceaf9SAlex Deucher /* bail if the connector does not have hpd pin, e.g., 50d38ceaf9SAlex Deucher * VGA, TV, etc. 51d38ceaf9SAlex Deucher */ 52d38ceaf9SAlex Deucher if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) 53d38ceaf9SAlex Deucher return; 54d38ceaf9SAlex Deucher 55d38ceaf9SAlex Deucher amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 56d38ceaf9SAlex Deucher 57d38ceaf9SAlex Deucher /* if the connector is already off, don't turn it back on */ 58d38ceaf9SAlex Deucher if (connector->dpms != DRM_MODE_DPMS_ON) 59d38ceaf9SAlex Deucher return; 60d38ceaf9SAlex Deucher 61d38ceaf9SAlex Deucher /* just deal with DP (not eDP) here. */ 62d38ceaf9SAlex Deucher if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 63d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *dig_connector = 64d38ceaf9SAlex Deucher amdgpu_connector->con_priv; 65d38ceaf9SAlex Deucher 66d38ceaf9SAlex Deucher /* if existing sink type was not DP no need to retrain */ 67d38ceaf9SAlex Deucher if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) 68d38ceaf9SAlex Deucher return; 69d38ceaf9SAlex Deucher 70d38ceaf9SAlex Deucher /* first get sink type as it may be reset after (un)plug */ 71d38ceaf9SAlex Deucher dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 72d38ceaf9SAlex Deucher /* don't do anything if sink is not display port, i.e., 73d38ceaf9SAlex Deucher * passive dp->(dvi|hdmi) adaptor 74d38ceaf9SAlex Deucher */ 75daf88096SMichel Dänzer if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT && 76daf88096SMichel Dänzer amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) && 77daf88096SMichel Dänzer amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 78daf88096SMichel Dänzer /* Don't start link training before we have the DPCD */ 790b39c531SArindam Nath if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 80a887adadSAlex Deucher return; 81a887adadSAlex Deucher 82daf88096SMichel Dänzer /* Turn the connector off and back on immediately, which 83daf88096SMichel Dänzer * will trigger link training 84d38ceaf9SAlex Deucher */ 85daf88096SMichel Dänzer drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 86d38ceaf9SAlex Deucher drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 87d38ceaf9SAlex Deucher } 88d38ceaf9SAlex Deucher } 89d38ceaf9SAlex Deucher } 90d38ceaf9SAlex Deucher 91d38ceaf9SAlex Deucher static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder) 92d38ceaf9SAlex Deucher { 93d38ceaf9SAlex Deucher struct drm_crtc *crtc = encoder->crtc; 94d38ceaf9SAlex Deucher 95d38ceaf9SAlex Deucher if (crtc && crtc->enabled) { 96d38ceaf9SAlex Deucher drm_crtc_helper_set_mode(crtc, &crtc->mode, 97d38ceaf9SAlex Deucher crtc->x, crtc->y, crtc->primary->fb); 98d38ceaf9SAlex Deucher } 99d38ceaf9SAlex Deucher } 100d38ceaf9SAlex Deucher 101d38ceaf9SAlex Deucher int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) 102d38ceaf9SAlex Deucher { 103d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 104d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *dig_connector; 105d38ceaf9SAlex Deucher int bpc = 8; 106*8a1de314SSrinivasan Shanmugam unsigned int mode_clock, max_tmds_clock; 107d38ceaf9SAlex Deucher 108d38ceaf9SAlex Deucher switch (connector->connector_type) { 109d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVII: 110d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIB: 111d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital) { 1123c021931SClaudio Suarez if (connector->display_info.is_hdmi) { 113d38ceaf9SAlex Deucher if (connector->display_info.bpc) 114d38ceaf9SAlex Deucher bpc = connector->display_info.bpc; 115d38ceaf9SAlex Deucher } 116d38ceaf9SAlex Deucher } 117d38ceaf9SAlex Deucher break; 118d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVID: 119d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIA: 1203c021931SClaudio Suarez if (connector->display_info.is_hdmi) { 121d38ceaf9SAlex Deucher if (connector->display_info.bpc) 122d38ceaf9SAlex Deucher bpc = connector->display_info.bpc; 123d38ceaf9SAlex Deucher } 124d38ceaf9SAlex Deucher break; 125d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DisplayPort: 126d38ceaf9SAlex Deucher dig_connector = amdgpu_connector->con_priv; 127d38ceaf9SAlex Deucher if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 128d38ceaf9SAlex Deucher (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || 1293c021931SClaudio Suarez connector->display_info.is_hdmi) { 130d38ceaf9SAlex Deucher if (connector->display_info.bpc) 131d38ceaf9SAlex Deucher bpc = connector->display_info.bpc; 132d38ceaf9SAlex Deucher } 133d38ceaf9SAlex Deucher break; 134d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_eDP: 135d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_LVDS: 136d38ceaf9SAlex Deucher if (connector->display_info.bpc) 137d38ceaf9SAlex Deucher bpc = connector->display_info.bpc; 138d38ceaf9SAlex Deucher else { 13917b10f94SAlex Deucher const struct drm_connector_helper_funcs *connector_funcs = 140d38ceaf9SAlex Deucher connector->helper_private; 141d38ceaf9SAlex Deucher struct drm_encoder *encoder = connector_funcs->best_encoder(connector); 142d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 143d38ceaf9SAlex Deucher struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 144d38ceaf9SAlex Deucher 145d38ceaf9SAlex Deucher if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR) 146d38ceaf9SAlex Deucher bpc = 6; 147d38ceaf9SAlex Deucher else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR) 148d38ceaf9SAlex Deucher bpc = 8; 149d38ceaf9SAlex Deucher } 150d38ceaf9SAlex Deucher break; 151d38ceaf9SAlex Deucher } 152d38ceaf9SAlex Deucher 1533c021931SClaudio Suarez if (connector->display_info.is_hdmi) { 154d38ceaf9SAlex Deucher /* 155d38ceaf9SAlex Deucher * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make 156d38ceaf9SAlex Deucher * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at 157d38ceaf9SAlex Deucher * 12 bpc is always supported on hdmi deep color sinks, as this is 158d38ceaf9SAlex Deucher * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. 159d38ceaf9SAlex Deucher */ 160d38ceaf9SAlex Deucher if (bpc > 12) { 161d38ceaf9SAlex Deucher DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", 162d38ceaf9SAlex Deucher connector->name, bpc); 163d38ceaf9SAlex Deucher bpc = 12; 164d38ceaf9SAlex Deucher } 165d38ceaf9SAlex Deucher 166d38ceaf9SAlex Deucher /* Any defined maximum tmds clock limit we must not exceed? */ 1672a272ca9SVille Syrjälä if (connector->display_info.max_tmds_clock > 0) { 168d38ceaf9SAlex Deucher /* mode_clock is clock in kHz for mode to be modeset on this connector */ 169d38ceaf9SAlex Deucher mode_clock = amdgpu_connector->pixelclock_for_modeset; 170d38ceaf9SAlex Deucher 171d38ceaf9SAlex Deucher /* Maximum allowable input clock in kHz */ 1722a272ca9SVille Syrjälä max_tmds_clock = connector->display_info.max_tmds_clock; 173d38ceaf9SAlex Deucher 174d38ceaf9SAlex Deucher DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n", 175d38ceaf9SAlex Deucher connector->name, mode_clock, max_tmds_clock); 176d38ceaf9SAlex Deucher 177d38ceaf9SAlex Deucher /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ 178d38ceaf9SAlex Deucher if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { 1794adc33f3SMaxime Ripard if ((connector->display_info.edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) && 180d38ceaf9SAlex Deucher (mode_clock * 5/4 <= max_tmds_clock)) 181d38ceaf9SAlex Deucher bpc = 10; 182d38ceaf9SAlex Deucher else 183d38ceaf9SAlex Deucher bpc = 8; 184d38ceaf9SAlex Deucher 185d38ceaf9SAlex Deucher DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", 186d38ceaf9SAlex Deucher connector->name, bpc); 187d38ceaf9SAlex Deucher } 188d38ceaf9SAlex Deucher 189d38ceaf9SAlex Deucher if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { 190d38ceaf9SAlex Deucher bpc = 8; 191d38ceaf9SAlex Deucher DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", 192d38ceaf9SAlex Deucher connector->name, bpc); 1939d746ab6SMario Kleiner } 194d38ceaf9SAlex Deucher } else if (bpc > 8) { 195d38ceaf9SAlex Deucher /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ 196d38ceaf9SAlex Deucher DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", 197d38ceaf9SAlex Deucher connector->name); 198d38ceaf9SAlex Deucher bpc = 8; 199d38ceaf9SAlex Deucher } 200d38ceaf9SAlex Deucher } 201d38ceaf9SAlex Deucher 202d38ceaf9SAlex Deucher if ((amdgpu_deep_color == 0) && (bpc > 8)) { 203d38ceaf9SAlex Deucher DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n", 204d38ceaf9SAlex Deucher connector->name); 205d38ceaf9SAlex Deucher bpc = 8; 206d38ceaf9SAlex Deucher } 207d38ceaf9SAlex Deucher 208d38ceaf9SAlex Deucher DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", 209d38ceaf9SAlex Deucher connector->name, connector->display_info.bpc, bpc); 210d38ceaf9SAlex Deucher 211d38ceaf9SAlex Deucher return bpc; 212d38ceaf9SAlex Deucher } 213d38ceaf9SAlex Deucher 214d38ceaf9SAlex Deucher static void 215d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(struct drm_connector *connector, 216d38ceaf9SAlex Deucher enum drm_connector_status status) 217d38ceaf9SAlex Deucher { 21898c0e348SVille Syrjälä struct drm_encoder *best_encoder; 21998c0e348SVille Syrjälä struct drm_encoder *encoder; 22017b10f94SAlex Deucher const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 221d38ceaf9SAlex Deucher bool connected; 222d38ceaf9SAlex Deucher 223d38ceaf9SAlex Deucher best_encoder = connector_funcs->best_encoder(connector); 224d38ceaf9SAlex Deucher 22562afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder) { 226d38ceaf9SAlex Deucher if ((encoder == best_encoder) && (status == connector_status_connected)) 227d38ceaf9SAlex Deucher connected = true; 228d38ceaf9SAlex Deucher else 229d38ceaf9SAlex Deucher connected = false; 230d38ceaf9SAlex Deucher 231d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected); 232d38ceaf9SAlex Deucher } 233d38ceaf9SAlex Deucher } 234d38ceaf9SAlex Deucher 235d38ceaf9SAlex Deucher static struct drm_encoder * 236d38ceaf9SAlex Deucher amdgpu_connector_find_encoder(struct drm_connector *connector, 237d38ceaf9SAlex Deucher int encoder_type) 238d38ceaf9SAlex Deucher { 239d38ceaf9SAlex Deucher struct drm_encoder *encoder; 240d38ceaf9SAlex Deucher 24162afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder) { 242d38ceaf9SAlex Deucher if (encoder->encoder_type == encoder_type) 243d38ceaf9SAlex Deucher return encoder; 244d38ceaf9SAlex Deucher } 24598c0e348SVille Syrjälä 246d38ceaf9SAlex Deucher return NULL; 247d38ceaf9SAlex Deucher } 248d38ceaf9SAlex Deucher 249d38ceaf9SAlex Deucher static struct edid * 250d38ceaf9SAlex Deucher amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) 251d38ceaf9SAlex Deucher { 252d38ceaf9SAlex Deucher if (adev->mode_info.bios_hardcoded_edid) { 253d903af1aSChen Jiahao return kmemdup((unsigned char *)adev->mode_info.bios_hardcoded_edid, 254d903af1aSChen Jiahao adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); 255d38ceaf9SAlex Deucher } 256d38ceaf9SAlex Deucher return NULL; 257d38ceaf9SAlex Deucher } 258d38ceaf9SAlex Deucher 259d38ceaf9SAlex Deucher static void amdgpu_connector_get_edid(struct drm_connector *connector) 260d38ceaf9SAlex Deucher { 261d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 2621348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev); 263d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 264d38ceaf9SAlex Deucher 265d38ceaf9SAlex Deucher if (amdgpu_connector->edid) 266d38ceaf9SAlex Deucher return; 267d38ceaf9SAlex Deucher 268d38ceaf9SAlex Deucher /* on hw with routers, select right port */ 269d38ceaf9SAlex Deucher if (amdgpu_connector->router.ddc_valid) 270d38ceaf9SAlex Deucher amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 271d38ceaf9SAlex Deucher 272d38ceaf9SAlex Deucher if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 273d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) && 274d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus->has_aux) { 275d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector, 276d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->aux.ddc); 277d38ceaf9SAlex Deucher } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 278d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 279d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; 280d38ceaf9SAlex Deucher 281d38ceaf9SAlex Deucher if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 282d38ceaf9SAlex Deucher dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && 283d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus->has_aux) 284d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector, 285d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->aux.ddc); 286d38ceaf9SAlex Deucher else if (amdgpu_connector->ddc_bus) 287d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector, 288d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->adapter); 289d38ceaf9SAlex Deucher } else if (amdgpu_connector->ddc_bus) { 290d38ceaf9SAlex Deucher amdgpu_connector->edid = drm_get_edid(connector, 291d38ceaf9SAlex Deucher &amdgpu_connector->ddc_bus->adapter); 292d38ceaf9SAlex Deucher } 293d38ceaf9SAlex Deucher 294d38ceaf9SAlex Deucher if (!amdgpu_connector->edid) { 295d38ceaf9SAlex Deucher /* some laptops provide a hardcoded edid in rom for LCDs */ 296d38ceaf9SAlex Deucher if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || 29720543be9SClaudio Suarez (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) { 298d38ceaf9SAlex Deucher amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev); 29920543be9SClaudio Suarez drm_connector_update_edid_property(connector, amdgpu_connector->edid); 30020543be9SClaudio Suarez } 301d38ceaf9SAlex Deucher } 302d38ceaf9SAlex Deucher } 303d38ceaf9SAlex Deucher 304d38ceaf9SAlex Deucher static void amdgpu_connector_free_edid(struct drm_connector *connector) 305d38ceaf9SAlex Deucher { 306d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 307d38ceaf9SAlex Deucher 308d38ceaf9SAlex Deucher kfree(amdgpu_connector->edid); 309d38ceaf9SAlex Deucher amdgpu_connector->edid = NULL; 310d38ceaf9SAlex Deucher } 311d38ceaf9SAlex Deucher 312d38ceaf9SAlex Deucher static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) 313d38ceaf9SAlex Deucher { 314d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 315d38ceaf9SAlex Deucher int ret; 316d38ceaf9SAlex Deucher 317d38ceaf9SAlex Deucher if (amdgpu_connector->edid) { 318c555f023SDaniel Vetter drm_connector_update_edid_property(connector, amdgpu_connector->edid); 319d38ceaf9SAlex Deucher ret = drm_add_edid_modes(connector, amdgpu_connector->edid); 320d38ceaf9SAlex Deucher return ret; 321d38ceaf9SAlex Deucher } 322c555f023SDaniel Vetter drm_connector_update_edid_property(connector, NULL); 323d38ceaf9SAlex Deucher return 0; 324d38ceaf9SAlex Deucher } 325d38ceaf9SAlex Deucher 326d38ceaf9SAlex Deucher static struct drm_encoder * 327d38ceaf9SAlex Deucher amdgpu_connector_best_single_encoder(struct drm_connector *connector) 328d38ceaf9SAlex Deucher { 32998c0e348SVille Syrjälä struct drm_encoder *encoder; 330d38ceaf9SAlex Deucher 33198c0e348SVille Syrjälä /* pick the first one */ 33262afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder) 33398c0e348SVille Syrjälä return encoder; 33498c0e348SVille Syrjälä 335d38ceaf9SAlex Deucher return NULL; 336d38ceaf9SAlex Deucher } 337d38ceaf9SAlex Deucher 338d38ceaf9SAlex Deucher static void amdgpu_get_native_mode(struct drm_connector *connector) 339d38ceaf9SAlex Deucher { 340d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 341d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 342d38ceaf9SAlex Deucher 343d38ceaf9SAlex Deucher if (encoder == NULL) 344d38ceaf9SAlex Deucher return; 345d38ceaf9SAlex Deucher 346d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 347d38ceaf9SAlex Deucher 348d38ceaf9SAlex Deucher if (!list_empty(&connector->probed_modes)) { 349d38ceaf9SAlex Deucher struct drm_display_mode *preferred_mode = 350d38ceaf9SAlex Deucher list_first_entry(&connector->probed_modes, 351d38ceaf9SAlex Deucher struct drm_display_mode, head); 352d38ceaf9SAlex Deucher 353d38ceaf9SAlex Deucher amdgpu_encoder->native_mode = *preferred_mode; 354d38ceaf9SAlex Deucher } else { 355d38ceaf9SAlex Deucher amdgpu_encoder->native_mode.clock = 0; 356d38ceaf9SAlex Deucher } 357d38ceaf9SAlex Deucher } 358d38ceaf9SAlex Deucher 359d38ceaf9SAlex Deucher static struct drm_display_mode * 360d38ceaf9SAlex Deucher amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder) 361d38ceaf9SAlex Deucher { 362d38ceaf9SAlex Deucher struct drm_device *dev = encoder->dev; 363d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 364d38ceaf9SAlex Deucher struct drm_display_mode *mode = NULL; 365d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 366d38ceaf9SAlex Deucher 367d38ceaf9SAlex Deucher if (native_mode->hdisplay != 0 && 368d38ceaf9SAlex Deucher native_mode->vdisplay != 0 && 369d38ceaf9SAlex Deucher native_mode->clock != 0) { 370d38ceaf9SAlex Deucher mode = drm_mode_duplicate(dev, native_mode); 371b220110eSZhou Qingyang if (!mode) 372b220110eSZhou Qingyang return NULL; 373b220110eSZhou Qingyang 374d38ceaf9SAlex Deucher mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 375d38ceaf9SAlex Deucher drm_mode_set_name(mode); 376d38ceaf9SAlex Deucher 377d38ceaf9SAlex Deucher DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); 378d38ceaf9SAlex Deucher } else if (native_mode->hdisplay != 0 && 379d38ceaf9SAlex Deucher native_mode->vdisplay != 0) { 380d38ceaf9SAlex Deucher /* mac laptops without an edid */ 381d38ceaf9SAlex Deucher /* Note that this is not necessarily the exact panel mode, 382d38ceaf9SAlex Deucher * but an approximation based on the cvt formula. For these 383d38ceaf9SAlex Deucher * systems we should ideally read the mode info out of the 384d38ceaf9SAlex Deucher * registers or add a mode table, but this works and is much 385d38ceaf9SAlex Deucher * simpler. 386d38ceaf9SAlex Deucher */ 387d38ceaf9SAlex Deucher mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); 388b220110eSZhou Qingyang if (!mode) 389b220110eSZhou Qingyang return NULL; 390b220110eSZhou Qingyang 391d38ceaf9SAlex Deucher mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 392d38ceaf9SAlex Deucher DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); 393d38ceaf9SAlex Deucher } 394d38ceaf9SAlex Deucher return mode; 395d38ceaf9SAlex Deucher } 396d38ceaf9SAlex Deucher 397d38ceaf9SAlex Deucher static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, 398d38ceaf9SAlex Deucher struct drm_connector *connector) 399d38ceaf9SAlex Deucher { 400d38ceaf9SAlex Deucher struct drm_device *dev = encoder->dev; 401d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 402d38ceaf9SAlex Deucher struct drm_display_mode *mode = NULL; 403d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 404d38ceaf9SAlex Deucher int i; 405aeba709aSNils Wallménius static const struct mode_size { 406d38ceaf9SAlex Deucher int w; 407d38ceaf9SAlex Deucher int h; 408d38ceaf9SAlex Deucher } common_modes[17] = { 409d38ceaf9SAlex Deucher { 640, 480}, 410d38ceaf9SAlex Deucher { 720, 480}, 411d38ceaf9SAlex Deucher { 800, 600}, 412d38ceaf9SAlex Deucher { 848, 480}, 413d38ceaf9SAlex Deucher {1024, 768}, 414d38ceaf9SAlex Deucher {1152, 768}, 415d38ceaf9SAlex Deucher {1280, 720}, 416d38ceaf9SAlex Deucher {1280, 800}, 417d38ceaf9SAlex Deucher {1280, 854}, 418d38ceaf9SAlex Deucher {1280, 960}, 419d38ceaf9SAlex Deucher {1280, 1024}, 420d38ceaf9SAlex Deucher {1440, 900}, 421d38ceaf9SAlex Deucher {1400, 1050}, 422d38ceaf9SAlex Deucher {1680, 1050}, 423d38ceaf9SAlex Deucher {1600, 1200}, 424d38ceaf9SAlex Deucher {1920, 1080}, 425d38ceaf9SAlex Deucher {1920, 1200} 426d38ceaf9SAlex Deucher }; 427d38ceaf9SAlex Deucher 428d38ceaf9SAlex Deucher for (i = 0; i < 17; i++) { 429d38ceaf9SAlex Deucher if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 430d38ceaf9SAlex Deucher if (common_modes[i].w > 1024 || 431d38ceaf9SAlex Deucher common_modes[i].h > 768) 432d38ceaf9SAlex Deucher continue; 433d38ceaf9SAlex Deucher } 434d38ceaf9SAlex Deucher if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 435d38ceaf9SAlex Deucher if (common_modes[i].w > native_mode->hdisplay || 436d38ceaf9SAlex Deucher common_modes[i].h > native_mode->vdisplay || 437d38ceaf9SAlex Deucher (common_modes[i].w == native_mode->hdisplay && 438d38ceaf9SAlex Deucher common_modes[i].h == native_mode->vdisplay)) 439d38ceaf9SAlex Deucher continue; 440d38ceaf9SAlex Deucher } 441d38ceaf9SAlex Deucher if (common_modes[i].w < 320 || common_modes[i].h < 200) 442d38ceaf9SAlex Deucher continue; 443d38ceaf9SAlex Deucher 444d38ceaf9SAlex Deucher mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); 445d38ceaf9SAlex Deucher drm_mode_probed_add(connector, mode); 446d38ceaf9SAlex Deucher } 447d38ceaf9SAlex Deucher } 448d38ceaf9SAlex Deucher 449d38ceaf9SAlex Deucher static int amdgpu_connector_set_property(struct drm_connector *connector, 450d38ceaf9SAlex Deucher struct drm_property *property, 451d38ceaf9SAlex Deucher uint64_t val) 452d38ceaf9SAlex Deucher { 453d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 4541348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev); 455d38ceaf9SAlex Deucher struct drm_encoder *encoder; 456d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 457d38ceaf9SAlex Deucher 458d38ceaf9SAlex Deucher if (property == adev->mode_info.coherent_mode_property) { 459d38ceaf9SAlex Deucher struct amdgpu_encoder_atom_dig *dig; 460d38ceaf9SAlex Deucher bool new_coherent_mode; 461d38ceaf9SAlex Deucher 462d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 463d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 464d38ceaf9SAlex Deucher if (!encoder) 465d38ceaf9SAlex Deucher return 0; 466d38ceaf9SAlex Deucher 467d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 468d38ceaf9SAlex Deucher 469d38ceaf9SAlex Deucher if (!amdgpu_encoder->enc_priv) 470d38ceaf9SAlex Deucher return 0; 471d38ceaf9SAlex Deucher 472d38ceaf9SAlex Deucher dig = amdgpu_encoder->enc_priv; 473d38ceaf9SAlex Deucher new_coherent_mode = val ? true : false; 474d38ceaf9SAlex Deucher if (dig->coherent_mode != new_coherent_mode) { 475d38ceaf9SAlex Deucher dig->coherent_mode = new_coherent_mode; 476d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 477d38ceaf9SAlex Deucher } 478d38ceaf9SAlex Deucher } 479d38ceaf9SAlex Deucher 480d38ceaf9SAlex Deucher if (property == adev->mode_info.audio_property) { 481d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 482d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 483d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 484d38ceaf9SAlex Deucher if (!encoder) 485d38ceaf9SAlex Deucher return 0; 486d38ceaf9SAlex Deucher 487d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 488d38ceaf9SAlex Deucher 489d38ceaf9SAlex Deucher if (amdgpu_connector->audio != val) { 490d38ceaf9SAlex Deucher amdgpu_connector->audio = val; 491d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 492d38ceaf9SAlex Deucher } 493d38ceaf9SAlex Deucher } 494d38ceaf9SAlex Deucher 495d38ceaf9SAlex Deucher if (property == adev->mode_info.dither_property) { 496d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 497d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 498d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 499d38ceaf9SAlex Deucher if (!encoder) 500d38ceaf9SAlex Deucher return 0; 501d38ceaf9SAlex Deucher 502d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 503d38ceaf9SAlex Deucher 504d38ceaf9SAlex Deucher if (amdgpu_connector->dither != val) { 505d38ceaf9SAlex Deucher amdgpu_connector->dither = val; 506d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 507d38ceaf9SAlex Deucher } 508d38ceaf9SAlex Deucher } 509d38ceaf9SAlex Deucher 510d38ceaf9SAlex Deucher if (property == adev->mode_info.underscan_property) { 511d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 512d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 513d38ceaf9SAlex Deucher if (!encoder) 514d38ceaf9SAlex Deucher return 0; 515d38ceaf9SAlex Deucher 516d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 517d38ceaf9SAlex Deucher 518d38ceaf9SAlex Deucher if (amdgpu_encoder->underscan_type != val) { 519d38ceaf9SAlex Deucher amdgpu_encoder->underscan_type = val; 520d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 521d38ceaf9SAlex Deucher } 522d38ceaf9SAlex Deucher } 523d38ceaf9SAlex Deucher 524d38ceaf9SAlex Deucher if (property == adev->mode_info.underscan_hborder_property) { 525d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 526d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 527d38ceaf9SAlex Deucher if (!encoder) 528d38ceaf9SAlex Deucher return 0; 529d38ceaf9SAlex Deucher 530d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 531d38ceaf9SAlex Deucher 532d38ceaf9SAlex Deucher if (amdgpu_encoder->underscan_hborder != val) { 533d38ceaf9SAlex Deucher amdgpu_encoder->underscan_hborder = val; 534d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 535d38ceaf9SAlex Deucher } 536d38ceaf9SAlex Deucher } 537d38ceaf9SAlex Deucher 538d38ceaf9SAlex Deucher if (property == adev->mode_info.underscan_vborder_property) { 539d38ceaf9SAlex Deucher /* need to find digital encoder on connector */ 540d38ceaf9SAlex Deucher encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 541d38ceaf9SAlex Deucher if (!encoder) 542d38ceaf9SAlex Deucher return 0; 543d38ceaf9SAlex Deucher 544d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 545d38ceaf9SAlex Deucher 546d38ceaf9SAlex Deucher if (amdgpu_encoder->underscan_vborder != val) { 547d38ceaf9SAlex Deucher amdgpu_encoder->underscan_vborder = val; 548d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 549d38ceaf9SAlex Deucher } 550d38ceaf9SAlex Deucher } 551d38ceaf9SAlex Deucher 552d38ceaf9SAlex Deucher if (property == adev->mode_info.load_detect_property) { 553d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = 554d38ceaf9SAlex Deucher to_amdgpu_connector(connector); 555d38ceaf9SAlex Deucher 556d38ceaf9SAlex Deucher if (val == 0) 557d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = false; 558d38ceaf9SAlex Deucher else 559d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 560d38ceaf9SAlex Deucher } 561d38ceaf9SAlex Deucher 562d38ceaf9SAlex Deucher if (property == dev->mode_config.scaling_mode_property) { 563d38ceaf9SAlex Deucher enum amdgpu_rmx_type rmx_type; 564d38ceaf9SAlex Deucher 565d38ceaf9SAlex Deucher if (connector->encoder) { 566d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 567d38ceaf9SAlex Deucher } else { 56817b10f94SAlex Deucher const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 569*8a1de314SSrinivasan Shanmugam 570d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 571d38ceaf9SAlex Deucher } 572d38ceaf9SAlex Deucher 573d38ceaf9SAlex Deucher switch (val) { 574d38ceaf9SAlex Deucher default: 575a6f7baa3SSrinivasan Shanmugam case DRM_MODE_SCALE_NONE: 576a6f7baa3SSrinivasan Shanmugam rmx_type = RMX_OFF; 577a6f7baa3SSrinivasan Shanmugam break; 578a6f7baa3SSrinivasan Shanmugam case DRM_MODE_SCALE_CENTER: 579a6f7baa3SSrinivasan Shanmugam rmx_type = RMX_CENTER; 580a6f7baa3SSrinivasan Shanmugam break; 581a6f7baa3SSrinivasan Shanmugam case DRM_MODE_SCALE_ASPECT: 582a6f7baa3SSrinivasan Shanmugam rmx_type = RMX_ASPECT; 583a6f7baa3SSrinivasan Shanmugam break; 584a6f7baa3SSrinivasan Shanmugam case DRM_MODE_SCALE_FULLSCREEN: 585a6f7baa3SSrinivasan Shanmugam rmx_type = RMX_FULL; 586a6f7baa3SSrinivasan Shanmugam break; 587d38ceaf9SAlex Deucher } 588a6f7baa3SSrinivasan Shanmugam 589d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == rmx_type) 590d38ceaf9SAlex Deucher return 0; 591d38ceaf9SAlex Deucher 592d38ceaf9SAlex Deucher if ((rmx_type != DRM_MODE_SCALE_NONE) && 593d38ceaf9SAlex Deucher (amdgpu_encoder->native_mode.clock == 0)) 594d38ceaf9SAlex Deucher return 0; 595d38ceaf9SAlex Deucher 596d38ceaf9SAlex Deucher amdgpu_encoder->rmx_type = rmx_type; 597d38ceaf9SAlex Deucher 598d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 599d38ceaf9SAlex Deucher } 600d38ceaf9SAlex Deucher 601d38ceaf9SAlex Deucher return 0; 602d38ceaf9SAlex Deucher } 603d38ceaf9SAlex Deucher 604d38ceaf9SAlex Deucher static void 605d38ceaf9SAlex Deucher amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder, 606d38ceaf9SAlex Deucher struct drm_connector *connector) 607d38ceaf9SAlex Deucher { 608d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 609d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 610d38ceaf9SAlex Deucher struct drm_display_mode *t, *mode; 611d38ceaf9SAlex Deucher 612d38ceaf9SAlex Deucher /* If the EDID preferred mode doesn't match the native mode, use it */ 613d38ceaf9SAlex Deucher list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 614d38ceaf9SAlex Deucher if (mode->type & DRM_MODE_TYPE_PREFERRED) { 615d38ceaf9SAlex Deucher if (mode->hdisplay != native_mode->hdisplay || 616d38ceaf9SAlex Deucher mode->vdisplay != native_mode->vdisplay) 617426c89aaSVille Syrjälä drm_mode_copy(native_mode, mode); 618d38ceaf9SAlex Deucher } 619d38ceaf9SAlex Deucher } 620d38ceaf9SAlex Deucher 621d38ceaf9SAlex Deucher /* Try to get native mode details from EDID if necessary */ 622d38ceaf9SAlex Deucher if (!native_mode->clock) { 623d38ceaf9SAlex Deucher list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 624d38ceaf9SAlex Deucher if (mode->hdisplay == native_mode->hdisplay && 625d38ceaf9SAlex Deucher mode->vdisplay == native_mode->vdisplay) { 626426c89aaSVille Syrjälä drm_mode_copy(native_mode, mode); 627d38ceaf9SAlex Deucher drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); 628d38ceaf9SAlex Deucher DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); 629d38ceaf9SAlex Deucher break; 630d38ceaf9SAlex Deucher } 631d38ceaf9SAlex Deucher } 632d38ceaf9SAlex Deucher } 633d38ceaf9SAlex Deucher 634d38ceaf9SAlex Deucher if (!native_mode->clock) { 635d38ceaf9SAlex Deucher DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n"); 636d38ceaf9SAlex Deucher amdgpu_encoder->rmx_type = RMX_OFF; 637d38ceaf9SAlex Deucher } 638d38ceaf9SAlex Deucher } 639d38ceaf9SAlex Deucher 640d38ceaf9SAlex Deucher static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) 641d38ceaf9SAlex Deucher { 642d38ceaf9SAlex Deucher struct drm_encoder *encoder; 643d38ceaf9SAlex Deucher int ret = 0; 644d38ceaf9SAlex Deucher struct drm_display_mode *mode; 645d38ceaf9SAlex Deucher 646d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 647d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 648d38ceaf9SAlex Deucher if (ret > 0) { 649d38ceaf9SAlex Deucher encoder = amdgpu_connector_best_single_encoder(connector); 650d38ceaf9SAlex Deucher if (encoder) { 651d38ceaf9SAlex Deucher amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 652d38ceaf9SAlex Deucher /* add scaled modes */ 653d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector); 654d38ceaf9SAlex Deucher } 655d38ceaf9SAlex Deucher return ret; 656d38ceaf9SAlex Deucher } 657d38ceaf9SAlex Deucher 658d38ceaf9SAlex Deucher encoder = amdgpu_connector_best_single_encoder(connector); 659d38ceaf9SAlex Deucher if (!encoder) 660d38ceaf9SAlex Deucher return 0; 661d38ceaf9SAlex Deucher 662d38ceaf9SAlex Deucher /* we have no EDID modes */ 663d38ceaf9SAlex Deucher mode = amdgpu_connector_lcd_native_mode(encoder); 664d38ceaf9SAlex Deucher if (mode) { 665d38ceaf9SAlex Deucher ret = 1; 666d38ceaf9SAlex Deucher drm_mode_probed_add(connector, mode); 667d38ceaf9SAlex Deucher /* add the width/height from vbios tables if available */ 668d38ceaf9SAlex Deucher connector->display_info.width_mm = mode->width_mm; 669d38ceaf9SAlex Deucher connector->display_info.height_mm = mode->height_mm; 670d38ceaf9SAlex Deucher /* add scaled modes */ 671d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector); 672d38ceaf9SAlex Deucher } 673d38ceaf9SAlex Deucher 674d38ceaf9SAlex Deucher return ret; 675d38ceaf9SAlex Deucher } 676d38ceaf9SAlex Deucher 677ba9ca088SLuc Van Oostenryck static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, 678d38ceaf9SAlex Deucher struct drm_display_mode *mode) 679d38ceaf9SAlex Deucher { 680d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 681d38ceaf9SAlex Deucher 682d38ceaf9SAlex Deucher if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 683d38ceaf9SAlex Deucher return MODE_PANEL; 684d38ceaf9SAlex Deucher 685d38ceaf9SAlex Deucher if (encoder) { 686d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 687d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 688d38ceaf9SAlex Deucher 689d38ceaf9SAlex Deucher /* AVIVO hardware supports downscaling modes larger than the panel 690d38ceaf9SAlex Deucher * to the panel size, but I'm not sure this is desirable. 691d38ceaf9SAlex Deucher */ 692d38ceaf9SAlex Deucher if ((mode->hdisplay > native_mode->hdisplay) || 693d38ceaf9SAlex Deucher (mode->vdisplay > native_mode->vdisplay)) 694d38ceaf9SAlex Deucher return MODE_PANEL; 695d38ceaf9SAlex Deucher 696d38ceaf9SAlex Deucher /* if scaling is disabled, block non-native modes */ 697d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == RMX_OFF) { 698d38ceaf9SAlex Deucher if ((mode->hdisplay != native_mode->hdisplay) || 699d38ceaf9SAlex Deucher (mode->vdisplay != native_mode->vdisplay)) 700d38ceaf9SAlex Deucher return MODE_PANEL; 701d38ceaf9SAlex Deucher } 702d38ceaf9SAlex Deucher } 703d38ceaf9SAlex Deucher 704d38ceaf9SAlex Deucher return MODE_OK; 705d38ceaf9SAlex Deucher } 706d38ceaf9SAlex Deucher 707d38ceaf9SAlex Deucher static enum drm_connector_status 708d38ceaf9SAlex Deucher amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force) 709d38ceaf9SAlex Deucher { 710d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 711d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 712d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected; 713d38ceaf9SAlex Deucher int r; 714d38ceaf9SAlex Deucher 715aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 716d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev); 717f79f9476SNavid Emamdoost if (r < 0) { 718f79f9476SNavid Emamdoost pm_runtime_put_autosuspend(connector->dev->dev); 719d38ceaf9SAlex Deucher return connector_status_disconnected; 720aa0aad57SLukas Wunner } 721f79f9476SNavid Emamdoost } 722d38ceaf9SAlex Deucher 723d38ceaf9SAlex Deucher if (encoder) { 724d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 725d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 726d38ceaf9SAlex Deucher 727d38ceaf9SAlex Deucher /* check if panel is valid */ 728d38ceaf9SAlex Deucher if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 729d38ceaf9SAlex Deucher ret = connector_status_connected; 730d38ceaf9SAlex Deucher 731d38ceaf9SAlex Deucher } 732d38ceaf9SAlex Deucher 733d38ceaf9SAlex Deucher /* check for edid as well */ 734d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 735d38ceaf9SAlex Deucher if (amdgpu_connector->edid) 736d38ceaf9SAlex Deucher ret = connector_status_connected; 737d38ceaf9SAlex Deucher /* check acpi lid status ??? */ 738d38ceaf9SAlex Deucher 739d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret); 740aa0aad57SLukas Wunner 741aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 742d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev); 743d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev); 744aa0aad57SLukas Wunner } 745aa0aad57SLukas Wunner 746d38ceaf9SAlex Deucher return ret; 747d38ceaf9SAlex Deucher } 748d38ceaf9SAlex Deucher 74940492f60SGrazvydas Ignotas static void amdgpu_connector_unregister(struct drm_connector *connector) 750d38ceaf9SAlex Deucher { 751d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 752d38ceaf9SAlex Deucher 753eef2b411SAlex Deucher if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) { 754d38ceaf9SAlex Deucher drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); 7552f9ba199SGrazvydas Ignotas amdgpu_connector->ddc_bus->has_aux = false; 7562f9ba199SGrazvydas Ignotas } 75740492f60SGrazvydas Ignotas } 75840492f60SGrazvydas Ignotas 75940492f60SGrazvydas Ignotas static void amdgpu_connector_destroy(struct drm_connector *connector) 76040492f60SGrazvydas Ignotas { 76140492f60SGrazvydas Ignotas struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 76240492f60SGrazvydas Ignotas 763d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 764d38ceaf9SAlex Deucher kfree(amdgpu_connector->con_priv); 765d38ceaf9SAlex Deucher drm_connector_unregister(connector); 766d38ceaf9SAlex Deucher drm_connector_cleanup(connector); 767d38ceaf9SAlex Deucher kfree(connector); 768d38ceaf9SAlex Deucher } 769d38ceaf9SAlex Deucher 770d38ceaf9SAlex Deucher static int amdgpu_connector_set_lcd_property(struct drm_connector *connector, 771d38ceaf9SAlex Deucher struct drm_property *property, 772d38ceaf9SAlex Deucher uint64_t value) 773d38ceaf9SAlex Deucher { 774d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 775d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 776d38ceaf9SAlex Deucher enum amdgpu_rmx_type rmx_type; 777d38ceaf9SAlex Deucher 778d38ceaf9SAlex Deucher DRM_DEBUG_KMS("\n"); 779d38ceaf9SAlex Deucher if (property != dev->mode_config.scaling_mode_property) 780d38ceaf9SAlex Deucher return 0; 781d38ceaf9SAlex Deucher 782d38ceaf9SAlex Deucher if (connector->encoder) 783d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 784d38ceaf9SAlex Deucher else { 78517b10f94SAlex Deucher const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 786*8a1de314SSrinivasan Shanmugam 787d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 788d38ceaf9SAlex Deucher } 789d38ceaf9SAlex Deucher 790d38ceaf9SAlex Deucher switch (value) { 791a6f7baa3SSrinivasan Shanmugam case DRM_MODE_SCALE_NONE: 792a6f7baa3SSrinivasan Shanmugam rmx_type = RMX_OFF; 793a6f7baa3SSrinivasan Shanmugam break; 794a6f7baa3SSrinivasan Shanmugam case DRM_MODE_SCALE_CENTER: 795a6f7baa3SSrinivasan Shanmugam rmx_type = RMX_CENTER; 796a6f7baa3SSrinivasan Shanmugam break; 797a6f7baa3SSrinivasan Shanmugam case DRM_MODE_SCALE_ASPECT: 798a6f7baa3SSrinivasan Shanmugam rmx_type = RMX_ASPECT; 799a6f7baa3SSrinivasan Shanmugam break; 800d38ceaf9SAlex Deucher default: 801a6f7baa3SSrinivasan Shanmugam case DRM_MODE_SCALE_FULLSCREEN: 802a6f7baa3SSrinivasan Shanmugam rmx_type = RMX_FULL; 803a6f7baa3SSrinivasan Shanmugam break; 804d38ceaf9SAlex Deucher } 805a6f7baa3SSrinivasan Shanmugam 806d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == rmx_type) 807d38ceaf9SAlex Deucher return 0; 808d38ceaf9SAlex Deucher 809d38ceaf9SAlex Deucher amdgpu_encoder->rmx_type = rmx_type; 810d38ceaf9SAlex Deucher 811d38ceaf9SAlex Deucher amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 812d38ceaf9SAlex Deucher return 0; 813d38ceaf9SAlex Deucher } 814d38ceaf9SAlex Deucher 815d38ceaf9SAlex Deucher 816d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = { 817d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_lvds_get_modes, 818d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_lvds_mode_valid, 819d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_best_single_encoder, 820d38ceaf9SAlex Deucher }; 821d38ceaf9SAlex Deucher 822d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = { 823d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 824d38ceaf9SAlex Deucher .detect = amdgpu_connector_lvds_detect, 825d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 82640492f60SGrazvydas Ignotas .early_unregister = amdgpu_connector_unregister, 827d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 828d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_lcd_property, 829d38ceaf9SAlex Deucher }; 830d38ceaf9SAlex Deucher 831d38ceaf9SAlex Deucher static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) 832d38ceaf9SAlex Deucher { 833d38ceaf9SAlex Deucher int ret; 834d38ceaf9SAlex Deucher 835d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 836d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 8376c5af7d2Shongao amdgpu_get_native_mode(connector); 838d38ceaf9SAlex Deucher 839d38ceaf9SAlex Deucher return ret; 840d38ceaf9SAlex Deucher } 841d38ceaf9SAlex Deucher 842ba9ca088SLuc Van Oostenryck static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector, 843d38ceaf9SAlex Deucher struct drm_display_mode *mode) 844d38ceaf9SAlex Deucher { 845d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 8461348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev); 847d38ceaf9SAlex Deucher 848d38ceaf9SAlex Deucher /* XXX check mode bandwidth */ 849d38ceaf9SAlex Deucher 850d38ceaf9SAlex Deucher if ((mode->clock / 10) > adev->clock.max_pixel_clock) 851d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 852d38ceaf9SAlex Deucher 853d38ceaf9SAlex Deucher return MODE_OK; 854d38ceaf9SAlex Deucher } 855d38ceaf9SAlex Deucher 856d38ceaf9SAlex Deucher static enum drm_connector_status 857d38ceaf9SAlex Deucher amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) 858d38ceaf9SAlex Deucher { 859d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 860d38ceaf9SAlex Deucher struct drm_encoder *encoder; 86117b10f94SAlex Deucher const struct drm_encoder_helper_funcs *encoder_funcs; 862d38ceaf9SAlex Deucher bool dret = false; 863d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected; 864d38ceaf9SAlex Deucher int r; 865d38ceaf9SAlex Deucher 866aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 867d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev); 868f79f9476SNavid Emamdoost if (r < 0) { 869f79f9476SNavid Emamdoost pm_runtime_put_autosuspend(connector->dev->dev); 870d38ceaf9SAlex Deucher return connector_status_disconnected; 871aa0aad57SLukas Wunner } 872f79f9476SNavid Emamdoost } 873d38ceaf9SAlex Deucher 874d38ceaf9SAlex Deucher encoder = amdgpu_connector_best_single_encoder(connector); 875d38ceaf9SAlex Deucher if (!encoder) 876d38ceaf9SAlex Deucher ret = connector_status_disconnected; 877d38ceaf9SAlex Deucher 878d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus) 879e0b5b5ecSSamuel Li dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 880d38ceaf9SAlex Deucher if (dret) { 881d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = false; 882d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 883d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 884d38ceaf9SAlex Deucher 885d38ceaf9SAlex Deucher if (!amdgpu_connector->edid) { 886d38ceaf9SAlex Deucher DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 887d38ceaf9SAlex Deucher connector->name); 888d38ceaf9SAlex Deucher ret = connector_status_connected; 889d38ceaf9SAlex Deucher } else { 890d38ceaf9SAlex Deucher amdgpu_connector->use_digital = 891d38ceaf9SAlex Deucher !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 892d38ceaf9SAlex Deucher 893d38ceaf9SAlex Deucher /* some oems have boards with separate digital and analog connectors 894d38ceaf9SAlex Deucher * with a shared ddc line (often vga + hdmi) 895d38ceaf9SAlex Deucher */ 896d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) { 897d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 898d38ceaf9SAlex Deucher ret = connector_status_disconnected; 899d38ceaf9SAlex Deucher } else { 900d38ceaf9SAlex Deucher ret = connector_status_connected; 901d38ceaf9SAlex Deucher } 902d38ceaf9SAlex Deucher } 903d38ceaf9SAlex Deucher } else { 904d38ceaf9SAlex Deucher 905d38ceaf9SAlex Deucher /* if we aren't forcing don't do destructive polling */ 906d38ceaf9SAlex Deucher if (!force) { 907d38ceaf9SAlex Deucher /* only return the previous status if we last 908d38ceaf9SAlex Deucher * detected a monitor via load. 909d38ceaf9SAlex Deucher */ 910d38ceaf9SAlex Deucher if (amdgpu_connector->detected_by_load) 911d38ceaf9SAlex Deucher ret = connector->status; 912d38ceaf9SAlex Deucher goto out; 913d38ceaf9SAlex Deucher } 914d38ceaf9SAlex Deucher 915d38ceaf9SAlex Deucher if (amdgpu_connector->dac_load_detect && encoder) { 916d38ceaf9SAlex Deucher encoder_funcs = encoder->helper_private; 917d38ceaf9SAlex Deucher ret = encoder_funcs->detect(encoder, connector); 918d38ceaf9SAlex Deucher if (ret != connector_status_disconnected) 919d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = true; 920d38ceaf9SAlex Deucher } 921d38ceaf9SAlex Deucher } 922d38ceaf9SAlex Deucher 923d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret); 924d38ceaf9SAlex Deucher 925d38ceaf9SAlex Deucher out: 926aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 927d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev); 928d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev); 929aa0aad57SLukas Wunner } 930d38ceaf9SAlex Deucher 931d38ceaf9SAlex Deucher return ret; 932d38ceaf9SAlex Deucher } 933d38ceaf9SAlex Deucher 934d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = { 935d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_vga_get_modes, 936d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_vga_mode_valid, 937d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_best_single_encoder, 938d38ceaf9SAlex Deucher }; 939d38ceaf9SAlex Deucher 940d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_vga_funcs = { 941d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 942d38ceaf9SAlex Deucher .detect = amdgpu_connector_vga_detect, 943d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 94440492f60SGrazvydas Ignotas .early_unregister = amdgpu_connector_unregister, 945d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 946d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_property, 947d38ceaf9SAlex Deucher }; 948d38ceaf9SAlex Deucher 949d38ceaf9SAlex Deucher static bool 950d38ceaf9SAlex Deucher amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector) 951d38ceaf9SAlex Deucher { 952d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 9531348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev); 954d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 955d38ceaf9SAlex Deucher enum drm_connector_status status; 956d38ceaf9SAlex Deucher 957d38ceaf9SAlex Deucher if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) { 958d38ceaf9SAlex Deucher if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) 959d38ceaf9SAlex Deucher status = connector_status_connected; 960d38ceaf9SAlex Deucher else 961d38ceaf9SAlex Deucher status = connector_status_disconnected; 962d38ceaf9SAlex Deucher if (connector->status == status) 963d38ceaf9SAlex Deucher return true; 964d38ceaf9SAlex Deucher } 965d38ceaf9SAlex Deucher 966d38ceaf9SAlex Deucher return false; 967d38ceaf9SAlex Deucher } 968d38ceaf9SAlex Deucher 969*8a1de314SSrinivasan Shanmugam static void amdgpu_connector_shared_ddc(enum drm_connector_status *status, 970*8a1de314SSrinivasan Shanmugam struct drm_connector *connector, 971*8a1de314SSrinivasan Shanmugam struct amdgpu_connector *amdgpu_connector) 972*8a1de314SSrinivasan Shanmugam { 973*8a1de314SSrinivasan Shanmugam struct drm_connector *list_connector; 974*8a1de314SSrinivasan Shanmugam struct drm_connector_list_iter iter; 975*8a1de314SSrinivasan Shanmugam struct amdgpu_connector *list_amdgpu_connector; 976*8a1de314SSrinivasan Shanmugam struct drm_device *dev = connector->dev; 977*8a1de314SSrinivasan Shanmugam struct amdgpu_device *adev = drm_to_adev(dev); 978*8a1de314SSrinivasan Shanmugam 979*8a1de314SSrinivasan Shanmugam if (amdgpu_connector->shared_ddc && *status == connector_status_connected) { 980*8a1de314SSrinivasan Shanmugam drm_connector_list_iter_begin(dev, &iter); 981*8a1de314SSrinivasan Shanmugam drm_for_each_connector_iter(list_connector, 982*8a1de314SSrinivasan Shanmugam &iter) { 983*8a1de314SSrinivasan Shanmugam if (connector == list_connector) 984*8a1de314SSrinivasan Shanmugam continue; 985*8a1de314SSrinivasan Shanmugam list_amdgpu_connector = to_amdgpu_connector(list_connector); 986*8a1de314SSrinivasan Shanmugam if (list_amdgpu_connector->shared_ddc && 987*8a1de314SSrinivasan Shanmugam list_amdgpu_connector->ddc_bus->rec.i2c_id == 988*8a1de314SSrinivasan Shanmugam amdgpu_connector->ddc_bus->rec.i2c_id) { 989*8a1de314SSrinivasan Shanmugam /* cases where both connectors are digital */ 990*8a1de314SSrinivasan Shanmugam if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { 991*8a1de314SSrinivasan Shanmugam /* hpd is our only option in this case */ 992*8a1de314SSrinivasan Shanmugam if (!amdgpu_display_hpd_sense(adev, 993*8a1de314SSrinivasan Shanmugam amdgpu_connector->hpd.hpd)) { 994*8a1de314SSrinivasan Shanmugam amdgpu_connector_free_edid(connector); 995*8a1de314SSrinivasan Shanmugam *status = connector_status_disconnected; 996*8a1de314SSrinivasan Shanmugam } 997*8a1de314SSrinivasan Shanmugam } 998*8a1de314SSrinivasan Shanmugam } 999*8a1de314SSrinivasan Shanmugam } 1000*8a1de314SSrinivasan Shanmugam drm_connector_list_iter_end(&iter); 1001*8a1de314SSrinivasan Shanmugam } 1002*8a1de314SSrinivasan Shanmugam } 1003*8a1de314SSrinivasan Shanmugam 1004d38ceaf9SAlex Deucher /* 1005d38ceaf9SAlex Deucher * DVI is complicated 1006d38ceaf9SAlex Deucher * Do a DDC probe, if DDC probe passes, get the full EDID so 1007d38ceaf9SAlex Deucher * we can do analog/digital monitor detection at this point. 1008d38ceaf9SAlex Deucher * If the monitor is an analog monitor or we got no DDC, 1009d38ceaf9SAlex Deucher * we need to find the DAC encoder object for this connector. 1010d38ceaf9SAlex Deucher * If we got no DDC, we do load detection on the DAC encoder object. 1011d38ceaf9SAlex Deucher * If we got analog DDC or load detection passes on the DAC encoder 1012d38ceaf9SAlex Deucher * we have to check if this analog encoder is shared with anyone else (TV) 1013d38ceaf9SAlex Deucher * if its shared we have to set the other connector to disconnected. 1014d38ceaf9SAlex Deucher */ 1015d38ceaf9SAlex Deucher static enum drm_connector_status 1016d38ceaf9SAlex Deucher amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) 1017d38ceaf9SAlex Deucher { 1018d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 10191348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev); 1020d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 102117b10f94SAlex Deucher const struct drm_encoder_helper_funcs *encoder_funcs; 102298c0e348SVille Syrjälä int r; 1023d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected; 1024d38ceaf9SAlex Deucher bool dret = false, broken_edid = false; 1025d38ceaf9SAlex Deucher 1026aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 1027d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev); 1028f79f9476SNavid Emamdoost if (r < 0) { 1029f79f9476SNavid Emamdoost pm_runtime_put_autosuspend(connector->dev->dev); 1030d38ceaf9SAlex Deucher return connector_status_disconnected; 1031aa0aad57SLukas Wunner } 1032f79f9476SNavid Emamdoost } 1033d38ceaf9SAlex Deucher 103490f56611Sxurui if (amdgpu_connector->detected_hpd_without_ddc) { 103590f56611Sxurui force = true; 103690f56611Sxurui amdgpu_connector->detected_hpd_without_ddc = false; 103790f56611Sxurui } 103890f56611Sxurui 1039d38ceaf9SAlex Deucher if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1040d38ceaf9SAlex Deucher ret = connector->status; 1041d38ceaf9SAlex Deucher goto exit; 1042d38ceaf9SAlex Deucher } 1043d38ceaf9SAlex Deucher 104490f56611Sxurui if (amdgpu_connector->ddc_bus) { 1045e0b5b5ecSSamuel Li dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 104690f56611Sxurui 104790f56611Sxurui /* Sometimes the pins required for the DDC probe on DVI 104890f56611Sxurui * connectors don't make contact at the same time that the ones 104990f56611Sxurui * for HPD do. If the DDC probe fails even though we had an HPD 105090f56611Sxurui * signal, try again later 105190f56611Sxurui */ 105290f56611Sxurui if (!dret && !force && 105390f56611Sxurui amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 105490f56611Sxurui DRM_DEBUG_KMS("hpd detected without ddc, retrying in 1 second\n"); 105590f56611Sxurui amdgpu_connector->detected_hpd_without_ddc = true; 105690f56611Sxurui schedule_delayed_work(&adev->hotplug_work, 105790f56611Sxurui msecs_to_jiffies(1000)); 105890f56611Sxurui goto exit; 105990f56611Sxurui } 106090f56611Sxurui } 1061d38ceaf9SAlex Deucher if (dret) { 1062d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = false; 1063d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 1064d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 1065d38ceaf9SAlex Deucher 1066d38ceaf9SAlex Deucher if (!amdgpu_connector->edid) { 1067d38ceaf9SAlex Deucher DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 1068d38ceaf9SAlex Deucher connector->name); 1069d38ceaf9SAlex Deucher ret = connector_status_connected; 1070d38ceaf9SAlex Deucher broken_edid = true; /* defer use_digital to later */ 1071d38ceaf9SAlex Deucher } else { 1072d38ceaf9SAlex Deucher amdgpu_connector->use_digital = 1073d38ceaf9SAlex Deucher !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 1074d38ceaf9SAlex Deucher 1075d38ceaf9SAlex Deucher /* some oems have boards with separate digital and analog connectors 1076d38ceaf9SAlex Deucher * with a shared ddc line (often vga + hdmi) 1077d38ceaf9SAlex Deucher */ 1078d38ceaf9SAlex Deucher if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) { 1079d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 1080d38ceaf9SAlex Deucher ret = connector_status_disconnected; 1081d38ceaf9SAlex Deucher } else { 1082d38ceaf9SAlex Deucher ret = connector_status_connected; 1083d38ceaf9SAlex Deucher } 1084d38ceaf9SAlex Deucher 1085d38ceaf9SAlex Deucher /* This gets complicated. We have boards with VGA + HDMI with a 1086d38ceaf9SAlex Deucher * shared DDC line and we have boards with DVI-D + HDMI with a shared 1087d38ceaf9SAlex Deucher * DDC line. The latter is more complex because with DVI<->HDMI adapters 1088d38ceaf9SAlex Deucher * you don't really know what's connected to which port as both are digital. 1089d38ceaf9SAlex Deucher */ 1090*8a1de314SSrinivasan Shanmugam amdgpu_connector_shared_ddc(&ret, connector, amdgpu_connector); 1091d38ceaf9SAlex Deucher } 1092d38ceaf9SAlex Deucher } 1093d38ceaf9SAlex Deucher 1094d38ceaf9SAlex Deucher if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true)) 1095d38ceaf9SAlex Deucher goto out; 1096d38ceaf9SAlex Deucher 1097d38ceaf9SAlex Deucher /* DVI-D and HDMI-A are digital only */ 1098d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) || 1099d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)) 1100d38ceaf9SAlex Deucher goto out; 1101d38ceaf9SAlex Deucher 1102d38ceaf9SAlex Deucher /* if we aren't forcing don't do destructive polling */ 1103d38ceaf9SAlex Deucher if (!force) { 1104d38ceaf9SAlex Deucher /* only return the previous status if we last 1105d38ceaf9SAlex Deucher * detected a monitor via load. 1106d38ceaf9SAlex Deucher */ 1107d38ceaf9SAlex Deucher if (amdgpu_connector->detected_by_load) 1108d38ceaf9SAlex Deucher ret = connector->status; 1109d38ceaf9SAlex Deucher goto out; 1110d38ceaf9SAlex Deucher } 1111d38ceaf9SAlex Deucher 1112d38ceaf9SAlex Deucher /* find analog encoder */ 1113d38ceaf9SAlex Deucher if (amdgpu_connector->dac_load_detect) { 111498c0e348SVille Syrjälä struct drm_encoder *encoder; 1115d38ceaf9SAlex Deucher 111662afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder) { 1117d38ceaf9SAlex Deucher if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && 1118d38ceaf9SAlex Deucher encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) 1119d38ceaf9SAlex Deucher continue; 1120d38ceaf9SAlex Deucher 1121d38ceaf9SAlex Deucher encoder_funcs = encoder->helper_private; 1122d38ceaf9SAlex Deucher if (encoder_funcs->detect) { 1123d38ceaf9SAlex Deucher if (!broken_edid) { 1124d38ceaf9SAlex Deucher if (ret != connector_status_connected) { 1125d38ceaf9SAlex Deucher /* deal with analog monitors without DDC */ 1126d38ceaf9SAlex Deucher ret = encoder_funcs->detect(encoder, connector); 1127d38ceaf9SAlex Deucher if (ret == connector_status_connected) { 1128d38ceaf9SAlex Deucher amdgpu_connector->use_digital = false; 1129d38ceaf9SAlex Deucher } 1130d38ceaf9SAlex Deucher if (ret != connector_status_disconnected) 1131d38ceaf9SAlex Deucher amdgpu_connector->detected_by_load = true; 1132d38ceaf9SAlex Deucher } 1133d38ceaf9SAlex Deucher } else { 1134d38ceaf9SAlex Deucher enum drm_connector_status lret; 1135d38ceaf9SAlex Deucher /* assume digital unless load detected otherwise */ 1136d38ceaf9SAlex Deucher amdgpu_connector->use_digital = true; 1137d38ceaf9SAlex Deucher lret = encoder_funcs->detect(encoder, connector); 1138a6f7baa3SSrinivasan Shanmugam DRM_DEBUG_KMS("load_detect %x returned: %x\n", 1139a6f7baa3SSrinivasan Shanmugam encoder->encoder_type, lret); 1140d38ceaf9SAlex Deucher if (lret == connector_status_connected) 1141d38ceaf9SAlex Deucher amdgpu_connector->use_digital = false; 1142d38ceaf9SAlex Deucher } 1143d38ceaf9SAlex Deucher break; 1144d38ceaf9SAlex Deucher } 1145d38ceaf9SAlex Deucher } 1146d38ceaf9SAlex Deucher } 1147d38ceaf9SAlex Deucher 1148d38ceaf9SAlex Deucher out: 1149d38ceaf9SAlex Deucher /* updated in get modes as well since we need to know if it's analog or digital */ 1150d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret); 1151d38ceaf9SAlex Deucher 1152d38ceaf9SAlex Deucher exit: 1153aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 1154d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev); 1155d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev); 1156aa0aad57SLukas Wunner } 1157d38ceaf9SAlex Deucher 1158d38ceaf9SAlex Deucher return ret; 1159d38ceaf9SAlex Deucher } 1160d38ceaf9SAlex Deucher 1161d38ceaf9SAlex Deucher /* okay need to be smart in here about which encoder to pick */ 1162d38ceaf9SAlex Deucher static struct drm_encoder * 1163d38ceaf9SAlex Deucher amdgpu_connector_dvi_encoder(struct drm_connector *connector) 1164d38ceaf9SAlex Deucher { 1165d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1166d38ceaf9SAlex Deucher struct drm_encoder *encoder; 1167d38ceaf9SAlex Deucher 116862afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder) { 1169d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital == true) { 1170d38ceaf9SAlex Deucher if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) 1171d38ceaf9SAlex Deucher return encoder; 1172d38ceaf9SAlex Deucher } else { 1173d38ceaf9SAlex Deucher if (encoder->encoder_type == DRM_MODE_ENCODER_DAC || 1174d38ceaf9SAlex Deucher encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1175d38ceaf9SAlex Deucher return encoder; 1176d38ceaf9SAlex Deucher } 1177d38ceaf9SAlex Deucher } 1178d38ceaf9SAlex Deucher 1179d38ceaf9SAlex Deucher /* see if we have a default encoder TODO */ 1180d38ceaf9SAlex Deucher 1181d38ceaf9SAlex Deucher /* then check use digitial */ 1182d38ceaf9SAlex Deucher /* pick the first one */ 118362afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder) 118498c0e348SVille Syrjälä return encoder; 118598c0e348SVille Syrjälä 1186d38ceaf9SAlex Deucher return NULL; 1187d38ceaf9SAlex Deucher } 1188d38ceaf9SAlex Deucher 1189d38ceaf9SAlex Deucher static void amdgpu_connector_dvi_force(struct drm_connector *connector) 1190d38ceaf9SAlex Deucher { 1191d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1192*8a1de314SSrinivasan Shanmugam 1193d38ceaf9SAlex Deucher if (connector->force == DRM_FORCE_ON) 1194d38ceaf9SAlex Deucher amdgpu_connector->use_digital = false; 1195d38ceaf9SAlex Deucher if (connector->force == DRM_FORCE_ON_DIGITAL) 1196d38ceaf9SAlex Deucher amdgpu_connector->use_digital = true; 1197d38ceaf9SAlex Deucher } 1198d38ceaf9SAlex Deucher 1199ba9ca088SLuc Van Oostenryck static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, 1200d38ceaf9SAlex Deucher struct drm_display_mode *mode) 1201d38ceaf9SAlex Deucher { 1202d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 12031348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev); 1204d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1205d38ceaf9SAlex Deucher 1206d38ceaf9SAlex Deucher /* XXX check mode bandwidth */ 1207d38ceaf9SAlex Deucher 1208d38ceaf9SAlex Deucher if (amdgpu_connector->use_digital && (mode->clock > 165000)) { 1209d38ceaf9SAlex Deucher if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) || 1210d38ceaf9SAlex Deucher (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || 1211d38ceaf9SAlex Deucher (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) { 1212d38ceaf9SAlex Deucher return MODE_OK; 12133c021931SClaudio Suarez } else if (connector->display_info.is_hdmi) { 1214d38ceaf9SAlex Deucher /* HDMI 1.3+ supports max clock of 340 Mhz */ 1215d38ceaf9SAlex Deucher if (mode->clock > 340000) 1216d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1217d38ceaf9SAlex Deucher else 1218d38ceaf9SAlex Deucher return MODE_OK; 1219d38ceaf9SAlex Deucher } else { 1220d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1221d38ceaf9SAlex Deucher } 1222d38ceaf9SAlex Deucher } 1223d38ceaf9SAlex Deucher 1224d38ceaf9SAlex Deucher /* check against the max pixel clock */ 1225d38ceaf9SAlex Deucher if ((mode->clock / 10) > adev->clock.max_pixel_clock) 1226d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1227d38ceaf9SAlex Deucher 1228d38ceaf9SAlex Deucher return MODE_OK; 1229d38ceaf9SAlex Deucher } 1230d38ceaf9SAlex Deucher 1231d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = { 1232d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_vga_get_modes, 1233d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_dvi_mode_valid, 1234d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_dvi_encoder, 1235d38ceaf9SAlex Deucher }; 1236d38ceaf9SAlex Deucher 1237d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = { 1238d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 1239d38ceaf9SAlex Deucher .detect = amdgpu_connector_dvi_detect, 1240d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 1241d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_property, 124240492f60SGrazvydas Ignotas .early_unregister = amdgpu_connector_unregister, 1243d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 1244d38ceaf9SAlex Deucher .force = amdgpu_connector_dvi_force, 1245d38ceaf9SAlex Deucher }; 1246d38ceaf9SAlex Deucher 1247d38ceaf9SAlex Deucher static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) 1248d38ceaf9SAlex Deucher { 1249d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1250d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1251d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1252d38ceaf9SAlex Deucher int ret; 1253d38ceaf9SAlex Deucher 1254d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1255d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1256d38ceaf9SAlex Deucher struct drm_display_mode *mode; 1257d38ceaf9SAlex Deucher 1258d38ceaf9SAlex Deucher if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1259d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on) 1260d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector, 1261d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_ON); 1262d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 1263d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 1264d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on) 1265d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector, 1266d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_OFF); 1267d38ceaf9SAlex Deucher } else { 1268d38ceaf9SAlex Deucher /* need to setup ddc on the bridge */ 1269d38ceaf9SAlex Deucher if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1270d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) { 1271d38ceaf9SAlex Deucher if (encoder) 1272d38ceaf9SAlex Deucher amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1273d38ceaf9SAlex Deucher } 1274d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 1275d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 1276d38ceaf9SAlex Deucher } 1277d38ceaf9SAlex Deucher 1278d38ceaf9SAlex Deucher if (ret > 0) { 1279d38ceaf9SAlex Deucher if (encoder) { 1280d38ceaf9SAlex Deucher amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 1281d38ceaf9SAlex Deucher /* add scaled modes */ 1282d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector); 1283d38ceaf9SAlex Deucher } 1284d38ceaf9SAlex Deucher return ret; 1285d38ceaf9SAlex Deucher } 1286d38ceaf9SAlex Deucher 1287d38ceaf9SAlex Deucher if (!encoder) 1288d38ceaf9SAlex Deucher return 0; 1289d38ceaf9SAlex Deucher 1290d38ceaf9SAlex Deucher /* we have no EDID modes */ 1291d38ceaf9SAlex Deucher mode = amdgpu_connector_lcd_native_mode(encoder); 1292d38ceaf9SAlex Deucher if (mode) { 1293d38ceaf9SAlex Deucher ret = 1; 1294d38ceaf9SAlex Deucher drm_mode_probed_add(connector, mode); 1295d38ceaf9SAlex Deucher /* add the width/height from vbios tables if available */ 1296d38ceaf9SAlex Deucher connector->display_info.width_mm = mode->width_mm; 1297d38ceaf9SAlex Deucher connector->display_info.height_mm = mode->height_mm; 1298d38ceaf9SAlex Deucher /* add scaled modes */ 1299d38ceaf9SAlex Deucher amdgpu_connector_add_common_modes(encoder, connector); 1300d38ceaf9SAlex Deucher } 1301d38ceaf9SAlex Deucher } else { 1302d38ceaf9SAlex Deucher /* need to setup ddc on the bridge */ 1303d38ceaf9SAlex Deucher if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1304d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) { 1305d38ceaf9SAlex Deucher if (encoder) 1306d38ceaf9SAlex Deucher amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1307d38ceaf9SAlex Deucher } 1308d38ceaf9SAlex Deucher amdgpu_connector_get_edid(connector); 1309d38ceaf9SAlex Deucher ret = amdgpu_connector_ddc_get_modes(connector); 1310d38ceaf9SAlex Deucher 1311d38ceaf9SAlex Deucher amdgpu_get_native_mode(connector); 1312d38ceaf9SAlex Deucher } 1313d38ceaf9SAlex Deucher 1314d38ceaf9SAlex Deucher return ret; 1315d38ceaf9SAlex Deucher } 1316d38ceaf9SAlex Deucher 1317d38ceaf9SAlex Deucher u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) 1318d38ceaf9SAlex Deucher { 1319d38ceaf9SAlex Deucher struct drm_encoder *encoder; 1320d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 1321d38ceaf9SAlex Deucher 132262afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder) { 1323d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 1324d38ceaf9SAlex Deucher 1325d38ceaf9SAlex Deucher switch (amdgpu_encoder->encoder_id) { 1326d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_TRAVIS: 1327d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_NUTMEG: 1328d38ceaf9SAlex Deucher return amdgpu_encoder->encoder_id; 1329d38ceaf9SAlex Deucher default: 1330d38ceaf9SAlex Deucher break; 1331d38ceaf9SAlex Deucher } 1332d38ceaf9SAlex Deucher } 1333d38ceaf9SAlex Deucher 1334d38ceaf9SAlex Deucher return ENCODER_OBJECT_ID_NONE; 1335d38ceaf9SAlex Deucher } 1336d38ceaf9SAlex Deucher 1337d38ceaf9SAlex Deucher static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) 1338d38ceaf9SAlex Deucher { 1339d38ceaf9SAlex Deucher struct drm_encoder *encoder; 1340d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 1341d38ceaf9SAlex Deucher bool found = false; 1342d38ceaf9SAlex Deucher 134362afb4adSJosé Roberto de Souza drm_connector_for_each_possible_encoder(connector, encoder) { 1344d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 1345d38ceaf9SAlex Deucher if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) 1346d38ceaf9SAlex Deucher found = true; 1347d38ceaf9SAlex Deucher } 1348d38ceaf9SAlex Deucher 1349d38ceaf9SAlex Deucher return found; 1350d38ceaf9SAlex Deucher } 1351d38ceaf9SAlex Deucher 1352d38ceaf9SAlex Deucher bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector) 1353d38ceaf9SAlex Deucher { 1354d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 13551348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev); 1356d38ceaf9SAlex Deucher 1357d38ceaf9SAlex Deucher if ((adev->clock.default_dispclk >= 53900) && 1358d38ceaf9SAlex Deucher amdgpu_connector_encoder_is_hbr2(connector)) { 1359d38ceaf9SAlex Deucher return true; 1360d38ceaf9SAlex Deucher } 1361d38ceaf9SAlex Deucher 1362d38ceaf9SAlex Deucher return false; 1363d38ceaf9SAlex Deucher } 1364d38ceaf9SAlex Deucher 1365d38ceaf9SAlex Deucher static enum drm_connector_status 1366d38ceaf9SAlex Deucher amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) 1367d38ceaf9SAlex Deucher { 1368d38ceaf9SAlex Deucher struct drm_device *dev = connector->dev; 13691348969aSLuben Tuikov struct amdgpu_device *adev = drm_to_adev(dev); 1370d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1371d38ceaf9SAlex Deucher enum drm_connector_status ret = connector_status_disconnected; 1372d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1373d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1374d38ceaf9SAlex Deucher int r; 1375d38ceaf9SAlex Deucher 1376aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 1377d38ceaf9SAlex Deucher r = pm_runtime_get_sync(connector->dev->dev); 1378f79f9476SNavid Emamdoost if (r < 0) { 1379f79f9476SNavid Emamdoost pm_runtime_put_autosuspend(connector->dev->dev); 1380d38ceaf9SAlex Deucher return connector_status_disconnected; 1381aa0aad57SLukas Wunner } 1382f79f9476SNavid Emamdoost } 1383d38ceaf9SAlex Deucher 1384d38ceaf9SAlex Deucher if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1385d38ceaf9SAlex Deucher ret = connector->status; 1386d38ceaf9SAlex Deucher goto out; 1387d38ceaf9SAlex Deucher } 1388d38ceaf9SAlex Deucher 1389d38ceaf9SAlex Deucher amdgpu_connector_free_edid(connector); 1390d38ceaf9SAlex Deucher 1391d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1392d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1393d38ceaf9SAlex Deucher if (encoder) { 1394d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1395d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1396d38ceaf9SAlex Deucher 1397d38ceaf9SAlex Deucher /* check if panel is valid */ 1398d38ceaf9SAlex Deucher if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 1399d38ceaf9SAlex Deucher ret = connector_status_connected; 1400d38ceaf9SAlex Deucher } 1401d38ceaf9SAlex Deucher /* eDP is always DP */ 1402d38ceaf9SAlex Deucher amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1403d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on) 1404d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector, 1405d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_ON); 1406d38ceaf9SAlex Deucher if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1407d38ceaf9SAlex Deucher ret = connector_status_connected; 1408d38ceaf9SAlex Deucher if (!amdgpu_dig_connector->edp_on) 1409d38ceaf9SAlex Deucher amdgpu_atombios_encoder_set_edp_panel_power(connector, 1410d38ceaf9SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_OFF); 1411d38ceaf9SAlex Deucher } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1412d38ceaf9SAlex Deucher ENCODER_OBJECT_ID_NONE) { 1413d38ceaf9SAlex Deucher /* DP bridges are always DP */ 1414d38ceaf9SAlex Deucher amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1415d38ceaf9SAlex Deucher /* get the DPCD from the bridge */ 1416d38ceaf9SAlex Deucher amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1417d38ceaf9SAlex Deucher 1418d38ceaf9SAlex Deucher if (encoder) { 1419d38ceaf9SAlex Deucher /* setup ddc on the bridge */ 1420d38ceaf9SAlex Deucher amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1421d38ceaf9SAlex Deucher /* bridge chips are always aux */ 1422e0b5b5ecSSamuel Li /* try DDC */ 1423e0b5b5ecSSamuel Li if (amdgpu_display_ddc_probe(amdgpu_connector, true)) 1424d38ceaf9SAlex Deucher ret = connector_status_connected; 1425d38ceaf9SAlex Deucher else if (amdgpu_connector->dac_load_detect) { /* try load detection */ 142617b10f94SAlex Deucher const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 1427*8a1de314SSrinivasan Shanmugam 1428d38ceaf9SAlex Deucher ret = encoder_funcs->detect(encoder, connector); 1429d38ceaf9SAlex Deucher } 1430d38ceaf9SAlex Deucher } 1431d38ceaf9SAlex Deucher } else { 1432d38ceaf9SAlex Deucher amdgpu_dig_connector->dp_sink_type = 1433d38ceaf9SAlex Deucher amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 1434d38ceaf9SAlex Deucher if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1435d38ceaf9SAlex Deucher ret = connector_status_connected; 1436d38ceaf9SAlex Deucher if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) 1437d38ceaf9SAlex Deucher amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1438d38ceaf9SAlex Deucher } else { 1439d38ceaf9SAlex Deucher if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 1440d38ceaf9SAlex Deucher if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1441d38ceaf9SAlex Deucher ret = connector_status_connected; 1442d38ceaf9SAlex Deucher } else { 1443d38ceaf9SAlex Deucher /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ 1444e0b5b5ecSSamuel Li if (amdgpu_display_ddc_probe(amdgpu_connector, 1445e0b5b5ecSSamuel Li false)) 1446d38ceaf9SAlex Deucher ret = connector_status_connected; 1447d38ceaf9SAlex Deucher } 1448d38ceaf9SAlex Deucher } 1449d38ceaf9SAlex Deucher } 1450d38ceaf9SAlex Deucher 1451d38ceaf9SAlex Deucher amdgpu_connector_update_scratch_regs(connector, ret); 1452d38ceaf9SAlex Deucher out: 1453aa0aad57SLukas Wunner if (!drm_kms_helper_is_poll_worker()) { 1454d38ceaf9SAlex Deucher pm_runtime_mark_last_busy(connector->dev->dev); 1455d38ceaf9SAlex Deucher pm_runtime_put_autosuspend(connector->dev->dev); 1456aa0aad57SLukas Wunner } 1457d38ceaf9SAlex Deucher 145805211e7fSAlex Deucher if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 145905211e7fSAlex Deucher connector->connector_type == DRM_MODE_CONNECTOR_eDP) 146065bf2cf9SOleg Vasilev drm_dp_set_subconnector_property(&amdgpu_connector->base, 146165bf2cf9SOleg Vasilev ret, 146265bf2cf9SOleg Vasilev amdgpu_dig_connector->dpcd, 146365bf2cf9SOleg Vasilev amdgpu_dig_connector->downstream_ports); 1464d38ceaf9SAlex Deucher return ret; 1465d38ceaf9SAlex Deucher } 1466d38ceaf9SAlex Deucher 1467ba9ca088SLuc Van Oostenryck static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector, 1468d38ceaf9SAlex Deucher struct drm_display_mode *mode) 1469d38ceaf9SAlex Deucher { 1470d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1471d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1472d38ceaf9SAlex Deucher 1473d38ceaf9SAlex Deucher /* XXX check mode bandwidth */ 1474d38ceaf9SAlex Deucher 1475d38ceaf9SAlex Deucher if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1476d38ceaf9SAlex Deucher (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1477d38ceaf9SAlex Deucher struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1478d38ceaf9SAlex Deucher 1479d38ceaf9SAlex Deucher if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 1480d38ceaf9SAlex Deucher return MODE_PANEL; 1481d38ceaf9SAlex Deucher 1482d38ceaf9SAlex Deucher if (encoder) { 1483d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1484d38ceaf9SAlex Deucher struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1485d38ceaf9SAlex Deucher 1486d38ceaf9SAlex Deucher /* AVIVO hardware supports downscaling modes larger than the panel 1487d38ceaf9SAlex Deucher * to the panel size, but I'm not sure this is desirable. 1488d38ceaf9SAlex Deucher */ 1489d38ceaf9SAlex Deucher if ((mode->hdisplay > native_mode->hdisplay) || 1490d38ceaf9SAlex Deucher (mode->vdisplay > native_mode->vdisplay)) 1491d38ceaf9SAlex Deucher return MODE_PANEL; 1492d38ceaf9SAlex Deucher 1493d38ceaf9SAlex Deucher /* if scaling is disabled, block non-native modes */ 1494d38ceaf9SAlex Deucher if (amdgpu_encoder->rmx_type == RMX_OFF) { 1495d38ceaf9SAlex Deucher if ((mode->hdisplay != native_mode->hdisplay) || 1496d38ceaf9SAlex Deucher (mode->vdisplay != native_mode->vdisplay)) 1497d38ceaf9SAlex Deucher return MODE_PANEL; 1498d38ceaf9SAlex Deucher } 1499d38ceaf9SAlex Deucher } 1500d38ceaf9SAlex Deucher return MODE_OK; 1501d38ceaf9SAlex Deucher } else { 1502d38ceaf9SAlex Deucher if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 1503d38ceaf9SAlex Deucher (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 1504d38ceaf9SAlex Deucher return amdgpu_atombios_dp_mode_valid_helper(connector, mode); 1505d38ceaf9SAlex Deucher } else { 15063c021931SClaudio Suarez if (connector->display_info.is_hdmi) { 1507d38ceaf9SAlex Deucher /* HDMI 1.3+ supports max clock of 340 Mhz */ 1508d38ceaf9SAlex Deucher if (mode->clock > 340000) 1509d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1510d38ceaf9SAlex Deucher } else { 1511d38ceaf9SAlex Deucher if (mode->clock > 165000) 1512d38ceaf9SAlex Deucher return MODE_CLOCK_HIGH; 1513d38ceaf9SAlex Deucher } 1514d38ceaf9SAlex Deucher } 1515d38ceaf9SAlex Deucher } 1516d38ceaf9SAlex Deucher 1517d38ceaf9SAlex Deucher return MODE_OK; 1518d38ceaf9SAlex Deucher } 1519d38ceaf9SAlex Deucher 1520405a1f90SAlex Deucher static int 1521405a1f90SAlex Deucher amdgpu_connector_late_register(struct drm_connector *connector) 1522405a1f90SAlex Deucher { 1523405a1f90SAlex Deucher struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1524405a1f90SAlex Deucher int r = 0; 1525405a1f90SAlex Deucher 1526405a1f90SAlex Deucher if (amdgpu_connector->ddc_bus->has_aux) { 1527405a1f90SAlex Deucher amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev; 1528405a1f90SAlex Deucher r = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux); 1529405a1f90SAlex Deucher } 1530405a1f90SAlex Deucher 1531405a1f90SAlex Deucher return r; 1532405a1f90SAlex Deucher } 1533405a1f90SAlex Deucher 1534d38ceaf9SAlex Deucher static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = { 1535d38ceaf9SAlex Deucher .get_modes = amdgpu_connector_dp_get_modes, 1536d38ceaf9SAlex Deucher .mode_valid = amdgpu_connector_dp_mode_valid, 1537d38ceaf9SAlex Deucher .best_encoder = amdgpu_connector_dvi_encoder, 1538d38ceaf9SAlex Deucher }; 1539d38ceaf9SAlex Deucher 1540d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_dp_funcs = { 1541d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 1542d38ceaf9SAlex Deucher .detect = amdgpu_connector_dp_detect, 1543d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 1544d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_property, 154540492f60SGrazvydas Ignotas .early_unregister = amdgpu_connector_unregister, 1546d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 1547d38ceaf9SAlex Deucher .force = amdgpu_connector_dvi_force, 1548405a1f90SAlex Deucher .late_register = amdgpu_connector_late_register, 1549d38ceaf9SAlex Deucher }; 1550d38ceaf9SAlex Deucher 1551d38ceaf9SAlex Deucher static const struct drm_connector_funcs amdgpu_connector_edp_funcs = { 1552d38ceaf9SAlex Deucher .dpms = drm_helper_connector_dpms, 1553d38ceaf9SAlex Deucher .detect = amdgpu_connector_dp_detect, 1554d38ceaf9SAlex Deucher .fill_modes = drm_helper_probe_single_connector_modes, 1555d38ceaf9SAlex Deucher .set_property = amdgpu_connector_set_lcd_property, 155640492f60SGrazvydas Ignotas .early_unregister = amdgpu_connector_unregister, 1557d38ceaf9SAlex Deucher .destroy = amdgpu_connector_destroy, 1558d38ceaf9SAlex Deucher .force = amdgpu_connector_dvi_force, 1559405a1f90SAlex Deucher .late_register = amdgpu_connector_late_register, 1560d38ceaf9SAlex Deucher }; 1561d38ceaf9SAlex Deucher 1562d38ceaf9SAlex Deucher void 1563d38ceaf9SAlex Deucher amdgpu_connector_add(struct amdgpu_device *adev, 1564d38ceaf9SAlex Deucher uint32_t connector_id, 1565d38ceaf9SAlex Deucher uint32_t supported_device, 1566d38ceaf9SAlex Deucher int connector_type, 1567d38ceaf9SAlex Deucher struct amdgpu_i2c_bus_rec *i2c_bus, 1568d38ceaf9SAlex Deucher uint16_t connector_object_id, 1569d38ceaf9SAlex Deucher struct amdgpu_hpd *hpd, 1570d38ceaf9SAlex Deucher struct amdgpu_router *router) 1571d38ceaf9SAlex Deucher { 15724a580877SLuben Tuikov struct drm_device *dev = adev_to_drm(adev); 1573d38ceaf9SAlex Deucher struct drm_connector *connector; 1574f8d2d39eSLyude Paul struct drm_connector_list_iter iter; 1575d38ceaf9SAlex Deucher struct amdgpu_connector *amdgpu_connector; 1576d38ceaf9SAlex Deucher struct amdgpu_connector_atom_dig *amdgpu_dig_connector; 1577d38ceaf9SAlex Deucher struct drm_encoder *encoder; 1578d38ceaf9SAlex Deucher struct amdgpu_encoder *amdgpu_encoder; 15795b50fa2bSAndrzej Pietrasiewicz struct i2c_adapter *ddc = NULL; 1580d38ceaf9SAlex Deucher uint32_t subpixel_order = SubPixelNone; 1581d38ceaf9SAlex Deucher bool shared_ddc = false; 1582d38ceaf9SAlex Deucher bool is_dp_bridge = false; 1583d38ceaf9SAlex Deucher bool has_aux = false; 1584d38ceaf9SAlex Deucher 1585d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1586d38ceaf9SAlex Deucher return; 1587d38ceaf9SAlex Deucher 1588d38ceaf9SAlex Deucher /* see if we already added it */ 1589f8d2d39eSLyude Paul drm_connector_list_iter_begin(dev, &iter); 1590f8d2d39eSLyude Paul drm_for_each_connector_iter(connector, &iter) { 1591d38ceaf9SAlex Deucher amdgpu_connector = to_amdgpu_connector(connector); 1592d38ceaf9SAlex Deucher if (amdgpu_connector->connector_id == connector_id) { 1593d38ceaf9SAlex Deucher amdgpu_connector->devices |= supported_device; 1594f8d2d39eSLyude Paul drm_connector_list_iter_end(&iter); 1595d38ceaf9SAlex Deucher return; 1596d38ceaf9SAlex Deucher } 1597d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus && i2c_bus->valid) { 1598d38ceaf9SAlex Deucher if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) { 1599d38ceaf9SAlex Deucher amdgpu_connector->shared_ddc = true; 1600d38ceaf9SAlex Deucher shared_ddc = true; 1601d38ceaf9SAlex Deucher } 1602d38ceaf9SAlex Deucher if (amdgpu_connector->router_bus && router->ddc_valid && 1603d38ceaf9SAlex Deucher (amdgpu_connector->router.router_id == router->router_id)) { 1604d38ceaf9SAlex Deucher amdgpu_connector->shared_ddc = false; 1605d38ceaf9SAlex Deucher shared_ddc = false; 1606d38ceaf9SAlex Deucher } 1607d38ceaf9SAlex Deucher } 1608d38ceaf9SAlex Deucher } 1609f8d2d39eSLyude Paul drm_connector_list_iter_end(&iter); 1610d38ceaf9SAlex Deucher 1611d38ceaf9SAlex Deucher /* check if it's a dp bridge */ 1612d38ceaf9SAlex Deucher list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1613d38ceaf9SAlex Deucher amdgpu_encoder = to_amdgpu_encoder(encoder); 1614d38ceaf9SAlex Deucher if (amdgpu_encoder->devices & supported_device) { 1615d38ceaf9SAlex Deucher switch (amdgpu_encoder->encoder_id) { 1616d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_TRAVIS: 1617d38ceaf9SAlex Deucher case ENCODER_OBJECT_ID_NUTMEG: 1618d38ceaf9SAlex Deucher is_dp_bridge = true; 1619d38ceaf9SAlex Deucher break; 1620d38ceaf9SAlex Deucher default: 1621d38ceaf9SAlex Deucher break; 1622d38ceaf9SAlex Deucher } 1623d38ceaf9SAlex Deucher } 1624d38ceaf9SAlex Deucher } 1625d38ceaf9SAlex Deucher 1626d38ceaf9SAlex Deucher amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL); 1627d38ceaf9SAlex Deucher if (!amdgpu_connector) 1628d38ceaf9SAlex Deucher return; 1629d38ceaf9SAlex Deucher 1630d38ceaf9SAlex Deucher connector = &amdgpu_connector->base; 1631d38ceaf9SAlex Deucher 1632d38ceaf9SAlex Deucher amdgpu_connector->connector_id = connector_id; 1633d38ceaf9SAlex Deucher amdgpu_connector->devices = supported_device; 1634d38ceaf9SAlex Deucher amdgpu_connector->shared_ddc = shared_ddc; 1635d38ceaf9SAlex Deucher amdgpu_connector->connector_object_id = connector_object_id; 1636d38ceaf9SAlex Deucher amdgpu_connector->hpd = *hpd; 1637d38ceaf9SAlex Deucher 1638d38ceaf9SAlex Deucher amdgpu_connector->router = *router; 1639d38ceaf9SAlex Deucher if (router->ddc_valid || router->cd_valid) { 1640d38ceaf9SAlex Deucher amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info); 1641d38ceaf9SAlex Deucher if (!amdgpu_connector->router_bus) 1642d38ceaf9SAlex Deucher DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); 1643d38ceaf9SAlex Deucher } 1644d38ceaf9SAlex Deucher 1645d38ceaf9SAlex Deucher if (is_dp_bridge) { 1646d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1647d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1648d38ceaf9SAlex Deucher goto failed; 1649d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1650d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1651d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 16525b50fa2bSAndrzej Pietrasiewicz if (amdgpu_connector->ddc_bus) { 1653d38ceaf9SAlex Deucher has_aux = true; 16545b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter; 16555b50fa2bSAndrzej Pietrasiewicz } else { 1656d38ceaf9SAlex Deucher DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1657d38ceaf9SAlex Deucher } 16585b50fa2bSAndrzej Pietrasiewicz } 1659d38ceaf9SAlex Deucher switch (connector_type) { 1660d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_VGA: 1661d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVIA: 1662d38ceaf9SAlex Deucher default: 16635b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 16645b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_dp_funcs, 16655b50fa2bSAndrzej Pietrasiewicz connector_type, 16665b50fa2bSAndrzej Pietrasiewicz ddc); 1667d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, 1668d38ceaf9SAlex Deucher &amdgpu_connector_dp_helper_funcs); 1669d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1670d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1671d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1672d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1673d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1674d38ceaf9SAlex Deucher 1); 1675d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1676d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1677d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1678d38ceaf9SAlex Deucher break; 1679d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVII: 1680d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVID: 1681d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIA: 1682d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIB: 1683d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DisplayPort: 16845b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 16855b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_dp_funcs, 16865b50fa2bSAndrzej Pietrasiewicz connector_type, 16875b50fa2bSAndrzej Pietrasiewicz ddc); 1688d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, 1689d38ceaf9SAlex Deucher &amdgpu_connector_dp_helper_funcs); 1690d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1691d38ceaf9SAlex Deucher adev->mode_info.underscan_property, 1692d38ceaf9SAlex Deucher UNDERSCAN_OFF); 1693d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1694d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property, 1695d38ceaf9SAlex Deucher 0); 1696d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1697d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property, 1698d38ceaf9SAlex Deucher 0); 1699d38ceaf9SAlex Deucher 1700d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1701d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1702d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1703d38ceaf9SAlex Deucher 1704d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1705d38ceaf9SAlex Deucher adev->mode_info.dither_property, 1706d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE); 1707d38ceaf9SAlex Deucher 17084bb71fceShongao if (amdgpu_audio != 0) { 1709d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1710d38ceaf9SAlex Deucher adev->mode_info.audio_property, 1711d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO); 17124bb71fceShongao amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 17134bb71fceShongao } 1714d38ceaf9SAlex Deucher 1715d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1716d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1717d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1718d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1719d38ceaf9SAlex Deucher else 1720d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1721d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1722d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1723d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1724d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1725d38ceaf9SAlex Deucher 1); 1726d38ceaf9SAlex Deucher } 1727d38ceaf9SAlex Deucher break; 1728d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_LVDS: 1729d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_eDP: 17305b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 17315b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_edp_funcs, 17325b50fa2bSAndrzej Pietrasiewicz connector_type, 17335b50fa2bSAndrzej Pietrasiewicz ddc); 1734d38ceaf9SAlex Deucher drm_connector_helper_add(&amdgpu_connector->base, 1735d38ceaf9SAlex Deucher &amdgpu_connector_dp_helper_funcs); 1736d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1737d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1738d38ceaf9SAlex Deucher DRM_MODE_SCALE_FULLSCREEN); 1739d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1740d38ceaf9SAlex Deucher connector->interlace_allowed = false; 1741d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1742d38ceaf9SAlex Deucher break; 1743d38ceaf9SAlex Deucher } 1744d38ceaf9SAlex Deucher } else { 1745d38ceaf9SAlex Deucher switch (connector_type) { 1746d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_VGA: 1747d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1748d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1749d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1750d38ceaf9SAlex Deucher DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 17515b50fa2bSAndrzej Pietrasiewicz else 17525b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter; 1753d38ceaf9SAlex Deucher } 17545b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 17555b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_vga_funcs, 17565b50fa2bSAndrzej Pietrasiewicz connector_type, 17575b50fa2bSAndrzej Pietrasiewicz ddc); 17585b50fa2bSAndrzej Pietrasiewicz drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1759d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1760d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1761d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1762d38ceaf9SAlex Deucher 1); 1763d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1764d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1765d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1766d38ceaf9SAlex Deucher /* no HPD on analog connectors */ 1767d38ceaf9SAlex Deucher amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1768d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1769d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1770d38ceaf9SAlex Deucher break; 1771d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVIA: 1772d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1773d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1774d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1775d38ceaf9SAlex Deucher DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 17765b50fa2bSAndrzej Pietrasiewicz else 17775b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter; 1778d38ceaf9SAlex Deucher } 17795b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 17805b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_vga_funcs, 17815b50fa2bSAndrzej Pietrasiewicz connector_type, 17825b50fa2bSAndrzej Pietrasiewicz ddc); 17835b50fa2bSAndrzej Pietrasiewicz drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1784d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1785d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1786d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1787d38ceaf9SAlex Deucher 1); 1788d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1789d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1790d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1791d38ceaf9SAlex Deucher /* no HPD on analog connectors */ 1792d38ceaf9SAlex Deucher amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1793d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1794d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1795d38ceaf9SAlex Deucher break; 1796d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVII: 1797d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DVID: 1798d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1799d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1800d38ceaf9SAlex Deucher goto failed; 1801d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1802d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1803d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1804d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1805d38ceaf9SAlex Deucher DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 18065b50fa2bSAndrzej Pietrasiewicz else 18075b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter; 1808d38ceaf9SAlex Deucher } 18095b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 18105b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_dvi_funcs, 18115b50fa2bSAndrzej Pietrasiewicz connector_type, 18125b50fa2bSAndrzej Pietrasiewicz ddc); 18135b50fa2bSAndrzej Pietrasiewicz drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1814d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1815d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1816d38ceaf9SAlex Deucher adev->mode_info.coherent_mode_property, 1817d38ceaf9SAlex Deucher 1); 1818d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1819d38ceaf9SAlex Deucher adev->mode_info.underscan_property, 1820d38ceaf9SAlex Deucher UNDERSCAN_OFF); 1821d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1822d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property, 1823d38ceaf9SAlex Deucher 0); 1824d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1825d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property, 1826d38ceaf9SAlex Deucher 0); 1827d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1828d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1829d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1830d38ceaf9SAlex Deucher 1831d38ceaf9SAlex Deucher if (amdgpu_audio != 0) { 1832d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1833d38ceaf9SAlex Deucher adev->mode_info.audio_property, 1834d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO); 18354bb71fceShongao amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1836d38ceaf9SAlex Deucher } 1837d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1838d38ceaf9SAlex Deucher adev->mode_info.dither_property, 1839d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE); 1840d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1841d38ceaf9SAlex Deucher amdgpu_connector->dac_load_detect = true; 1842d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1843d38ceaf9SAlex Deucher adev->mode_info.load_detect_property, 1844d38ceaf9SAlex Deucher 1); 1845d38ceaf9SAlex Deucher } 1846d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1847d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_DVII) 1848d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1849d38ceaf9SAlex Deucher else 1850d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1851d38ceaf9SAlex Deucher break; 1852d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIA: 1853d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_HDMIB: 1854d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1855d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1856d38ceaf9SAlex Deucher goto failed; 1857d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1858d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1859d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1860d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1861d38ceaf9SAlex Deucher DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 18625b50fa2bSAndrzej Pietrasiewicz else 18635b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter; 1864d38ceaf9SAlex Deucher } 18655b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 18665b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_dvi_funcs, 18675b50fa2bSAndrzej Pietrasiewicz connector_type, 18685b50fa2bSAndrzej Pietrasiewicz ddc); 18695b50fa2bSAndrzej Pietrasiewicz drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1870d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1871d38ceaf9SAlex Deucher adev->mode_info.coherent_mode_property, 1872d38ceaf9SAlex Deucher 1); 1873d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1874d38ceaf9SAlex Deucher adev->mode_info.underscan_property, 1875d38ceaf9SAlex Deucher UNDERSCAN_OFF); 1876d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1877d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property, 1878d38ceaf9SAlex Deucher 0); 1879d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1880d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property, 1881d38ceaf9SAlex Deucher 0); 1882d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1883d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1884d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1885d38ceaf9SAlex Deucher if (amdgpu_audio != 0) { 1886d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1887d38ceaf9SAlex Deucher adev->mode_info.audio_property, 1888d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO); 18894bb71fceShongao amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1890d38ceaf9SAlex Deucher } 1891d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1892d38ceaf9SAlex Deucher adev->mode_info.dither_property, 1893d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE); 1894d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1895d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1896d38ceaf9SAlex Deucher if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1897d38ceaf9SAlex Deucher connector->doublescan_allowed = true; 1898d38ceaf9SAlex Deucher else 1899d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1900d38ceaf9SAlex Deucher break; 1901d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_DisplayPort: 1902d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1903d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1904d38ceaf9SAlex Deucher goto failed; 1905d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1906d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1907d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 19085b50fa2bSAndrzej Pietrasiewicz if (amdgpu_connector->ddc_bus) { 1909d38ceaf9SAlex Deucher has_aux = true; 19105b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter; 19115b50fa2bSAndrzej Pietrasiewicz } else { 1912d38ceaf9SAlex Deucher DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1913d38ceaf9SAlex Deucher } 19145b50fa2bSAndrzej Pietrasiewicz } 19155b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 19165b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_dp_funcs, 19175b50fa2bSAndrzej Pietrasiewicz connector_type, 19185b50fa2bSAndrzej Pietrasiewicz ddc); 19195b50fa2bSAndrzej Pietrasiewicz drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1920d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1921d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1922d38ceaf9SAlex Deucher adev->mode_info.coherent_mode_property, 1923d38ceaf9SAlex Deucher 1); 1924d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1925d38ceaf9SAlex Deucher adev->mode_info.underscan_property, 1926d38ceaf9SAlex Deucher UNDERSCAN_OFF); 1927d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1928d38ceaf9SAlex Deucher adev->mode_info.underscan_hborder_property, 1929d38ceaf9SAlex Deucher 0); 1930d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1931d38ceaf9SAlex Deucher adev->mode_info.underscan_vborder_property, 1932d38ceaf9SAlex Deucher 0); 1933d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1934d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1935d38ceaf9SAlex Deucher DRM_MODE_SCALE_NONE); 1936d38ceaf9SAlex Deucher if (amdgpu_audio != 0) { 1937d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1938d38ceaf9SAlex Deucher adev->mode_info.audio_property, 1939d38ceaf9SAlex Deucher AMDGPU_AUDIO_AUTO); 19404bb71fceShongao amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1941d38ceaf9SAlex Deucher } 1942d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1943d38ceaf9SAlex Deucher adev->mode_info.dither_property, 1944d38ceaf9SAlex Deucher AMDGPU_FMT_DITHER_DISABLE); 1945d38ceaf9SAlex Deucher connector->interlace_allowed = true; 1946d38ceaf9SAlex Deucher /* in theory with a DP to VGA converter... */ 1947d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1948d38ceaf9SAlex Deucher break; 1949d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_eDP: 1950d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1951d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1952d38ceaf9SAlex Deucher goto failed; 1953d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1954d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1955d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 19565b50fa2bSAndrzej Pietrasiewicz if (amdgpu_connector->ddc_bus) { 1957d38ceaf9SAlex Deucher has_aux = true; 19585b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter; 19595b50fa2bSAndrzej Pietrasiewicz } else { 1960d38ceaf9SAlex Deucher DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1961d38ceaf9SAlex Deucher } 19625b50fa2bSAndrzej Pietrasiewicz } 19635b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 19645b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_edp_funcs, 19655b50fa2bSAndrzej Pietrasiewicz connector_type, 19665b50fa2bSAndrzej Pietrasiewicz ddc); 19675b50fa2bSAndrzej Pietrasiewicz drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1968d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1969d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1970d38ceaf9SAlex Deucher DRM_MODE_SCALE_FULLSCREEN); 1971d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1972d38ceaf9SAlex Deucher connector->interlace_allowed = false; 1973d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1974d38ceaf9SAlex Deucher break; 1975d38ceaf9SAlex Deucher case DRM_MODE_CONNECTOR_LVDS: 1976d38ceaf9SAlex Deucher amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1977d38ceaf9SAlex Deucher if (!amdgpu_dig_connector) 1978d38ceaf9SAlex Deucher goto failed; 1979d38ceaf9SAlex Deucher amdgpu_connector->con_priv = amdgpu_dig_connector; 1980d38ceaf9SAlex Deucher if (i2c_bus->valid) { 1981d38ceaf9SAlex Deucher amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1982d38ceaf9SAlex Deucher if (!amdgpu_connector->ddc_bus) 1983d38ceaf9SAlex Deucher DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 19845b50fa2bSAndrzej Pietrasiewicz else 19855b50fa2bSAndrzej Pietrasiewicz ddc = &amdgpu_connector->ddc_bus->adapter; 1986d38ceaf9SAlex Deucher } 19875b50fa2bSAndrzej Pietrasiewicz drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 19885b50fa2bSAndrzej Pietrasiewicz &amdgpu_connector_lvds_funcs, 19895b50fa2bSAndrzej Pietrasiewicz connector_type, 19905b50fa2bSAndrzej Pietrasiewicz ddc); 19915b50fa2bSAndrzej Pietrasiewicz drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); 1992d38ceaf9SAlex Deucher drm_object_attach_property(&amdgpu_connector->base.base, 1993d38ceaf9SAlex Deucher dev->mode_config.scaling_mode_property, 1994d38ceaf9SAlex Deucher DRM_MODE_SCALE_FULLSCREEN); 1995d38ceaf9SAlex Deucher subpixel_order = SubPixelHorizontalRGB; 1996d38ceaf9SAlex Deucher connector->interlace_allowed = false; 1997d38ceaf9SAlex Deucher connector->doublescan_allowed = false; 1998d38ceaf9SAlex Deucher break; 1999d38ceaf9SAlex Deucher } 2000d38ceaf9SAlex Deucher } 2001d38ceaf9SAlex Deucher 2002d38ceaf9SAlex Deucher if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) { 2003b636a1b3SLyude if (i2c_bus->valid) { 2004b636a1b3SLyude connector->polled = DRM_CONNECTOR_POLL_CONNECT | 2005b636a1b3SLyude DRM_CONNECTOR_POLL_DISCONNECT; 2006b636a1b3SLyude } 2007d38ceaf9SAlex Deucher } else 2008d38ceaf9SAlex Deucher connector->polled = DRM_CONNECTOR_POLL_HPD; 2009d38ceaf9SAlex Deucher 2010d38ceaf9SAlex Deucher connector->display_info.subpixel_order = subpixel_order; 2011d38ceaf9SAlex Deucher 2012d38ceaf9SAlex Deucher if (has_aux) 2013d38ceaf9SAlex Deucher amdgpu_atombios_dp_aux_init(amdgpu_connector); 2014d38ceaf9SAlex Deucher 201565bf2cf9SOleg Vasilev if (connector_type == DRM_MODE_CONNECTOR_DisplayPort || 201665bf2cf9SOleg Vasilev connector_type == DRM_MODE_CONNECTOR_eDP) { 201765bf2cf9SOleg Vasilev drm_connector_attach_dp_subconnector_property(&amdgpu_connector->base); 201865bf2cf9SOleg Vasilev } 201965bf2cf9SOleg Vasilev 2020d38ceaf9SAlex Deucher return; 2021d38ceaf9SAlex Deucher 2022d38ceaf9SAlex Deucher failed: 2023d38ceaf9SAlex Deucher drm_connector_cleanup(connector); 2024d38ceaf9SAlex Deucher kfree(connector); 2025d38ceaf9SAlex Deucher } 2026