1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27 #include <drm/amdgpu_drm.h> 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_atomfirmware.h" 31 #include "amdgpu_i2c.h" 32 #include "amdgpu_display.h" 33 34 #include "atom.h" 35 #include "atom-bits.h" 36 #include "atombios_encoders.h" 37 #include "bif/bif_4_1_d.h" 38 39 /* VBIOS-reported table size is unchecked against the image; cap iterations and 40 * adev->i2c_bus[] indexing to AMDGPU_MAX_I2C_BUS. 41 */ 42 static int amdgpu_atombios_gpio_i2c_num_entries(uint16_t size) 43 { 44 u32 bytes; 45 46 if (size < sizeof(ATOM_COMMON_TABLE_HEADER)) 47 return 0; 48 49 bytes = size - sizeof(ATOM_COMMON_TABLE_HEADER); 50 return (int)min_t(u32, bytes / sizeof(ATOM_GPIO_I2C_ASSIGMENT), 51 AMDGPU_MAX_I2C_BUS); 52 } 53 54 static struct amdgpu_i2c_bus_rec amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio) 55 { 56 struct amdgpu_i2c_bus_rec i2c; 57 58 memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec)); 59 60 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex); 61 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex); 62 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex); 63 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex); 64 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex); 65 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex); 66 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex); 67 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex); 68 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift); 69 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift); 70 i2c.en_clk_mask = (1 << gpio->ucClkEnShift); 71 i2c.en_data_mask = (1 << gpio->ucDataEnShift); 72 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift); 73 i2c.y_data_mask = (1 << gpio->ucDataY_Shift); 74 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift); 75 i2c.a_data_mask = (1 << gpio->ucDataA_Shift); 76 77 if (gpio->sucI2cId.sbfAccess.bfHW_Capable) 78 i2c.hw_capable = true; 79 else 80 i2c.hw_capable = false; 81 82 if (gpio->sucI2cId.ucAccess == 0xa0) 83 i2c.mm_i2c = true; 84 else 85 i2c.mm_i2c = false; 86 87 i2c.i2c_id = gpio->sucI2cId.ucAccess; 88 89 if (i2c.mask_clk_reg) 90 i2c.valid = true; 91 else 92 i2c.valid = false; 93 94 return i2c; 95 } 96 97 struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev, 98 uint8_t id) 99 { 100 struct atom_context *ctx = adev->mode_info.atom_context; 101 ATOM_GPIO_I2C_ASSIGMENT *gpio; 102 struct amdgpu_i2c_bus_rec i2c; 103 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 104 struct _ATOM_GPIO_I2C_INFO *i2c_info; 105 uint16_t data_offset, size; 106 int i, num_indices; 107 108 memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec)); 109 i2c.valid = false; 110 111 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 112 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 113 114 num_indices = amdgpu_atombios_gpio_i2c_num_entries(size); 115 116 gpio = &i2c_info->asGPIO_Info[0]; 117 for (i = 0; i < num_indices; i++) { 118 if (gpio->sucI2cId.ucAccess == id) { 119 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio); 120 break; 121 } 122 gpio = (ATOM_GPIO_I2C_ASSIGMENT *) 123 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); 124 } 125 } 126 127 return i2c; 128 } 129 130 void amdgpu_atombios_i2c_init(struct amdgpu_device *adev) 131 { 132 struct atom_context *ctx = adev->mode_info.atom_context; 133 ATOM_GPIO_I2C_ASSIGMENT *gpio; 134 struct amdgpu_i2c_bus_rec i2c; 135 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 136 struct _ATOM_GPIO_I2C_INFO *i2c_info; 137 uint16_t data_offset, size; 138 int i, num_indices; 139 char stmp[32]; 140 141 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 142 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 143 144 num_indices = amdgpu_atombios_gpio_i2c_num_entries(size); 145 146 gpio = &i2c_info->asGPIO_Info[0]; 147 for (i = 0; i < num_indices; i++) { 148 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio); 149 150 if (i2c.valid) { 151 sprintf(stmp, "0x%x", i2c.i2c_id); 152 adev->i2c_bus[i] = amdgpu_i2c_create(adev_to_drm(adev), &i2c, stmp); 153 } 154 gpio = (ATOM_GPIO_I2C_ASSIGMENT *) 155 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); 156 } 157 } 158 } 159 160 void amdgpu_atombios_oem_i2c_init(struct amdgpu_device *adev, u8 i2c_id) 161 { 162 struct atom_context *ctx = adev->mode_info.atom_context; 163 ATOM_GPIO_I2C_ASSIGMENT *gpio; 164 struct amdgpu_i2c_bus_rec i2c; 165 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 166 struct _ATOM_GPIO_I2C_INFO *i2c_info; 167 uint16_t data_offset, size; 168 int i, num_indices; 169 char stmp[32]; 170 171 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 172 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 173 174 num_indices = amdgpu_atombios_gpio_i2c_num_entries(size); 175 176 gpio = &i2c_info->asGPIO_Info[0]; 177 for (i = 0; i < num_indices; i++) { 178 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio); 179 180 if (i2c.valid && i2c.i2c_id == i2c_id) { 181 sprintf(stmp, "OEM 0x%x", i2c.i2c_id); 182 adev->i2c_bus[i] = amdgpu_i2c_create(adev_to_drm(adev), &i2c, stmp); 183 break; 184 } 185 gpio = (ATOM_GPIO_I2C_ASSIGMENT *) 186 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); 187 } 188 } 189 } 190 191 struct amdgpu_gpio_rec 192 amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev, 193 u8 id) 194 { 195 struct atom_context *ctx = adev->mode_info.atom_context; 196 struct amdgpu_gpio_rec gpio; 197 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT); 198 struct _ATOM_GPIO_PIN_LUT *gpio_info; 199 ATOM_GPIO_PIN_ASSIGNMENT *pin; 200 u16 data_offset, size; 201 int i, num_indices; 202 203 memset(&gpio, 0, sizeof(struct amdgpu_gpio_rec)); 204 gpio.valid = false; 205 206 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 207 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset); 208 209 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 210 sizeof(ATOM_GPIO_PIN_ASSIGNMENT); 211 212 pin = gpio_info->asGPIO_Pin; 213 for (i = 0; i < num_indices; i++) { 214 if (id == pin->ucGPIO_ID) { 215 gpio.id = pin->ucGPIO_ID; 216 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex); 217 gpio.shift = pin->ucGpioPinBitShift; 218 gpio.mask = (1 << pin->ucGpioPinBitShift); 219 gpio.valid = true; 220 break; 221 } 222 pin = (ATOM_GPIO_PIN_ASSIGNMENT *) 223 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT)); 224 } 225 } 226 227 return gpio; 228 } 229 230 static struct amdgpu_hpd 231 amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device *adev, 232 struct amdgpu_gpio_rec *gpio) 233 { 234 struct amdgpu_hpd hpd; 235 u32 reg; 236 237 memset(&hpd, 0, sizeof(struct amdgpu_hpd)); 238 239 reg = amdgpu_display_hpd_get_gpio_reg(adev); 240 241 hpd.gpio = *gpio; 242 if (gpio->reg == reg) { 243 switch(gpio->mask) { 244 case (1 << 0): 245 hpd.hpd = AMDGPU_HPD_1; 246 break; 247 case (1 << 8): 248 hpd.hpd = AMDGPU_HPD_2; 249 break; 250 case (1 << 16): 251 hpd.hpd = AMDGPU_HPD_3; 252 break; 253 case (1 << 24): 254 hpd.hpd = AMDGPU_HPD_4; 255 break; 256 case (1 << 26): 257 hpd.hpd = AMDGPU_HPD_5; 258 break; 259 case (1 << 28): 260 hpd.hpd = AMDGPU_HPD_6; 261 break; 262 default: 263 hpd.hpd = AMDGPU_HPD_NONE; 264 break; 265 } 266 } else 267 hpd.hpd = AMDGPU_HPD_NONE; 268 return hpd; 269 } 270 271 static const int object_connector_convert[] = { 272 DRM_MODE_CONNECTOR_Unknown, 273 DRM_MODE_CONNECTOR_DVII, 274 DRM_MODE_CONNECTOR_DVII, 275 DRM_MODE_CONNECTOR_DVID, 276 DRM_MODE_CONNECTOR_DVID, 277 DRM_MODE_CONNECTOR_VGA, 278 DRM_MODE_CONNECTOR_Composite, 279 DRM_MODE_CONNECTOR_SVIDEO, 280 DRM_MODE_CONNECTOR_Unknown, 281 DRM_MODE_CONNECTOR_Unknown, 282 DRM_MODE_CONNECTOR_9PinDIN, 283 DRM_MODE_CONNECTOR_Unknown, 284 DRM_MODE_CONNECTOR_HDMIA, 285 DRM_MODE_CONNECTOR_HDMIB, 286 DRM_MODE_CONNECTOR_LVDS, 287 DRM_MODE_CONNECTOR_9PinDIN, 288 DRM_MODE_CONNECTOR_Unknown, 289 DRM_MODE_CONNECTOR_Unknown, 290 DRM_MODE_CONNECTOR_Unknown, 291 DRM_MODE_CONNECTOR_DisplayPort, 292 DRM_MODE_CONNECTOR_eDP, 293 DRM_MODE_CONNECTOR_Unknown 294 }; 295 296 bool amdgpu_atombios_has_dce_engine_info(struct amdgpu_device *adev) 297 { 298 struct amdgpu_mode_info *mode_info = &adev->mode_info; 299 struct atom_context *ctx = mode_info->atom_context; 300 int index = GetIndexIntoMasterTable(DATA, Object_Header); 301 u16 size, data_offset; 302 u8 frev, crev; 303 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; 304 ATOM_OBJECT_HEADER *obj_header; 305 306 if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) 307 return false; 308 309 if (crev < 2) 310 return false; 311 312 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); 313 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) 314 (ctx->bios + data_offset + 315 le16_to_cpu(obj_header->usDisplayPathTableOffset)); 316 317 if (path_obj->ucNumOfDispPath) 318 return true; 319 else 320 return false; 321 } 322 323 bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev) 324 { 325 struct amdgpu_mode_info *mode_info = &adev->mode_info; 326 struct atom_context *ctx = mode_info->atom_context; 327 int index = GetIndexIntoMasterTable(DATA, Object_Header); 328 u16 size, data_offset; 329 u8 frev, crev; 330 ATOM_CONNECTOR_OBJECT_TABLE *con_obj; 331 ATOM_ENCODER_OBJECT_TABLE *enc_obj; 332 ATOM_OBJECT_TABLE *router_obj; 333 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; 334 ATOM_OBJECT_HEADER *obj_header; 335 int i, j, k, path_size, device_support; 336 int connector_type; 337 u16 conn_id, connector_object_id; 338 struct amdgpu_i2c_bus_rec ddc_bus; 339 struct amdgpu_router router; 340 struct amdgpu_gpio_rec gpio; 341 struct amdgpu_hpd hpd; 342 343 if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) 344 return false; 345 346 if (crev < 2) 347 return false; 348 349 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); 350 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) 351 (ctx->bios + data_offset + 352 le16_to_cpu(obj_header->usDisplayPathTableOffset)); 353 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) 354 (ctx->bios + data_offset + 355 le16_to_cpu(obj_header->usConnectorObjectTableOffset)); 356 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *) 357 (ctx->bios + data_offset + 358 le16_to_cpu(obj_header->usEncoderObjectTableOffset)); 359 router_obj = (ATOM_OBJECT_TABLE *) 360 (ctx->bios + data_offset + 361 le16_to_cpu(obj_header->usRouterObjectTableOffset)); 362 device_support = le16_to_cpu(obj_header->usDeviceSupport); 363 364 path_size = 0; 365 for (i = 0; i < path_obj->ucNumOfDispPath; i++) { 366 uint8_t *addr = (uint8_t *) path_obj->asDispPath; 367 ATOM_DISPLAY_OBJECT_PATH *path; 368 addr += path_size; 369 path = (ATOM_DISPLAY_OBJECT_PATH *) addr; 370 path_size += le16_to_cpu(path->usSize); 371 372 if (device_support & le16_to_cpu(path->usDeviceTag)) { 373 uint8_t con_obj_id = 374 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) 375 >> OBJECT_ID_SHIFT; 376 377 /* Skip TV/CV support */ 378 if ((le16_to_cpu(path->usDeviceTag) == 379 ATOM_DEVICE_TV1_SUPPORT) || 380 (le16_to_cpu(path->usDeviceTag) == 381 ATOM_DEVICE_CV_SUPPORT)) 382 continue; 383 384 if (con_obj_id >= ARRAY_SIZE(object_connector_convert)) { 385 DRM_ERROR("invalid con_obj_id %d for device tag 0x%04x\n", 386 con_obj_id, le16_to_cpu(path->usDeviceTag)); 387 continue; 388 } 389 390 connector_type = 391 object_connector_convert[con_obj_id]; 392 connector_object_id = con_obj_id; 393 394 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 395 continue; 396 397 router.ddc_valid = false; 398 router.cd_valid = false; 399 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) { 400 uint8_t grph_obj_type = 401 (le16_to_cpu(path->usGraphicObjIds[j]) & 402 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 403 404 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { 405 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) { 406 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID); 407 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) { 408 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 409 (ctx->bios + data_offset + 410 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset)); 411 ATOM_ENCODER_CAP_RECORD *cap_record; 412 u16 caps = 0; 413 414 while (record->ucRecordSize > 0 && 415 record->ucRecordType > 0 && 416 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 417 switch (record->ucRecordType) { 418 case ATOM_ENCODER_CAP_RECORD_TYPE: 419 cap_record =(ATOM_ENCODER_CAP_RECORD *) 420 record; 421 caps = le16_to_cpu(cap_record->usEncoderCap); 422 break; 423 } 424 record = (ATOM_COMMON_RECORD_HEADER *) 425 ((char *)record + record->ucRecordSize); 426 } 427 amdgpu_display_add_encoder(adev, encoder_obj, 428 le16_to_cpu(path->usDeviceTag), 429 caps); 430 } 431 } 432 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) { 433 for (k = 0; k < router_obj->ucNumberOfObjects; k++) { 434 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID); 435 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) { 436 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 437 (ctx->bios + data_offset + 438 le16_to_cpu(router_obj->asObjects[k].usRecordOffset)); 439 ATOM_I2C_RECORD *i2c_record; 440 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 441 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path; 442 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path; 443 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table = 444 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *) 445 (ctx->bios + data_offset + 446 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset)); 447 u8 *num_dst_objs = (u8 *) 448 ((u8 *)router_src_dst_table + 1 + 449 (router_src_dst_table->ucNumberOfSrc * 2)); 450 u16 *dst_objs = (u16 *)(num_dst_objs + 1); 451 int enum_id; 452 453 router.router_id = router_obj_id; 454 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) { 455 if (le16_to_cpu(path->usConnObjectId) == 456 le16_to_cpu(dst_objs[enum_id])) 457 break; 458 } 459 460 while (record->ucRecordSize > 0 && 461 record->ucRecordType > 0 && 462 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 463 switch (record->ucRecordType) { 464 case ATOM_I2C_RECORD_TYPE: 465 i2c_record = 466 (ATOM_I2C_RECORD *) 467 record; 468 i2c_config = 469 (ATOM_I2C_ID_CONFIG_ACCESS *) 470 &i2c_record->sucI2cId; 471 router.i2c_info = 472 amdgpu_atombios_lookup_i2c_gpio(adev, 473 i2c_config-> 474 ucAccess); 475 router.i2c_addr = i2c_record->ucI2CAddr >> 1; 476 break; 477 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE: 478 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *) 479 record; 480 router.ddc_valid = true; 481 router.ddc_mux_type = ddc_path->ucMuxType; 482 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin; 483 router.ddc_mux_state = ddc_path->ucMuxState[enum_id]; 484 break; 485 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE: 486 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *) 487 record; 488 router.cd_valid = true; 489 router.cd_mux_type = cd_path->ucMuxType; 490 router.cd_mux_control_pin = cd_path->ucMuxControlPin; 491 router.cd_mux_state = cd_path->ucMuxState[enum_id]; 492 break; 493 } 494 record = (ATOM_COMMON_RECORD_HEADER *) 495 ((char *)record + record->ucRecordSize); 496 } 497 } 498 } 499 } 500 } 501 502 /* look up gpio for ddc, hpd */ 503 ddc_bus.valid = false; 504 hpd.hpd = AMDGPU_HPD_NONE; 505 if ((le16_to_cpu(path->usDeviceTag) & 506 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) { 507 for (j = 0; j < con_obj->ucNumberOfObjects; j++) { 508 if (le16_to_cpu(path->usConnObjectId) == 509 le16_to_cpu(con_obj->asObjects[j]. 510 usObjectID)) { 511 ATOM_COMMON_RECORD_HEADER 512 *record = 513 (ATOM_COMMON_RECORD_HEADER 514 *) 515 (ctx->bios + data_offset + 516 le16_to_cpu(con_obj-> 517 asObjects[j]. 518 usRecordOffset)); 519 ATOM_I2C_RECORD *i2c_record; 520 ATOM_HPD_INT_RECORD *hpd_record; 521 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 522 523 while (record->ucRecordSize > 0 && 524 record->ucRecordType > 0 && 525 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 526 switch (record->ucRecordType) { 527 case ATOM_I2C_RECORD_TYPE: 528 i2c_record = 529 (ATOM_I2C_RECORD *) 530 record; 531 i2c_config = 532 (ATOM_I2C_ID_CONFIG_ACCESS *) 533 &i2c_record->sucI2cId; 534 ddc_bus = amdgpu_atombios_lookup_i2c_gpio(adev, 535 i2c_config-> 536 ucAccess); 537 break; 538 case ATOM_HPD_INT_RECORD_TYPE: 539 hpd_record = 540 (ATOM_HPD_INT_RECORD *) 541 record; 542 gpio = amdgpu_atombios_lookup_gpio(adev, 543 hpd_record->ucHPDIntGPIOID); 544 hpd = amdgpu_atombios_get_hpd_info_from_gpio(adev, &gpio); 545 hpd.plugged_state = hpd_record->ucPlugged_PinState; 546 break; 547 } 548 record = 549 (ATOM_COMMON_RECORD_HEADER 550 *) ((char *)record 551 + 552 record-> 553 ucRecordSize); 554 } 555 break; 556 } 557 } 558 } 559 560 /* needed for aux chan transactions */ 561 ddc_bus.hpd = hpd.hpd; 562 563 conn_id = le16_to_cpu(path->usConnObjectId); 564 565 amdgpu_display_add_connector(adev, 566 conn_id, 567 le16_to_cpu(path->usDeviceTag), 568 connector_type, &ddc_bus, 569 connector_object_id, 570 &hpd, 571 &router); 572 573 } 574 } 575 576 amdgpu_link_encoder_connector(adev_to_drm(adev)); 577 578 return true; 579 } 580 581 union firmware_info { 582 ATOM_FIRMWARE_INFO info; 583 ATOM_FIRMWARE_INFO_V1_2 info_12; 584 ATOM_FIRMWARE_INFO_V1_3 info_13; 585 ATOM_FIRMWARE_INFO_V1_4 info_14; 586 ATOM_FIRMWARE_INFO_V2_1 info_21; 587 ATOM_FIRMWARE_INFO_V2_2 info_22; 588 }; 589 590 int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev) 591 { 592 struct amdgpu_mode_info *mode_info = &adev->mode_info; 593 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 594 uint8_t frev, crev; 595 uint16_t data_offset; 596 int ret = -EINVAL; 597 598 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 599 &frev, &crev, &data_offset)) { 600 int i; 601 struct amdgpu_pll *ppll = &adev->clock.ppll[0]; 602 struct amdgpu_pll *spll = &adev->clock.spll; 603 struct amdgpu_pll *mpll = &adev->clock.mpll; 604 union firmware_info *firmware_info = 605 (union firmware_info *)(mode_info->atom_context->bios + 606 data_offset); 607 /* pixel clocks */ 608 ppll->reference_freq = 609 le16_to_cpu(firmware_info->info.usReferenceClock); 610 ppll->reference_div = 0; 611 612 ppll->pll_out_min = 613 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output); 614 ppll->pll_out_max = 615 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); 616 617 ppll->lcd_pll_out_min = 618 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100; 619 if (ppll->lcd_pll_out_min == 0) 620 ppll->lcd_pll_out_min = ppll->pll_out_min; 621 ppll->lcd_pll_out_max = 622 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100; 623 if (ppll->lcd_pll_out_max == 0) 624 ppll->lcd_pll_out_max = ppll->pll_out_max; 625 626 if (ppll->pll_out_min == 0) 627 ppll->pll_out_min = 64800; 628 629 ppll->pll_in_min = 630 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input); 631 ppll->pll_in_max = 632 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input); 633 634 ppll->min_post_div = 2; 635 ppll->max_post_div = 0x7f; 636 ppll->min_frac_feedback_div = 0; 637 ppll->max_frac_feedback_div = 9; 638 ppll->min_ref_div = 2; 639 ppll->max_ref_div = 0x3ff; 640 ppll->min_feedback_div = 4; 641 ppll->max_feedback_div = 0xfff; 642 ppll->best_vco = 0; 643 644 for (i = 1; i < AMDGPU_MAX_PPLL; i++) 645 adev->clock.ppll[i] = *ppll; 646 647 /* system clock */ 648 spll->reference_freq = 649 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock); 650 spll->reference_div = 0; 651 652 spll->pll_out_min = 653 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output); 654 spll->pll_out_max = 655 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output); 656 657 /* ??? */ 658 if (spll->pll_out_min == 0) 659 spll->pll_out_min = 64800; 660 661 spll->pll_in_min = 662 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input); 663 spll->pll_in_max = 664 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); 665 666 spll->min_post_div = 1; 667 spll->max_post_div = 1; 668 spll->min_ref_div = 2; 669 spll->max_ref_div = 0xff; 670 spll->min_feedback_div = 4; 671 spll->max_feedback_div = 0xff; 672 spll->best_vco = 0; 673 674 /* memory clock */ 675 mpll->reference_freq = 676 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock); 677 mpll->reference_div = 0; 678 679 mpll->pll_out_min = 680 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output); 681 mpll->pll_out_max = 682 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output); 683 684 /* ??? */ 685 if (mpll->pll_out_min == 0) 686 mpll->pll_out_min = 64800; 687 688 mpll->pll_in_min = 689 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input); 690 mpll->pll_in_max = 691 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input); 692 693 adev->clock.default_sclk = 694 le32_to_cpu(firmware_info->info.ulDefaultEngineClock); 695 adev->clock.default_mclk = 696 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); 697 698 mpll->min_post_div = 1; 699 mpll->max_post_div = 1; 700 mpll->min_ref_div = 2; 701 mpll->max_ref_div = 0xff; 702 mpll->min_feedback_div = 4; 703 mpll->max_feedback_div = 0xff; 704 mpll->best_vco = 0; 705 706 /* disp clock */ 707 adev->clock.default_dispclk = 708 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); 709 /* set a reasonable default for DP */ 710 if (adev->clock.default_dispclk < 53900) { 711 DRM_DEBUG("Changing default dispclk from %dMhz to 600Mhz\n", 712 adev->clock.default_dispclk / 100); 713 adev->clock.default_dispclk = 60000; 714 } else if (adev->clock.default_dispclk <= 60000) { 715 DRM_DEBUG("Changing default dispclk from %dMhz to 625Mhz\n", 716 adev->clock.default_dispclk / 100); 717 adev->clock.default_dispclk = 62500; 718 } 719 adev->clock.dp_extclk = 720 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); 721 722 adev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock); 723 if (adev->clock.max_pixel_clock == 0) 724 adev->clock.max_pixel_clock = 40000; 725 726 /* not technically a clock, but... */ 727 adev->mode_info.firmware_flags = 728 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess); 729 730 ret = 0; 731 } 732 733 adev->pm.current_sclk = adev->clock.default_sclk; 734 adev->pm.current_mclk = adev->clock.default_mclk; 735 736 return ret; 737 } 738 739 union gfx_info { 740 ATOM_GFX_INFO_V2_1 info; 741 }; 742 743 int amdgpu_atombios_get_gfx_info(struct amdgpu_device *adev) 744 { 745 struct amdgpu_mode_info *mode_info = &adev->mode_info; 746 int index = GetIndexIntoMasterTable(DATA, GFX_Info); 747 uint8_t frev, crev; 748 uint16_t data_offset; 749 int ret = -EINVAL; 750 751 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 752 &frev, &crev, &data_offset)) { 753 union gfx_info *gfx_info = (union gfx_info *) 754 (mode_info->atom_context->bios + data_offset); 755 756 adev->gfx.config.max_shader_engines = gfx_info->info.max_shader_engines; 757 adev->gfx.config.max_tile_pipes = gfx_info->info.max_tile_pipes; 758 adev->gfx.config.max_cu_per_sh = gfx_info->info.max_cu_per_sh; 759 adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se; 760 adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se; 761 adev->gfx.config.max_texture_channel_caches = 762 gfx_info->info.max_texture_channel_caches; 763 764 ret = 0; 765 } 766 return ret; 767 } 768 769 union igp_info { 770 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 771 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; 772 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; 773 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7; 774 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8; 775 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9; 776 }; 777 778 /* 779 * Return vram width from integrated system info table, if available, 780 * or 0 if not. 781 */ 782 int amdgpu_atombios_get_vram_width(struct amdgpu_device *adev) 783 { 784 struct amdgpu_mode_info *mode_info = &adev->mode_info; 785 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 786 u16 data_offset, size; 787 union igp_info *igp_info; 788 u8 frev, crev; 789 790 /* get any igp specific overrides */ 791 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size, 792 &frev, &crev, &data_offset)) { 793 igp_info = (union igp_info *) 794 (mode_info->atom_context->bios + data_offset); 795 switch (crev) { 796 case 8: 797 case 9: 798 return igp_info->info_8.ucUMAChannelNumber * 64; 799 default: 800 return 0; 801 } 802 } 803 804 return 0; 805 } 806 807 static void amdgpu_atombios_get_igp_ss_overrides(struct amdgpu_device *adev, 808 struct amdgpu_atom_ss *ss, 809 int id) 810 { 811 struct amdgpu_mode_info *mode_info = &adev->mode_info; 812 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 813 u16 data_offset, size; 814 union igp_info *igp_info; 815 u8 frev, crev; 816 u16 percentage = 0, rate = 0; 817 818 /* get any igp specific overrides */ 819 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size, 820 &frev, &crev, &data_offset)) { 821 igp_info = (union igp_info *) 822 (mode_info->atom_context->bios + data_offset); 823 switch (crev) { 824 case 6: 825 switch (id) { 826 case ASIC_INTERNAL_SS_ON_TMDS: 827 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage); 828 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz); 829 break; 830 case ASIC_INTERNAL_SS_ON_HDMI: 831 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage); 832 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz); 833 break; 834 case ASIC_INTERNAL_SS_ON_LVDS: 835 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage); 836 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz); 837 break; 838 } 839 break; 840 case 7: 841 switch (id) { 842 case ASIC_INTERNAL_SS_ON_TMDS: 843 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage); 844 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz); 845 break; 846 case ASIC_INTERNAL_SS_ON_HDMI: 847 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage); 848 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz); 849 break; 850 case ASIC_INTERNAL_SS_ON_LVDS: 851 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage); 852 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz); 853 break; 854 } 855 break; 856 case 8: 857 switch (id) { 858 case ASIC_INTERNAL_SS_ON_TMDS: 859 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage); 860 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz); 861 break; 862 case ASIC_INTERNAL_SS_ON_HDMI: 863 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage); 864 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz); 865 break; 866 case ASIC_INTERNAL_SS_ON_LVDS: 867 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage); 868 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz); 869 break; 870 } 871 break; 872 case 9: 873 switch (id) { 874 case ASIC_INTERNAL_SS_ON_TMDS: 875 percentage = le16_to_cpu(igp_info->info_9.usDVISSPercentage); 876 rate = le16_to_cpu(igp_info->info_9.usDVISSpreadRateIn10Hz); 877 break; 878 case ASIC_INTERNAL_SS_ON_HDMI: 879 percentage = le16_to_cpu(igp_info->info_9.usHDMISSPercentage); 880 rate = le16_to_cpu(igp_info->info_9.usHDMISSpreadRateIn10Hz); 881 break; 882 case ASIC_INTERNAL_SS_ON_LVDS: 883 percentage = le16_to_cpu(igp_info->info_9.usLvdsSSPercentage); 884 rate = le16_to_cpu(igp_info->info_9.usLvdsSSpreadRateIn10Hz); 885 break; 886 } 887 break; 888 default: 889 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 890 break; 891 } 892 if (percentage) 893 ss->percentage = percentage; 894 if (rate) 895 ss->rate = rate; 896 } 897 } 898 899 union asic_ss_info { 900 struct _ATOM_ASIC_INTERNAL_SS_INFO info; 901 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2; 902 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3; 903 }; 904 905 union asic_ss_assignment { 906 struct _ATOM_ASIC_SS_ASSIGNMENT v1; 907 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2; 908 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3; 909 }; 910 911 bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev, 912 struct amdgpu_atom_ss *ss, 913 int id, u32 clock) 914 { 915 struct amdgpu_mode_info *mode_info = &adev->mode_info; 916 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 917 uint16_t data_offset, size; 918 union asic_ss_info *ss_info; 919 union asic_ss_assignment *ss_assign; 920 uint8_t frev, crev; 921 int i, num_indices; 922 923 if (id == ASIC_INTERNAL_MEMORY_SS) { 924 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT)) 925 return false; 926 } 927 if (id == ASIC_INTERNAL_ENGINE_SS) { 928 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT)) 929 return false; 930 } 931 932 memset(ss, 0, sizeof(struct amdgpu_atom_ss)); 933 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size, 934 &frev, &crev, &data_offset)) { 935 936 ss_info = 937 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset); 938 939 switch (frev) { 940 case 1: 941 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 942 sizeof(ATOM_ASIC_SS_ASSIGNMENT); 943 944 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]); 945 for (i = 0; i < num_indices; i++) { 946 if ((ss_assign->v1.ucClockIndication == id) && 947 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) { 948 ss->percentage = 949 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage); 950 ss->type = ss_assign->v1.ucSpreadSpectrumMode; 951 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz); 952 ss->percentage_divider = 100; 953 return true; 954 } 955 ss_assign = (union asic_ss_assignment *) 956 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT)); 957 } 958 break; 959 case 2: 960 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 961 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2); 962 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]); 963 for (i = 0; i < num_indices; i++) { 964 if ((ss_assign->v2.ucClockIndication == id) && 965 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) { 966 ss->percentage = 967 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage); 968 ss->type = ss_assign->v2.ucSpreadSpectrumMode; 969 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz); 970 ss->percentage_divider = 100; 971 if ((crev == 2) && 972 ((id == ASIC_INTERNAL_ENGINE_SS) || 973 (id == ASIC_INTERNAL_MEMORY_SS))) 974 ss->rate /= 100; 975 return true; 976 } 977 ss_assign = (union asic_ss_assignment *) 978 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2)); 979 } 980 break; 981 case 3: 982 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 983 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3); 984 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]); 985 for (i = 0; i < num_indices; i++) { 986 if ((ss_assign->v3.ucClockIndication == id) && 987 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) { 988 ss->percentage = 989 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage); 990 ss->type = ss_assign->v3.ucSpreadSpectrumMode; 991 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz); 992 if (ss_assign->v3.ucSpreadSpectrumMode & 993 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK) 994 ss->percentage_divider = 1000; 995 else 996 ss->percentage_divider = 100; 997 if ((id == ASIC_INTERNAL_ENGINE_SS) || 998 (id == ASIC_INTERNAL_MEMORY_SS)) 999 ss->rate /= 100; 1000 if (adev->flags & AMD_IS_APU) 1001 amdgpu_atombios_get_igp_ss_overrides(adev, ss, id); 1002 return true; 1003 } 1004 ss_assign = (union asic_ss_assignment *) 1005 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3)); 1006 } 1007 break; 1008 default: 1009 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev); 1010 break; 1011 } 1012 1013 } 1014 return false; 1015 } 1016 1017 union get_clock_dividers { 1018 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1; 1019 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2; 1020 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3; 1021 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4; 1022 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5; 1023 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in; 1024 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out; 1025 }; 1026 1027 int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev, 1028 u8 clock_type, 1029 u32 clock, 1030 bool strobe_mode, 1031 struct atom_clock_dividers *dividers) 1032 { 1033 union get_clock_dividers args; 1034 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL); 1035 u8 frev, crev; 1036 1037 memset(&args, 0, sizeof(args)); 1038 memset(dividers, 0, sizeof(struct atom_clock_dividers)); 1039 1040 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) 1041 return -EINVAL; 1042 1043 switch (crev) { 1044 case 2: 1045 case 3: 1046 case 5: 1047 /* r6xx, r7xx, evergreen, ni, si. 1048 * TODO: add support for asic_type <= CHIP_RV770*/ 1049 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) { 1050 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock); 1051 1052 if (amdgpu_atom_execute_table(adev->mode_info.atom_context, 1053 index, (uint32_t *)&args, sizeof(args))) 1054 return -EINVAL; 1055 1056 dividers->post_div = args.v3.ucPostDiv; 1057 dividers->enable_post_div = (args.v3.ucCntlFlag & 1058 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; 1059 dividers->enable_dithen = (args.v3.ucCntlFlag & 1060 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; 1061 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv); 1062 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac); 1063 dividers->ref_div = args.v3.ucRefDiv; 1064 dividers->vco_mode = (args.v3.ucCntlFlag & 1065 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; 1066 } else { 1067 /* for SI we use ComputeMemoryClockParam for memory plls */ 1068 if (adev->asic_type >= CHIP_TAHITI) 1069 return -EINVAL; 1070 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock); 1071 if (strobe_mode) 1072 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN; 1073 1074 if (amdgpu_atom_execute_table(adev->mode_info.atom_context, 1075 index, (uint32_t *)&args, sizeof(args))) 1076 return -EINVAL; 1077 1078 dividers->post_div = args.v5.ucPostDiv; 1079 dividers->enable_post_div = (args.v5.ucCntlFlag & 1080 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; 1081 dividers->enable_dithen = (args.v5.ucCntlFlag & 1082 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; 1083 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv); 1084 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac); 1085 dividers->ref_div = args.v5.ucRefDiv; 1086 dividers->vco_mode = (args.v5.ucCntlFlag & 1087 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; 1088 } 1089 break; 1090 case 4: 1091 /* fusion */ 1092 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */ 1093 1094 if (amdgpu_atom_execute_table(adev->mode_info.atom_context, 1095 index, (uint32_t *)&args, sizeof(args))) 1096 return -EINVAL; 1097 1098 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; 1099 dividers->real_clock = le32_to_cpu(args.v4.ulClock); 1100 break; 1101 case 6: 1102 /* CI */ 1103 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */ 1104 args.v6_in.ulClock.ulComputeClockFlag = clock_type; 1105 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */ 1106 1107 if (amdgpu_atom_execute_table(adev->mode_info.atom_context, 1108 index, (uint32_t *)&args, sizeof(args))) 1109 return -EINVAL; 1110 1111 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv); 1112 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac); 1113 dividers->ref_div = args.v6_out.ucPllRefDiv; 1114 dividers->post_div = args.v6_out.ucPllPostDiv; 1115 dividers->flags = args.v6_out.ucPllCntlFlag; 1116 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock); 1117 dividers->post_divider = args.v6_out.ulClock.ucPostDiv; 1118 break; 1119 default: 1120 return -EINVAL; 1121 } 1122 return 0; 1123 } 1124 1125 #ifdef CONFIG_DRM_AMDGPU_SI 1126 int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev, 1127 u32 clock, 1128 bool strobe_mode, 1129 struct atom_mpll_param *mpll_param) 1130 { 1131 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args; 1132 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam); 1133 u8 frev, crev; 1134 1135 memset(&args, 0, sizeof(args)); 1136 memset(mpll_param, 0, sizeof(struct atom_mpll_param)); 1137 1138 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) 1139 return -EINVAL; 1140 1141 switch (frev) { 1142 case 2: 1143 switch (crev) { 1144 case 1: 1145 /* SI */ 1146 args.ulClock = cpu_to_le32(clock); /* 10 khz */ 1147 args.ucInputFlag = 0; 1148 if (strobe_mode) 1149 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN; 1150 1151 if (amdgpu_atom_execute_table(adev->mode_info.atom_context, 1152 index, (uint32_t *)&args, sizeof(args))) 1153 return -EINVAL; 1154 1155 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac); 1156 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv); 1157 mpll_param->post_div = args.ucPostDiv; 1158 mpll_param->dll_speed = args.ucDllSpeed; 1159 mpll_param->bwcntl = args.ucBWCntl; 1160 mpll_param->vco_mode = 1161 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK); 1162 mpll_param->yclk_sel = 1163 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0; 1164 mpll_param->qdr = 1165 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0; 1166 mpll_param->half_rate = 1167 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0; 1168 break; 1169 default: 1170 return -EINVAL; 1171 } 1172 break; 1173 default: 1174 return -EINVAL; 1175 } 1176 return 0; 1177 } 1178 1179 int amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev, 1180 u32 eng_clock, u32 mem_clock) 1181 { 1182 SET_ENGINE_CLOCK_PS_ALLOCATION args; 1183 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 1184 u32 tmp; 1185 1186 memset(&args, 0, sizeof(args)); 1187 1188 tmp = eng_clock & SET_CLOCK_FREQ_MASK; 1189 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24); 1190 1191 args.ulTargetEngineClock = cpu_to_le32(tmp); 1192 if (mem_clock) 1193 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK); 1194 1195 return amdgpu_atom_execute_table(adev->mode_info.atom_context, index, 1196 (uint32_t *)&args, sizeof(args)); 1197 } 1198 1199 void amdgpu_atombios_get_default_voltages(struct amdgpu_device *adev, 1200 u16 *vddc, u16 *vddci, u16 *mvdd) 1201 { 1202 struct amdgpu_mode_info *mode_info = &adev->mode_info; 1203 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 1204 u8 frev, crev; 1205 u16 data_offset; 1206 union firmware_info *firmware_info; 1207 1208 *vddc = 0; 1209 *vddci = 0; 1210 *mvdd = 0; 1211 1212 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 1213 &frev, &crev, &data_offset)) { 1214 firmware_info = 1215 (union firmware_info *)(mode_info->atom_context->bios + 1216 data_offset); 1217 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage); 1218 if ((frev == 2) && (crev >= 2)) { 1219 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage); 1220 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage); 1221 } 1222 } 1223 } 1224 1225 union set_voltage { 1226 struct _SET_VOLTAGE_PS_ALLOCATION alloc; 1227 struct _SET_VOLTAGE_PARAMETERS v1; 1228 struct _SET_VOLTAGE_PARAMETERS_V2 v2; 1229 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3; 1230 }; 1231 1232 int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type, 1233 u16 voltage_id, u16 *voltage) 1234 { 1235 union set_voltage args; 1236 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 1237 u8 frev, crev; 1238 1239 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) 1240 return -EINVAL; 1241 1242 switch (crev) { 1243 case 1: 1244 return -EINVAL; 1245 case 2: 1246 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE; 1247 args.v2.ucVoltageMode = 0; 1248 args.v2.usVoltageLevel = 0; 1249 1250 if (amdgpu_atom_execute_table(adev->mode_info.atom_context, 1251 index, (uint32_t *)&args, sizeof(args))) 1252 return -EINVAL; 1253 1254 *voltage = le16_to_cpu(args.v2.usVoltageLevel); 1255 break; 1256 case 3: 1257 args.v3.ucVoltageType = voltage_type; 1258 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL; 1259 args.v3.usVoltageLevel = cpu_to_le16(voltage_id); 1260 1261 if (amdgpu_atom_execute_table(adev->mode_info.atom_context, 1262 index, (uint32_t *)&args, sizeof(args))) 1263 return -EINVAL; 1264 1265 *voltage = le16_to_cpu(args.v3.usVoltageLevel); 1266 break; 1267 default: 1268 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1269 return -EINVAL; 1270 } 1271 1272 return 0; 1273 } 1274 1275 int amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(struct amdgpu_device *adev, 1276 u16 *voltage, 1277 u16 leakage_idx) 1278 { 1279 return amdgpu_atombios_get_max_vddc(adev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage); 1280 } 1281 1282 union voltage_object_info { 1283 struct _ATOM_VOLTAGE_OBJECT_INFO v1; 1284 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2; 1285 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3; 1286 }; 1287 1288 union voltage_object { 1289 struct _ATOM_VOLTAGE_OBJECT v1; 1290 struct _ATOM_VOLTAGE_OBJECT_V2 v2; 1291 union _ATOM_VOLTAGE_OBJECT_V3 v3; 1292 }; 1293 1294 1295 static ATOM_VOLTAGE_OBJECT_V3 *amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3, 1296 u8 voltage_type, u8 voltage_mode) 1297 { 1298 u32 size = le16_to_cpu(v3->sHeader.usStructureSize); 1299 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]); 1300 u8 *start = (u8 *)v3; 1301 1302 while (offset < size) { 1303 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset); 1304 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) && 1305 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode)) 1306 return vo; 1307 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize); 1308 } 1309 return NULL; 1310 } 1311 1312 int amdgpu_atombios_get_svi2_info(struct amdgpu_device *adev, 1313 u8 voltage_type, 1314 u8 *svd_gpio_id, u8 *svc_gpio_id) 1315 { 1316 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 1317 u8 frev, crev; 1318 u16 data_offset, size; 1319 union voltage_object_info *voltage_info; 1320 union voltage_object *voltage_object = NULL; 1321 1322 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, 1323 &frev, &crev, &data_offset)) { 1324 voltage_info = (union voltage_object_info *) 1325 (adev->mode_info.atom_context->bios + data_offset); 1326 1327 switch (frev) { 1328 case 3: 1329 switch (crev) { 1330 case 1: 1331 voltage_object = (union voltage_object *) 1332 amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3, 1333 voltage_type, 1334 VOLTAGE_OBJ_SVID2); 1335 if (voltage_object) { 1336 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId; 1337 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId; 1338 } else { 1339 return -EINVAL; 1340 } 1341 break; 1342 default: 1343 DRM_ERROR("unknown voltage object table\n"); 1344 return -EINVAL; 1345 } 1346 break; 1347 default: 1348 DRM_ERROR("unknown voltage object table\n"); 1349 return -EINVAL; 1350 } 1351 1352 } 1353 return 0; 1354 } 1355 1356 bool 1357 amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev, 1358 u8 voltage_type, u8 voltage_mode) 1359 { 1360 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 1361 u8 frev, crev; 1362 u16 data_offset, size; 1363 union voltage_object_info *voltage_info; 1364 1365 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, 1366 &frev, &crev, &data_offset)) { 1367 voltage_info = (union voltage_object_info *) 1368 (adev->mode_info.atom_context->bios + data_offset); 1369 1370 switch (frev) { 1371 case 3: 1372 switch (crev) { 1373 case 1: 1374 if (amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3, 1375 voltage_type, voltage_mode)) 1376 return true; 1377 break; 1378 default: 1379 DRM_ERROR("unknown voltage object table\n"); 1380 return false; 1381 } 1382 break; 1383 default: 1384 DRM_ERROR("unknown voltage object table\n"); 1385 return false; 1386 } 1387 1388 } 1389 return false; 1390 } 1391 1392 int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev, 1393 u8 voltage_type, u8 voltage_mode, 1394 struct atom_voltage_table *voltage_table) 1395 { 1396 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 1397 u8 frev, crev; 1398 u16 data_offset, size; 1399 int i; 1400 union voltage_object_info *voltage_info; 1401 union voltage_object *voltage_object = NULL; 1402 1403 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, 1404 &frev, &crev, &data_offset)) { 1405 voltage_info = (union voltage_object_info *) 1406 (adev->mode_info.atom_context->bios + data_offset); 1407 1408 switch (frev) { 1409 case 3: 1410 switch (crev) { 1411 case 1: 1412 voltage_object = (union voltage_object *) 1413 amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3, 1414 voltage_type, voltage_mode); 1415 if (voltage_object) { 1416 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio = 1417 &voltage_object->v3.asGpioVoltageObj; 1418 VOLTAGE_LUT_ENTRY_V2 *lut; 1419 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES) 1420 return -EINVAL; 1421 lut = &gpio->asVolGpioLut[0]; 1422 for (i = 0; i < gpio->ucGpioEntryNum; i++) { 1423 voltage_table->entries[i].value = 1424 le16_to_cpu(lut->usVoltageValue); 1425 voltage_table->entries[i].smio_low = 1426 le32_to_cpu(lut->ulVoltageId); 1427 lut = (VOLTAGE_LUT_ENTRY_V2 *) 1428 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2)); 1429 } 1430 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal); 1431 voltage_table->count = gpio->ucGpioEntryNum; 1432 voltage_table->phase_delay = gpio->ucPhaseDelay; 1433 return 0; 1434 } 1435 break; 1436 default: 1437 DRM_ERROR("unknown voltage object table\n"); 1438 return -EINVAL; 1439 } 1440 break; 1441 default: 1442 DRM_ERROR("unknown voltage object table\n"); 1443 return -EINVAL; 1444 } 1445 } 1446 return -EINVAL; 1447 } 1448 1449 union vram_info { 1450 struct _ATOM_VRAM_INFO_V3 v1_3; 1451 struct _ATOM_VRAM_INFO_V4 v1_4; 1452 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1; 1453 }; 1454 1455 #define MEM_ID_MASK 0xff000000 1456 #define MEM_ID_SHIFT 24 1457 #define CLOCK_RANGE_MASK 0x00ffffff 1458 #define CLOCK_RANGE_SHIFT 0 1459 #define LOW_NIBBLE_MASK 0xf 1460 #define DATA_EQU_PREV 0 1461 #define DATA_FROM_TABLE 4 1462 1463 int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev, 1464 u8 module_index, 1465 struct atom_mc_reg_table *reg_table) 1466 { 1467 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 1468 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0; 1469 u32 i = 0, j; 1470 u16 data_offset, size; 1471 union vram_info *vram_info; 1472 1473 memset(reg_table, 0, sizeof(struct atom_mc_reg_table)); 1474 1475 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, 1476 &frev, &crev, &data_offset)) { 1477 vram_info = (union vram_info *) 1478 (adev->mode_info.atom_context->bios + data_offset); 1479 switch (frev) { 1480 case 1: 1481 DRM_ERROR("old table version %d, %d\n", frev, crev); 1482 return -EINVAL; 1483 case 2: 1484 switch (crev) { 1485 case 1: 1486 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { 1487 ATOM_INIT_REG_BLOCK *reg_block = 1488 (ATOM_INIT_REG_BLOCK *) 1489 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset)); 1490 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = 1491 (ATOM_MEMORY_SETTING_DATA_BLOCK *) 1492 ((u8 *)reg_block + (2 * sizeof(u16)) + 1493 le16_to_cpu(reg_block->usRegIndexTblSize)); 1494 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0]; 1495 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) / 1496 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1; 1497 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE) 1498 return -EINVAL; 1499 while (i < num_entries) { 1500 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER) 1501 break; 1502 reg_table->mc_reg_address[i].s1 = 1503 (u16)(le16_to_cpu(format->usRegIndex)); 1504 reg_table->mc_reg_address[i].pre_reg_data = 1505 (u8)(format->ucPreRegDataLength); 1506 i++; 1507 format = (ATOM_INIT_REG_INDEX_FORMAT *) 1508 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT)); 1509 } 1510 reg_table->last = i; 1511 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) && 1512 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) { 1513 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK) 1514 >> MEM_ID_SHIFT); 1515 if (module_index == t_mem_id) { 1516 reg_table->mc_reg_table_entry[num_ranges].mclk_max = 1517 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK) 1518 >> CLOCK_RANGE_SHIFT); 1519 for (i = 0, j = 1; i < reg_table->last; i++) { 1520 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) { 1521 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = 1522 (u32)le32_to_cpu(*((u32 *)reg_data + j)); 1523 j++; 1524 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) { 1525 if (i == 0) 1526 continue; 1527 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = 1528 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1]; 1529 } 1530 } 1531 num_ranges++; 1532 } 1533 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) 1534 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); 1535 } 1536 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) 1537 return -EINVAL; 1538 reg_table->num_entries = num_ranges; 1539 } else 1540 return -EINVAL; 1541 break; 1542 default: 1543 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1544 return -EINVAL; 1545 } 1546 break; 1547 default: 1548 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1549 return -EINVAL; 1550 } 1551 return 0; 1552 } 1553 return -EINVAL; 1554 } 1555 #endif 1556 1557 bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev) 1558 { 1559 int index = GetIndexIntoMasterTable(DATA, GPUVirtualizationInfo); 1560 u8 frev, crev; 1561 u16 data_offset, size; 1562 1563 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, 1564 &frev, &crev, &data_offset)) 1565 return true; 1566 1567 return false; 1568 } 1569 1570 void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock) 1571 { 1572 uint32_t bios_6_scratch; 1573 1574 bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6); 1575 1576 if (lock) { 1577 bios_6_scratch |= ATOM_S6_CRITICAL_STATE; 1578 bios_6_scratch &= ~ATOM_S6_ACC_MODE; 1579 } else { 1580 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE; 1581 bios_6_scratch |= ATOM_S6_ACC_MODE; 1582 } 1583 1584 WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch); 1585 } 1586 1587 static void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev) 1588 { 1589 uint32_t bios_2_scratch, bios_6_scratch; 1590 1591 adev->bios_scratch_reg_offset = mmBIOS_SCRATCH_0; 1592 1593 bios_2_scratch = RREG32(adev->bios_scratch_reg_offset + 2); 1594 bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6); 1595 1596 /* let the bios control the backlight */ 1597 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; 1598 1599 /* tell the bios not to handle mode switching */ 1600 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH; 1601 1602 /* clear the vbios dpms state */ 1603 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE; 1604 1605 WREG32(adev->bios_scratch_reg_offset + 2, bios_2_scratch); 1606 WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch); 1607 } 1608 1609 void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev, 1610 bool hung) 1611 { 1612 u32 tmp = RREG32(adev->bios_scratch_reg_offset + 3); 1613 1614 if (hung) 1615 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1616 else 1617 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1618 1619 WREG32(adev->bios_scratch_reg_offset + 3, tmp); 1620 } 1621 1622 void amdgpu_atombios_scratch_regs_set_backlight_level(struct amdgpu_device *adev, 1623 u32 backlight_level) 1624 { 1625 u32 tmp = RREG32(adev->bios_scratch_reg_offset + 2); 1626 1627 tmp &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK; 1628 tmp |= (backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) & 1629 ATOM_S2_CURRENT_BL_LEVEL_MASK; 1630 1631 WREG32(adev->bios_scratch_reg_offset + 2, tmp); 1632 } 1633 1634 bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev) 1635 { 1636 u32 tmp = RREG32(adev->bios_scratch_reg_offset + 7); 1637 1638 if (tmp & ATOM_S7_ASIC_INIT_COMPLETE_MASK) 1639 return false; 1640 else 1641 return true; 1642 } 1643 1644 /* Atom needs data in little endian format so swap as appropriate when copying 1645 * data to or from atom. Note that atom operates on dw units. 1646 * 1647 * Use to_le=true when sending data to atom and provide at least 1648 * ALIGN(num_bytes,4) bytes in the dst buffer. 1649 * 1650 * Use to_le=false when receiving data from atom and provide ALIGN(num_bytes,4) 1651 * byes in the src buffer. 1652 */ 1653 void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le) 1654 { 1655 #ifdef __BIG_ENDIAN 1656 u32 src_tmp[5], dst_tmp[5]; 1657 int i; 1658 u8 align_num_bytes = ALIGN(num_bytes, 4); 1659 1660 if (to_le) { 1661 memcpy(src_tmp, src, num_bytes); 1662 for (i = 0; i < align_num_bytes / 4; i++) 1663 dst_tmp[i] = cpu_to_le32(src_tmp[i]); 1664 memcpy(dst, dst_tmp, align_num_bytes); 1665 } else { 1666 memcpy(src_tmp, src, align_num_bytes); 1667 for (i = 0; i < align_num_bytes / 4; i++) 1668 dst_tmp[i] = le32_to_cpu(src_tmp[i]); 1669 memcpy(dst, dst_tmp, num_bytes); 1670 } 1671 #else 1672 memcpy(dst, src, num_bytes); 1673 #endif 1674 } 1675 1676 static int amdgpu_atombios_allocate_fb_scratch(struct amdgpu_device *adev) 1677 { 1678 struct atom_context *ctx = adev->mode_info.atom_context; 1679 int index = GetIndexIntoMasterTable(DATA, VRAM_UsageByFirmware); 1680 uint16_t data_offset; 1681 int usage_bytes = 0; 1682 struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage; 1683 u64 start_addr; 1684 u64 size; 1685 1686 if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { 1687 firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset); 1688 1689 DRM_DEBUG("atom firmware requested %08x %dkb\n", 1690 le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware), 1691 le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb)); 1692 1693 start_addr = firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware; 1694 size = firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb; 1695 1696 if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) == 1697 (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION << 1698 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) { 1699 /* Firmware request VRAM reservation for SR-IOV */ 1700 amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW_VRAM_USAGE, 1701 (start_addr & (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10, 1702 size << 10, true); 1703 /* Use the default scratch size */ 1704 usage_bytes = 0; 1705 } else { 1706 usage_bytes = le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024; 1707 } 1708 } 1709 ctx->scratch_size_bytes = 0; 1710 if (usage_bytes == 0) 1711 usage_bytes = 20 * 1024; 1712 /* allocate some scratch memory */ 1713 ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL); 1714 if (!ctx->scratch) 1715 return -ENOMEM; 1716 ctx->scratch_size_bytes = usage_bytes; 1717 return 0; 1718 } 1719 1720 /* ATOM accessor methods */ 1721 /* 1722 * ATOM is an interpreted byte code stored in tables in the vbios. The 1723 * driver registers callbacks to access registers and the interpreter 1724 * in the driver parses the tables and executes then to program specific 1725 * actions (set display modes, asic init, etc.). See amdgpu_atombios.c, 1726 * atombios.h, and atom.c 1727 */ 1728 1729 /** 1730 * cail_pll_read - read PLL register 1731 * 1732 * @info: atom card_info pointer 1733 * @reg: PLL register offset 1734 * 1735 * Provides a PLL register accessor for the atom interpreter (r4xx+). 1736 * Returns the value of the PLL register. 1737 */ 1738 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) 1739 { 1740 return 0; 1741 } 1742 1743 /** 1744 * cail_pll_write - write PLL register 1745 * 1746 * @info: atom card_info pointer 1747 * @reg: PLL register offset 1748 * @val: value to write to the pll register 1749 * 1750 * Provides a PLL register accessor for the atom interpreter (r4xx+). 1751 */ 1752 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) 1753 { 1754 1755 } 1756 1757 /** 1758 * cail_mc_read - read MC (Memory Controller) register 1759 * 1760 * @info: atom card_info pointer 1761 * @reg: MC register offset 1762 * 1763 * Provides an MC register accessor for the atom interpreter (r4xx+). 1764 * Returns the value of the MC register. 1765 */ 1766 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) 1767 { 1768 return 0; 1769 } 1770 1771 /** 1772 * cail_mc_write - write MC (Memory Controller) register 1773 * 1774 * @info: atom card_info pointer 1775 * @reg: MC register offset 1776 * @val: value to write to the pll register 1777 * 1778 * Provides a MC register accessor for the atom interpreter (r4xx+). 1779 */ 1780 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) 1781 { 1782 1783 } 1784 1785 /** 1786 * cail_reg_write - write MMIO register 1787 * 1788 * @info: atom card_info pointer 1789 * @reg: MMIO register offset 1790 * @val: value to write to the pll register 1791 * 1792 * Provides a MMIO register accessor for the atom interpreter (r4xx+). 1793 */ 1794 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) 1795 { 1796 struct amdgpu_device *adev = drm_to_adev(info->dev); 1797 1798 WREG32(reg, val); 1799 } 1800 1801 /** 1802 * cail_reg_read - read MMIO register 1803 * 1804 * @info: atom card_info pointer 1805 * @reg: MMIO register offset 1806 * 1807 * Provides an MMIO register accessor for the atom interpreter (r4xx+). 1808 * Returns the value of the MMIO register. 1809 */ 1810 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) 1811 { 1812 struct amdgpu_device *adev = drm_to_adev(info->dev); 1813 uint32_t r; 1814 1815 r = RREG32(reg); 1816 return r; 1817 } 1818 1819 static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev, 1820 struct device_attribute *attr, 1821 char *buf) 1822 { 1823 struct drm_device *ddev = dev_get_drvdata(dev); 1824 struct amdgpu_device *adev = drm_to_adev(ddev); 1825 struct atom_context *ctx = adev->mode_info.atom_context; 1826 1827 return sysfs_emit(buf, "%s\n", ctx->vbios_pn); 1828 } 1829 1830 static ssize_t amdgpu_atombios_get_vbios_build(struct device *dev, 1831 struct device_attribute *attr, 1832 char *buf) 1833 { 1834 struct drm_device *ddev = dev_get_drvdata(dev); 1835 struct amdgpu_device *adev = drm_to_adev(ddev); 1836 struct atom_context *ctx = adev->mode_info.atom_context; 1837 1838 return sysfs_emit(buf, "%s\n", ctx->build_num); 1839 } 1840 1841 static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version, 1842 NULL); 1843 static DEVICE_ATTR(vbios_build, 0444, amdgpu_atombios_get_vbios_build, NULL); 1844 1845 static struct attribute *amdgpu_vbios_version_attrs[] = { 1846 &dev_attr_vbios_version.attr, &dev_attr_vbios_build.attr, NULL 1847 }; 1848 1849 static umode_t amdgpu_vbios_version_attrs_is_visible(struct kobject *kobj, 1850 struct attribute *attr, 1851 int index) 1852 { 1853 struct device *dev = kobj_to_dev(kobj); 1854 struct drm_device *ddev = dev_get_drvdata(dev); 1855 struct amdgpu_device *adev = drm_to_adev(ddev); 1856 struct atom_context *ctx = adev->mode_info.atom_context; 1857 1858 if (attr == &dev_attr_vbios_build.attr && !strlen(ctx->build_num)) 1859 return 0; 1860 1861 return attr->mode; 1862 } 1863 1864 const struct attribute_group amdgpu_vbios_version_attr_group = { 1865 .attrs = amdgpu_vbios_version_attrs, 1866 .is_visible = amdgpu_vbios_version_attrs_is_visible, 1867 }; 1868 1869 int amdgpu_atombios_sysfs_init(struct amdgpu_device *adev) 1870 { 1871 if (adev->mode_info.atom_context) 1872 return devm_device_add_group(adev->dev, 1873 &amdgpu_vbios_version_attr_group); 1874 1875 return 0; 1876 } 1877 1878 /** 1879 * amdgpu_atombios_fini - free the driver info and callbacks for atombios 1880 * 1881 * @adev: amdgpu_device pointer 1882 * 1883 * Frees the driver info and register access callbacks for the ATOM 1884 * interpreter (r4xx+). 1885 * Called at driver shutdown. 1886 */ 1887 void amdgpu_atombios_fini(struct amdgpu_device *adev) 1888 { 1889 if (adev->mode_info.atom_context) { 1890 kfree(adev->mode_info.atom_context->scratch); 1891 kfree(adev->mode_info.atom_context->iio); 1892 } 1893 kfree(adev->mode_info.atom_context); 1894 adev->mode_info.atom_context = NULL; 1895 kfree(adev->mode_info.atom_card_info); 1896 adev->mode_info.atom_card_info = NULL; 1897 } 1898 1899 /** 1900 * amdgpu_atombios_init - init the driver info and callbacks for atombios 1901 * 1902 * @adev: amdgpu_device pointer 1903 * 1904 * Initializes the driver info and register access callbacks for the 1905 * ATOM interpreter (r4xx+). 1906 * Returns 0 on sucess, -ENOMEM on failure. 1907 * Called at driver startup. 1908 */ 1909 int amdgpu_atombios_init(struct amdgpu_device *adev) 1910 { 1911 struct card_info *atom_card_info = 1912 kzalloc_obj(struct card_info); 1913 1914 if (!atom_card_info) 1915 return -ENOMEM; 1916 1917 adev->mode_info.atom_card_info = atom_card_info; 1918 atom_card_info->dev = adev_to_drm(adev); 1919 atom_card_info->reg_read = cail_reg_read; 1920 atom_card_info->reg_write = cail_reg_write; 1921 atom_card_info->mc_read = cail_mc_read; 1922 atom_card_info->mc_write = cail_mc_write; 1923 atom_card_info->pll_read = cail_pll_read; 1924 atom_card_info->pll_write = cail_pll_write; 1925 1926 adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios); 1927 if (!adev->mode_info.atom_context) { 1928 amdgpu_atombios_fini(adev); 1929 return -ENOMEM; 1930 } 1931 1932 mutex_init(&adev->mode_info.atom_context->mutex); 1933 if (adev->is_atom_fw) { 1934 amdgpu_atomfirmware_scratch_regs_init(adev); 1935 amdgpu_atomfirmware_allocate_fb_scratch(adev); 1936 /* cached firmware_flags for further usage */ 1937 adev->mode_info.firmware_flags = 1938 amdgpu_atomfirmware_query_firmware_capability(adev); 1939 } else { 1940 amdgpu_atombios_scratch_regs_init(adev); 1941 amdgpu_atombios_allocate_fb_scratch(adev); 1942 } 1943 1944 return 0; 1945 } 1946 1947 int amdgpu_atombios_get_data_table(struct amdgpu_device *adev, 1948 uint32_t table, 1949 uint16_t *size, 1950 uint8_t *frev, 1951 uint8_t *crev, 1952 uint8_t **addr) 1953 { 1954 uint16_t data_start; 1955 1956 if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, table, 1957 size, frev, crev, &data_start)) 1958 return -EINVAL; 1959 1960 *addr = (uint8_t *)adev->mode_info.atom_context->bios + data_start; 1961 1962 return 0; 1963 } 1964