xref: /linux/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c (revision fd7d598270724cc787982ea48bbe17ad383a8b7f)
1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright 2014-2018 Advanced Micro Devices, Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  */
23 #include <linux/dma-buf.h>
24 #include <linux/list.h>
25 #include <linux/pagemap.h>
26 #include <linux/sched/mm.h>
27 #include <linux/sched/task.h>
28 #include <drm/ttm/ttm_tt.h>
29 
30 #include <drm/drm_exec.h>
31 
32 #include "amdgpu_object.h"
33 #include "amdgpu_gem.h"
34 #include "amdgpu_vm.h"
35 #include "amdgpu_hmm.h"
36 #include "amdgpu_amdkfd.h"
37 #include "amdgpu_dma_buf.h"
38 #include <uapi/linux/kfd_ioctl.h>
39 #include "amdgpu_xgmi.h"
40 #include "kfd_priv.h"
41 #include "kfd_smi_events.h"
42 
43 /* Userptr restore delay, just long enough to allow consecutive VM
44  * changes to accumulate
45  */
46 #define AMDGPU_USERPTR_RESTORE_DELAY_MS 1
47 #define AMDGPU_RESERVE_MEM_LIMIT			(3UL << 29)
48 
49 /*
50  * Align VRAM availability to 2MB to avoid fragmentation caused by 4K allocations in the tail 2MB
51  * BO chunk
52  */
53 #define VRAM_AVAILABLITY_ALIGN (1 << 21)
54 
55 /* Impose limit on how much memory KFD can use */
56 static struct {
57 	uint64_t max_system_mem_limit;
58 	uint64_t max_ttm_mem_limit;
59 	int64_t system_mem_used;
60 	int64_t ttm_mem_used;
61 	spinlock_t mem_limit_lock;
62 } kfd_mem_limit;
63 
64 static const char * const domain_bit_to_string[] = {
65 		"CPU",
66 		"GTT",
67 		"VRAM",
68 		"GDS",
69 		"GWS",
70 		"OA"
71 };
72 
73 #define domain_string(domain) domain_bit_to_string[ffs(domain)-1]
74 
75 static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work);
76 
77 static bool kfd_mem_is_attached(struct amdgpu_vm *avm,
78 		struct kgd_mem *mem)
79 {
80 	struct kfd_mem_attachment *entry;
81 
82 	list_for_each_entry(entry, &mem->attachments, list)
83 		if (entry->bo_va->base.vm == avm)
84 			return true;
85 
86 	return false;
87 }
88 
89 /**
90  * reuse_dmamap() - Check whether adev can share the original
91  * userptr BO
92  *
93  * If both adev and bo_adev are in direct mapping or
94  * in the same iommu group, they can share the original BO.
95  *
96  * @adev: Device to which can or cannot share the original BO
97  * @bo_adev: Device to which allocated BO belongs to
98  *
99  * Return: returns true if adev can share original userptr BO,
100  * false otherwise.
101  */
102 static bool reuse_dmamap(struct amdgpu_device *adev, struct amdgpu_device *bo_adev)
103 {
104 	return (adev->ram_is_direct_mapped && bo_adev->ram_is_direct_mapped) ||
105 			(adev->dev->iommu_group == bo_adev->dev->iommu_group);
106 }
107 
108 /* Set memory usage limits. Current, limits are
109  *  System (TTM + userptr) memory - 15/16th System RAM
110  *  TTM memory - 3/8th System RAM
111  */
112 void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
113 {
114 	struct sysinfo si;
115 	uint64_t mem;
116 
117 	if (kfd_mem_limit.max_system_mem_limit)
118 		return;
119 
120 	si_meminfo(&si);
121 	mem = si.totalram - si.totalhigh;
122 	mem *= si.mem_unit;
123 
124 	spin_lock_init(&kfd_mem_limit.mem_limit_lock);
125 	kfd_mem_limit.max_system_mem_limit = mem - (mem >> 6);
126 	if (kfd_mem_limit.max_system_mem_limit < 2 * AMDGPU_RESERVE_MEM_LIMIT)
127 		kfd_mem_limit.max_system_mem_limit >>= 1;
128 	else
129 		kfd_mem_limit.max_system_mem_limit -= AMDGPU_RESERVE_MEM_LIMIT;
130 
131 	kfd_mem_limit.max_ttm_mem_limit = ttm_tt_pages_limit() << PAGE_SHIFT;
132 	pr_debug("Kernel memory limit %lluM, TTM limit %lluM\n",
133 		(kfd_mem_limit.max_system_mem_limit >> 20),
134 		(kfd_mem_limit.max_ttm_mem_limit >> 20));
135 }
136 
137 void amdgpu_amdkfd_reserve_system_mem(uint64_t size)
138 {
139 	kfd_mem_limit.system_mem_used += size;
140 }
141 
142 /* Estimate page table size needed to represent a given memory size
143  *
144  * With 4KB pages, we need one 8 byte PTE for each 4KB of memory
145  * (factor 512, >> 9). With 2MB pages, we need one 8 byte PTE for 2MB
146  * of memory (factor 256K, >> 18). ROCm user mode tries to optimize
147  * for 2MB pages for TLB efficiency. However, small allocations and
148  * fragmented system memory still need some 4KB pages. We choose a
149  * compromise that should work in most cases without reserving too
150  * much memory for page tables unnecessarily (factor 16K, >> 14).
151  */
152 
153 #define ESTIMATE_PT_SIZE(mem_size) max(((mem_size) >> 14), AMDGPU_VM_RESERVED_VRAM)
154 
155 /**
156  * amdgpu_amdkfd_reserve_mem_limit() - Decrease available memory by size
157  * of buffer.
158  *
159  * @adev: Device to which allocated BO belongs to
160  * @size: Size of buffer, in bytes, encapsulated by B0. This should be
161  * equivalent to amdgpu_bo_size(BO)
162  * @alloc_flag: Flag used in allocating a BO as noted above
163  * @xcp_id: xcp_id is used to get xcp from xcp manager, one xcp is
164  * managed as one compute node in driver for app
165  *
166  * Return:
167  *	returns -ENOMEM in case of error, ZERO otherwise
168  */
169 int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
170 		uint64_t size, u32 alloc_flag, int8_t xcp_id)
171 {
172 	uint64_t reserved_for_pt =
173 		ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
174 	size_t system_mem_needed, ttm_mem_needed, vram_needed;
175 	int ret = 0;
176 	uint64_t vram_size = 0;
177 
178 	system_mem_needed = 0;
179 	ttm_mem_needed = 0;
180 	vram_needed = 0;
181 	if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
182 		system_mem_needed = size;
183 		ttm_mem_needed = size;
184 	} else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
185 		/*
186 		 * Conservatively round up the allocation requirement to 2 MB
187 		 * to avoid fragmentation caused by 4K allocations in the tail
188 		 * 2M BO chunk.
189 		 */
190 		vram_needed = size;
191 		/*
192 		 * For GFX 9.4.3, get the VRAM size from XCP structs
193 		 */
194 		if (WARN_ONCE(xcp_id < 0, "invalid XCP ID %d", xcp_id))
195 			return -EINVAL;
196 
197 		vram_size = KFD_XCP_MEMORY_SIZE(adev, xcp_id);
198 		if (adev->gmc.is_app_apu) {
199 			system_mem_needed = size;
200 			ttm_mem_needed = size;
201 		}
202 	} else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
203 		system_mem_needed = size;
204 	} else if (!(alloc_flag &
205 				(KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
206 				 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
207 		pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag);
208 		return -ENOMEM;
209 	}
210 
211 	spin_lock(&kfd_mem_limit.mem_limit_lock);
212 
213 	if (kfd_mem_limit.system_mem_used + system_mem_needed >
214 	    kfd_mem_limit.max_system_mem_limit)
215 		pr_debug("Set no_system_mem_limit=1 if using shared memory\n");
216 
217 	if ((kfd_mem_limit.system_mem_used + system_mem_needed >
218 	     kfd_mem_limit.max_system_mem_limit && !no_system_mem_limit) ||
219 	    (kfd_mem_limit.ttm_mem_used + ttm_mem_needed >
220 	     kfd_mem_limit.max_ttm_mem_limit) ||
221 	    (adev && xcp_id >= 0 && adev->kfd.vram_used[xcp_id] + vram_needed >
222 	     vram_size - reserved_for_pt)) {
223 		ret = -ENOMEM;
224 		goto release;
225 	}
226 
227 	/* Update memory accounting by decreasing available system
228 	 * memory, TTM memory and GPU memory as computed above
229 	 */
230 	WARN_ONCE(vram_needed && !adev,
231 		  "adev reference can't be null when vram is used");
232 	if (adev && xcp_id >= 0) {
233 		adev->kfd.vram_used[xcp_id] += vram_needed;
234 		adev->kfd.vram_used_aligned[xcp_id] += adev->gmc.is_app_apu ?
235 				vram_needed :
236 				ALIGN(vram_needed, VRAM_AVAILABLITY_ALIGN);
237 	}
238 	kfd_mem_limit.system_mem_used += system_mem_needed;
239 	kfd_mem_limit.ttm_mem_used += ttm_mem_needed;
240 
241 release:
242 	spin_unlock(&kfd_mem_limit.mem_limit_lock);
243 	return ret;
244 }
245 
246 void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev,
247 		uint64_t size, u32 alloc_flag, int8_t xcp_id)
248 {
249 	spin_lock(&kfd_mem_limit.mem_limit_lock);
250 
251 	if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
252 		kfd_mem_limit.system_mem_used -= size;
253 		kfd_mem_limit.ttm_mem_used -= size;
254 	} else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
255 		WARN_ONCE(!adev,
256 			  "adev reference can't be null when alloc mem flags vram is set");
257 		if (WARN_ONCE(xcp_id < 0, "invalid XCP ID %d", xcp_id))
258 			goto release;
259 
260 		if (adev) {
261 			adev->kfd.vram_used[xcp_id] -= size;
262 			if (adev->gmc.is_app_apu) {
263 				adev->kfd.vram_used_aligned[xcp_id] -= size;
264 				kfd_mem_limit.system_mem_used -= size;
265 				kfd_mem_limit.ttm_mem_used -= size;
266 			} else {
267 				adev->kfd.vram_used_aligned[xcp_id] -=
268 					ALIGN(size, VRAM_AVAILABLITY_ALIGN);
269 			}
270 		}
271 	} else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
272 		kfd_mem_limit.system_mem_used -= size;
273 	} else if (!(alloc_flag &
274 				(KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
275 				 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
276 		pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag);
277 		goto release;
278 	}
279 	WARN_ONCE(adev && xcp_id >= 0 && adev->kfd.vram_used[xcp_id] < 0,
280 		  "KFD VRAM memory accounting unbalanced for xcp: %d", xcp_id);
281 	WARN_ONCE(kfd_mem_limit.ttm_mem_used < 0,
282 		  "KFD TTM memory accounting unbalanced");
283 	WARN_ONCE(kfd_mem_limit.system_mem_used < 0,
284 		  "KFD system memory accounting unbalanced");
285 
286 release:
287 	spin_unlock(&kfd_mem_limit.mem_limit_lock);
288 }
289 
290 void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo)
291 {
292 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
293 	u32 alloc_flags = bo->kfd_bo->alloc_flags;
294 	u64 size = amdgpu_bo_size(bo);
295 
296 	amdgpu_amdkfd_unreserve_mem_limit(adev, size, alloc_flags,
297 					  bo->xcp_id);
298 
299 	kfree(bo->kfd_bo);
300 }
301 
302 /**
303  * create_dmamap_sg_bo() - Creates a amdgpu_bo object to reflect information
304  * about USERPTR or DOOREBELL or MMIO BO.
305  *
306  * @adev: Device for which dmamap BO is being created
307  * @mem: BO of peer device that is being DMA mapped. Provides parameters
308  *	 in building the dmamap BO
309  * @bo_out: Output parameter updated with handle of dmamap BO
310  */
311 static int
312 create_dmamap_sg_bo(struct amdgpu_device *adev,
313 		 struct kgd_mem *mem, struct amdgpu_bo **bo_out)
314 {
315 	struct drm_gem_object *gem_obj;
316 	int ret;
317 	uint64_t flags = 0;
318 
319 	ret = amdgpu_bo_reserve(mem->bo, false);
320 	if (ret)
321 		return ret;
322 
323 	if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR)
324 		flags |= mem->bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
325 					AMDGPU_GEM_CREATE_UNCACHED);
326 
327 	ret = amdgpu_gem_object_create(adev, mem->bo->tbo.base.size, 1,
328 			AMDGPU_GEM_DOMAIN_CPU, AMDGPU_GEM_CREATE_PREEMPTIBLE | flags,
329 			ttm_bo_type_sg, mem->bo->tbo.base.resv, &gem_obj, 0);
330 
331 	amdgpu_bo_unreserve(mem->bo);
332 
333 	if (ret) {
334 		pr_err("Error in creating DMA mappable SG BO on domain: %d\n", ret);
335 		return -EINVAL;
336 	}
337 
338 	*bo_out = gem_to_amdgpu_bo(gem_obj);
339 	(*bo_out)->parent = amdgpu_bo_ref(mem->bo);
340 	return ret;
341 }
342 
343 /* amdgpu_amdkfd_remove_eviction_fence - Removes eviction fence from BO's
344  *  reservation object.
345  *
346  * @bo: [IN] Remove eviction fence(s) from this BO
347  * @ef: [IN] This eviction fence is removed if it
348  *  is present in the shared list.
349  *
350  * NOTE: Must be called with BO reserved i.e. bo->tbo.resv->lock held.
351  */
352 static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo,
353 					struct amdgpu_amdkfd_fence *ef)
354 {
355 	struct dma_fence *replacement;
356 
357 	if (!ef)
358 		return -EINVAL;
359 
360 	/* TODO: Instead of block before we should use the fence of the page
361 	 * table update and TLB flush here directly.
362 	 */
363 	replacement = dma_fence_get_stub();
364 	dma_resv_replace_fences(bo->tbo.base.resv, ef->base.context,
365 				replacement, DMA_RESV_USAGE_BOOKKEEP);
366 	dma_fence_put(replacement);
367 	return 0;
368 }
369 
370 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
371 {
372 	struct amdgpu_bo *root = bo;
373 	struct amdgpu_vm_bo_base *vm_bo;
374 	struct amdgpu_vm *vm;
375 	struct amdkfd_process_info *info;
376 	struct amdgpu_amdkfd_fence *ef;
377 	int ret;
378 
379 	/* we can always get vm_bo from root PD bo.*/
380 	while (root->parent)
381 		root = root->parent;
382 
383 	vm_bo = root->vm_bo;
384 	if (!vm_bo)
385 		return 0;
386 
387 	vm = vm_bo->vm;
388 	if (!vm)
389 		return 0;
390 
391 	info = vm->process_info;
392 	if (!info || !info->eviction_fence)
393 		return 0;
394 
395 	ef = container_of(dma_fence_get(&info->eviction_fence->base),
396 			struct amdgpu_amdkfd_fence, base);
397 
398 	BUG_ON(!dma_resv_trylock(bo->tbo.base.resv));
399 	ret = amdgpu_amdkfd_remove_eviction_fence(bo, ef);
400 	dma_resv_unlock(bo->tbo.base.resv);
401 
402 	dma_fence_put(&ef->base);
403 	return ret;
404 }
405 
406 static int amdgpu_amdkfd_bo_validate(struct amdgpu_bo *bo, uint32_t domain,
407 				     bool wait)
408 {
409 	struct ttm_operation_ctx ctx = { false, false };
410 	int ret;
411 
412 	if (WARN(amdgpu_ttm_tt_get_usermm(bo->tbo.ttm),
413 		 "Called with userptr BO"))
414 		return -EINVAL;
415 
416 	amdgpu_bo_placement_from_domain(bo, domain);
417 
418 	ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
419 	if (ret)
420 		goto validate_fail;
421 	if (wait)
422 		amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
423 
424 validate_fail:
425 	return ret;
426 }
427 
428 static int amdgpu_amdkfd_validate_vm_bo(void *_unused, struct amdgpu_bo *bo)
429 {
430 	return amdgpu_amdkfd_bo_validate(bo, bo->allowed_domains, false);
431 }
432 
433 /* vm_validate_pt_pd_bos - Validate page table and directory BOs
434  *
435  * Page directories are not updated here because huge page handling
436  * during page table updates can invalidate page directory entries
437  * again. Page directories are only updated after updating page
438  * tables.
439  */
440 static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm)
441 {
442 	struct amdgpu_bo *pd = vm->root.bo;
443 	struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
444 	int ret;
445 
446 	ret = amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_amdkfd_validate_vm_bo, NULL);
447 	if (ret) {
448 		pr_err("failed to validate PT BOs\n");
449 		return ret;
450 	}
451 
452 	vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.bo);
453 
454 	return 0;
455 }
456 
457 static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
458 {
459 	struct amdgpu_bo *pd = vm->root.bo;
460 	struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
461 	int ret;
462 
463 	ret = amdgpu_vm_update_pdes(adev, vm, false);
464 	if (ret)
465 		return ret;
466 
467 	return amdgpu_sync_fence(sync, vm->last_update);
468 }
469 
470 static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
471 {
472 	uint32_t mapping_flags = AMDGPU_VM_PAGE_READABLE |
473 				 AMDGPU_VM_MTYPE_DEFAULT;
474 
475 	if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE)
476 		mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE;
477 	if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE)
478 		mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;
479 
480 	return amdgpu_gem_va_map_flags(adev, mapping_flags);
481 }
482 
483 /**
484  * create_sg_table() - Create an sg_table for a contiguous DMA addr range
485  * @addr: The starting address to point to
486  * @size: Size of memory area in bytes being pointed to
487  *
488  * Allocates an instance of sg_table and initializes it to point to memory
489  * area specified by input parameters. The address used to build is assumed
490  * to be DMA mapped, if needed.
491  *
492  * DOORBELL or MMIO BOs use only one scatterlist node in their sg_table
493  * because they are physically contiguous.
494  *
495  * Return: Initialized instance of SG Table or NULL
496  */
497 static struct sg_table *create_sg_table(uint64_t addr, uint32_t size)
498 {
499 	struct sg_table *sg = kmalloc(sizeof(*sg), GFP_KERNEL);
500 
501 	if (!sg)
502 		return NULL;
503 	if (sg_alloc_table(sg, 1, GFP_KERNEL)) {
504 		kfree(sg);
505 		return NULL;
506 	}
507 	sg_dma_address(sg->sgl) = addr;
508 	sg->sgl->length = size;
509 #ifdef CONFIG_NEED_SG_DMA_LENGTH
510 	sg->sgl->dma_length = size;
511 #endif
512 	return sg;
513 }
514 
515 static int
516 kfd_mem_dmamap_userptr(struct kgd_mem *mem,
517 		       struct kfd_mem_attachment *attachment)
518 {
519 	enum dma_data_direction direction =
520 		mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
521 		DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
522 	struct ttm_operation_ctx ctx = {.interruptible = true};
523 	struct amdgpu_bo *bo = attachment->bo_va->base.bo;
524 	struct amdgpu_device *adev = attachment->adev;
525 	struct ttm_tt *src_ttm = mem->bo->tbo.ttm;
526 	struct ttm_tt *ttm = bo->tbo.ttm;
527 	int ret;
528 
529 	if (WARN_ON(ttm->num_pages != src_ttm->num_pages))
530 		return -EINVAL;
531 
532 	ttm->sg = kmalloc(sizeof(*ttm->sg), GFP_KERNEL);
533 	if (unlikely(!ttm->sg))
534 		return -ENOMEM;
535 
536 	/* Same sequence as in amdgpu_ttm_tt_pin_userptr */
537 	ret = sg_alloc_table_from_pages(ttm->sg, src_ttm->pages,
538 					ttm->num_pages, 0,
539 					(u64)ttm->num_pages << PAGE_SHIFT,
540 					GFP_KERNEL);
541 	if (unlikely(ret))
542 		goto free_sg;
543 
544 	ret = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
545 	if (unlikely(ret))
546 		goto release_sg;
547 
548 	amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
549 	ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
550 	if (ret)
551 		goto unmap_sg;
552 
553 	return 0;
554 
555 unmap_sg:
556 	dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
557 release_sg:
558 	pr_err("DMA map userptr failed: %d\n", ret);
559 	sg_free_table(ttm->sg);
560 free_sg:
561 	kfree(ttm->sg);
562 	ttm->sg = NULL;
563 	return ret;
564 }
565 
566 static int
567 kfd_mem_dmamap_dmabuf(struct kfd_mem_attachment *attachment)
568 {
569 	struct ttm_operation_ctx ctx = {.interruptible = true};
570 	struct amdgpu_bo *bo = attachment->bo_va->base.bo;
571 	int ret;
572 
573 	amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
574 	ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
575 	if (ret)
576 		return ret;
577 
578 	amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
579 	return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
580 }
581 
582 /**
583  * kfd_mem_dmamap_sg_bo() - Create DMA mapped sg_table to access DOORBELL or MMIO BO
584  * @mem: SG BO of the DOORBELL or MMIO resource on the owning device
585  * @attachment: Virtual address attachment of the BO on accessing device
586  *
587  * An access request from the device that owns DOORBELL does not require DMA mapping.
588  * This is because the request doesn't go through PCIe root complex i.e. it instead
589  * loops back. The need to DMA map arises only when accessing peer device's DOORBELL
590  *
591  * In contrast, all access requests for MMIO need to be DMA mapped without regard to
592  * device ownership. This is because access requests for MMIO go through PCIe root
593  * complex.
594  *
595  * This is accomplished in two steps:
596  *   - Obtain DMA mapped address of DOORBELL or MMIO memory that could be used
597  *         in updating requesting device's page table
598  *   - Signal TTM to mark memory pointed to by requesting device's BO as GPU
599  *         accessible. This allows an update of requesting device's page table
600  *         with entries associated with DOOREBELL or MMIO memory
601  *
602  * This method is invoked in the following contexts:
603  *   - Mapping of DOORBELL or MMIO BO of same or peer device
604  *   - Validating an evicted DOOREBELL or MMIO BO on device seeking access
605  *
606  * Return: ZERO if successful, NON-ZERO otherwise
607  */
608 static int
609 kfd_mem_dmamap_sg_bo(struct kgd_mem *mem,
610 		     struct kfd_mem_attachment *attachment)
611 {
612 	struct ttm_operation_ctx ctx = {.interruptible = true};
613 	struct amdgpu_bo *bo = attachment->bo_va->base.bo;
614 	struct amdgpu_device *adev = attachment->adev;
615 	struct ttm_tt *ttm = bo->tbo.ttm;
616 	enum dma_data_direction dir;
617 	dma_addr_t dma_addr;
618 	bool mmio;
619 	int ret;
620 
621 	/* Expect SG Table of dmapmap BO to be NULL */
622 	mmio = (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP);
623 	if (unlikely(ttm->sg)) {
624 		pr_err("SG Table of %d BO for peer device is UNEXPECTEDLY NON-NULL", mmio);
625 		return -EINVAL;
626 	}
627 
628 	dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
629 			DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
630 	dma_addr = mem->bo->tbo.sg->sgl->dma_address;
631 	pr_debug("%d BO size: %d\n", mmio, mem->bo->tbo.sg->sgl->length);
632 	pr_debug("%d BO address before DMA mapping: %llx\n", mmio, dma_addr);
633 	dma_addr = dma_map_resource(adev->dev, dma_addr,
634 			mem->bo->tbo.sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC);
635 	ret = dma_mapping_error(adev->dev, dma_addr);
636 	if (unlikely(ret))
637 		return ret;
638 	pr_debug("%d BO address after DMA mapping: %llx\n", mmio, dma_addr);
639 
640 	ttm->sg = create_sg_table(dma_addr, mem->bo->tbo.sg->sgl->length);
641 	if (unlikely(!ttm->sg)) {
642 		ret = -ENOMEM;
643 		goto unmap_sg;
644 	}
645 
646 	amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
647 	ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
648 	if (unlikely(ret))
649 		goto free_sg;
650 
651 	return ret;
652 
653 free_sg:
654 	sg_free_table(ttm->sg);
655 	kfree(ttm->sg);
656 	ttm->sg = NULL;
657 unmap_sg:
658 	dma_unmap_resource(adev->dev, dma_addr, mem->bo->tbo.sg->sgl->length,
659 			   dir, DMA_ATTR_SKIP_CPU_SYNC);
660 	return ret;
661 }
662 
663 static int
664 kfd_mem_dmamap_attachment(struct kgd_mem *mem,
665 			  struct kfd_mem_attachment *attachment)
666 {
667 	switch (attachment->type) {
668 	case KFD_MEM_ATT_SHARED:
669 		return 0;
670 	case KFD_MEM_ATT_USERPTR:
671 		return kfd_mem_dmamap_userptr(mem, attachment);
672 	case KFD_MEM_ATT_DMABUF:
673 		return kfd_mem_dmamap_dmabuf(attachment);
674 	case KFD_MEM_ATT_SG:
675 		return kfd_mem_dmamap_sg_bo(mem, attachment);
676 	default:
677 		WARN_ON_ONCE(1);
678 	}
679 	return -EINVAL;
680 }
681 
682 static void
683 kfd_mem_dmaunmap_userptr(struct kgd_mem *mem,
684 			 struct kfd_mem_attachment *attachment)
685 {
686 	enum dma_data_direction direction =
687 		mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
688 		DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
689 	struct ttm_operation_ctx ctx = {.interruptible = false};
690 	struct amdgpu_bo *bo = attachment->bo_va->base.bo;
691 	struct amdgpu_device *adev = attachment->adev;
692 	struct ttm_tt *ttm = bo->tbo.ttm;
693 
694 	if (unlikely(!ttm->sg))
695 		return;
696 
697 	amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
698 	ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
699 
700 	dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
701 	sg_free_table(ttm->sg);
702 	kfree(ttm->sg);
703 	ttm->sg = NULL;
704 }
705 
706 static void
707 kfd_mem_dmaunmap_dmabuf(struct kfd_mem_attachment *attachment)
708 {
709 	/* This is a no-op. We don't want to trigger eviction fences when
710 	 * unmapping DMABufs. Therefore the invalidation (moving to system
711 	 * domain) is done in kfd_mem_dmamap_dmabuf.
712 	 */
713 }
714 
715 /**
716  * kfd_mem_dmaunmap_sg_bo() - Free DMA mapped sg_table of DOORBELL or MMIO BO
717  * @mem: SG BO of the DOORBELL or MMIO resource on the owning device
718  * @attachment: Virtual address attachment of the BO on accessing device
719  *
720  * The method performs following steps:
721  *   - Signal TTM to mark memory pointed to by BO as GPU inaccessible
722  *   - Free SG Table that is used to encapsulate DMA mapped memory of
723  *          peer device's DOORBELL or MMIO memory
724  *
725  * This method is invoked in the following contexts:
726  *     UNMapping of DOORBELL or MMIO BO on a device having access to its memory
727  *     Eviction of DOOREBELL or MMIO BO on device having access to its memory
728  *
729  * Return: void
730  */
731 static void
732 kfd_mem_dmaunmap_sg_bo(struct kgd_mem *mem,
733 		       struct kfd_mem_attachment *attachment)
734 {
735 	struct ttm_operation_ctx ctx = {.interruptible = true};
736 	struct amdgpu_bo *bo = attachment->bo_va->base.bo;
737 	struct amdgpu_device *adev = attachment->adev;
738 	struct ttm_tt *ttm = bo->tbo.ttm;
739 	enum dma_data_direction dir;
740 
741 	if (unlikely(!ttm->sg)) {
742 		pr_debug("SG Table of BO is NULL");
743 		return;
744 	}
745 
746 	amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
747 	ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
748 
749 	dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
750 				DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
751 	dma_unmap_resource(adev->dev, ttm->sg->sgl->dma_address,
752 			ttm->sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC);
753 	sg_free_table(ttm->sg);
754 	kfree(ttm->sg);
755 	ttm->sg = NULL;
756 	bo->tbo.sg = NULL;
757 }
758 
759 static void
760 kfd_mem_dmaunmap_attachment(struct kgd_mem *mem,
761 			    struct kfd_mem_attachment *attachment)
762 {
763 	switch (attachment->type) {
764 	case KFD_MEM_ATT_SHARED:
765 		break;
766 	case KFD_MEM_ATT_USERPTR:
767 		kfd_mem_dmaunmap_userptr(mem, attachment);
768 		break;
769 	case KFD_MEM_ATT_DMABUF:
770 		kfd_mem_dmaunmap_dmabuf(attachment);
771 		break;
772 	case KFD_MEM_ATT_SG:
773 		kfd_mem_dmaunmap_sg_bo(mem, attachment);
774 		break;
775 	default:
776 		WARN_ON_ONCE(1);
777 	}
778 }
779 
780 static int kfd_mem_export_dmabuf(struct kgd_mem *mem)
781 {
782 	if (!mem->dmabuf) {
783 		struct dma_buf *ret = amdgpu_gem_prime_export(
784 			&mem->bo->tbo.base,
785 			mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
786 				DRM_RDWR : 0);
787 		if (IS_ERR(ret))
788 			return PTR_ERR(ret);
789 		mem->dmabuf = ret;
790 	}
791 
792 	return 0;
793 }
794 
795 static int
796 kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem,
797 		      struct amdgpu_bo **bo)
798 {
799 	struct drm_gem_object *gobj;
800 	int ret;
801 
802 	ret = kfd_mem_export_dmabuf(mem);
803 	if (ret)
804 		return ret;
805 
806 	gobj = amdgpu_gem_prime_import(adev_to_drm(adev), mem->dmabuf);
807 	if (IS_ERR(gobj))
808 		return PTR_ERR(gobj);
809 
810 	*bo = gem_to_amdgpu_bo(gobj);
811 	(*bo)->flags |= AMDGPU_GEM_CREATE_PREEMPTIBLE;
812 
813 	return 0;
814 }
815 
816 /* kfd_mem_attach - Add a BO to a VM
817  *
818  * Everything that needs to bo done only once when a BO is first added
819  * to a VM. It can later be mapped and unmapped many times without
820  * repeating these steps.
821  *
822  * 0. Create BO for DMA mapping, if needed
823  * 1. Allocate and initialize BO VA entry data structure
824  * 2. Add BO to the VM
825  * 3. Determine ASIC-specific PTE flags
826  * 4. Alloc page tables and directories if needed
827  * 4a.  Validate new page tables and directories
828  */
829 static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
830 		struct amdgpu_vm *vm, bool is_aql)
831 {
832 	struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
833 	unsigned long bo_size = mem->bo->tbo.base.size;
834 	uint64_t va = mem->va;
835 	struct kfd_mem_attachment *attachment[2] = {NULL, NULL};
836 	struct amdgpu_bo *bo[2] = {NULL, NULL};
837 	struct amdgpu_bo_va *bo_va;
838 	bool same_hive = false;
839 	int i, ret;
840 
841 	if (!va) {
842 		pr_err("Invalid VA when adding BO to VM\n");
843 		return -EINVAL;
844 	}
845 
846 	/* Determine access to VRAM, MMIO and DOORBELL BOs of peer devices
847 	 *
848 	 * The access path of MMIO and DOORBELL BOs of is always over PCIe.
849 	 * In contrast the access path of VRAM BOs depens upon the type of
850 	 * link that connects the peer device. Access over PCIe is allowed
851 	 * if peer device has large BAR. In contrast, access over xGMI is
852 	 * allowed for both small and large BAR configurations of peer device
853 	 */
854 	if ((adev != bo_adev && !adev->gmc.is_app_apu) &&
855 	    ((mem->domain == AMDGPU_GEM_DOMAIN_VRAM) ||
856 	     (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) ||
857 	     (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
858 		if (mem->domain == AMDGPU_GEM_DOMAIN_VRAM)
859 			same_hive = amdgpu_xgmi_same_hive(adev, bo_adev);
860 		if (!same_hive && !amdgpu_device_is_peer_accessible(bo_adev, adev))
861 			return -EINVAL;
862 	}
863 
864 	for (i = 0; i <= is_aql; i++) {
865 		attachment[i] = kzalloc(sizeof(*attachment[i]), GFP_KERNEL);
866 		if (unlikely(!attachment[i])) {
867 			ret = -ENOMEM;
868 			goto unwind;
869 		}
870 
871 		pr_debug("\t add VA 0x%llx - 0x%llx to vm %p\n", va,
872 			 va + bo_size, vm);
873 
874 		if ((adev == bo_adev && !(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) ||
875 		    (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) && reuse_dmamap(adev, bo_adev)) ||
876 		    (mem->domain == AMDGPU_GEM_DOMAIN_GTT && reuse_dmamap(adev, bo_adev)) ||
877 		    same_hive) {
878 			/* Mappings on the local GPU, or VRAM mappings in the
879 			 * local hive, or userptr, or GTT mapping can reuse dma map
880 			 * address space share the original BO
881 			 */
882 			attachment[i]->type = KFD_MEM_ATT_SHARED;
883 			bo[i] = mem->bo;
884 			drm_gem_object_get(&bo[i]->tbo.base);
885 		} else if (i > 0) {
886 			/* Multiple mappings on the same GPU share the BO */
887 			attachment[i]->type = KFD_MEM_ATT_SHARED;
888 			bo[i] = bo[0];
889 			drm_gem_object_get(&bo[i]->tbo.base);
890 		} else if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
891 			/* Create an SG BO to DMA-map userptrs on other GPUs */
892 			attachment[i]->type = KFD_MEM_ATT_USERPTR;
893 			ret = create_dmamap_sg_bo(adev, mem, &bo[i]);
894 			if (ret)
895 				goto unwind;
896 		/* Handle DOORBELL BOs of peer devices and MMIO BOs of local and peer devices */
897 		} else if (mem->bo->tbo.type == ttm_bo_type_sg) {
898 			WARN_ONCE(!(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL ||
899 				    mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP),
900 				  "Handing invalid SG BO in ATTACH request");
901 			attachment[i]->type = KFD_MEM_ATT_SG;
902 			ret = create_dmamap_sg_bo(adev, mem, &bo[i]);
903 			if (ret)
904 				goto unwind;
905 		/* Enable acces to GTT and VRAM BOs of peer devices */
906 		} else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT ||
907 			   mem->domain == AMDGPU_GEM_DOMAIN_VRAM) {
908 			attachment[i]->type = KFD_MEM_ATT_DMABUF;
909 			ret = kfd_mem_attach_dmabuf(adev, mem, &bo[i]);
910 			if (ret)
911 				goto unwind;
912 			pr_debug("Employ DMABUF mechanism to enable peer GPU access\n");
913 		} else {
914 			WARN_ONCE(true, "Handling invalid ATTACH request");
915 			ret = -EINVAL;
916 			goto unwind;
917 		}
918 
919 		/* Add BO to VM internal data structures */
920 		ret = amdgpu_bo_reserve(bo[i], false);
921 		if (ret) {
922 			pr_debug("Unable to reserve BO during memory attach");
923 			goto unwind;
924 		}
925 		bo_va = amdgpu_vm_bo_find(vm, bo[i]);
926 		if (!bo_va)
927 			bo_va = amdgpu_vm_bo_add(adev, vm, bo[i]);
928 		else
929 			++bo_va->ref_count;
930 		attachment[i]->bo_va = bo_va;
931 		amdgpu_bo_unreserve(bo[i]);
932 		if (unlikely(!attachment[i]->bo_va)) {
933 			ret = -ENOMEM;
934 			pr_err("Failed to add BO object to VM. ret == %d\n",
935 			       ret);
936 			goto unwind;
937 		}
938 		attachment[i]->va = va;
939 		attachment[i]->pte_flags = get_pte_flags(adev, mem);
940 		attachment[i]->adev = adev;
941 		list_add(&attachment[i]->list, &mem->attachments);
942 
943 		va += bo_size;
944 	}
945 
946 	return 0;
947 
948 unwind:
949 	for (; i >= 0; i--) {
950 		if (!attachment[i])
951 			continue;
952 		if (attachment[i]->bo_va) {
953 			amdgpu_bo_reserve(bo[i], true);
954 			if (--attachment[i]->bo_va->ref_count == 0)
955 				amdgpu_vm_bo_del(adev, attachment[i]->bo_va);
956 			amdgpu_bo_unreserve(bo[i]);
957 			list_del(&attachment[i]->list);
958 		}
959 		if (bo[i])
960 			drm_gem_object_put(&bo[i]->tbo.base);
961 		kfree(attachment[i]);
962 	}
963 	return ret;
964 }
965 
966 static void kfd_mem_detach(struct kfd_mem_attachment *attachment)
967 {
968 	struct amdgpu_bo *bo = attachment->bo_va->base.bo;
969 
970 	pr_debug("\t remove VA 0x%llx in entry %p\n",
971 			attachment->va, attachment);
972 	if (--attachment->bo_va->ref_count == 0)
973 		amdgpu_vm_bo_del(attachment->adev, attachment->bo_va);
974 	drm_gem_object_put(&bo->tbo.base);
975 	list_del(&attachment->list);
976 	kfree(attachment);
977 }
978 
979 static void add_kgd_mem_to_kfd_bo_list(struct kgd_mem *mem,
980 				struct amdkfd_process_info *process_info,
981 				bool userptr)
982 {
983 	mutex_lock(&process_info->lock);
984 	if (userptr)
985 		list_add_tail(&mem->validate_list,
986 			      &process_info->userptr_valid_list);
987 	else
988 		list_add_tail(&mem->validate_list, &process_info->kfd_bo_list);
989 	mutex_unlock(&process_info->lock);
990 }
991 
992 static void remove_kgd_mem_from_kfd_bo_list(struct kgd_mem *mem,
993 		struct amdkfd_process_info *process_info)
994 {
995 	mutex_lock(&process_info->lock);
996 	list_del(&mem->validate_list);
997 	mutex_unlock(&process_info->lock);
998 }
999 
1000 /* Initializes user pages. It registers the MMU notifier and validates
1001  * the userptr BO in the GTT domain.
1002  *
1003  * The BO must already be on the userptr_valid_list. Otherwise an
1004  * eviction and restore may happen that leaves the new BO unmapped
1005  * with the user mode queues running.
1006  *
1007  * Takes the process_info->lock to protect against concurrent restore
1008  * workers.
1009  *
1010  * Returns 0 for success, negative errno for errors.
1011  */
1012 static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr,
1013 			   bool criu_resume)
1014 {
1015 	struct amdkfd_process_info *process_info = mem->process_info;
1016 	struct amdgpu_bo *bo = mem->bo;
1017 	struct ttm_operation_ctx ctx = { true, false };
1018 	struct hmm_range *range;
1019 	int ret = 0;
1020 
1021 	mutex_lock(&process_info->lock);
1022 
1023 	ret = amdgpu_ttm_tt_set_userptr(&bo->tbo, user_addr, 0);
1024 	if (ret) {
1025 		pr_err("%s: Failed to set userptr: %d\n", __func__, ret);
1026 		goto out;
1027 	}
1028 
1029 	ret = amdgpu_hmm_register(bo, user_addr);
1030 	if (ret) {
1031 		pr_err("%s: Failed to register MMU notifier: %d\n",
1032 		       __func__, ret);
1033 		goto out;
1034 	}
1035 
1036 	if (criu_resume) {
1037 		/*
1038 		 * During a CRIU restore operation, the userptr buffer objects
1039 		 * will be validated in the restore_userptr_work worker at a
1040 		 * later stage when it is scheduled by another ioctl called by
1041 		 * CRIU master process for the target pid for restore.
1042 		 */
1043 		mutex_lock(&process_info->notifier_lock);
1044 		mem->invalid++;
1045 		mutex_unlock(&process_info->notifier_lock);
1046 		mutex_unlock(&process_info->lock);
1047 		return 0;
1048 	}
1049 
1050 	ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, &range);
1051 	if (ret) {
1052 		pr_err("%s: Failed to get user pages: %d\n", __func__, ret);
1053 		goto unregister_out;
1054 	}
1055 
1056 	ret = amdgpu_bo_reserve(bo, true);
1057 	if (ret) {
1058 		pr_err("%s: Failed to reserve BO\n", __func__);
1059 		goto release_out;
1060 	}
1061 	amdgpu_bo_placement_from_domain(bo, mem->domain);
1062 	ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1063 	if (ret)
1064 		pr_err("%s: failed to validate BO\n", __func__);
1065 	amdgpu_bo_unreserve(bo);
1066 
1067 release_out:
1068 	amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range);
1069 unregister_out:
1070 	if (ret)
1071 		amdgpu_hmm_unregister(bo);
1072 out:
1073 	mutex_unlock(&process_info->lock);
1074 	return ret;
1075 }
1076 
1077 /* Reserving a BO and its page table BOs must happen atomically to
1078  * avoid deadlocks. Some operations update multiple VMs at once. Track
1079  * all the reservation info in a context structure. Optionally a sync
1080  * object can track VM updates.
1081  */
1082 struct bo_vm_reservation_context {
1083 	/* DRM execution context for the reservation */
1084 	struct drm_exec exec;
1085 	/* Number of VMs reserved */
1086 	unsigned int n_vms;
1087 	/* Pointer to sync object */
1088 	struct amdgpu_sync *sync;
1089 };
1090 
1091 enum bo_vm_match {
1092 	BO_VM_NOT_MAPPED = 0,	/* Match VMs where a BO is not mapped */
1093 	BO_VM_MAPPED,		/* Match VMs where a BO is mapped     */
1094 	BO_VM_ALL,		/* Match all VMs a BO was added to    */
1095 };
1096 
1097 /**
1098  * reserve_bo_and_vm - reserve a BO and a VM unconditionally.
1099  * @mem: KFD BO structure.
1100  * @vm: the VM to reserve.
1101  * @ctx: the struct that will be used in unreserve_bo_and_vms().
1102  */
1103 static int reserve_bo_and_vm(struct kgd_mem *mem,
1104 			      struct amdgpu_vm *vm,
1105 			      struct bo_vm_reservation_context *ctx)
1106 {
1107 	struct amdgpu_bo *bo = mem->bo;
1108 	int ret;
1109 
1110 	WARN_ON(!vm);
1111 
1112 	ctx->n_vms = 1;
1113 	ctx->sync = &mem->sync;
1114 	drm_exec_init(&ctx->exec, DRM_EXEC_INTERRUPTIBLE_WAIT);
1115 	drm_exec_until_all_locked(&ctx->exec) {
1116 		ret = amdgpu_vm_lock_pd(vm, &ctx->exec, 2);
1117 		drm_exec_retry_on_contention(&ctx->exec);
1118 		if (unlikely(ret))
1119 			goto error;
1120 
1121 		ret = drm_exec_lock_obj(&ctx->exec, &bo->tbo.base);
1122 		drm_exec_retry_on_contention(&ctx->exec);
1123 		if (unlikely(ret))
1124 			goto error;
1125 	}
1126 	return 0;
1127 
1128 error:
1129 	pr_err("Failed to reserve buffers in ttm.\n");
1130 	drm_exec_fini(&ctx->exec);
1131 	return ret;
1132 }
1133 
1134 /**
1135  * reserve_bo_and_cond_vms - reserve a BO and some VMs conditionally
1136  * @mem: KFD BO structure.
1137  * @vm: the VM to reserve. If NULL, then all VMs associated with the BO
1138  * is used. Otherwise, a single VM associated with the BO.
1139  * @map_type: the mapping status that will be used to filter the VMs.
1140  * @ctx: the struct that will be used in unreserve_bo_and_vms().
1141  *
1142  * Returns 0 for success, negative for failure.
1143  */
1144 static int reserve_bo_and_cond_vms(struct kgd_mem *mem,
1145 				struct amdgpu_vm *vm, enum bo_vm_match map_type,
1146 				struct bo_vm_reservation_context *ctx)
1147 {
1148 	struct kfd_mem_attachment *entry;
1149 	struct amdgpu_bo *bo = mem->bo;
1150 	int ret;
1151 
1152 	ctx->sync = &mem->sync;
1153 	drm_exec_init(&ctx->exec, DRM_EXEC_INTERRUPTIBLE_WAIT);
1154 	drm_exec_until_all_locked(&ctx->exec) {
1155 		ctx->n_vms = 0;
1156 		list_for_each_entry(entry, &mem->attachments, list) {
1157 			if ((vm && vm != entry->bo_va->base.vm) ||
1158 				(entry->is_mapped != map_type
1159 				&& map_type != BO_VM_ALL))
1160 				continue;
1161 
1162 			ret = amdgpu_vm_lock_pd(entry->bo_va->base.vm,
1163 						&ctx->exec, 2);
1164 			drm_exec_retry_on_contention(&ctx->exec);
1165 			if (unlikely(ret))
1166 				goto error;
1167 			++ctx->n_vms;
1168 		}
1169 
1170 		ret = drm_exec_prepare_obj(&ctx->exec, &bo->tbo.base, 1);
1171 		drm_exec_retry_on_contention(&ctx->exec);
1172 		if (unlikely(ret))
1173 			goto error;
1174 	}
1175 	return 0;
1176 
1177 error:
1178 	pr_err("Failed to reserve buffers in ttm.\n");
1179 	drm_exec_fini(&ctx->exec);
1180 	return ret;
1181 }
1182 
1183 /**
1184  * unreserve_bo_and_vms - Unreserve BO and VMs from a reservation context
1185  * @ctx: Reservation context to unreserve
1186  * @wait: Optionally wait for a sync object representing pending VM updates
1187  * @intr: Whether the wait is interruptible
1188  *
1189  * Also frees any resources allocated in
1190  * reserve_bo_and_(cond_)vm(s). Returns the status from
1191  * amdgpu_sync_wait.
1192  */
1193 static int unreserve_bo_and_vms(struct bo_vm_reservation_context *ctx,
1194 				 bool wait, bool intr)
1195 {
1196 	int ret = 0;
1197 
1198 	if (wait)
1199 		ret = amdgpu_sync_wait(ctx->sync, intr);
1200 
1201 	drm_exec_fini(&ctx->exec);
1202 	ctx->sync = NULL;
1203 	return ret;
1204 }
1205 
1206 static void unmap_bo_from_gpuvm(struct kgd_mem *mem,
1207 				struct kfd_mem_attachment *entry,
1208 				struct amdgpu_sync *sync)
1209 {
1210 	struct amdgpu_bo_va *bo_va = entry->bo_va;
1211 	struct amdgpu_device *adev = entry->adev;
1212 	struct amdgpu_vm *vm = bo_va->base.vm;
1213 
1214 	amdgpu_vm_bo_unmap(adev, bo_va, entry->va);
1215 
1216 	amdgpu_vm_clear_freed(adev, vm, &bo_va->last_pt_update);
1217 
1218 	amdgpu_sync_fence(sync, bo_va->last_pt_update);
1219 }
1220 
1221 static int update_gpuvm_pte(struct kgd_mem *mem,
1222 			    struct kfd_mem_attachment *entry,
1223 			    struct amdgpu_sync *sync)
1224 {
1225 	struct amdgpu_bo_va *bo_va = entry->bo_va;
1226 	struct amdgpu_device *adev = entry->adev;
1227 	int ret;
1228 
1229 	ret = kfd_mem_dmamap_attachment(mem, entry);
1230 	if (ret)
1231 		return ret;
1232 
1233 	/* Update the page tables  */
1234 	ret = amdgpu_vm_bo_update(adev, bo_va, false);
1235 	if (ret) {
1236 		pr_err("amdgpu_vm_bo_update failed\n");
1237 		return ret;
1238 	}
1239 
1240 	return amdgpu_sync_fence(sync, bo_va->last_pt_update);
1241 }
1242 
1243 static int map_bo_to_gpuvm(struct kgd_mem *mem,
1244 			   struct kfd_mem_attachment *entry,
1245 			   struct amdgpu_sync *sync,
1246 			   bool no_update_pte)
1247 {
1248 	int ret;
1249 
1250 	/* Set virtual address for the allocation */
1251 	ret = amdgpu_vm_bo_map(entry->adev, entry->bo_va, entry->va, 0,
1252 			       amdgpu_bo_size(entry->bo_va->base.bo),
1253 			       entry->pte_flags);
1254 	if (ret) {
1255 		pr_err("Failed to map VA 0x%llx in vm. ret %d\n",
1256 				entry->va, ret);
1257 		return ret;
1258 	}
1259 
1260 	if (no_update_pte)
1261 		return 0;
1262 
1263 	ret = update_gpuvm_pte(mem, entry, sync);
1264 	if (ret) {
1265 		pr_err("update_gpuvm_pte() failed\n");
1266 		goto update_gpuvm_pte_failed;
1267 	}
1268 
1269 	return 0;
1270 
1271 update_gpuvm_pte_failed:
1272 	unmap_bo_from_gpuvm(mem, entry, sync);
1273 	kfd_mem_dmaunmap_attachment(mem, entry);
1274 	return ret;
1275 }
1276 
1277 static int process_validate_vms(struct amdkfd_process_info *process_info)
1278 {
1279 	struct amdgpu_vm *peer_vm;
1280 	int ret;
1281 
1282 	list_for_each_entry(peer_vm, &process_info->vm_list_head,
1283 			    vm_list_node) {
1284 		ret = vm_validate_pt_pd_bos(peer_vm);
1285 		if (ret)
1286 			return ret;
1287 	}
1288 
1289 	return 0;
1290 }
1291 
1292 static int process_sync_pds_resv(struct amdkfd_process_info *process_info,
1293 				 struct amdgpu_sync *sync)
1294 {
1295 	struct amdgpu_vm *peer_vm;
1296 	int ret;
1297 
1298 	list_for_each_entry(peer_vm, &process_info->vm_list_head,
1299 			    vm_list_node) {
1300 		struct amdgpu_bo *pd = peer_vm->root.bo;
1301 
1302 		ret = amdgpu_sync_resv(NULL, sync, pd->tbo.base.resv,
1303 				       AMDGPU_SYNC_NE_OWNER,
1304 				       AMDGPU_FENCE_OWNER_KFD);
1305 		if (ret)
1306 			return ret;
1307 	}
1308 
1309 	return 0;
1310 }
1311 
1312 static int process_update_pds(struct amdkfd_process_info *process_info,
1313 			      struct amdgpu_sync *sync)
1314 {
1315 	struct amdgpu_vm *peer_vm;
1316 	int ret;
1317 
1318 	list_for_each_entry(peer_vm, &process_info->vm_list_head,
1319 			    vm_list_node) {
1320 		ret = vm_update_pds(peer_vm, sync);
1321 		if (ret)
1322 			return ret;
1323 	}
1324 
1325 	return 0;
1326 }
1327 
1328 static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info,
1329 		       struct dma_fence **ef)
1330 {
1331 	struct amdkfd_process_info *info = NULL;
1332 	int ret;
1333 
1334 	if (!*process_info) {
1335 		info = kzalloc(sizeof(*info), GFP_KERNEL);
1336 		if (!info)
1337 			return -ENOMEM;
1338 
1339 		mutex_init(&info->lock);
1340 		mutex_init(&info->notifier_lock);
1341 		INIT_LIST_HEAD(&info->vm_list_head);
1342 		INIT_LIST_HEAD(&info->kfd_bo_list);
1343 		INIT_LIST_HEAD(&info->userptr_valid_list);
1344 		INIT_LIST_HEAD(&info->userptr_inval_list);
1345 
1346 		info->eviction_fence =
1347 			amdgpu_amdkfd_fence_create(dma_fence_context_alloc(1),
1348 						   current->mm,
1349 						   NULL);
1350 		if (!info->eviction_fence) {
1351 			pr_err("Failed to create eviction fence\n");
1352 			ret = -ENOMEM;
1353 			goto create_evict_fence_fail;
1354 		}
1355 
1356 		info->pid = get_task_pid(current->group_leader, PIDTYPE_PID);
1357 		INIT_DELAYED_WORK(&info->restore_userptr_work,
1358 				  amdgpu_amdkfd_restore_userptr_worker);
1359 
1360 		*process_info = info;
1361 		*ef = dma_fence_get(&info->eviction_fence->base);
1362 	}
1363 
1364 	vm->process_info = *process_info;
1365 
1366 	/* Validate page directory and attach eviction fence */
1367 	ret = amdgpu_bo_reserve(vm->root.bo, true);
1368 	if (ret)
1369 		goto reserve_pd_fail;
1370 	ret = vm_validate_pt_pd_bos(vm);
1371 	if (ret) {
1372 		pr_err("validate_pt_pd_bos() failed\n");
1373 		goto validate_pd_fail;
1374 	}
1375 	ret = amdgpu_bo_sync_wait(vm->root.bo,
1376 				  AMDGPU_FENCE_OWNER_KFD, false);
1377 	if (ret)
1378 		goto wait_pd_fail;
1379 	ret = dma_resv_reserve_fences(vm->root.bo->tbo.base.resv, 1);
1380 	if (ret)
1381 		goto reserve_shared_fail;
1382 	dma_resv_add_fence(vm->root.bo->tbo.base.resv,
1383 			   &vm->process_info->eviction_fence->base,
1384 			   DMA_RESV_USAGE_BOOKKEEP);
1385 	amdgpu_bo_unreserve(vm->root.bo);
1386 
1387 	/* Update process info */
1388 	mutex_lock(&vm->process_info->lock);
1389 	list_add_tail(&vm->vm_list_node,
1390 			&(vm->process_info->vm_list_head));
1391 	vm->process_info->n_vms++;
1392 	mutex_unlock(&vm->process_info->lock);
1393 
1394 	return 0;
1395 
1396 reserve_shared_fail:
1397 wait_pd_fail:
1398 validate_pd_fail:
1399 	amdgpu_bo_unreserve(vm->root.bo);
1400 reserve_pd_fail:
1401 	vm->process_info = NULL;
1402 	if (info) {
1403 		/* Two fence references: one in info and one in *ef */
1404 		dma_fence_put(&info->eviction_fence->base);
1405 		dma_fence_put(*ef);
1406 		*ef = NULL;
1407 		*process_info = NULL;
1408 		put_pid(info->pid);
1409 create_evict_fence_fail:
1410 		mutex_destroy(&info->lock);
1411 		mutex_destroy(&info->notifier_lock);
1412 		kfree(info);
1413 	}
1414 	return ret;
1415 }
1416 
1417 /**
1418  * amdgpu_amdkfd_gpuvm_pin_bo() - Pins a BO using following criteria
1419  * @bo: Handle of buffer object being pinned
1420  * @domain: Domain into which BO should be pinned
1421  *
1422  *   - USERPTR BOs are UNPINNABLE and will return error
1423  *   - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their
1424  *     PIN count incremented. It is valid to PIN a BO multiple times
1425  *
1426  * Return: ZERO if successful in pinning, Non-Zero in case of error.
1427  */
1428 static int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain)
1429 {
1430 	int ret = 0;
1431 
1432 	ret = amdgpu_bo_reserve(bo, false);
1433 	if (unlikely(ret))
1434 		return ret;
1435 
1436 	ret = amdgpu_bo_pin_restricted(bo, domain, 0, 0);
1437 	if (ret)
1438 		pr_err("Error in Pinning BO to domain: %d\n", domain);
1439 
1440 	amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
1441 	amdgpu_bo_unreserve(bo);
1442 
1443 	return ret;
1444 }
1445 
1446 /**
1447  * amdgpu_amdkfd_gpuvm_unpin_bo() - Unpins BO using following criteria
1448  * @bo: Handle of buffer object being unpinned
1449  *
1450  *   - Is a illegal request for USERPTR BOs and is ignored
1451  *   - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their
1452  *     PIN count decremented. Calls to UNPIN must balance calls to PIN
1453  */
1454 static void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo)
1455 {
1456 	int ret = 0;
1457 
1458 	ret = amdgpu_bo_reserve(bo, false);
1459 	if (unlikely(ret))
1460 		return;
1461 
1462 	amdgpu_bo_unpin(bo);
1463 	amdgpu_bo_unreserve(bo);
1464 }
1465 
1466 int amdgpu_amdkfd_gpuvm_set_vm_pasid(struct amdgpu_device *adev,
1467 				     struct amdgpu_vm *avm, u32 pasid)
1468 
1469 {
1470 	int ret;
1471 
1472 	/* Free the original amdgpu allocated pasid,
1473 	 * will be replaced with kfd allocated pasid.
1474 	 */
1475 	if (avm->pasid) {
1476 		amdgpu_pasid_free(avm->pasid);
1477 		amdgpu_vm_set_pasid(adev, avm, 0);
1478 	}
1479 
1480 	ret = amdgpu_vm_set_pasid(adev, avm, pasid);
1481 	if (ret)
1482 		return ret;
1483 
1484 	return 0;
1485 }
1486 
1487 int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,
1488 					   struct amdgpu_vm *avm,
1489 					   void **process_info,
1490 					   struct dma_fence **ef)
1491 {
1492 	int ret;
1493 
1494 	/* Already a compute VM? */
1495 	if (avm->process_info)
1496 		return -EINVAL;
1497 
1498 	/* Convert VM into a compute VM */
1499 	ret = amdgpu_vm_make_compute(adev, avm);
1500 	if (ret)
1501 		return ret;
1502 
1503 	/* Initialize KFD part of the VM and process info */
1504 	ret = init_kfd_vm(avm, process_info, ef);
1505 	if (ret)
1506 		return ret;
1507 
1508 	amdgpu_vm_set_task_info(avm);
1509 
1510 	return 0;
1511 }
1512 
1513 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
1514 				    struct amdgpu_vm *vm)
1515 {
1516 	struct amdkfd_process_info *process_info = vm->process_info;
1517 
1518 	if (!process_info)
1519 		return;
1520 
1521 	/* Update process info */
1522 	mutex_lock(&process_info->lock);
1523 	process_info->n_vms--;
1524 	list_del(&vm->vm_list_node);
1525 	mutex_unlock(&process_info->lock);
1526 
1527 	vm->process_info = NULL;
1528 
1529 	/* Release per-process resources when last compute VM is destroyed */
1530 	if (!process_info->n_vms) {
1531 		WARN_ON(!list_empty(&process_info->kfd_bo_list));
1532 		WARN_ON(!list_empty(&process_info->userptr_valid_list));
1533 		WARN_ON(!list_empty(&process_info->userptr_inval_list));
1534 
1535 		dma_fence_put(&process_info->eviction_fence->base);
1536 		cancel_delayed_work_sync(&process_info->restore_userptr_work);
1537 		put_pid(process_info->pid);
1538 		mutex_destroy(&process_info->lock);
1539 		mutex_destroy(&process_info->notifier_lock);
1540 		kfree(process_info);
1541 	}
1542 }
1543 
1544 void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev,
1545 					    void *drm_priv)
1546 {
1547 	struct amdgpu_vm *avm;
1548 
1549 	if (WARN_ON(!adev || !drm_priv))
1550 		return;
1551 
1552 	avm = drm_priv_to_vm(drm_priv);
1553 
1554 	pr_debug("Releasing process vm %p\n", avm);
1555 
1556 	/* The original pasid of amdgpu vm has already been
1557 	 * released during making a amdgpu vm to a compute vm
1558 	 * The current pasid is managed by kfd and will be
1559 	 * released on kfd process destroy. Set amdgpu pasid
1560 	 * to 0 to avoid duplicate release.
1561 	 */
1562 	amdgpu_vm_release_compute(adev, avm);
1563 }
1564 
1565 uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv)
1566 {
1567 	struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1568 	struct amdgpu_bo *pd = avm->root.bo;
1569 	struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
1570 
1571 	if (adev->asic_type < CHIP_VEGA10)
1572 		return avm->pd_phys_addr >> AMDGPU_GPU_PAGE_SHIFT;
1573 	return avm->pd_phys_addr;
1574 }
1575 
1576 void amdgpu_amdkfd_block_mmu_notifications(void *p)
1577 {
1578 	struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p;
1579 
1580 	mutex_lock(&pinfo->lock);
1581 	WRITE_ONCE(pinfo->block_mmu_notifications, true);
1582 	mutex_unlock(&pinfo->lock);
1583 }
1584 
1585 int amdgpu_amdkfd_criu_resume(void *p)
1586 {
1587 	int ret = 0;
1588 	struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p;
1589 
1590 	mutex_lock(&pinfo->lock);
1591 	pr_debug("scheduling work\n");
1592 	mutex_lock(&pinfo->notifier_lock);
1593 	pinfo->evicted_bos++;
1594 	mutex_unlock(&pinfo->notifier_lock);
1595 	if (!READ_ONCE(pinfo->block_mmu_notifications)) {
1596 		ret = -EINVAL;
1597 		goto out_unlock;
1598 	}
1599 	WRITE_ONCE(pinfo->block_mmu_notifications, false);
1600 	schedule_delayed_work(&pinfo->restore_userptr_work, 0);
1601 
1602 out_unlock:
1603 	mutex_unlock(&pinfo->lock);
1604 	return ret;
1605 }
1606 
1607 size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev,
1608 					  uint8_t xcp_id)
1609 {
1610 	uint64_t reserved_for_pt =
1611 		ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
1612 	ssize_t available;
1613 	uint64_t vram_available, system_mem_available, ttm_mem_available;
1614 
1615 	spin_lock(&kfd_mem_limit.mem_limit_lock);
1616 	vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id)
1617 		- adev->kfd.vram_used_aligned[xcp_id]
1618 		- atomic64_read(&adev->vram_pin_size)
1619 		- reserved_for_pt;
1620 
1621 	if (adev->gmc.is_app_apu) {
1622 		system_mem_available = no_system_mem_limit ?
1623 					kfd_mem_limit.max_system_mem_limit :
1624 					kfd_mem_limit.max_system_mem_limit -
1625 					kfd_mem_limit.system_mem_used;
1626 
1627 		ttm_mem_available = kfd_mem_limit.max_ttm_mem_limit -
1628 				kfd_mem_limit.ttm_mem_used;
1629 
1630 		available = min3(system_mem_available, ttm_mem_available,
1631 				 vram_available);
1632 		available = ALIGN_DOWN(available, PAGE_SIZE);
1633 	} else {
1634 		available = ALIGN_DOWN(vram_available, VRAM_AVAILABLITY_ALIGN);
1635 	}
1636 
1637 	spin_unlock(&kfd_mem_limit.mem_limit_lock);
1638 
1639 	if (available < 0)
1640 		available = 0;
1641 
1642 	return available;
1643 }
1644 
1645 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
1646 		struct amdgpu_device *adev, uint64_t va, uint64_t size,
1647 		void *drm_priv, struct kgd_mem **mem,
1648 		uint64_t *offset, uint32_t flags, bool criu_resume)
1649 {
1650 	struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1651 	struct amdgpu_fpriv *fpriv = container_of(avm, struct amdgpu_fpriv, vm);
1652 	enum ttm_bo_type bo_type = ttm_bo_type_device;
1653 	struct sg_table *sg = NULL;
1654 	uint64_t user_addr = 0;
1655 	struct amdgpu_bo *bo;
1656 	struct drm_gem_object *gobj = NULL;
1657 	u32 domain, alloc_domain;
1658 	uint64_t aligned_size;
1659 	int8_t xcp_id = -1;
1660 	u64 alloc_flags;
1661 	int ret;
1662 
1663 	/*
1664 	 * Check on which domain to allocate BO
1665 	 */
1666 	if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
1667 		domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM;
1668 
1669 		if (adev->gmc.is_app_apu) {
1670 			domain = AMDGPU_GEM_DOMAIN_GTT;
1671 			alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
1672 			alloc_flags = 0;
1673 		} else {
1674 			alloc_flags = AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
1675 			alloc_flags |= (flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) ?
1676 			AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED : 0;
1677 		}
1678 		xcp_id = fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION ?
1679 					0 : fpriv->xcp_id;
1680 	} else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
1681 		domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
1682 		alloc_flags = 0;
1683 	} else {
1684 		domain = AMDGPU_GEM_DOMAIN_GTT;
1685 		alloc_domain = AMDGPU_GEM_DOMAIN_CPU;
1686 		alloc_flags = AMDGPU_GEM_CREATE_PREEMPTIBLE;
1687 
1688 		if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
1689 			if (!offset || !*offset)
1690 				return -EINVAL;
1691 			user_addr = untagged_addr(*offset);
1692 		} else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1693 				    KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1694 			bo_type = ttm_bo_type_sg;
1695 			if (size > UINT_MAX)
1696 				return -EINVAL;
1697 			sg = create_sg_table(*offset, size);
1698 			if (!sg)
1699 				return -ENOMEM;
1700 		} else {
1701 			return -EINVAL;
1702 		}
1703 	}
1704 
1705 	if (flags & KFD_IOC_ALLOC_MEM_FLAGS_COHERENT)
1706 		alloc_flags |= AMDGPU_GEM_CREATE_COHERENT;
1707 	if (flags & KFD_IOC_ALLOC_MEM_FLAGS_EXT_COHERENT)
1708 		alloc_flags |= AMDGPU_GEM_CREATE_EXT_COHERENT;
1709 	if (flags & KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED)
1710 		alloc_flags |= AMDGPU_GEM_CREATE_UNCACHED;
1711 
1712 	*mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
1713 	if (!*mem) {
1714 		ret = -ENOMEM;
1715 		goto err;
1716 	}
1717 	INIT_LIST_HEAD(&(*mem)->attachments);
1718 	mutex_init(&(*mem)->lock);
1719 	(*mem)->aql_queue = !!(flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM);
1720 
1721 	/* Workaround for AQL queue wraparound bug. Map the same
1722 	 * memory twice. That means we only actually allocate half
1723 	 * the memory.
1724 	 */
1725 	if ((*mem)->aql_queue)
1726 		size >>= 1;
1727 	aligned_size = PAGE_ALIGN(size);
1728 
1729 	(*mem)->alloc_flags = flags;
1730 
1731 	amdgpu_sync_create(&(*mem)->sync);
1732 
1733 	ret = amdgpu_amdkfd_reserve_mem_limit(adev, aligned_size, flags,
1734 					      xcp_id);
1735 	if (ret) {
1736 		pr_debug("Insufficient memory\n");
1737 		goto err_reserve_limit;
1738 	}
1739 
1740 	pr_debug("\tcreate BO VA 0x%llx size 0x%llx domain %s xcp_id %d\n",
1741 		 va, (*mem)->aql_queue ? size << 1 : size,
1742 		 domain_string(alloc_domain), xcp_id);
1743 
1744 	ret = amdgpu_gem_object_create(adev, aligned_size, 1, alloc_domain, alloc_flags,
1745 				       bo_type, NULL, &gobj, xcp_id + 1);
1746 	if (ret) {
1747 		pr_debug("Failed to create BO on domain %s. ret %d\n",
1748 			 domain_string(alloc_domain), ret);
1749 		goto err_bo_create;
1750 	}
1751 	ret = drm_vma_node_allow(&gobj->vma_node, drm_priv);
1752 	if (ret) {
1753 		pr_debug("Failed to allow vma node access. ret %d\n", ret);
1754 		goto err_node_allow;
1755 	}
1756 	bo = gem_to_amdgpu_bo(gobj);
1757 	if (bo_type == ttm_bo_type_sg) {
1758 		bo->tbo.sg = sg;
1759 		bo->tbo.ttm->sg = sg;
1760 	}
1761 	bo->kfd_bo = *mem;
1762 	(*mem)->bo = bo;
1763 	if (user_addr)
1764 		bo->flags |= AMDGPU_AMDKFD_CREATE_USERPTR_BO;
1765 
1766 	(*mem)->va = va;
1767 	(*mem)->domain = domain;
1768 	(*mem)->mapped_to_gpu_memory = 0;
1769 	(*mem)->process_info = avm->process_info;
1770 
1771 	add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, user_addr);
1772 
1773 	if (user_addr) {
1774 		pr_debug("creating userptr BO for user_addr = %llx\n", user_addr);
1775 		ret = init_user_pages(*mem, user_addr, criu_resume);
1776 		if (ret)
1777 			goto allocate_init_user_pages_failed;
1778 	} else  if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1779 				KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1780 		ret = amdgpu_amdkfd_gpuvm_pin_bo(bo, AMDGPU_GEM_DOMAIN_GTT);
1781 		if (ret) {
1782 			pr_err("Pinning MMIO/DOORBELL BO during ALLOC FAILED\n");
1783 			goto err_pin_bo;
1784 		}
1785 		bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
1786 		bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
1787 	}
1788 
1789 	if (offset)
1790 		*offset = amdgpu_bo_mmap_offset(bo);
1791 
1792 	return 0;
1793 
1794 allocate_init_user_pages_failed:
1795 err_pin_bo:
1796 	remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
1797 	drm_vma_node_revoke(&gobj->vma_node, drm_priv);
1798 err_node_allow:
1799 	/* Don't unreserve system mem limit twice */
1800 	goto err_reserve_limit;
1801 err_bo_create:
1802 	amdgpu_amdkfd_unreserve_mem_limit(adev, aligned_size, flags, xcp_id);
1803 err_reserve_limit:
1804 	mutex_destroy(&(*mem)->lock);
1805 	if (gobj)
1806 		drm_gem_object_put(gobj);
1807 	else
1808 		kfree(*mem);
1809 err:
1810 	if (sg) {
1811 		sg_free_table(sg);
1812 		kfree(sg);
1813 	}
1814 	return ret;
1815 }
1816 
1817 int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
1818 		struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv,
1819 		uint64_t *size)
1820 {
1821 	struct amdkfd_process_info *process_info = mem->process_info;
1822 	unsigned long bo_size = mem->bo->tbo.base.size;
1823 	bool use_release_notifier = (mem->bo->kfd_bo == mem);
1824 	struct kfd_mem_attachment *entry, *tmp;
1825 	struct bo_vm_reservation_context ctx;
1826 	unsigned int mapped_to_gpu_memory;
1827 	int ret;
1828 	bool is_imported = false;
1829 
1830 	mutex_lock(&mem->lock);
1831 
1832 	/* Unpin MMIO/DOORBELL BO's that were pinned during allocation */
1833 	if (mem->alloc_flags &
1834 	    (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1835 	     KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1836 		amdgpu_amdkfd_gpuvm_unpin_bo(mem->bo);
1837 	}
1838 
1839 	mapped_to_gpu_memory = mem->mapped_to_gpu_memory;
1840 	is_imported = mem->is_imported;
1841 	mutex_unlock(&mem->lock);
1842 	/* lock is not needed after this, since mem is unused and will
1843 	 * be freed anyway
1844 	 */
1845 
1846 	if (mapped_to_gpu_memory > 0) {
1847 		pr_debug("BO VA 0x%llx size 0x%lx is still mapped.\n",
1848 				mem->va, bo_size);
1849 		return -EBUSY;
1850 	}
1851 
1852 	/* Make sure restore workers don't access the BO any more */
1853 	mutex_lock(&process_info->lock);
1854 	list_del(&mem->validate_list);
1855 	mutex_unlock(&process_info->lock);
1856 
1857 	/* Cleanup user pages and MMU notifiers */
1858 	if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
1859 		amdgpu_hmm_unregister(mem->bo);
1860 		mutex_lock(&process_info->notifier_lock);
1861 		amdgpu_ttm_tt_discard_user_pages(mem->bo->tbo.ttm, mem->range);
1862 		mutex_unlock(&process_info->notifier_lock);
1863 	}
1864 
1865 	ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx);
1866 	if (unlikely(ret))
1867 		return ret;
1868 
1869 	/* The eviction fence should be removed by the last unmap.
1870 	 * TODO: Log an error condition if the bo still has the eviction fence
1871 	 * attached
1872 	 */
1873 	amdgpu_amdkfd_remove_eviction_fence(mem->bo,
1874 					process_info->eviction_fence);
1875 	pr_debug("Release VA 0x%llx - 0x%llx\n", mem->va,
1876 		mem->va + bo_size * (1 + mem->aql_queue));
1877 
1878 	/* Remove from VM internal data structures */
1879 	list_for_each_entry_safe(entry, tmp, &mem->attachments, list) {
1880 		kfd_mem_dmaunmap_attachment(mem, entry);
1881 		kfd_mem_detach(entry);
1882 	}
1883 
1884 	ret = unreserve_bo_and_vms(&ctx, false, false);
1885 
1886 	/* Free the sync object */
1887 	amdgpu_sync_free(&mem->sync);
1888 
1889 	/* If the SG is not NULL, it's one we created for a doorbell or mmio
1890 	 * remap BO. We need to free it.
1891 	 */
1892 	if (mem->bo->tbo.sg) {
1893 		sg_free_table(mem->bo->tbo.sg);
1894 		kfree(mem->bo->tbo.sg);
1895 	}
1896 
1897 	/* Update the size of the BO being freed if it was allocated from
1898 	 * VRAM and is not imported. For APP APU VRAM allocations are done
1899 	 * in GTT domain
1900 	 */
1901 	if (size) {
1902 		if (!is_imported &&
1903 		   (mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_VRAM ||
1904 		   (adev->gmc.is_app_apu &&
1905 		    mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_GTT)))
1906 			*size = bo_size;
1907 		else
1908 			*size = 0;
1909 	}
1910 
1911 	/* Free the BO*/
1912 	drm_vma_node_revoke(&mem->bo->tbo.base.vma_node, drm_priv);
1913 	if (mem->dmabuf)
1914 		dma_buf_put(mem->dmabuf);
1915 	mutex_destroy(&mem->lock);
1916 
1917 	/* If this releases the last reference, it will end up calling
1918 	 * amdgpu_amdkfd_release_notify and kfree the mem struct. That's why
1919 	 * this needs to be the last call here.
1920 	 */
1921 	drm_gem_object_put(&mem->bo->tbo.base);
1922 
1923 	/*
1924 	 * For kgd_mem allocated in amdgpu_amdkfd_gpuvm_import_dmabuf(),
1925 	 * explicitly free it here.
1926 	 */
1927 	if (!use_release_notifier)
1928 		kfree(mem);
1929 
1930 	return ret;
1931 }
1932 
1933 int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
1934 		struct amdgpu_device *adev, struct kgd_mem *mem,
1935 		void *drm_priv)
1936 {
1937 	struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1938 	int ret;
1939 	struct amdgpu_bo *bo;
1940 	uint32_t domain;
1941 	struct kfd_mem_attachment *entry;
1942 	struct bo_vm_reservation_context ctx;
1943 	unsigned long bo_size;
1944 	bool is_invalid_userptr = false;
1945 
1946 	bo = mem->bo;
1947 	if (!bo) {
1948 		pr_err("Invalid BO when mapping memory to GPU\n");
1949 		return -EINVAL;
1950 	}
1951 
1952 	/* Make sure restore is not running concurrently. Since we
1953 	 * don't map invalid userptr BOs, we rely on the next restore
1954 	 * worker to do the mapping
1955 	 */
1956 	mutex_lock(&mem->process_info->lock);
1957 
1958 	/* Lock notifier lock. If we find an invalid userptr BO, we can be
1959 	 * sure that the MMU notifier is no longer running
1960 	 * concurrently and the queues are actually stopped
1961 	 */
1962 	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
1963 		mutex_lock(&mem->process_info->notifier_lock);
1964 		is_invalid_userptr = !!mem->invalid;
1965 		mutex_unlock(&mem->process_info->notifier_lock);
1966 	}
1967 
1968 	mutex_lock(&mem->lock);
1969 
1970 	domain = mem->domain;
1971 	bo_size = bo->tbo.base.size;
1972 
1973 	pr_debug("Map VA 0x%llx - 0x%llx to vm %p domain %s\n",
1974 			mem->va,
1975 			mem->va + bo_size * (1 + mem->aql_queue),
1976 			avm, domain_string(domain));
1977 
1978 	if (!kfd_mem_is_attached(avm, mem)) {
1979 		ret = kfd_mem_attach(adev, mem, avm, mem->aql_queue);
1980 		if (ret)
1981 			goto out;
1982 	}
1983 
1984 	ret = reserve_bo_and_vm(mem, avm, &ctx);
1985 	if (unlikely(ret))
1986 		goto out;
1987 
1988 	/* Userptr can be marked as "not invalid", but not actually be
1989 	 * validated yet (still in the system domain). In that case
1990 	 * the queues are still stopped and we can leave mapping for
1991 	 * the next restore worker
1992 	 */
1993 	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) &&
1994 	    bo->tbo.resource->mem_type == TTM_PL_SYSTEM)
1995 		is_invalid_userptr = true;
1996 
1997 	ret = vm_validate_pt_pd_bos(avm);
1998 	if (unlikely(ret))
1999 		goto out_unreserve;
2000 
2001 	if (mem->mapped_to_gpu_memory == 0 &&
2002 	    !amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
2003 		/* Validate BO only once. The eviction fence gets added to BO
2004 		 * the first time it is mapped. Validate will wait for all
2005 		 * background evictions to complete.
2006 		 */
2007 		ret = amdgpu_amdkfd_bo_validate(bo, domain, true);
2008 		if (ret) {
2009 			pr_debug("Validate failed\n");
2010 			goto out_unreserve;
2011 		}
2012 	}
2013 
2014 	list_for_each_entry(entry, &mem->attachments, list) {
2015 		if (entry->bo_va->base.vm != avm || entry->is_mapped)
2016 			continue;
2017 
2018 		pr_debug("\t map VA 0x%llx - 0x%llx in entry %p\n",
2019 			 entry->va, entry->va + bo_size, entry);
2020 
2021 		ret = map_bo_to_gpuvm(mem, entry, ctx.sync,
2022 				      is_invalid_userptr);
2023 		if (ret) {
2024 			pr_err("Failed to map bo to gpuvm\n");
2025 			goto out_unreserve;
2026 		}
2027 
2028 		ret = vm_update_pds(avm, ctx.sync);
2029 		if (ret) {
2030 			pr_err("Failed to update page directories\n");
2031 			goto out_unreserve;
2032 		}
2033 
2034 		entry->is_mapped = true;
2035 		mem->mapped_to_gpu_memory++;
2036 		pr_debug("\t INC mapping count %d\n",
2037 			 mem->mapped_to_gpu_memory);
2038 	}
2039 
2040 	if (!amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) && !bo->tbo.pin_count)
2041 		dma_resv_add_fence(bo->tbo.base.resv,
2042 				   &avm->process_info->eviction_fence->base,
2043 				   DMA_RESV_USAGE_BOOKKEEP);
2044 	ret = unreserve_bo_and_vms(&ctx, false, false);
2045 
2046 	goto out;
2047 
2048 out_unreserve:
2049 	unreserve_bo_and_vms(&ctx, false, false);
2050 out:
2051 	mutex_unlock(&mem->process_info->lock);
2052 	mutex_unlock(&mem->lock);
2053 	return ret;
2054 }
2055 
2056 void amdgpu_amdkfd_gpuvm_dmaunmap_mem(struct kgd_mem *mem, void *drm_priv)
2057 {
2058 	struct kfd_mem_attachment *entry;
2059 	struct amdgpu_vm *vm;
2060 
2061 	vm = drm_priv_to_vm(drm_priv);
2062 
2063 	mutex_lock(&mem->lock);
2064 
2065 	list_for_each_entry(entry, &mem->attachments, list) {
2066 		if (entry->bo_va->base.vm == vm)
2067 			kfd_mem_dmaunmap_attachment(mem, entry);
2068 	}
2069 
2070 	mutex_unlock(&mem->lock);
2071 }
2072 
2073 int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
2074 		struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv)
2075 {
2076 	struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
2077 	struct amdkfd_process_info *process_info = avm->process_info;
2078 	unsigned long bo_size = mem->bo->tbo.base.size;
2079 	struct kfd_mem_attachment *entry;
2080 	struct bo_vm_reservation_context ctx;
2081 	int ret;
2082 
2083 	mutex_lock(&mem->lock);
2084 
2085 	ret = reserve_bo_and_cond_vms(mem, avm, BO_VM_MAPPED, &ctx);
2086 	if (unlikely(ret))
2087 		goto out;
2088 	/* If no VMs were reserved, it means the BO wasn't actually mapped */
2089 	if (ctx.n_vms == 0) {
2090 		ret = -EINVAL;
2091 		goto unreserve_out;
2092 	}
2093 
2094 	ret = vm_validate_pt_pd_bos(avm);
2095 	if (unlikely(ret))
2096 		goto unreserve_out;
2097 
2098 	pr_debug("Unmap VA 0x%llx - 0x%llx from vm %p\n",
2099 		mem->va,
2100 		mem->va + bo_size * (1 + mem->aql_queue),
2101 		avm);
2102 
2103 	list_for_each_entry(entry, &mem->attachments, list) {
2104 		if (entry->bo_va->base.vm != avm || !entry->is_mapped)
2105 			continue;
2106 
2107 		pr_debug("\t unmap VA 0x%llx - 0x%llx from entry %p\n",
2108 			 entry->va, entry->va + bo_size, entry);
2109 
2110 		unmap_bo_from_gpuvm(mem, entry, ctx.sync);
2111 		entry->is_mapped = false;
2112 
2113 		mem->mapped_to_gpu_memory--;
2114 		pr_debug("\t DEC mapping count %d\n",
2115 			 mem->mapped_to_gpu_memory);
2116 	}
2117 
2118 	/* If BO is unmapped from all VMs, unfence it. It can be evicted if
2119 	 * required.
2120 	 */
2121 	if (mem->mapped_to_gpu_memory == 0 &&
2122 	    !amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) &&
2123 	    !mem->bo->tbo.pin_count)
2124 		amdgpu_amdkfd_remove_eviction_fence(mem->bo,
2125 						process_info->eviction_fence);
2126 
2127 unreserve_out:
2128 	unreserve_bo_and_vms(&ctx, false, false);
2129 out:
2130 	mutex_unlock(&mem->lock);
2131 	return ret;
2132 }
2133 
2134 int amdgpu_amdkfd_gpuvm_sync_memory(
2135 		struct amdgpu_device *adev, struct kgd_mem *mem, bool intr)
2136 {
2137 	struct amdgpu_sync sync;
2138 	int ret;
2139 
2140 	amdgpu_sync_create(&sync);
2141 
2142 	mutex_lock(&mem->lock);
2143 	amdgpu_sync_clone(&mem->sync, &sync);
2144 	mutex_unlock(&mem->lock);
2145 
2146 	ret = amdgpu_sync_wait(&sync, intr);
2147 	amdgpu_sync_free(&sync);
2148 	return ret;
2149 }
2150 
2151 /**
2152  * amdgpu_amdkfd_map_gtt_bo_to_gart - Map BO to GART and increment reference count
2153  * @adev: Device to which allocated BO belongs
2154  * @bo: Buffer object to be mapped
2155  *
2156  * Before return, bo reference count is incremented. To release the reference and unpin/
2157  * unmap the BO, call amdgpu_amdkfd_free_gtt_mem.
2158  */
2159 int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct amdgpu_bo *bo)
2160 {
2161 	int ret;
2162 
2163 	ret = amdgpu_bo_reserve(bo, true);
2164 	if (ret) {
2165 		pr_err("Failed to reserve bo. ret %d\n", ret);
2166 		goto err_reserve_bo_failed;
2167 	}
2168 
2169 	ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
2170 	if (ret) {
2171 		pr_err("Failed to pin bo. ret %d\n", ret);
2172 		goto err_pin_bo_failed;
2173 	}
2174 
2175 	ret = amdgpu_ttm_alloc_gart(&bo->tbo);
2176 	if (ret) {
2177 		pr_err("Failed to bind bo to GART. ret %d\n", ret);
2178 		goto err_map_bo_gart_failed;
2179 	}
2180 
2181 	amdgpu_amdkfd_remove_eviction_fence(
2182 		bo, bo->vm_bo->vm->process_info->eviction_fence);
2183 
2184 	amdgpu_bo_unreserve(bo);
2185 
2186 	bo = amdgpu_bo_ref(bo);
2187 
2188 	return 0;
2189 
2190 err_map_bo_gart_failed:
2191 	amdgpu_bo_unpin(bo);
2192 err_pin_bo_failed:
2193 	amdgpu_bo_unreserve(bo);
2194 err_reserve_bo_failed:
2195 
2196 	return ret;
2197 }
2198 
2199 /** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Map a GTT BO for kernel CPU access
2200  *
2201  * @mem: Buffer object to be mapped for CPU access
2202  * @kptr[out]: pointer in kernel CPU address space
2203  * @size[out]: size of the buffer
2204  *
2205  * Pins the BO and maps it for kernel CPU access. The eviction fence is removed
2206  * from the BO, since pinned BOs cannot be evicted. The bo must remain on the
2207  * validate_list, so the GPU mapping can be restored after a page table was
2208  * evicted.
2209  *
2210  * Return: 0 on success, error code on failure
2211  */
2212 int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem,
2213 					     void **kptr, uint64_t *size)
2214 {
2215 	int ret;
2216 	struct amdgpu_bo *bo = mem->bo;
2217 
2218 	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
2219 		pr_err("userptr can't be mapped to kernel\n");
2220 		return -EINVAL;
2221 	}
2222 
2223 	mutex_lock(&mem->process_info->lock);
2224 
2225 	ret = amdgpu_bo_reserve(bo, true);
2226 	if (ret) {
2227 		pr_err("Failed to reserve bo. ret %d\n", ret);
2228 		goto bo_reserve_failed;
2229 	}
2230 
2231 	ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
2232 	if (ret) {
2233 		pr_err("Failed to pin bo. ret %d\n", ret);
2234 		goto pin_failed;
2235 	}
2236 
2237 	ret = amdgpu_bo_kmap(bo, kptr);
2238 	if (ret) {
2239 		pr_err("Failed to map bo to kernel. ret %d\n", ret);
2240 		goto kmap_failed;
2241 	}
2242 
2243 	amdgpu_amdkfd_remove_eviction_fence(
2244 		bo, mem->process_info->eviction_fence);
2245 
2246 	if (size)
2247 		*size = amdgpu_bo_size(bo);
2248 
2249 	amdgpu_bo_unreserve(bo);
2250 
2251 	mutex_unlock(&mem->process_info->lock);
2252 	return 0;
2253 
2254 kmap_failed:
2255 	amdgpu_bo_unpin(bo);
2256 pin_failed:
2257 	amdgpu_bo_unreserve(bo);
2258 bo_reserve_failed:
2259 	mutex_unlock(&mem->process_info->lock);
2260 
2261 	return ret;
2262 }
2263 
2264 /** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Unmap a GTT BO for kernel CPU access
2265  *
2266  * @mem: Buffer object to be unmapped for CPU access
2267  *
2268  * Removes the kernel CPU mapping and unpins the BO. It does not restore the
2269  * eviction fence, so this function should only be used for cleanup before the
2270  * BO is destroyed.
2271  */
2272 void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem)
2273 {
2274 	struct amdgpu_bo *bo = mem->bo;
2275 
2276 	amdgpu_bo_reserve(bo, true);
2277 	amdgpu_bo_kunmap(bo);
2278 	amdgpu_bo_unpin(bo);
2279 	amdgpu_bo_unreserve(bo);
2280 }
2281 
2282 int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev,
2283 					  struct kfd_vm_fault_info *mem)
2284 {
2285 	if (atomic_read(&adev->gmc.vm_fault_info_updated) == 1) {
2286 		*mem = *adev->gmc.vm_fault_info;
2287 		mb(); /* make sure read happened */
2288 		atomic_set(&adev->gmc.vm_fault_info_updated, 0);
2289 	}
2290 	return 0;
2291 }
2292 
2293 int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev,
2294 				      struct dma_buf *dma_buf,
2295 				      uint64_t va, void *drm_priv,
2296 				      struct kgd_mem **mem, uint64_t *size,
2297 				      uint64_t *mmap_offset)
2298 {
2299 	struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
2300 	struct drm_gem_object *obj;
2301 	struct amdgpu_bo *bo;
2302 	int ret;
2303 
2304 	obj = amdgpu_gem_prime_import(adev_to_drm(adev), dma_buf);
2305 	if (IS_ERR(obj))
2306 		return PTR_ERR(obj);
2307 
2308 	bo = gem_to_amdgpu_bo(obj);
2309 	if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
2310 				    AMDGPU_GEM_DOMAIN_GTT))) {
2311 		/* Only VRAM and GTT BOs are supported */
2312 		ret = -EINVAL;
2313 		goto err_put_obj;
2314 	}
2315 
2316 	*mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
2317 	if (!*mem) {
2318 		ret = -ENOMEM;
2319 		goto err_put_obj;
2320 	}
2321 
2322 	ret = drm_vma_node_allow(&obj->vma_node, drm_priv);
2323 	if (ret)
2324 		goto err_free_mem;
2325 
2326 	if (size)
2327 		*size = amdgpu_bo_size(bo);
2328 
2329 	if (mmap_offset)
2330 		*mmap_offset = amdgpu_bo_mmap_offset(bo);
2331 
2332 	INIT_LIST_HEAD(&(*mem)->attachments);
2333 	mutex_init(&(*mem)->lock);
2334 
2335 	(*mem)->alloc_flags =
2336 		((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
2337 		KFD_IOC_ALLOC_MEM_FLAGS_VRAM : KFD_IOC_ALLOC_MEM_FLAGS_GTT)
2338 		| KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE
2339 		| KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE;
2340 
2341 	get_dma_buf(dma_buf);
2342 	(*mem)->dmabuf = dma_buf;
2343 	(*mem)->bo = bo;
2344 	(*mem)->va = va;
2345 	(*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) && !adev->gmc.is_app_apu ?
2346 		AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT;
2347 
2348 	(*mem)->mapped_to_gpu_memory = 0;
2349 	(*mem)->process_info = avm->process_info;
2350 	add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, false);
2351 	amdgpu_sync_create(&(*mem)->sync);
2352 	(*mem)->is_imported = true;
2353 
2354 	return 0;
2355 
2356 err_free_mem:
2357 	kfree(*mem);
2358 err_put_obj:
2359 	drm_gem_object_put(obj);
2360 	return ret;
2361 }
2362 
2363 int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem,
2364 				      struct dma_buf **dma_buf)
2365 {
2366 	int ret;
2367 
2368 	mutex_lock(&mem->lock);
2369 	ret = kfd_mem_export_dmabuf(mem);
2370 	if (ret)
2371 		goto out;
2372 
2373 	get_dma_buf(mem->dmabuf);
2374 	*dma_buf = mem->dmabuf;
2375 out:
2376 	mutex_unlock(&mem->lock);
2377 	return ret;
2378 }
2379 
2380 /* Evict a userptr BO by stopping the queues if necessary
2381  *
2382  * Runs in MMU notifier, may be in RECLAIM_FS context. This means it
2383  * cannot do any memory allocations, and cannot take any locks that
2384  * are held elsewhere while allocating memory.
2385  *
2386  * It doesn't do anything to the BO itself. The real work happens in
2387  * restore, where we get updated page addresses. This function only
2388  * ensures that GPU access to the BO is stopped.
2389  */
2390 int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,
2391 				unsigned long cur_seq, struct kgd_mem *mem)
2392 {
2393 	struct amdkfd_process_info *process_info = mem->process_info;
2394 	int r = 0;
2395 
2396 	/* Do not process MMU notifications during CRIU restore until
2397 	 * KFD_CRIU_OP_RESUME IOCTL is received
2398 	 */
2399 	if (READ_ONCE(process_info->block_mmu_notifications))
2400 		return 0;
2401 
2402 	mutex_lock(&process_info->notifier_lock);
2403 	mmu_interval_set_seq(mni, cur_seq);
2404 
2405 	mem->invalid++;
2406 	if (++process_info->evicted_bos == 1) {
2407 		/* First eviction, stop the queues */
2408 		r = kgd2kfd_quiesce_mm(mni->mm,
2409 				       KFD_QUEUE_EVICTION_TRIGGER_USERPTR);
2410 		if (r)
2411 			pr_err("Failed to quiesce KFD\n");
2412 		schedule_delayed_work(&process_info->restore_userptr_work,
2413 			msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
2414 	}
2415 	mutex_unlock(&process_info->notifier_lock);
2416 
2417 	return r;
2418 }
2419 
2420 /* Update invalid userptr BOs
2421  *
2422  * Moves invalidated (evicted) userptr BOs from userptr_valid_list to
2423  * userptr_inval_list and updates user pages for all BOs that have
2424  * been invalidated since their last update.
2425  */
2426 static int update_invalid_user_pages(struct amdkfd_process_info *process_info,
2427 				     struct mm_struct *mm)
2428 {
2429 	struct kgd_mem *mem, *tmp_mem;
2430 	struct amdgpu_bo *bo;
2431 	struct ttm_operation_ctx ctx = { false, false };
2432 	uint32_t invalid;
2433 	int ret = 0;
2434 
2435 	mutex_lock(&process_info->notifier_lock);
2436 
2437 	/* Move all invalidated BOs to the userptr_inval_list */
2438 	list_for_each_entry_safe(mem, tmp_mem,
2439 				 &process_info->userptr_valid_list,
2440 				 validate_list)
2441 		if (mem->invalid)
2442 			list_move_tail(&mem->validate_list,
2443 				       &process_info->userptr_inval_list);
2444 
2445 	/* Go through userptr_inval_list and update any invalid user_pages */
2446 	list_for_each_entry(mem, &process_info->userptr_inval_list,
2447 			    validate_list) {
2448 		invalid = mem->invalid;
2449 		if (!invalid)
2450 			/* BO hasn't been invalidated since the last
2451 			 * revalidation attempt. Keep its page list.
2452 			 */
2453 			continue;
2454 
2455 		bo = mem->bo;
2456 
2457 		amdgpu_ttm_tt_discard_user_pages(bo->tbo.ttm, mem->range);
2458 		mem->range = NULL;
2459 
2460 		/* BO reservations and getting user pages (hmm_range_fault)
2461 		 * must happen outside the notifier lock
2462 		 */
2463 		mutex_unlock(&process_info->notifier_lock);
2464 
2465 		/* Move the BO to system (CPU) domain if necessary to unmap
2466 		 * and free the SG table
2467 		 */
2468 		if (bo->tbo.resource->mem_type != TTM_PL_SYSTEM) {
2469 			if (amdgpu_bo_reserve(bo, true))
2470 				return -EAGAIN;
2471 			amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
2472 			ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2473 			amdgpu_bo_unreserve(bo);
2474 			if (ret) {
2475 				pr_err("%s: Failed to invalidate userptr BO\n",
2476 				       __func__);
2477 				return -EAGAIN;
2478 			}
2479 		}
2480 
2481 		/* Get updated user pages */
2482 		ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages,
2483 						   &mem->range);
2484 		if (ret) {
2485 			pr_debug("Failed %d to get user pages\n", ret);
2486 
2487 			/* Return -EFAULT bad address error as success. It will
2488 			 * fail later with a VM fault if the GPU tries to access
2489 			 * it. Better than hanging indefinitely with stalled
2490 			 * user mode queues.
2491 			 *
2492 			 * Return other error -EBUSY or -ENOMEM to retry restore
2493 			 */
2494 			if (ret != -EFAULT)
2495 				return ret;
2496 
2497 			ret = 0;
2498 		}
2499 
2500 		mutex_lock(&process_info->notifier_lock);
2501 
2502 		/* Mark the BO as valid unless it was invalidated
2503 		 * again concurrently.
2504 		 */
2505 		if (mem->invalid != invalid) {
2506 			ret = -EAGAIN;
2507 			goto unlock_out;
2508 		}
2509 		 /* set mem valid if mem has hmm range associated */
2510 		if (mem->range)
2511 			mem->invalid = 0;
2512 	}
2513 
2514 unlock_out:
2515 	mutex_unlock(&process_info->notifier_lock);
2516 
2517 	return ret;
2518 }
2519 
2520 /* Validate invalid userptr BOs
2521  *
2522  * Validates BOs on the userptr_inval_list. Also updates GPUVM page tables
2523  * with new page addresses and waits for the page table updates to complete.
2524  */
2525 static int validate_invalid_user_pages(struct amdkfd_process_info *process_info)
2526 {
2527 	struct ttm_operation_ctx ctx = { false, false };
2528 	struct amdgpu_sync sync;
2529 	struct drm_exec exec;
2530 
2531 	struct amdgpu_vm *peer_vm;
2532 	struct kgd_mem *mem, *tmp_mem;
2533 	struct amdgpu_bo *bo;
2534 	int ret;
2535 
2536 	amdgpu_sync_create(&sync);
2537 
2538 	drm_exec_init(&exec, 0);
2539 	/* Reserve all BOs and page tables for validation */
2540 	drm_exec_until_all_locked(&exec) {
2541 		/* Reserve all the page directories */
2542 		list_for_each_entry(peer_vm, &process_info->vm_list_head,
2543 				    vm_list_node) {
2544 			ret = amdgpu_vm_lock_pd(peer_vm, &exec, 2);
2545 			drm_exec_retry_on_contention(&exec);
2546 			if (unlikely(ret))
2547 				goto unreserve_out;
2548 		}
2549 
2550 		/* Reserve the userptr_inval_list entries to resv_list */
2551 		list_for_each_entry(mem, &process_info->userptr_inval_list,
2552 				    validate_list) {
2553 			struct drm_gem_object *gobj;
2554 
2555 			gobj = &mem->bo->tbo.base;
2556 			ret = drm_exec_prepare_obj(&exec, gobj, 1);
2557 			drm_exec_retry_on_contention(&exec);
2558 			if (unlikely(ret))
2559 				goto unreserve_out;
2560 		}
2561 	}
2562 
2563 	ret = process_validate_vms(process_info);
2564 	if (ret)
2565 		goto unreserve_out;
2566 
2567 	/* Validate BOs and update GPUVM page tables */
2568 	list_for_each_entry_safe(mem, tmp_mem,
2569 				 &process_info->userptr_inval_list,
2570 				 validate_list) {
2571 		struct kfd_mem_attachment *attachment;
2572 
2573 		bo = mem->bo;
2574 
2575 		/* Validate the BO if we got user pages */
2576 		if (bo->tbo.ttm->pages[0]) {
2577 			amdgpu_bo_placement_from_domain(bo, mem->domain);
2578 			ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2579 			if (ret) {
2580 				pr_err("%s: failed to validate BO\n", __func__);
2581 				goto unreserve_out;
2582 			}
2583 		}
2584 
2585 		/* Update mapping. If the BO was not validated
2586 		 * (because we couldn't get user pages), this will
2587 		 * clear the page table entries, which will result in
2588 		 * VM faults if the GPU tries to access the invalid
2589 		 * memory.
2590 		 */
2591 		list_for_each_entry(attachment, &mem->attachments, list) {
2592 			if (!attachment->is_mapped)
2593 				continue;
2594 
2595 			kfd_mem_dmaunmap_attachment(mem, attachment);
2596 			ret = update_gpuvm_pte(mem, attachment, &sync);
2597 			if (ret) {
2598 				pr_err("%s: update PTE failed\n", __func__);
2599 				/* make sure this gets validated again */
2600 				mutex_lock(&process_info->notifier_lock);
2601 				mem->invalid++;
2602 				mutex_unlock(&process_info->notifier_lock);
2603 				goto unreserve_out;
2604 			}
2605 		}
2606 	}
2607 
2608 	/* Update page directories */
2609 	ret = process_update_pds(process_info, &sync);
2610 
2611 unreserve_out:
2612 	drm_exec_fini(&exec);
2613 	amdgpu_sync_wait(&sync, false);
2614 	amdgpu_sync_free(&sync);
2615 
2616 	return ret;
2617 }
2618 
2619 /* Confirm that all user pages are valid while holding the notifier lock
2620  *
2621  * Moves valid BOs from the userptr_inval_list back to userptr_val_list.
2622  */
2623 static int confirm_valid_user_pages_locked(struct amdkfd_process_info *process_info)
2624 {
2625 	struct kgd_mem *mem, *tmp_mem;
2626 	int ret = 0;
2627 
2628 	list_for_each_entry_safe(mem, tmp_mem,
2629 				 &process_info->userptr_inval_list,
2630 				 validate_list) {
2631 		bool valid;
2632 
2633 		/* keep mem without hmm range at userptr_inval_list */
2634 		if (!mem->range)
2635 			 continue;
2636 
2637 		/* Only check mem with hmm range associated */
2638 		valid = amdgpu_ttm_tt_get_user_pages_done(
2639 					mem->bo->tbo.ttm, mem->range);
2640 
2641 		mem->range = NULL;
2642 		if (!valid) {
2643 			WARN(!mem->invalid, "Invalid BO not marked invalid");
2644 			ret = -EAGAIN;
2645 			continue;
2646 		}
2647 
2648 		if (mem->invalid) {
2649 			WARN(1, "Valid BO is marked invalid");
2650 			ret = -EAGAIN;
2651 			continue;
2652 		}
2653 
2654 		list_move_tail(&mem->validate_list,
2655 			       &process_info->userptr_valid_list);
2656 	}
2657 
2658 	return ret;
2659 }
2660 
2661 /* Worker callback to restore evicted userptr BOs
2662  *
2663  * Tries to update and validate all userptr BOs. If successful and no
2664  * concurrent evictions happened, the queues are restarted. Otherwise,
2665  * reschedule for another attempt later.
2666  */
2667 static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work)
2668 {
2669 	struct delayed_work *dwork = to_delayed_work(work);
2670 	struct amdkfd_process_info *process_info =
2671 		container_of(dwork, struct amdkfd_process_info,
2672 			     restore_userptr_work);
2673 	struct task_struct *usertask;
2674 	struct mm_struct *mm;
2675 	uint32_t evicted_bos;
2676 
2677 	mutex_lock(&process_info->notifier_lock);
2678 	evicted_bos = process_info->evicted_bos;
2679 	mutex_unlock(&process_info->notifier_lock);
2680 	if (!evicted_bos)
2681 		return;
2682 
2683 	/* Reference task and mm in case of concurrent process termination */
2684 	usertask = get_pid_task(process_info->pid, PIDTYPE_PID);
2685 	if (!usertask)
2686 		return;
2687 	mm = get_task_mm(usertask);
2688 	if (!mm) {
2689 		put_task_struct(usertask);
2690 		return;
2691 	}
2692 
2693 	mutex_lock(&process_info->lock);
2694 
2695 	if (update_invalid_user_pages(process_info, mm))
2696 		goto unlock_out;
2697 	/* userptr_inval_list can be empty if all evicted userptr BOs
2698 	 * have been freed. In that case there is nothing to validate
2699 	 * and we can just restart the queues.
2700 	 */
2701 	if (!list_empty(&process_info->userptr_inval_list)) {
2702 		if (validate_invalid_user_pages(process_info))
2703 			goto unlock_out;
2704 	}
2705 	/* Final check for concurrent evicton and atomic update. If
2706 	 * another eviction happens after successful update, it will
2707 	 * be a first eviction that calls quiesce_mm. The eviction
2708 	 * reference counting inside KFD will handle this case.
2709 	 */
2710 	mutex_lock(&process_info->notifier_lock);
2711 	if (process_info->evicted_bos != evicted_bos)
2712 		goto unlock_notifier_out;
2713 
2714 	if (confirm_valid_user_pages_locked(process_info)) {
2715 		WARN(1, "User pages unexpectedly invalid");
2716 		goto unlock_notifier_out;
2717 	}
2718 
2719 	process_info->evicted_bos = evicted_bos = 0;
2720 
2721 	if (kgd2kfd_resume_mm(mm)) {
2722 		pr_err("%s: Failed to resume KFD\n", __func__);
2723 		/* No recovery from this failure. Probably the CP is
2724 		 * hanging. No point trying again.
2725 		 */
2726 	}
2727 
2728 unlock_notifier_out:
2729 	mutex_unlock(&process_info->notifier_lock);
2730 unlock_out:
2731 	mutex_unlock(&process_info->lock);
2732 
2733 	/* If validation failed, reschedule another attempt */
2734 	if (evicted_bos) {
2735 		schedule_delayed_work(&process_info->restore_userptr_work,
2736 			msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
2737 
2738 		kfd_smi_event_queue_restore_rescheduled(mm);
2739 	}
2740 	mmput(mm);
2741 	put_task_struct(usertask);
2742 }
2743 
2744 /** amdgpu_amdkfd_gpuvm_restore_process_bos - Restore all BOs for the given
2745  *   KFD process identified by process_info
2746  *
2747  * @process_info: amdkfd_process_info of the KFD process
2748  *
2749  * After memory eviction, restore thread calls this function. The function
2750  * should be called when the Process is still valid. BO restore involves -
2751  *
2752  * 1.  Release old eviction fence and create new one
2753  * 2.  Get two copies of PD BO list from all the VMs. Keep one copy as pd_list.
2754  * 3   Use the second PD list and kfd_bo_list to create a list (ctx.list) of
2755  *     BOs that need to be reserved.
2756  * 4.  Reserve all the BOs
2757  * 5.  Validate of PD and PT BOs.
2758  * 6.  Validate all KFD BOs using kfd_bo_list and Map them and add new fence
2759  * 7.  Add fence to all PD and PT BOs.
2760  * 8.  Unreserve all BOs
2761  */
2762 int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef)
2763 {
2764 	struct amdkfd_process_info *process_info = info;
2765 	struct amdgpu_vm *peer_vm;
2766 	struct kgd_mem *mem;
2767 	struct amdgpu_amdkfd_fence *new_fence;
2768 	struct list_head duplicate_save;
2769 	struct amdgpu_sync sync_obj;
2770 	unsigned long failed_size = 0;
2771 	unsigned long total_size = 0;
2772 	struct drm_exec exec;
2773 	int ret;
2774 
2775 	INIT_LIST_HEAD(&duplicate_save);
2776 
2777 	mutex_lock(&process_info->lock);
2778 
2779 	drm_exec_init(&exec, 0);
2780 	drm_exec_until_all_locked(&exec) {
2781 		list_for_each_entry(peer_vm, &process_info->vm_list_head,
2782 				    vm_list_node) {
2783 			ret = amdgpu_vm_lock_pd(peer_vm, &exec, 2);
2784 			drm_exec_retry_on_contention(&exec);
2785 			if (unlikely(ret))
2786 				goto ttm_reserve_fail;
2787 		}
2788 
2789 		/* Reserve all BOs and page tables/directory. Add all BOs from
2790 		 * kfd_bo_list to ctx.list
2791 		 */
2792 		list_for_each_entry(mem, &process_info->kfd_bo_list,
2793 				    validate_list) {
2794 			struct drm_gem_object *gobj;
2795 
2796 			gobj = &mem->bo->tbo.base;
2797 			ret = drm_exec_prepare_obj(&exec, gobj, 1);
2798 			drm_exec_retry_on_contention(&exec);
2799 			if (unlikely(ret))
2800 				goto ttm_reserve_fail;
2801 		}
2802 	}
2803 
2804 	amdgpu_sync_create(&sync_obj);
2805 
2806 	/* Validate PDs and PTs */
2807 	ret = process_validate_vms(process_info);
2808 	if (ret)
2809 		goto validate_map_fail;
2810 
2811 	ret = process_sync_pds_resv(process_info, &sync_obj);
2812 	if (ret) {
2813 		pr_debug("Memory eviction: Failed to sync to PD BO moving fence. Try again\n");
2814 		goto validate_map_fail;
2815 	}
2816 
2817 	/* Validate BOs and map them to GPUVM (update VM page tables). */
2818 	list_for_each_entry(mem, &process_info->kfd_bo_list,
2819 			    validate_list) {
2820 
2821 		struct amdgpu_bo *bo = mem->bo;
2822 		uint32_t domain = mem->domain;
2823 		struct kfd_mem_attachment *attachment;
2824 		struct dma_resv_iter cursor;
2825 		struct dma_fence *fence;
2826 
2827 		total_size += amdgpu_bo_size(bo);
2828 
2829 		ret = amdgpu_amdkfd_bo_validate(bo, domain, false);
2830 		if (ret) {
2831 			pr_debug("Memory eviction: Validate BOs failed\n");
2832 			failed_size += amdgpu_bo_size(bo);
2833 			ret = amdgpu_amdkfd_bo_validate(bo,
2834 						AMDGPU_GEM_DOMAIN_GTT, false);
2835 			if (ret) {
2836 				pr_debug("Memory eviction: Try again\n");
2837 				goto validate_map_fail;
2838 			}
2839 		}
2840 		dma_resv_for_each_fence(&cursor, bo->tbo.base.resv,
2841 					DMA_RESV_USAGE_KERNEL, fence) {
2842 			ret = amdgpu_sync_fence(&sync_obj, fence);
2843 			if (ret) {
2844 				pr_debug("Memory eviction: Sync BO fence failed. Try again\n");
2845 				goto validate_map_fail;
2846 			}
2847 		}
2848 		list_for_each_entry(attachment, &mem->attachments, list) {
2849 			if (!attachment->is_mapped)
2850 				continue;
2851 
2852 			if (attachment->bo_va->base.bo->tbo.pin_count)
2853 				continue;
2854 
2855 			kfd_mem_dmaunmap_attachment(mem, attachment);
2856 			ret = update_gpuvm_pte(mem, attachment, &sync_obj);
2857 			if (ret) {
2858 				pr_debug("Memory eviction: update PTE failed. Try again\n");
2859 				goto validate_map_fail;
2860 			}
2861 		}
2862 	}
2863 
2864 	if (failed_size)
2865 		pr_debug("0x%lx/0x%lx in system\n", failed_size, total_size);
2866 
2867 	/* Update page directories */
2868 	ret = process_update_pds(process_info, &sync_obj);
2869 	if (ret) {
2870 		pr_debug("Memory eviction: update PDs failed. Try again\n");
2871 		goto validate_map_fail;
2872 	}
2873 
2874 	/* Wait for validate and PT updates to finish */
2875 	amdgpu_sync_wait(&sync_obj, false);
2876 
2877 	/* Release old eviction fence and create new one, because fence only
2878 	 * goes from unsignaled to signaled, fence cannot be reused.
2879 	 * Use context and mm from the old fence.
2880 	 */
2881 	new_fence = amdgpu_amdkfd_fence_create(
2882 				process_info->eviction_fence->base.context,
2883 				process_info->eviction_fence->mm,
2884 				NULL);
2885 	if (!new_fence) {
2886 		pr_err("Failed to create eviction fence\n");
2887 		ret = -ENOMEM;
2888 		goto validate_map_fail;
2889 	}
2890 	dma_fence_put(&process_info->eviction_fence->base);
2891 	process_info->eviction_fence = new_fence;
2892 	*ef = dma_fence_get(&new_fence->base);
2893 
2894 	/* Attach new eviction fence to all BOs except pinned ones */
2895 	list_for_each_entry(mem, &process_info->kfd_bo_list, validate_list) {
2896 		if (mem->bo->tbo.pin_count)
2897 			continue;
2898 
2899 		dma_resv_add_fence(mem->bo->tbo.base.resv,
2900 				   &process_info->eviction_fence->base,
2901 				   DMA_RESV_USAGE_BOOKKEEP);
2902 	}
2903 	/* Attach eviction fence to PD / PT BOs */
2904 	list_for_each_entry(peer_vm, &process_info->vm_list_head,
2905 			    vm_list_node) {
2906 		struct amdgpu_bo *bo = peer_vm->root.bo;
2907 
2908 		dma_resv_add_fence(bo->tbo.base.resv,
2909 				   &process_info->eviction_fence->base,
2910 				   DMA_RESV_USAGE_BOOKKEEP);
2911 	}
2912 
2913 validate_map_fail:
2914 	amdgpu_sync_free(&sync_obj);
2915 ttm_reserve_fail:
2916 	drm_exec_fini(&exec);
2917 	mutex_unlock(&process_info->lock);
2918 	return ret;
2919 }
2920 
2921 int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem)
2922 {
2923 	struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
2924 	struct amdgpu_bo *gws_bo = (struct amdgpu_bo *)gws;
2925 	int ret;
2926 
2927 	if (!info || !gws)
2928 		return -EINVAL;
2929 
2930 	*mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
2931 	if (!*mem)
2932 		return -ENOMEM;
2933 
2934 	mutex_init(&(*mem)->lock);
2935 	INIT_LIST_HEAD(&(*mem)->attachments);
2936 	(*mem)->bo = amdgpu_bo_ref(gws_bo);
2937 	(*mem)->domain = AMDGPU_GEM_DOMAIN_GWS;
2938 	(*mem)->process_info = process_info;
2939 	add_kgd_mem_to_kfd_bo_list(*mem, process_info, false);
2940 	amdgpu_sync_create(&(*mem)->sync);
2941 
2942 
2943 	/* Validate gws bo the first time it is added to process */
2944 	mutex_lock(&(*mem)->process_info->lock);
2945 	ret = amdgpu_bo_reserve(gws_bo, false);
2946 	if (unlikely(ret)) {
2947 		pr_err("Reserve gws bo failed %d\n", ret);
2948 		goto bo_reservation_failure;
2949 	}
2950 
2951 	ret = amdgpu_amdkfd_bo_validate(gws_bo, AMDGPU_GEM_DOMAIN_GWS, true);
2952 	if (ret) {
2953 		pr_err("GWS BO validate failed %d\n", ret);
2954 		goto bo_validation_failure;
2955 	}
2956 	/* GWS resource is shared b/t amdgpu and amdkfd
2957 	 * Add process eviction fence to bo so they can
2958 	 * evict each other.
2959 	 */
2960 	ret = dma_resv_reserve_fences(gws_bo->tbo.base.resv, 1);
2961 	if (ret)
2962 		goto reserve_shared_fail;
2963 	dma_resv_add_fence(gws_bo->tbo.base.resv,
2964 			   &process_info->eviction_fence->base,
2965 			   DMA_RESV_USAGE_BOOKKEEP);
2966 	amdgpu_bo_unreserve(gws_bo);
2967 	mutex_unlock(&(*mem)->process_info->lock);
2968 
2969 	return ret;
2970 
2971 reserve_shared_fail:
2972 bo_validation_failure:
2973 	amdgpu_bo_unreserve(gws_bo);
2974 bo_reservation_failure:
2975 	mutex_unlock(&(*mem)->process_info->lock);
2976 	amdgpu_sync_free(&(*mem)->sync);
2977 	remove_kgd_mem_from_kfd_bo_list(*mem, process_info);
2978 	amdgpu_bo_unref(&gws_bo);
2979 	mutex_destroy(&(*mem)->lock);
2980 	kfree(*mem);
2981 	*mem = NULL;
2982 	return ret;
2983 }
2984 
2985 int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem)
2986 {
2987 	int ret;
2988 	struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
2989 	struct kgd_mem *kgd_mem = (struct kgd_mem *)mem;
2990 	struct amdgpu_bo *gws_bo = kgd_mem->bo;
2991 
2992 	/* Remove BO from process's validate list so restore worker won't touch
2993 	 * it anymore
2994 	 */
2995 	remove_kgd_mem_from_kfd_bo_list(kgd_mem, process_info);
2996 
2997 	ret = amdgpu_bo_reserve(gws_bo, false);
2998 	if (unlikely(ret)) {
2999 		pr_err("Reserve gws bo failed %d\n", ret);
3000 		//TODO add BO back to validate_list?
3001 		return ret;
3002 	}
3003 	amdgpu_amdkfd_remove_eviction_fence(gws_bo,
3004 			process_info->eviction_fence);
3005 	amdgpu_bo_unreserve(gws_bo);
3006 	amdgpu_sync_free(&kgd_mem->sync);
3007 	amdgpu_bo_unref(&gws_bo);
3008 	mutex_destroy(&kgd_mem->lock);
3009 	kfree(mem);
3010 	return 0;
3011 }
3012 
3013 /* Returns GPU-specific tiling mode information */
3014 int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,
3015 				struct tile_config *config)
3016 {
3017 	config->gb_addr_config = adev->gfx.config.gb_addr_config;
3018 	config->tile_config_ptr = adev->gfx.config.tile_mode_array;
3019 	config->num_tile_configs =
3020 			ARRAY_SIZE(adev->gfx.config.tile_mode_array);
3021 	config->macro_tile_config_ptr =
3022 			adev->gfx.config.macrotile_mode_array;
3023 	config->num_macro_tile_configs =
3024 			ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
3025 
3026 	/* Those values are not set from GFX9 onwards */
3027 	config->num_banks = adev->gfx.config.num_banks;
3028 	config->num_ranks = adev->gfx.config.num_ranks;
3029 
3030 	return 0;
3031 }
3032 
3033 bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem *mem)
3034 {
3035 	struct kfd_mem_attachment *entry;
3036 
3037 	list_for_each_entry(entry, &mem->attachments, list) {
3038 		if (entry->is_mapped && entry->adev == adev)
3039 			return true;
3040 	}
3041 	return false;
3042 }
3043 
3044 #if defined(CONFIG_DEBUG_FS)
3045 
3046 int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data)
3047 {
3048 
3049 	spin_lock(&kfd_mem_limit.mem_limit_lock);
3050 	seq_printf(m, "System mem used %lldM out of %lluM\n",
3051 		  (kfd_mem_limit.system_mem_used >> 20),
3052 		  (kfd_mem_limit.max_system_mem_limit >> 20));
3053 	seq_printf(m, "TTM mem used %lldM out of %lluM\n",
3054 		  (kfd_mem_limit.ttm_mem_used >> 20),
3055 		  (kfd_mem_limit.max_ttm_mem_limit >> 20));
3056 	spin_unlock(&kfd_mem_limit.mem_limit_lock);
3057 
3058 	return 0;
3059 }
3060 
3061 #endif
3062