1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/module.h> 24 #include <linux/fdtable.h> 25 #include <linux/uaccess.h> 26 #include <linux/firmware.h> 27 #include <drm/drmP.h> 28 #include "amdgpu.h" 29 #include "amdgpu_amdkfd.h" 30 #include "amdgpu_ucode.h" 31 #include "gfx_v8_0.h" 32 #include "gca/gfx_8_0_sh_mask.h" 33 #include "gca/gfx_8_0_d.h" 34 #include "gca/gfx_8_0_enum.h" 35 #include "oss/oss_3_0_sh_mask.h" 36 #include "oss/oss_3_0_d.h" 37 #include "gmc/gmc_8_1_sh_mask.h" 38 #include "gmc/gmc_8_1_d.h" 39 #include "vi_structs.h" 40 #include "vid.h" 41 42 enum hqd_dequeue_request_type { 43 NO_ACTION = 0, 44 DRAIN_PIPE, 45 RESET_WAVES 46 }; 47 48 struct vi_sdma_mqd; 49 50 /* 51 * Register access functions 52 */ 53 54 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 55 uint32_t sh_mem_config, 56 uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit, 57 uint32_t sh_mem_bases); 58 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, 59 unsigned int vmid); 60 static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id, 61 uint32_t hpd_size, uint64_t hpd_gpu_addr); 62 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id); 63 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 64 uint32_t queue_id, uint32_t __user *wptr, 65 uint32_t wptr_shift, uint32_t wptr_mask, 66 struct mm_struct *mm); 67 static int kgd_hqd_dump(struct kgd_dev *kgd, 68 uint32_t pipe_id, uint32_t queue_id, 69 uint32_t (**dump)[2], uint32_t *n_regs); 70 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, 71 uint32_t __user *wptr, struct mm_struct *mm); 72 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, 73 uint32_t engine_id, uint32_t queue_id, 74 uint32_t (**dump)[2], uint32_t *n_regs); 75 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, 76 uint32_t pipe_id, uint32_t queue_id); 77 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd); 78 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, 79 enum kfd_preempt_type reset_type, 80 unsigned int utimeout, uint32_t pipe_id, 81 uint32_t queue_id); 82 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, 83 unsigned int utimeout); 84 static int kgd_address_watch_disable(struct kgd_dev *kgd); 85 static int kgd_address_watch_execute(struct kgd_dev *kgd, 86 unsigned int watch_point_id, 87 uint32_t cntl_val, 88 uint32_t addr_hi, 89 uint32_t addr_lo); 90 static int kgd_wave_control_execute(struct kgd_dev *kgd, 91 uint32_t gfx_index_val, 92 uint32_t sq_cmd); 93 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, 94 unsigned int watch_point_id, 95 unsigned int reg_offset); 96 97 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, 98 uint8_t vmid); 99 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, 100 uint8_t vmid); 101 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type); 102 static void set_scratch_backing_va(struct kgd_dev *kgd, 103 uint64_t va, uint32_t vmid); 104 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, 105 uint32_t page_table_base); 106 static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid); 107 static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid); 108 109 /* Because of REG_GET_FIELD() being used, we put this function in the 110 * asic specific file. 111 */ 112 static int get_tile_config(struct kgd_dev *kgd, 113 struct tile_config *config) 114 { 115 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 116 117 config->gb_addr_config = adev->gfx.config.gb_addr_config; 118 config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, 119 MC_ARB_RAMCFG, NOOFBANK); 120 config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, 121 MC_ARB_RAMCFG, NOOFRANKS); 122 123 config->tile_config_ptr = adev->gfx.config.tile_mode_array; 124 config->num_tile_configs = 125 ARRAY_SIZE(adev->gfx.config.tile_mode_array); 126 config->macro_tile_config_ptr = 127 adev->gfx.config.macrotile_mode_array; 128 config->num_macro_tile_configs = 129 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); 130 131 return 0; 132 } 133 134 static const struct kfd2kgd_calls kfd2kgd = { 135 .init_gtt_mem_allocation = alloc_gtt_mem, 136 .free_gtt_mem = free_gtt_mem, 137 .get_local_mem_info = get_local_mem_info, 138 .get_gpu_clock_counter = get_gpu_clock_counter, 139 .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz, 140 .alloc_pasid = amdgpu_pasid_alloc, 141 .free_pasid = amdgpu_pasid_free, 142 .program_sh_mem_settings = kgd_program_sh_mem_settings, 143 .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping, 144 .init_pipeline = kgd_init_pipeline, 145 .init_interrupts = kgd_init_interrupts, 146 .hqd_load = kgd_hqd_load, 147 .hqd_sdma_load = kgd_hqd_sdma_load, 148 .hqd_dump = kgd_hqd_dump, 149 .hqd_sdma_dump = kgd_hqd_sdma_dump, 150 .hqd_is_occupied = kgd_hqd_is_occupied, 151 .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied, 152 .hqd_destroy = kgd_hqd_destroy, 153 .hqd_sdma_destroy = kgd_hqd_sdma_destroy, 154 .address_watch_disable = kgd_address_watch_disable, 155 .address_watch_execute = kgd_address_watch_execute, 156 .wave_control_execute = kgd_wave_control_execute, 157 .address_watch_get_offset = kgd_address_watch_get_offset, 158 .get_atc_vmid_pasid_mapping_pasid = 159 get_atc_vmid_pasid_mapping_pasid, 160 .get_atc_vmid_pasid_mapping_valid = 161 get_atc_vmid_pasid_mapping_valid, 162 .get_fw_version = get_fw_version, 163 .set_scratch_backing_va = set_scratch_backing_va, 164 .get_tile_config = get_tile_config, 165 .get_cu_info = get_cu_info, 166 .get_vram_usage = amdgpu_amdkfd_get_vram_usage, 167 .create_process_vm = amdgpu_amdkfd_gpuvm_create_process_vm, 168 .destroy_process_vm = amdgpu_amdkfd_gpuvm_destroy_process_vm, 169 .get_process_page_dir = amdgpu_amdkfd_gpuvm_get_process_page_dir, 170 .set_vm_context_page_table_base = set_vm_context_page_table_base, 171 .alloc_memory_of_gpu = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu, 172 .free_memory_of_gpu = amdgpu_amdkfd_gpuvm_free_memory_of_gpu, 173 .map_memory_to_gpu = amdgpu_amdkfd_gpuvm_map_memory_to_gpu, 174 .unmap_memory_to_gpu = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu, 175 .sync_memory = amdgpu_amdkfd_gpuvm_sync_memory, 176 .map_gtt_bo_to_kernel = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel, 177 .restore_process_bos = amdgpu_amdkfd_gpuvm_restore_process_bos, 178 .invalidate_tlbs = invalidate_tlbs, 179 .invalidate_tlbs_vmid = invalidate_tlbs_vmid, 180 .submit_ib = amdgpu_amdkfd_submit_ib, 181 }; 182 183 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void) 184 { 185 return (struct kfd2kgd_calls *)&kfd2kgd; 186 } 187 188 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd) 189 { 190 return (struct amdgpu_device *)kgd; 191 } 192 193 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe, 194 uint32_t queue, uint32_t vmid) 195 { 196 struct amdgpu_device *adev = get_amdgpu_device(kgd); 197 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue); 198 199 mutex_lock(&adev->srbm_mutex); 200 WREG32(mmSRBM_GFX_CNTL, value); 201 } 202 203 static void unlock_srbm(struct kgd_dev *kgd) 204 { 205 struct amdgpu_device *adev = get_amdgpu_device(kgd); 206 207 WREG32(mmSRBM_GFX_CNTL, 0); 208 mutex_unlock(&adev->srbm_mutex); 209 } 210 211 static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id, 212 uint32_t queue_id) 213 { 214 struct amdgpu_device *adev = get_amdgpu_device(kgd); 215 216 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 217 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 218 219 lock_srbm(kgd, mec, pipe, queue_id, 0); 220 } 221 222 static void release_queue(struct kgd_dev *kgd) 223 { 224 unlock_srbm(kgd); 225 } 226 227 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 228 uint32_t sh_mem_config, 229 uint32_t sh_mem_ape1_base, 230 uint32_t sh_mem_ape1_limit, 231 uint32_t sh_mem_bases) 232 { 233 struct amdgpu_device *adev = get_amdgpu_device(kgd); 234 235 lock_srbm(kgd, 0, 0, 0, vmid); 236 237 WREG32(mmSH_MEM_CONFIG, sh_mem_config); 238 WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base); 239 WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit); 240 WREG32(mmSH_MEM_BASES, sh_mem_bases); 241 242 unlock_srbm(kgd); 243 } 244 245 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, 246 unsigned int vmid) 247 { 248 struct amdgpu_device *adev = get_amdgpu_device(kgd); 249 250 /* 251 * We have to assume that there is no outstanding mapping. 252 * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because 253 * a mapping is in progress or because a mapping finished 254 * and the SW cleared it. 255 * So the protocol is to always wait & clear. 256 */ 257 uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid | 258 ATC_VMID0_PASID_MAPPING__VALID_MASK; 259 260 WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping); 261 262 while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid))) 263 cpu_relax(); 264 WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid); 265 266 /* Mapping vmid to pasid also for IH block */ 267 WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping); 268 269 return 0; 270 } 271 272 static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id, 273 uint32_t hpd_size, uint64_t hpd_gpu_addr) 274 { 275 /* amdgpu owns the per-pipe state */ 276 return 0; 277 } 278 279 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) 280 { 281 struct amdgpu_device *adev = get_amdgpu_device(kgd); 282 uint32_t mec; 283 uint32_t pipe; 284 285 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 286 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 287 288 lock_srbm(kgd, mec, pipe, 0, 0); 289 290 WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK); 291 292 unlock_srbm(kgd); 293 294 return 0; 295 } 296 297 static inline uint32_t get_sdma_base_addr(struct vi_sdma_mqd *m) 298 { 299 uint32_t retval; 300 301 retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET + 302 m->sdma_queue_id * KFD_VI_SDMA_QUEUE_OFFSET; 303 pr_debug("kfd: sdma base address: 0x%x\n", retval); 304 305 return retval; 306 } 307 308 static inline struct vi_mqd *get_mqd(void *mqd) 309 { 310 return (struct vi_mqd *)mqd; 311 } 312 313 static inline struct vi_sdma_mqd *get_sdma_mqd(void *mqd) 314 { 315 return (struct vi_sdma_mqd *)mqd; 316 } 317 318 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 319 uint32_t queue_id, uint32_t __user *wptr, 320 uint32_t wptr_shift, uint32_t wptr_mask, 321 struct mm_struct *mm) 322 { 323 struct amdgpu_device *adev = get_amdgpu_device(kgd); 324 struct vi_mqd *m; 325 uint32_t *mqd_hqd; 326 uint32_t reg, wptr_val, data; 327 bool valid_wptr = false; 328 329 m = get_mqd(mqd); 330 331 acquire_queue(kgd, pipe_id, queue_id); 332 333 /* HIQ is set during driver init period with vmid set to 0*/ 334 if (m->cp_hqd_vmid == 0) { 335 uint32_t value, mec, pipe; 336 337 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 338 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 339 340 pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n", 341 mec, pipe, queue_id); 342 value = RREG32(mmRLC_CP_SCHEDULERS); 343 value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1, 344 ((mec << 5) | (pipe << 3) | queue_id | 0x80)); 345 WREG32(mmRLC_CP_SCHEDULERS, value); 346 } 347 348 /* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */ 349 mqd_hqd = &m->cp_mqd_base_addr_lo; 350 351 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_CONTROL; reg++) 352 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); 353 354 /* Tonga errata: EOP RPTR/WPTR should be left unmodified. 355 * This is safe since EOP RPTR==WPTR for any inactive HQD 356 * on ASICs that do not support context-save. 357 * EOP writes/reads can start anywhere in the ring. 358 */ 359 if (get_amdgpu_device(kgd)->asic_type != CHIP_TONGA) { 360 WREG32(mmCP_HQD_EOP_RPTR, m->cp_hqd_eop_rptr); 361 WREG32(mmCP_HQD_EOP_WPTR, m->cp_hqd_eop_wptr); 362 WREG32(mmCP_HQD_EOP_WPTR_MEM, m->cp_hqd_eop_wptr_mem); 363 } 364 365 for (reg = mmCP_HQD_EOP_EVENTS; reg <= mmCP_HQD_ERROR; reg++) 366 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); 367 368 /* Copy userspace write pointer value to register. 369 * Activate doorbell logic to monitor subsequent changes. 370 */ 371 data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control, 372 CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); 373 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data); 374 375 /* read_user_ptr may take the mm->mmap_sem. 376 * release srbm_mutex to avoid circular dependency between 377 * srbm_mutex->mm_sem->reservation_ww_class_mutex->srbm_mutex. 378 */ 379 release_queue(kgd); 380 valid_wptr = read_user_wptr(mm, wptr, wptr_val); 381 acquire_queue(kgd, pipe_id, queue_id); 382 if (valid_wptr) 383 WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask); 384 385 data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1); 386 WREG32(mmCP_HQD_ACTIVE, data); 387 388 release_queue(kgd); 389 390 return 0; 391 } 392 393 static int kgd_hqd_dump(struct kgd_dev *kgd, 394 uint32_t pipe_id, uint32_t queue_id, 395 uint32_t (**dump)[2], uint32_t *n_regs) 396 { 397 struct amdgpu_device *adev = get_amdgpu_device(kgd); 398 uint32_t i = 0, reg; 399 #define HQD_N_REGS (54+4) 400 #define DUMP_REG(addr) do { \ 401 if (WARN_ON_ONCE(i >= HQD_N_REGS)) \ 402 break; \ 403 (*dump)[i][0] = (addr) << 2; \ 404 (*dump)[i++][1] = RREG32(addr); \ 405 } while (0) 406 407 *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); 408 if (*dump == NULL) 409 return -ENOMEM; 410 411 acquire_queue(kgd, pipe_id, queue_id); 412 413 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE0); 414 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE1); 415 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE2); 416 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE3); 417 418 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_DONES; reg++) 419 DUMP_REG(reg); 420 421 release_queue(kgd); 422 423 WARN_ON_ONCE(i != HQD_N_REGS); 424 *n_regs = i; 425 426 return 0; 427 } 428 429 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, 430 uint32_t __user *wptr, struct mm_struct *mm) 431 { 432 struct amdgpu_device *adev = get_amdgpu_device(kgd); 433 struct vi_sdma_mqd *m; 434 unsigned long end_jiffies; 435 uint32_t sdma_base_addr; 436 uint32_t data; 437 438 m = get_sdma_mqd(mqd); 439 sdma_base_addr = get_sdma_base_addr(m); 440 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, 441 m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)); 442 443 end_jiffies = msecs_to_jiffies(2000) + jiffies; 444 while (true) { 445 data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); 446 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 447 break; 448 if (time_after(jiffies, end_jiffies)) 449 return -ETIME; 450 usleep_range(500, 1000); 451 } 452 if (m->sdma_engine_id) { 453 data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL); 454 data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL, 455 RESUME_CTX, 0); 456 WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data); 457 } else { 458 data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL); 459 data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL, 460 RESUME_CTX, 0); 461 WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data); 462 } 463 464 data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL, 465 ENABLE, 1); 466 WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data); 467 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr); 468 469 if (read_user_wptr(mm, wptr, data)) 470 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data); 471 else 472 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 473 m->sdmax_rlcx_rb_rptr); 474 475 WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR, 476 m->sdmax_rlcx_virtual_addr); 477 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); 478 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI, 479 m->sdmax_rlcx_rb_base_hi); 480 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 481 m->sdmax_rlcx_rb_rptr_addr_lo); 482 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, 483 m->sdmax_rlcx_rb_rptr_addr_hi); 484 485 data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL, 486 RB_ENABLE, 1); 487 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data); 488 489 return 0; 490 } 491 492 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, 493 uint32_t engine_id, uint32_t queue_id, 494 uint32_t (**dump)[2], uint32_t *n_regs) 495 { 496 struct amdgpu_device *adev = get_amdgpu_device(kgd); 497 uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET + 498 queue_id * KFD_VI_SDMA_QUEUE_OFFSET; 499 uint32_t i = 0, reg; 500 #undef HQD_N_REGS 501 #define HQD_N_REGS (19+4+2+3+7) 502 503 *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); 504 if (*dump == NULL) 505 return -ENOMEM; 506 507 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) 508 DUMP_REG(sdma_offset + reg); 509 for (reg = mmSDMA0_RLC0_VIRTUAL_ADDR; reg <= mmSDMA0_RLC0_WATERMARK; 510 reg++) 511 DUMP_REG(sdma_offset + reg); 512 for (reg = mmSDMA0_RLC0_CSA_ADDR_LO; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; 513 reg++) 514 DUMP_REG(sdma_offset + reg); 515 for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; reg <= mmSDMA0_RLC0_DUMMY_REG; 516 reg++) 517 DUMP_REG(sdma_offset + reg); 518 for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; reg <= mmSDMA0_RLC0_MIDCMD_CNTL; 519 reg++) 520 DUMP_REG(sdma_offset + reg); 521 522 WARN_ON_ONCE(i != HQD_N_REGS); 523 *n_regs = i; 524 525 return 0; 526 } 527 528 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, 529 uint32_t pipe_id, uint32_t queue_id) 530 { 531 struct amdgpu_device *adev = get_amdgpu_device(kgd); 532 uint32_t act; 533 bool retval = false; 534 uint32_t low, high; 535 536 acquire_queue(kgd, pipe_id, queue_id); 537 act = RREG32(mmCP_HQD_ACTIVE); 538 if (act) { 539 low = lower_32_bits(queue_address >> 8); 540 high = upper_32_bits(queue_address >> 8); 541 542 if (low == RREG32(mmCP_HQD_PQ_BASE) && 543 high == RREG32(mmCP_HQD_PQ_BASE_HI)) 544 retval = true; 545 } 546 release_queue(kgd); 547 return retval; 548 } 549 550 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) 551 { 552 struct amdgpu_device *adev = get_amdgpu_device(kgd); 553 struct vi_sdma_mqd *m; 554 uint32_t sdma_base_addr; 555 uint32_t sdma_rlc_rb_cntl; 556 557 m = get_sdma_mqd(mqd); 558 sdma_base_addr = get_sdma_base_addr(m); 559 560 sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); 561 562 if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK) 563 return true; 564 565 return false; 566 } 567 568 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, 569 enum kfd_preempt_type reset_type, 570 unsigned int utimeout, uint32_t pipe_id, 571 uint32_t queue_id) 572 { 573 struct amdgpu_device *adev = get_amdgpu_device(kgd); 574 uint32_t temp; 575 enum hqd_dequeue_request_type type; 576 unsigned long flags, end_jiffies; 577 int retry; 578 struct vi_mqd *m = get_mqd(mqd); 579 580 acquire_queue(kgd, pipe_id, queue_id); 581 582 if (m->cp_hqd_vmid == 0) 583 WREG32_FIELD(RLC_CP_SCHEDULERS, scheduler1, 0); 584 585 switch (reset_type) { 586 case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN: 587 type = DRAIN_PIPE; 588 break; 589 case KFD_PREEMPT_TYPE_WAVEFRONT_RESET: 590 type = RESET_WAVES; 591 break; 592 default: 593 type = DRAIN_PIPE; 594 break; 595 } 596 597 /* Workaround: If IQ timer is active and the wait time is close to or 598 * equal to 0, dequeueing is not safe. Wait until either the wait time 599 * is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is 600 * cleared before continuing. Also, ensure wait times are set to at 601 * least 0x3. 602 */ 603 local_irq_save(flags); 604 preempt_disable(); 605 retry = 5000; /* wait for 500 usecs at maximum */ 606 while (true) { 607 temp = RREG32(mmCP_HQD_IQ_TIMER); 608 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { 609 pr_debug("HW is processing IQ\n"); 610 goto loop; 611 } 612 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { 613 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) 614 == 3) /* SEM-rearm is safe */ 615 break; 616 /* Wait time 3 is safe for CP, but our MMIO read/write 617 * time is close to 1 microsecond, so check for 10 to 618 * leave more buffer room 619 */ 620 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) 621 >= 10) 622 break; 623 pr_debug("IQ timer is active\n"); 624 } else 625 break; 626 loop: 627 if (!retry) { 628 pr_err("CP HQD IQ timer status time out\n"); 629 break; 630 } 631 ndelay(100); 632 --retry; 633 } 634 retry = 1000; 635 while (true) { 636 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); 637 if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK)) 638 break; 639 pr_debug("Dequeue request is pending\n"); 640 641 if (!retry) { 642 pr_err("CP HQD dequeue request time out\n"); 643 break; 644 } 645 ndelay(100); 646 --retry; 647 } 648 local_irq_restore(flags); 649 preempt_enable(); 650 651 WREG32(mmCP_HQD_DEQUEUE_REQUEST, type); 652 653 end_jiffies = (utimeout * HZ / 1000) + jiffies; 654 while (true) { 655 temp = RREG32(mmCP_HQD_ACTIVE); 656 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK)) 657 break; 658 if (time_after(jiffies, end_jiffies)) { 659 pr_err("cp queue preemption time out.\n"); 660 release_queue(kgd); 661 return -ETIME; 662 } 663 usleep_range(500, 1000); 664 } 665 666 release_queue(kgd); 667 return 0; 668 } 669 670 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, 671 unsigned int utimeout) 672 { 673 struct amdgpu_device *adev = get_amdgpu_device(kgd); 674 struct vi_sdma_mqd *m; 675 uint32_t sdma_base_addr; 676 uint32_t temp; 677 unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies; 678 679 m = get_sdma_mqd(mqd); 680 sdma_base_addr = get_sdma_base_addr(m); 681 682 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); 683 temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK; 684 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp); 685 686 while (true) { 687 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); 688 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 689 break; 690 if (time_after(jiffies, end_jiffies)) 691 return -ETIME; 692 usleep_range(500, 1000); 693 } 694 695 WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0); 696 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, 697 RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) | 698 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK); 699 700 m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR); 701 702 return 0; 703 } 704 705 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, 706 uint8_t vmid) 707 { 708 uint32_t reg; 709 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 710 711 reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); 712 return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK; 713 } 714 715 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, 716 uint8_t vmid) 717 { 718 uint32_t reg; 719 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 720 721 reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); 722 return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK; 723 } 724 725 static int kgd_address_watch_disable(struct kgd_dev *kgd) 726 { 727 return 0; 728 } 729 730 static int kgd_address_watch_execute(struct kgd_dev *kgd, 731 unsigned int watch_point_id, 732 uint32_t cntl_val, 733 uint32_t addr_hi, 734 uint32_t addr_lo) 735 { 736 return 0; 737 } 738 739 static int kgd_wave_control_execute(struct kgd_dev *kgd, 740 uint32_t gfx_index_val, 741 uint32_t sq_cmd) 742 { 743 struct amdgpu_device *adev = get_amdgpu_device(kgd); 744 uint32_t data = 0; 745 746 mutex_lock(&adev->grbm_idx_mutex); 747 748 WREG32(mmGRBM_GFX_INDEX, gfx_index_val); 749 WREG32(mmSQ_CMD, sq_cmd); 750 751 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 752 INSTANCE_BROADCAST_WRITES, 1); 753 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 754 SH_BROADCAST_WRITES, 1); 755 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 756 SE_BROADCAST_WRITES, 1); 757 758 WREG32(mmGRBM_GFX_INDEX, data); 759 mutex_unlock(&adev->grbm_idx_mutex); 760 761 return 0; 762 } 763 764 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, 765 unsigned int watch_point_id, 766 unsigned int reg_offset) 767 { 768 return 0; 769 } 770 771 static void set_scratch_backing_va(struct kgd_dev *kgd, 772 uint64_t va, uint32_t vmid) 773 { 774 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 775 776 lock_srbm(kgd, 0, 0, 0, vmid); 777 WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va); 778 unlock_srbm(kgd); 779 } 780 781 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type) 782 { 783 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 784 const union amdgpu_firmware_header *hdr; 785 786 switch (type) { 787 case KGD_ENGINE_PFP: 788 hdr = (const union amdgpu_firmware_header *) 789 adev->gfx.pfp_fw->data; 790 break; 791 792 case KGD_ENGINE_ME: 793 hdr = (const union amdgpu_firmware_header *) 794 adev->gfx.me_fw->data; 795 break; 796 797 case KGD_ENGINE_CE: 798 hdr = (const union amdgpu_firmware_header *) 799 adev->gfx.ce_fw->data; 800 break; 801 802 case KGD_ENGINE_MEC1: 803 hdr = (const union amdgpu_firmware_header *) 804 adev->gfx.mec_fw->data; 805 break; 806 807 case KGD_ENGINE_MEC2: 808 hdr = (const union amdgpu_firmware_header *) 809 adev->gfx.mec2_fw->data; 810 break; 811 812 case KGD_ENGINE_RLC: 813 hdr = (const union amdgpu_firmware_header *) 814 adev->gfx.rlc_fw->data; 815 break; 816 817 case KGD_ENGINE_SDMA1: 818 hdr = (const union amdgpu_firmware_header *) 819 adev->sdma.instance[0].fw->data; 820 break; 821 822 case KGD_ENGINE_SDMA2: 823 hdr = (const union amdgpu_firmware_header *) 824 adev->sdma.instance[1].fw->data; 825 break; 826 827 default: 828 return 0; 829 } 830 831 if (hdr == NULL) 832 return 0; 833 834 /* Only 12 bit in use*/ 835 return hdr->common.ucode_version; 836 } 837 838 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, 839 uint32_t page_table_base) 840 { 841 struct amdgpu_device *adev = get_amdgpu_device(kgd); 842 843 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) { 844 pr_err("trying to set page table base for wrong VMID\n"); 845 return; 846 } 847 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8, page_table_base); 848 } 849 850 static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid) 851 { 852 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 853 int vmid; 854 unsigned int tmp; 855 856 for (vmid = 0; vmid < 16; vmid++) { 857 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) 858 continue; 859 860 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); 861 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) && 862 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) { 863 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 864 RREG32(mmVM_INVALIDATE_RESPONSE); 865 break; 866 } 867 } 868 869 return 0; 870 } 871 872 static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid) 873 { 874 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 875 876 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) { 877 pr_err("non kfd vmid %d\n", vmid); 878 return -EINVAL; 879 } 880 881 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 882 RREG32(mmVM_INVALIDATE_RESPONSE); 883 return 0; 884 } 885