1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/fdtable.h> 24 #include <linux/uaccess.h> 25 #include <linux/firmware.h> 26 #include <drm/drmP.h> 27 #include "amdgpu.h" 28 #include "amdgpu_amdkfd.h" 29 #include "cikd.h" 30 #include "cik_sdma.h" 31 #include "amdgpu_ucode.h" 32 #include "gfx_v7_0.h" 33 #include "gca/gfx_7_2_d.h" 34 #include "gca/gfx_7_2_enum.h" 35 #include "gca/gfx_7_2_sh_mask.h" 36 #include "oss/oss_2_0_d.h" 37 #include "oss/oss_2_0_sh_mask.h" 38 #include "gmc/gmc_7_1_d.h" 39 #include "gmc/gmc_7_1_sh_mask.h" 40 #include "cik_structs.h" 41 42 enum hqd_dequeue_request_type { 43 NO_ACTION = 0, 44 DRAIN_PIPE, 45 RESET_WAVES 46 }; 47 48 enum { 49 MAX_TRAPID = 8, /* 3 bits in the bitfield. */ 50 MAX_WATCH_ADDRESSES = 4 51 }; 52 53 enum { 54 ADDRESS_WATCH_REG_ADDR_HI = 0, 55 ADDRESS_WATCH_REG_ADDR_LO, 56 ADDRESS_WATCH_REG_CNTL, 57 ADDRESS_WATCH_REG_MAX 58 }; 59 60 /* not defined in the CI/KV reg file */ 61 enum { 62 ADDRESS_WATCH_REG_CNTL_ATC_BIT = 0x10000000UL, 63 ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK = 0x00FFFFFF, 64 ADDRESS_WATCH_REG_ADDLOW_MASK_EXTENSION = 0x03000000, 65 /* extend the mask to 26 bits to match the low address field */ 66 ADDRESS_WATCH_REG_ADDLOW_SHIFT = 6, 67 ADDRESS_WATCH_REG_ADDHIGH_MASK = 0xFFFF 68 }; 69 70 static const uint32_t watchRegs[MAX_WATCH_ADDRESSES * ADDRESS_WATCH_REG_MAX] = { 71 mmTCP_WATCH0_ADDR_H, mmTCP_WATCH0_ADDR_L, mmTCP_WATCH0_CNTL, 72 mmTCP_WATCH1_ADDR_H, mmTCP_WATCH1_ADDR_L, mmTCP_WATCH1_CNTL, 73 mmTCP_WATCH2_ADDR_H, mmTCP_WATCH2_ADDR_L, mmTCP_WATCH2_CNTL, 74 mmTCP_WATCH3_ADDR_H, mmTCP_WATCH3_ADDR_L, mmTCP_WATCH3_CNTL 75 }; 76 77 union TCP_WATCH_CNTL_BITS { 78 struct { 79 uint32_t mask:24; 80 uint32_t vmid:4; 81 uint32_t atc:1; 82 uint32_t mode:2; 83 uint32_t valid:1; 84 } bitfields, bits; 85 uint32_t u32All; 86 signed int i32All; 87 float f32All; 88 }; 89 90 /* 91 * Register access functions 92 */ 93 94 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 95 uint32_t sh_mem_config, uint32_t sh_mem_ape1_base, 96 uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases); 97 98 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, 99 unsigned int vmid); 100 101 static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id, 102 uint32_t hpd_size, uint64_t hpd_gpu_addr); 103 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id); 104 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 105 uint32_t queue_id, uint32_t __user *wptr, 106 uint32_t wptr_shift, uint32_t wptr_mask, 107 struct mm_struct *mm); 108 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd); 109 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, 110 uint32_t pipe_id, uint32_t queue_id); 111 112 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, 113 enum kfd_preempt_type reset_type, 114 unsigned int utimeout, uint32_t pipe_id, 115 uint32_t queue_id); 116 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd); 117 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, 118 unsigned int utimeout); 119 static int kgd_address_watch_disable(struct kgd_dev *kgd); 120 static int kgd_address_watch_execute(struct kgd_dev *kgd, 121 unsigned int watch_point_id, 122 uint32_t cntl_val, 123 uint32_t addr_hi, 124 uint32_t addr_lo); 125 static int kgd_wave_control_execute(struct kgd_dev *kgd, 126 uint32_t gfx_index_val, 127 uint32_t sq_cmd); 128 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, 129 unsigned int watch_point_id, 130 unsigned int reg_offset); 131 132 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, uint8_t vmid); 133 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, 134 uint8_t vmid); 135 static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid); 136 137 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type); 138 static void set_scratch_backing_va(struct kgd_dev *kgd, 139 uint64_t va, uint32_t vmid); 140 141 /* Because of REG_GET_FIELD() being used, we put this function in the 142 * asic specific file. 143 */ 144 static int get_tile_config(struct kgd_dev *kgd, 145 struct tile_config *config) 146 { 147 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 148 149 config->gb_addr_config = adev->gfx.config.gb_addr_config; 150 config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, 151 MC_ARB_RAMCFG, NOOFBANK); 152 config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, 153 MC_ARB_RAMCFG, NOOFRANKS); 154 155 config->tile_config_ptr = adev->gfx.config.tile_mode_array; 156 config->num_tile_configs = 157 ARRAY_SIZE(adev->gfx.config.tile_mode_array); 158 config->macro_tile_config_ptr = 159 adev->gfx.config.macrotile_mode_array; 160 config->num_macro_tile_configs = 161 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); 162 163 return 0; 164 } 165 166 static const struct kfd2kgd_calls kfd2kgd = { 167 .init_gtt_mem_allocation = alloc_gtt_mem, 168 .free_gtt_mem = free_gtt_mem, 169 .get_vmem_size = get_vmem_size, 170 .get_gpu_clock_counter = get_gpu_clock_counter, 171 .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz, 172 .alloc_pasid = amdgpu_vm_alloc_pasid, 173 .free_pasid = amdgpu_vm_free_pasid, 174 .program_sh_mem_settings = kgd_program_sh_mem_settings, 175 .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping, 176 .init_pipeline = kgd_init_pipeline, 177 .init_interrupts = kgd_init_interrupts, 178 .hqd_load = kgd_hqd_load, 179 .hqd_sdma_load = kgd_hqd_sdma_load, 180 .hqd_is_occupied = kgd_hqd_is_occupied, 181 .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied, 182 .hqd_destroy = kgd_hqd_destroy, 183 .hqd_sdma_destroy = kgd_hqd_sdma_destroy, 184 .address_watch_disable = kgd_address_watch_disable, 185 .address_watch_execute = kgd_address_watch_execute, 186 .wave_control_execute = kgd_wave_control_execute, 187 .address_watch_get_offset = kgd_address_watch_get_offset, 188 .get_atc_vmid_pasid_mapping_pasid = get_atc_vmid_pasid_mapping_pasid, 189 .get_atc_vmid_pasid_mapping_valid = get_atc_vmid_pasid_mapping_valid, 190 .write_vmid_invalidate_request = write_vmid_invalidate_request, 191 .get_fw_version = get_fw_version, 192 .set_scratch_backing_va = set_scratch_backing_va, 193 .get_tile_config = get_tile_config, 194 }; 195 196 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void) 197 { 198 return (struct kfd2kgd_calls *)&kfd2kgd; 199 } 200 201 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd) 202 { 203 return (struct amdgpu_device *)kgd; 204 } 205 206 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe, 207 uint32_t queue, uint32_t vmid) 208 { 209 struct amdgpu_device *adev = get_amdgpu_device(kgd); 210 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue); 211 212 mutex_lock(&adev->srbm_mutex); 213 WREG32(mmSRBM_GFX_CNTL, value); 214 } 215 216 static void unlock_srbm(struct kgd_dev *kgd) 217 { 218 struct amdgpu_device *adev = get_amdgpu_device(kgd); 219 220 WREG32(mmSRBM_GFX_CNTL, 0); 221 mutex_unlock(&adev->srbm_mutex); 222 } 223 224 static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id, 225 uint32_t queue_id) 226 { 227 struct amdgpu_device *adev = get_amdgpu_device(kgd); 228 229 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 230 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 231 232 lock_srbm(kgd, mec, pipe, queue_id, 0); 233 } 234 235 static void release_queue(struct kgd_dev *kgd) 236 { 237 unlock_srbm(kgd); 238 } 239 240 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 241 uint32_t sh_mem_config, 242 uint32_t sh_mem_ape1_base, 243 uint32_t sh_mem_ape1_limit, 244 uint32_t sh_mem_bases) 245 { 246 struct amdgpu_device *adev = get_amdgpu_device(kgd); 247 248 lock_srbm(kgd, 0, 0, 0, vmid); 249 250 WREG32(mmSH_MEM_CONFIG, sh_mem_config); 251 WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base); 252 WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit); 253 WREG32(mmSH_MEM_BASES, sh_mem_bases); 254 255 unlock_srbm(kgd); 256 } 257 258 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, 259 unsigned int vmid) 260 { 261 struct amdgpu_device *adev = get_amdgpu_device(kgd); 262 263 /* 264 * We have to assume that there is no outstanding mapping. 265 * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because 266 * a mapping is in progress or because a mapping finished and the 267 * SW cleared it. So the protocol is to always wait & clear. 268 */ 269 uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid | 270 ATC_VMID0_PASID_MAPPING__VALID_MASK; 271 272 WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping); 273 274 while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid))) 275 cpu_relax(); 276 WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid); 277 278 /* Mapping vmid to pasid also for IH block */ 279 WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping); 280 281 return 0; 282 } 283 284 static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id, 285 uint32_t hpd_size, uint64_t hpd_gpu_addr) 286 { 287 /* amdgpu owns the per-pipe state */ 288 return 0; 289 } 290 291 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) 292 { 293 struct amdgpu_device *adev = get_amdgpu_device(kgd); 294 uint32_t mec; 295 uint32_t pipe; 296 297 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 298 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 299 300 lock_srbm(kgd, mec, pipe, 0, 0); 301 302 WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | 303 CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK); 304 305 unlock_srbm(kgd); 306 307 return 0; 308 } 309 310 static inline uint32_t get_sdma_base_addr(struct cik_sdma_rlc_registers *m) 311 { 312 uint32_t retval; 313 314 retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET + 315 m->sdma_queue_id * KFD_CIK_SDMA_QUEUE_OFFSET; 316 317 pr_debug("kfd: sdma base address: 0x%x\n", retval); 318 319 return retval; 320 } 321 322 static inline struct cik_mqd *get_mqd(void *mqd) 323 { 324 return (struct cik_mqd *)mqd; 325 } 326 327 static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd) 328 { 329 return (struct cik_sdma_rlc_registers *)mqd; 330 } 331 332 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 333 uint32_t queue_id, uint32_t __user *wptr, 334 uint32_t wptr_shift, uint32_t wptr_mask, 335 struct mm_struct *mm) 336 { 337 struct amdgpu_device *adev = get_amdgpu_device(kgd); 338 struct cik_mqd *m; 339 uint32_t *mqd_hqd; 340 uint32_t reg, wptr_val, data; 341 342 m = get_mqd(mqd); 343 344 acquire_queue(kgd, pipe_id, queue_id); 345 346 /* HQD registers extend from CP_MQD_BASE_ADDR to CP_MQD_CONTROL. */ 347 mqd_hqd = &m->cp_mqd_base_addr_lo; 348 349 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++) 350 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); 351 352 /* Copy userspace write pointer value to register. 353 * Activate doorbell logic to monitor subsequent changes. 354 */ 355 data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control, 356 CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); 357 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data); 358 359 if (read_user_wptr(mm, wptr, wptr_val)) 360 WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask); 361 362 data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1); 363 WREG32(mmCP_HQD_ACTIVE, data); 364 365 release_queue(kgd); 366 367 return 0; 368 } 369 370 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd) 371 { 372 struct amdgpu_device *adev = get_amdgpu_device(kgd); 373 struct cik_sdma_rlc_registers *m; 374 uint32_t sdma_base_addr; 375 376 m = get_sdma_mqd(mqd); 377 sdma_base_addr = get_sdma_base_addr(m); 378 379 WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR, 380 m->sdma_rlc_virtual_addr); 381 382 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, 383 m->sdma_rlc_rb_base); 384 385 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI, 386 m->sdma_rlc_rb_base_hi); 387 388 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 389 m->sdma_rlc_rb_rptr_addr_lo); 390 391 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, 392 m->sdma_rlc_rb_rptr_addr_hi); 393 394 WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 395 m->sdma_rlc_doorbell); 396 397 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, 398 m->sdma_rlc_rb_cntl); 399 400 return 0; 401 } 402 403 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, 404 uint32_t pipe_id, uint32_t queue_id) 405 { 406 struct amdgpu_device *adev = get_amdgpu_device(kgd); 407 uint32_t act; 408 bool retval = false; 409 uint32_t low, high; 410 411 acquire_queue(kgd, pipe_id, queue_id); 412 act = RREG32(mmCP_HQD_ACTIVE); 413 if (act) { 414 low = lower_32_bits(queue_address >> 8); 415 high = upper_32_bits(queue_address >> 8); 416 417 if (low == RREG32(mmCP_HQD_PQ_BASE) && 418 high == RREG32(mmCP_HQD_PQ_BASE_HI)) 419 retval = true; 420 } 421 release_queue(kgd); 422 return retval; 423 } 424 425 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) 426 { 427 struct amdgpu_device *adev = get_amdgpu_device(kgd); 428 struct cik_sdma_rlc_registers *m; 429 uint32_t sdma_base_addr; 430 uint32_t sdma_rlc_rb_cntl; 431 432 m = get_sdma_mqd(mqd); 433 sdma_base_addr = get_sdma_base_addr(m); 434 435 sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); 436 437 if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK) 438 return true; 439 440 return false; 441 } 442 443 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, 444 enum kfd_preempt_type reset_type, 445 unsigned int utimeout, uint32_t pipe_id, 446 uint32_t queue_id) 447 { 448 struct amdgpu_device *adev = get_amdgpu_device(kgd); 449 uint32_t temp; 450 enum hqd_dequeue_request_type type; 451 unsigned long flags, end_jiffies; 452 int retry; 453 454 acquire_queue(kgd, pipe_id, queue_id); 455 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 456 457 switch (reset_type) { 458 case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN: 459 type = DRAIN_PIPE; 460 break; 461 case KFD_PREEMPT_TYPE_WAVEFRONT_RESET: 462 type = RESET_WAVES; 463 break; 464 default: 465 type = DRAIN_PIPE; 466 break; 467 } 468 469 /* Workaround: If IQ timer is active and the wait time is close to or 470 * equal to 0, dequeueing is not safe. Wait until either the wait time 471 * is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is 472 * cleared before continuing. Also, ensure wait times are set to at 473 * least 0x3. 474 */ 475 local_irq_save(flags); 476 preempt_disable(); 477 retry = 5000; /* wait for 500 usecs at maximum */ 478 while (true) { 479 temp = RREG32(mmCP_HQD_IQ_TIMER); 480 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { 481 pr_debug("HW is processing IQ\n"); 482 goto loop; 483 } 484 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { 485 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) 486 == 3) /* SEM-rearm is safe */ 487 break; 488 /* Wait time 3 is safe for CP, but our MMIO read/write 489 * time is close to 1 microsecond, so check for 10 to 490 * leave more buffer room 491 */ 492 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) 493 >= 10) 494 break; 495 pr_debug("IQ timer is active\n"); 496 } else 497 break; 498 loop: 499 if (!retry) { 500 pr_err("CP HQD IQ timer status time out\n"); 501 break; 502 } 503 ndelay(100); 504 --retry; 505 } 506 retry = 1000; 507 while (true) { 508 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); 509 if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK)) 510 break; 511 pr_debug("Dequeue request is pending\n"); 512 513 if (!retry) { 514 pr_err("CP HQD dequeue request time out\n"); 515 break; 516 } 517 ndelay(100); 518 --retry; 519 } 520 local_irq_restore(flags); 521 preempt_enable(); 522 523 WREG32(mmCP_HQD_DEQUEUE_REQUEST, type); 524 525 end_jiffies = (utimeout * HZ / 1000) + jiffies; 526 while (true) { 527 temp = RREG32(mmCP_HQD_ACTIVE); 528 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK)) 529 break; 530 if (time_after(jiffies, end_jiffies)) { 531 pr_err("cp queue preemption time out\n"); 532 release_queue(kgd); 533 return -ETIME; 534 } 535 usleep_range(500, 1000); 536 } 537 538 release_queue(kgd); 539 return 0; 540 } 541 542 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, 543 unsigned int utimeout) 544 { 545 struct amdgpu_device *adev = get_amdgpu_device(kgd); 546 struct cik_sdma_rlc_registers *m; 547 uint32_t sdma_base_addr; 548 uint32_t temp; 549 int timeout = utimeout; 550 551 m = get_sdma_mqd(mqd); 552 sdma_base_addr = get_sdma_base_addr(m); 553 554 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); 555 temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK; 556 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp); 557 558 while (true) { 559 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); 560 if (temp & SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT) 561 break; 562 if (timeout <= 0) 563 return -ETIME; 564 msleep(20); 565 timeout -= 20; 566 } 567 568 WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0); 569 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, 0); 570 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 0); 571 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, 0); 572 573 return 0; 574 } 575 576 static int kgd_address_watch_disable(struct kgd_dev *kgd) 577 { 578 struct amdgpu_device *adev = get_amdgpu_device(kgd); 579 union TCP_WATCH_CNTL_BITS cntl; 580 unsigned int i; 581 582 cntl.u32All = 0; 583 584 cntl.bitfields.valid = 0; 585 cntl.bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK; 586 cntl.bitfields.atc = 1; 587 588 /* Turning off this address until we set all the registers */ 589 for (i = 0; i < MAX_WATCH_ADDRESSES; i++) 590 WREG32(watchRegs[i * ADDRESS_WATCH_REG_MAX + 591 ADDRESS_WATCH_REG_CNTL], cntl.u32All); 592 593 return 0; 594 } 595 596 static int kgd_address_watch_execute(struct kgd_dev *kgd, 597 unsigned int watch_point_id, 598 uint32_t cntl_val, 599 uint32_t addr_hi, 600 uint32_t addr_lo) 601 { 602 struct amdgpu_device *adev = get_amdgpu_device(kgd); 603 union TCP_WATCH_CNTL_BITS cntl; 604 605 cntl.u32All = cntl_val; 606 607 /* Turning off this watch point until we set all the registers */ 608 cntl.bitfields.valid = 0; 609 WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + 610 ADDRESS_WATCH_REG_CNTL], cntl.u32All); 611 612 WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + 613 ADDRESS_WATCH_REG_ADDR_HI], addr_hi); 614 615 WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + 616 ADDRESS_WATCH_REG_ADDR_LO], addr_lo); 617 618 /* Enable the watch point */ 619 cntl.bitfields.valid = 1; 620 621 WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + 622 ADDRESS_WATCH_REG_CNTL], cntl.u32All); 623 624 return 0; 625 } 626 627 static int kgd_wave_control_execute(struct kgd_dev *kgd, 628 uint32_t gfx_index_val, 629 uint32_t sq_cmd) 630 { 631 struct amdgpu_device *adev = get_amdgpu_device(kgd); 632 uint32_t data; 633 634 mutex_lock(&adev->grbm_idx_mutex); 635 636 WREG32(mmGRBM_GFX_INDEX, gfx_index_val); 637 WREG32(mmSQ_CMD, sq_cmd); 638 639 /* Restore the GRBM_GFX_INDEX register */ 640 641 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | 642 GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 643 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK; 644 645 WREG32(mmGRBM_GFX_INDEX, data); 646 647 mutex_unlock(&adev->grbm_idx_mutex); 648 649 return 0; 650 } 651 652 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, 653 unsigned int watch_point_id, 654 unsigned int reg_offset) 655 { 656 return watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset]; 657 } 658 659 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, 660 uint8_t vmid) 661 { 662 uint32_t reg; 663 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 664 665 reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); 666 return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK; 667 } 668 669 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, 670 uint8_t vmid) 671 { 672 uint32_t reg; 673 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 674 675 reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); 676 return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK; 677 } 678 679 static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid) 680 { 681 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 682 683 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 684 } 685 686 static void set_scratch_backing_va(struct kgd_dev *kgd, 687 uint64_t va, uint32_t vmid) 688 { 689 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 690 691 lock_srbm(kgd, 0, 0, 0, vmid); 692 WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va); 693 unlock_srbm(kgd); 694 } 695 696 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type) 697 { 698 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 699 const union amdgpu_firmware_header *hdr; 700 701 BUG_ON(kgd == NULL); 702 703 switch (type) { 704 case KGD_ENGINE_PFP: 705 hdr = (const union amdgpu_firmware_header *) 706 adev->gfx.pfp_fw->data; 707 break; 708 709 case KGD_ENGINE_ME: 710 hdr = (const union amdgpu_firmware_header *) 711 adev->gfx.me_fw->data; 712 break; 713 714 case KGD_ENGINE_CE: 715 hdr = (const union amdgpu_firmware_header *) 716 adev->gfx.ce_fw->data; 717 break; 718 719 case KGD_ENGINE_MEC1: 720 hdr = (const union amdgpu_firmware_header *) 721 adev->gfx.mec_fw->data; 722 break; 723 724 case KGD_ENGINE_MEC2: 725 hdr = (const union amdgpu_firmware_header *) 726 adev->gfx.mec2_fw->data; 727 break; 728 729 case KGD_ENGINE_RLC: 730 hdr = (const union amdgpu_firmware_header *) 731 adev->gfx.rlc_fw->data; 732 break; 733 734 case KGD_ENGINE_SDMA1: 735 hdr = (const union amdgpu_firmware_header *) 736 adev->sdma.instance[0].fw->data; 737 break; 738 739 case KGD_ENGINE_SDMA2: 740 hdr = (const union amdgpu_firmware_header *) 741 adev->sdma.instance[1].fw->data; 742 break; 743 744 default: 745 return 0; 746 } 747 748 if (hdr == NULL) 749 return 0; 750 751 /* Only 12 bit in use*/ 752 return hdr->common.ucode_version; 753 } 754 755