1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include "amdgpu.h" 24 #include "amdgpu_amdkfd.h" 25 #include "gc/gc_12_0_0_offset.h" 26 #include "gc/gc_12_0_0_sh_mask.h" 27 #include "soc24.h" 28 #include <uapi/linux/kfd_ioctl.h> 29 30 static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe, 31 uint32_t queue, uint32_t vmid) 32 { 33 mutex_lock(&adev->srbm_mutex); 34 soc24_grbm_select(adev, mec, pipe, queue, vmid); 35 } 36 37 static void unlock_srbm(struct amdgpu_device *adev) 38 { 39 soc24_grbm_select(adev, 0, 0, 0, 0); 40 mutex_unlock(&adev->srbm_mutex); 41 } 42 43 static void acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id, 44 uint32_t queue_id) 45 { 46 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 47 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 48 49 lock_srbm(adev, mec, pipe, queue_id, 0); 50 } 51 52 static void release_queue(struct amdgpu_device *adev) 53 { 54 unlock_srbm(adev); 55 } 56 57 static int init_interrupts_v12(struct amdgpu_device *adev, uint32_t pipe_id, uint32_t inst) 58 { 59 uint32_t mec; 60 uint32_t pipe; 61 62 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 63 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 64 65 lock_srbm(adev, mec, pipe, 0, 0); 66 67 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, 68 CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | 69 CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK); 70 71 unlock_srbm(adev); 72 73 return 0; 74 } 75 76 static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev, 77 unsigned int engine_id, 78 unsigned int queue_id) 79 { 80 uint32_t sdma_engine_reg_base = 0; 81 uint32_t sdma_rlc_reg_offset; 82 83 switch (engine_id) { 84 case 0: 85 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, 86 regSDMA0_QUEUE0_RB_CNTL) - regSDMA0_QUEUE0_RB_CNTL; 87 break; 88 case 1: 89 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0, 90 regSDMA1_QUEUE0_RB_CNTL) - regSDMA0_QUEUE0_RB_CNTL; 91 break; 92 default: 93 BUG(); 94 } 95 96 sdma_rlc_reg_offset = sdma_engine_reg_base 97 + queue_id * (regSDMA0_QUEUE1_RB_CNTL - regSDMA0_QUEUE0_RB_CNTL); 98 99 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id, 100 queue_id, sdma_rlc_reg_offset); 101 102 return sdma_rlc_reg_offset; 103 } 104 105 static int hqd_dump_v12(struct amdgpu_device *adev, 106 uint32_t pipe_id, uint32_t queue_id, 107 uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst) 108 { 109 uint32_t i = 0, reg; 110 #define HQD_N_REGS 56 111 #define DUMP_REG(addr) do { \ 112 if (WARN_ON_ONCE(i >= HQD_N_REGS)) \ 113 break; \ 114 (*dump)[i][0] = (addr) << 2; \ 115 (*dump)[i++][1] = RREG32(addr); \ 116 } while (0) 117 118 *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); 119 if (*dump == NULL) 120 return -ENOMEM; 121 122 acquire_queue(adev, pipe_id, queue_id); 123 124 for (reg = SOC15_REG_OFFSET(GC, 0, regCP_MQD_BASE_ADDR); 125 reg <= SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_HI); reg++) 126 DUMP_REG(reg); 127 128 release_queue(adev); 129 130 WARN_ON_ONCE(i != HQD_N_REGS); 131 *n_regs = i; 132 133 return 0; 134 } 135 136 static int hqd_sdma_dump_v12(struct amdgpu_device *adev, 137 uint32_t engine_id, uint32_t queue_id, 138 uint32_t (**dump)[2], uint32_t *n_regs) 139 { 140 uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, 141 engine_id, queue_id); 142 uint32_t i = 0, reg; 143 144 const uint32_t first_reg = regSDMA0_QUEUE0_RB_CNTL; 145 const uint32_t last_reg = regSDMA0_QUEUE0_CONTEXT_STATUS; 146 #undef HQD_N_REGS 147 #define HQD_N_REGS (last_reg - first_reg + 1) 148 149 *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); 150 if (*dump == NULL) 151 return -ENOMEM; 152 153 for (reg = first_reg; 154 reg <= last_reg; reg++) 155 DUMP_REG(sdma_rlc_reg_offset + reg); 156 157 WARN_ON_ONCE(i != HQD_N_REGS); 158 *n_regs = i; 159 160 return 0; 161 } 162 163 static int wave_control_execute_v12(struct amdgpu_device *adev, 164 uint32_t gfx_index_val, 165 uint32_t sq_cmd, uint32_t inst) 166 { 167 uint32_t data = 0; 168 169 mutex_lock(&adev->grbm_idx_mutex); 170 171 WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), gfx_index_val); 172 WREG32(SOC15_REG_OFFSET(GC, 0, regSQ_CMD), sq_cmd); 173 174 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 175 INSTANCE_BROADCAST_WRITES, 1); 176 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 177 SA_BROADCAST_WRITES, 1); 178 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 179 SE_BROADCAST_WRITES, 1); 180 181 WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), data); 182 mutex_unlock(&adev->grbm_idx_mutex); 183 184 return 0; 185 } 186 187 /* returns TRAP_EN, EXCP_EN and EXCP_REPLACE. */ 188 static uint32_t kgd_gfx_v12_enable_debug_trap(struct amdgpu_device *adev, 189 bool restore_dbg_registers, 190 uint32_t vmid) 191 { 192 uint32_t data = 0; 193 194 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 195 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0); 196 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0); 197 198 return data; 199 } 200 201 /* returns TRAP_EN, EXCP_EN and EXCP_REPLACE. */ 202 static uint32_t kgd_gfx_v12_disable_debug_trap(struct amdgpu_device *adev, 203 bool keep_trap_enabled, 204 uint32_t vmid) 205 { 206 uint32_t data = 0; 207 208 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 209 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0); 210 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0); 211 212 return data; 213 } 214 215 static int kgd_gfx_v12_validate_trap_override_request(struct amdgpu_device *adev, 216 uint32_t trap_override, 217 uint32_t *trap_mask_supported) 218 { 219 *trap_mask_supported &= KFD_DBG_TRAP_MASK_FP_INVALID | 220 KFD_DBG_TRAP_MASK_FP_INPUT_DENORMAL | 221 KFD_DBG_TRAP_MASK_FP_DIVIDE_BY_ZERO | 222 KFD_DBG_TRAP_MASK_FP_OVERFLOW | 223 KFD_DBG_TRAP_MASK_FP_UNDERFLOW | 224 KFD_DBG_TRAP_MASK_FP_INEXACT | 225 KFD_DBG_TRAP_MASK_INT_DIVIDE_BY_ZERO | 226 KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH | 227 KFD_DBG_TRAP_MASK_DBG_MEMORY_VIOLATION | 228 KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_START | 229 KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_END; 230 231 232 if (trap_override != KFD_DBG_TRAP_OVERRIDE_OR && 233 trap_override != KFD_DBG_TRAP_OVERRIDE_REPLACE) 234 return -EPERM; 235 236 return 0; 237 } 238 239 static uint32_t trap_mask_map_sw_to_hw(uint32_t mask) 240 { 241 uint32_t trap_on_start = (mask & KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_START) ? 1 : 0; 242 uint32_t trap_on_end = (mask & KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_END) ? 1 : 0; 243 uint32_t excp_en = mask & (KFD_DBG_TRAP_MASK_FP_INVALID | 244 KFD_DBG_TRAP_MASK_FP_INPUT_DENORMAL | 245 KFD_DBG_TRAP_MASK_FP_DIVIDE_BY_ZERO | 246 KFD_DBG_TRAP_MASK_FP_OVERFLOW | 247 KFD_DBG_TRAP_MASK_FP_UNDERFLOW | 248 KFD_DBG_TRAP_MASK_FP_INEXACT | 249 KFD_DBG_TRAP_MASK_INT_DIVIDE_BY_ZERO | 250 KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH | 251 KFD_DBG_TRAP_MASK_DBG_MEMORY_VIOLATION); 252 uint32_t ret; 253 254 ret = REG_SET_FIELD(0, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, excp_en); 255 ret = REG_SET_FIELD(ret, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_START, trap_on_start); 256 ret = REG_SET_FIELD(ret, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_END, trap_on_end); 257 258 return ret; 259 } 260 261 static uint32_t trap_mask_map_hw_to_sw(uint32_t mask) 262 { 263 uint32_t ret = REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, EXCP_EN); 264 265 if (REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_START)) 266 ret |= KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_START; 267 268 if (REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_END)) 269 ret |= KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_END; 270 271 return ret; 272 } 273 274 /* returns TRAP_EN, EXCP_EN and EXCP_REPLACE. */ 275 static uint32_t kgd_gfx_v12_set_wave_launch_trap_override(struct amdgpu_device *adev, 276 uint32_t vmid, 277 uint32_t trap_override, 278 uint32_t trap_mask_bits, 279 uint32_t trap_mask_request, 280 uint32_t *trap_mask_prev, 281 uint32_t kfd_dbg_trap_cntl_prev) 282 283 { 284 uint32_t data = 0; 285 286 *trap_mask_prev = trap_mask_map_hw_to_sw(kfd_dbg_trap_cntl_prev); 287 288 data = (trap_mask_bits & trap_mask_request) | (*trap_mask_prev & ~trap_mask_request); 289 data = trap_mask_map_sw_to_hw(data); 290 291 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 292 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, trap_override); 293 294 return data; 295 } 296 297 /* returns STALL_VMID or LAUNCH_MODE. */ 298 static uint32_t kgd_gfx_v12_set_wave_launch_mode(struct amdgpu_device *adev, 299 uint8_t wave_launch_mode, 300 uint32_t vmid) 301 { 302 uint32_t data = 0; 303 bool is_stall_mode = wave_launch_mode == 4; 304 305 if (is_stall_mode) 306 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, STALL_VMID, 307 1); 308 else 309 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, LAUNCH_MODE, 310 wave_launch_mode); 311 312 return data; 313 } 314 315 #define TCP_WATCH_STRIDE (regTCP_WATCH1_ADDR_H - regTCP_WATCH0_ADDR_H) 316 static uint32_t kgd_gfx_v12_set_address_watch(struct amdgpu_device *adev, 317 uint64_t watch_address, 318 uint32_t watch_address_mask, 319 uint32_t watch_id, 320 uint32_t watch_mode, 321 uint32_t debug_vmid, 322 uint32_t inst) 323 { 324 uint32_t watch_address_high; 325 uint32_t watch_address_low; 326 uint32_t watch_address_cntl; 327 328 watch_address_cntl = 0; 329 watch_address_low = lower_32_bits(watch_address); 330 watch_address_high = upper_32_bits(watch_address) & 0xffff; 331 332 watch_address_cntl = REG_SET_FIELD(watch_address_cntl, 333 TCP_WATCH0_CNTL, 334 MODE, 335 watch_mode); 336 337 watch_address_cntl = REG_SET_FIELD(watch_address_cntl, 338 TCP_WATCH0_CNTL, 339 MASK, 340 watch_address_mask >> 7); 341 342 watch_address_cntl = REG_SET_FIELD(watch_address_cntl, 343 TCP_WATCH0_CNTL, 344 VALID, 345 1); 346 347 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_H) + 348 (watch_id * TCP_WATCH_STRIDE)), 349 watch_address_high); 350 351 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_L) + 352 (watch_id * TCP_WATCH_STRIDE)), 353 watch_address_low); 354 355 return watch_address_cntl; 356 } 357 358 static uint32_t kgd_gfx_v12_clear_address_watch(struct amdgpu_device *adev, 359 uint32_t watch_id) 360 { 361 return 0; 362 } 363 364 const struct kfd2kgd_calls gfx_v12_kfd2kgd = { 365 .init_interrupts = init_interrupts_v12, 366 .hqd_dump = hqd_dump_v12, 367 .hqd_sdma_dump = hqd_sdma_dump_v12, 368 .wave_control_execute = wave_control_execute_v12, 369 .get_atc_vmid_pasid_mapping_info = NULL, 370 .enable_debug_trap = kgd_gfx_v12_enable_debug_trap, 371 .disable_debug_trap = kgd_gfx_v12_disable_debug_trap, 372 .validate_trap_override_request = kgd_gfx_v12_validate_trap_override_request, 373 .set_wave_launch_trap_override = kgd_gfx_v12_set_wave_launch_trap_override, 374 .set_wave_launch_mode = kgd_gfx_v12_set_wave_launch_mode, 375 .set_address_watch = kgd_gfx_v12_set_address_watch, 376 .clear_address_watch = kgd_gfx_v12_clear_address_watch, 377 }; 378