1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 /* amdgpu_amdkfd.h defines the private interface between amdgpu and amdkfd. */ 24 25 #ifndef AMDGPU_AMDKFD_H_INCLUDED 26 #define AMDGPU_AMDKFD_H_INCLUDED 27 28 #include <linux/list.h> 29 #include <linux/types.h> 30 #include <linux/mm.h> 31 #include <linux/kthread.h> 32 #include <linux/workqueue.h> 33 #include <linux/mmu_notifier.h> 34 #include <linux/memremap.h> 35 #include <kgd_kfd_interface.h> 36 #include <drm/drm_client.h> 37 #include "amdgpu_sync.h" 38 #include "amdgpu_vm.h" 39 #include "amdgpu_xcp.h" 40 41 extern uint64_t amdgpu_amdkfd_total_mem_size; 42 43 enum TLB_FLUSH_TYPE { 44 TLB_FLUSH_LEGACY = 0, 45 TLB_FLUSH_LIGHTWEIGHT, 46 TLB_FLUSH_HEAVYWEIGHT 47 }; 48 49 struct amdgpu_device; 50 struct kfd_process_device; 51 struct amdgpu_reset_context; 52 53 enum kfd_mem_attachment_type { 54 KFD_MEM_ATT_SHARED, /* Share kgd_mem->bo or another attachment's */ 55 KFD_MEM_ATT_USERPTR, /* SG bo to DMA map pages from a userptr bo */ 56 KFD_MEM_ATT_DMABUF, /* DMAbuf to DMA map TTM BOs */ 57 KFD_MEM_ATT_SG /* Tag to DMA map SG BOs */ 58 }; 59 60 struct kfd_mem_attachment { 61 struct list_head list; 62 enum kfd_mem_attachment_type type; 63 bool is_mapped; 64 struct amdgpu_bo_va *bo_va; 65 struct amdgpu_device *adev; 66 uint64_t va; 67 uint64_t pte_flags; 68 }; 69 70 struct kgd_mem { 71 struct mutex lock; 72 struct amdgpu_bo *bo; 73 struct dma_buf *dmabuf; 74 struct hmm_range *range; 75 struct list_head attachments; 76 /* protected by amdkfd_process_info.lock */ 77 struct list_head validate_list; 78 uint32_t domain; 79 unsigned int mapped_to_gpu_memory; 80 uint64_t va; 81 82 uint32_t alloc_flags; 83 84 uint32_t invalid; 85 struct amdkfd_process_info *process_info; 86 87 struct amdgpu_sync sync; 88 89 uint32_t gem_handle; 90 bool aql_queue; 91 bool is_imported; 92 }; 93 94 /* KFD Memory Eviction */ 95 struct amdgpu_amdkfd_fence { 96 struct dma_fence base; 97 struct mm_struct *mm; 98 spinlock_t lock; 99 char timeline_name[TASK_COMM_LEN]; 100 struct svm_range_bo *svm_bo; 101 }; 102 103 struct amdgpu_kfd_dev { 104 struct kfd_dev *dev; 105 int64_t vram_used[MAX_XCP]; 106 uint64_t vram_used_aligned[MAX_XCP]; 107 bool init_complete; 108 struct work_struct reset_work; 109 110 /* HMM page migration MEMORY_DEVICE_PRIVATE mapping */ 111 struct dev_pagemap pgmap; 112 113 /* Client for KFD BO GEM handle allocations */ 114 struct drm_client_dev client; 115 }; 116 117 enum kgd_engine_type { 118 KGD_ENGINE_PFP = 1, 119 KGD_ENGINE_ME, 120 KGD_ENGINE_CE, 121 KGD_ENGINE_MEC1, 122 KGD_ENGINE_MEC2, 123 KGD_ENGINE_RLC, 124 KGD_ENGINE_SDMA1, 125 KGD_ENGINE_SDMA2, 126 KGD_ENGINE_MAX 127 }; 128 129 130 struct amdkfd_process_info { 131 /* List head of all VMs that belong to a KFD process */ 132 struct list_head vm_list_head; 133 /* List head for all KFD BOs that belong to a KFD process. */ 134 struct list_head kfd_bo_list; 135 /* List of userptr BOs that are valid or invalid */ 136 struct list_head userptr_valid_list; 137 struct list_head userptr_inval_list; 138 /* Lock to protect kfd_bo_list */ 139 struct mutex lock; 140 141 /* Number of VMs */ 142 unsigned int n_vms; 143 /* Eviction Fence */ 144 struct amdgpu_amdkfd_fence *eviction_fence; 145 146 /* MMU-notifier related fields */ 147 struct mutex notifier_lock; 148 uint32_t evicted_bos; 149 struct delayed_work restore_userptr_work; 150 struct pid *pid; 151 bool block_mmu_notifications; 152 }; 153 154 int amdgpu_amdkfd_init(void); 155 void amdgpu_amdkfd_fini(void); 156 157 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm); 158 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm); 159 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, 160 const void *ih_ring_entry); 161 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev); 162 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev); 163 void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev); 164 int amdgpu_amdkfd_check_and_lock_kfd(struct amdgpu_device *adev); 165 void amdgpu_amdkfd_unlock_kfd(struct amdgpu_device *adev); 166 int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, 167 enum kgd_engine_type engine, 168 uint32_t vmid, uint64_t gpu_addr, 169 uint32_t *ib_cmd, uint32_t ib_len); 170 void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle); 171 bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev); 172 173 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid); 174 175 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev, 176 struct amdgpu_reset_context *reset_context); 177 178 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev); 179 180 void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev); 181 182 int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev, 183 int queue_bit); 184 185 struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context, 186 struct mm_struct *mm, 187 struct svm_range_bo *svm_bo); 188 189 int amdgpu_amdkfd_drm_client_create(struct amdgpu_device *adev); 190 #if defined(CONFIG_DEBUG_FS) 191 int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data); 192 #endif 193 #if IS_ENABLED(CONFIG_HSA_AMD) 194 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm); 195 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f); 196 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo); 197 int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni, 198 unsigned long cur_seq, struct kgd_mem *mem); 199 int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo, 200 uint32_t domain, 201 struct dma_fence *fence); 202 #else 203 static inline 204 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm) 205 { 206 return false; 207 } 208 209 static inline 210 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f) 211 { 212 return NULL; 213 } 214 215 static inline 216 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo) 217 { 218 return 0; 219 } 220 221 static inline 222 int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni, 223 unsigned long cur_seq, struct kgd_mem *mem) 224 { 225 return 0; 226 } 227 static inline 228 int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo, 229 uint32_t domain, 230 struct dma_fence *fence) 231 { 232 return 0; 233 } 234 #endif 235 /* Shared API */ 236 int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size, 237 void **mem_obj, uint64_t *gpu_addr, 238 void **cpu_ptr, bool mqd_gfx9); 239 void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void **mem_obj); 240 int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size, 241 void **mem_obj); 242 void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj); 243 int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem); 244 int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem); 245 uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev, 246 enum kgd_engine_type type); 247 void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev, 248 struct kfd_local_mem_info *mem_info, 249 struct amdgpu_xcp *xcp); 250 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev); 251 252 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev); 253 int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, 254 struct amdgpu_device **dmabuf_adev, 255 uint64_t *bo_size, void *metadata_buffer, 256 size_t buffer_size, uint32_t *metadata_size, 257 uint32_t *flags, int8_t *xcp_id); 258 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct amdgpu_device *dst, 259 struct amdgpu_device *src); 260 int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct amdgpu_device *dst, 261 struct amdgpu_device *src, 262 bool is_min); 263 int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min); 264 int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev, 265 uint32_t *payload); 266 int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off, 267 u32 inst); 268 int amdgpu_amdkfd_start_sched(struct amdgpu_device *adev, uint32_t node_id); 269 int amdgpu_amdkfd_stop_sched(struct amdgpu_device *adev, uint32_t node_id); 270 int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcp_id, 271 bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable); 272 bool amdgpu_amdkfd_compute_active(struct amdgpu_device *adev, uint32_t node_id); 273 274 275 /* Read user wptr from a specified user address space with page fault 276 * disabled. The memory must be pinned and mapped to the hardware when 277 * this is called in hqd_load functions, so it should never fault in 278 * the first place. This resolves a circular lock dependency involving 279 * four locks, including the DQM lock and mmap_lock. 280 */ 281 #define read_user_wptr(mmptr, wptr, dst) \ 282 ({ \ 283 bool valid = false; \ 284 if ((mmptr) && (wptr)) { \ 285 pagefault_disable(); \ 286 if ((mmptr) == current->mm) { \ 287 valid = !get_user((dst), (wptr)); \ 288 } else if (current->flags & PF_KTHREAD) { \ 289 kthread_use_mm(mmptr); \ 290 valid = !get_user((dst), (wptr)); \ 291 kthread_unuse_mm(mmptr); \ 292 } \ 293 pagefault_enable(); \ 294 } \ 295 valid; \ 296 }) 297 298 /* GPUVM API */ 299 #define drm_priv_to_vm(drm_priv) \ 300 (&((struct amdgpu_fpriv *) \ 301 ((struct drm_file *)(drm_priv))->driver_priv)->vm) 302 303 int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev, 304 struct amdgpu_vm *avm, 305 void **process_info, 306 struct dma_fence **ef); 307 uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv); 308 size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev, 309 uint8_t xcp_id); 310 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( 311 struct amdgpu_device *adev, uint64_t va, uint64_t size, 312 void *drm_priv, struct kgd_mem **mem, 313 uint64_t *offset, uint32_t flags, bool criu_resume); 314 int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( 315 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv, 316 uint64_t *size); 317 int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(struct amdgpu_device *adev, 318 struct kgd_mem *mem, void *drm_priv); 319 int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( 320 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv); 321 int amdgpu_amdkfd_gpuvm_dmaunmap_mem(struct kgd_mem *mem, void *drm_priv); 322 int amdgpu_amdkfd_gpuvm_sync_memory( 323 struct amdgpu_device *adev, struct kgd_mem *mem, bool intr); 324 int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem, 325 void **kptr, uint64_t *size); 326 void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem); 327 328 int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_bo *bo, struct amdgpu_bo **bo_gart); 329 330 int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info, 331 struct dma_fence __rcu **ef); 332 int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev, 333 struct kfd_vm_fault_info *info); 334 int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd, 335 uint64_t va, void *drm_priv, 336 struct kgd_mem **mem, uint64_t *size, 337 uint64_t *mmap_offset); 338 int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, 339 struct dma_buf **dmabuf); 340 void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev); 341 int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, 342 struct tile_config *config); 343 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, 344 enum amdgpu_ras_block block, uint32_t reset); 345 346 void amdgpu_amdkfd_ras_pasid_poison_consumption_handler(struct amdgpu_device *adev, 347 enum amdgpu_ras_block block, uint16_t pasid, 348 pasid_notify pasid_fn, void *data, uint32_t reset); 349 350 bool amdgpu_amdkfd_is_fed(struct amdgpu_device *adev); 351 bool amdgpu_amdkfd_bo_mapped_to_dev(void *drm_priv, struct kgd_mem *mem); 352 void amdgpu_amdkfd_block_mmu_notifications(void *p); 353 int amdgpu_amdkfd_criu_resume(void *p); 354 int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev, 355 uint64_t size, u32 alloc_flag, int8_t xcp_id); 356 void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev, 357 uint64_t size, u32 alloc_flag, int8_t xcp_id); 358 359 u64 amdgpu_amdkfd_xcp_memory_size(struct amdgpu_device *adev, int xcp_id); 360 361 #define KFD_XCP_MEM_ID(adev, xcp_id) \ 362 ((adev)->xcp_mgr && (xcp_id) >= 0 ?\ 363 (adev)->xcp_mgr->xcp[(xcp_id)].mem_id : -1) 364 365 #define KFD_XCP_MEMORY_SIZE(adev, xcp_id) amdgpu_amdkfd_xcp_memory_size((adev), (xcp_id)) 366 367 368 #if IS_ENABLED(CONFIG_HSA_AMD) 369 void amdgpu_amdkfd_gpuvm_init_mem_limits(void); 370 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, 371 struct amdgpu_vm *vm); 372 373 /** 374 * @amdgpu_amdkfd_release_notify() - Notify KFD when GEM object is released 375 * 376 * Allows KFD to release its resources associated with the GEM object. 377 */ 378 void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo); 379 void amdgpu_amdkfd_reserve_system_mem(uint64_t size); 380 #else 381 static inline 382 void amdgpu_amdkfd_gpuvm_init_mem_limits(void) 383 { 384 } 385 386 static inline 387 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, 388 struct amdgpu_vm *vm) 389 { 390 } 391 392 static inline 393 void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo) 394 { 395 } 396 #endif 397 398 #if IS_ENABLED(CONFIG_HSA_AMD_SVM) 399 int kgd2kfd_init_zone_device(struct amdgpu_device *adev); 400 #else 401 static inline 402 int kgd2kfd_init_zone_device(struct amdgpu_device *adev) 403 { 404 return 0; 405 } 406 #endif 407 408 /* KGD2KFD callbacks */ 409 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger); 410 int kgd2kfd_resume_mm(struct mm_struct *mm); 411 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 412 struct dma_fence *fence); 413 #if IS_ENABLED(CONFIG_HSA_AMD) 414 int kgd2kfd_init(void); 415 void kgd2kfd_exit(void); 416 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf); 417 bool kgd2kfd_device_init(struct kfd_dev *kfd, 418 const struct kgd2kfd_shared_resources *gpu_resources); 419 void kgd2kfd_device_exit(struct kfd_dev *kfd); 420 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm); 421 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm); 422 int kgd2kfd_pre_reset(struct kfd_dev *kfd, 423 struct amdgpu_reset_context *reset_context); 424 int kgd2kfd_post_reset(struct kfd_dev *kfd); 425 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry); 426 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd); 427 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask); 428 int kgd2kfd_check_and_lock_kfd(void); 429 void kgd2kfd_unlock_kfd(void); 430 int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id); 431 int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id); 432 bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id); 433 bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry, 434 bool retry_fault); 435 436 #else 437 static inline int kgd2kfd_init(void) 438 { 439 return -ENOENT; 440 } 441 442 static inline void kgd2kfd_exit(void) 443 { 444 } 445 446 static inline 447 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 448 { 449 return NULL; 450 } 451 452 static inline 453 bool kgd2kfd_device_init(struct kfd_dev *kfd, 454 const struct kgd2kfd_shared_resources *gpu_resources) 455 { 456 return false; 457 } 458 459 static inline void kgd2kfd_device_exit(struct kfd_dev *kfd) 460 { 461 } 462 463 static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 464 { 465 } 466 467 static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 468 { 469 return 0; 470 } 471 472 static inline int kgd2kfd_pre_reset(struct kfd_dev *kfd, 473 struct amdgpu_reset_context *reset_context) 474 { 475 return 0; 476 } 477 478 static inline int kgd2kfd_post_reset(struct kfd_dev *kfd) 479 { 480 return 0; 481 } 482 483 static inline 484 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 485 { 486 } 487 488 static inline 489 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 490 { 491 } 492 493 static inline 494 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 495 { 496 } 497 498 static inline int kgd2kfd_check_and_lock_kfd(void) 499 { 500 return 0; 501 } 502 503 static inline void kgd2kfd_unlock_kfd(void) 504 { 505 } 506 507 static inline int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id) 508 { 509 return 0; 510 } 511 512 static inline int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id) 513 { 514 return 0; 515 } 516 517 static inline bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id) 518 { 519 return false; 520 } 521 522 static inline bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry, 523 bool retry_fault) 524 { 525 return false; 526 } 527 528 #endif 529 #endif /* AMDGPU_AMDKFD_H_INCLUDED */ 530