1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 /* amdgpu_amdkfd.h defines the private interface between amdgpu and amdkfd. */ 24 25 #ifndef AMDGPU_AMDKFD_H_INCLUDED 26 #define AMDGPU_AMDKFD_H_INCLUDED 27 28 #include <linux/list.h> 29 #include <linux/types.h> 30 #include <linux/mm.h> 31 #include <linux/kthread.h> 32 #include <linux/workqueue.h> 33 #include <linux/mmu_notifier.h> 34 #include <linux/memremap.h> 35 #include <kgd_kfd_interface.h> 36 #include <drm/drm_client.h> 37 #include "amdgpu_sync.h" 38 #include "amdgpu_vm.h" 39 #include "amdgpu_xcp.h" 40 #include "kfd_topology.h" 41 #include "amdgpu_ptl.h" 42 43 extern uint64_t amdgpu_amdkfd_total_mem_size; 44 45 enum TLB_FLUSH_TYPE { 46 TLB_FLUSH_LEGACY = 0, 47 TLB_FLUSH_LIGHTWEIGHT, 48 TLB_FLUSH_HEAVYWEIGHT 49 }; 50 51 struct amdgpu_device; 52 struct kfd_process_device; 53 struct amdgpu_reset_context; 54 55 enum kfd_mem_attachment_type { 56 KFD_MEM_ATT_SHARED, /* Share kgd_mem->bo or another attachment's */ 57 KFD_MEM_ATT_USERPTR, /* SG bo to DMA map pages from a userptr bo */ 58 KFD_MEM_ATT_DMABUF, /* DMAbuf to DMA map TTM BOs */ 59 KFD_MEM_ATT_SG /* Tag to DMA map SG BOs */ 60 }; 61 62 struct kfd_mem_attachment { 63 struct list_head list; 64 enum kfd_mem_attachment_type type; 65 bool is_mapped; 66 struct amdgpu_bo_va *bo_va; 67 struct amdgpu_device *adev; 68 uint64_t va; 69 uint64_t pte_flags; 70 }; 71 72 struct kgd_mem { 73 struct mutex lock; 74 struct amdgpu_bo *bo; 75 struct dma_buf *dmabuf; 76 struct amdgpu_hmm_range *range; 77 struct list_head attachments; 78 /* protected by amdkfd_process_info.lock */ 79 struct list_head validate_list; 80 uint32_t domain; 81 unsigned int mapped_to_gpu_memory; 82 uint64_t va; 83 84 uint32_t alloc_flags; 85 86 uint32_t invalid; 87 struct amdkfd_process_info *process_info; 88 89 struct amdgpu_sync sync; 90 91 uint32_t gem_handle; 92 bool aql_queue; 93 bool is_imported; 94 }; 95 96 /* KFD Memory Eviction */ 97 struct amdgpu_amdkfd_fence { 98 struct dma_fence base; 99 struct mm_struct *mm; 100 spinlock_t lock; 101 char timeline_name[TASK_COMM_LEN]; 102 struct svm_range_bo *svm_bo; 103 uint16_t context_id; 104 }; 105 106 struct amdgpu_kfd_dev { 107 struct kfd_dev *dev; 108 int64_t vram_used[MAX_XCP]; 109 uint64_t vram_used_aligned[MAX_XCP]; 110 bool init_complete; 111 struct work_struct reset_work; 112 113 /* Client for KFD BO GEM handle allocations */ 114 struct drm_client_dev client; 115 116 /* HMM page migration MEMORY_DEVICE_PRIVATE mapping 117 * Must be last --ends in a flexible-array member. 118 */ 119 struct dev_pagemap pgmap; 120 }; 121 122 enum kgd_engine_type { 123 KGD_ENGINE_PFP = 1, 124 KGD_ENGINE_ME, 125 KGD_ENGINE_CE, 126 KGD_ENGINE_MEC1, 127 KGD_ENGINE_MEC2, 128 KGD_ENGINE_RLC, 129 KGD_ENGINE_SDMA1, 130 KGD_ENGINE_SDMA2, 131 KGD_ENGINE_MAX 132 }; 133 134 135 struct amdkfd_process_info { 136 /* List head of all VMs that belong to a KFD process */ 137 struct list_head vm_list_head; 138 /* List head for all KFD BOs that belong to a KFD process. */ 139 struct list_head kfd_bo_list; 140 /* List of userptr BOs that are valid or invalid */ 141 struct list_head userptr_valid_list; 142 struct list_head userptr_inval_list; 143 /* Lock to protect kfd_bo_list */ 144 struct mutex lock; 145 146 /* Number of VMs */ 147 unsigned int n_vms; 148 /* Eviction Fence */ 149 struct amdgpu_amdkfd_fence *eviction_fence; 150 151 /* MMU-notifier related fields */ 152 struct mutex notifier_lock; 153 uint32_t evicted_bos; 154 /* kfd context id */ 155 u16 context_id; 156 struct delayed_work restore_userptr_work; 157 struct pid *pid; 158 bool block_mmu_notifications; 159 }; 160 161 int amdgpu_amdkfd_init(void); 162 void amdgpu_amdkfd_fini(void); 163 void amdgpu_amdkfd_teardown_processes(struct amdgpu_device *adev); 164 165 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool suspend_proc); 166 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool resume_proc); 167 void amdgpu_amdkfd_suspend_process(struct amdgpu_device *adev); 168 int amdgpu_amdkfd_resume_process(struct amdgpu_device *adev); 169 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, 170 const void *ih_ring_entry); 171 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev); 172 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev); 173 void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev); 174 int amdgpu_amdkfd_check_and_lock_kfd(struct amdgpu_device *adev); 175 void amdgpu_amdkfd_unlock_kfd(struct amdgpu_device *adev); 176 int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, 177 enum kgd_engine_type engine, 178 uint32_t vmid, uint64_t gpu_addr, 179 uint32_t *ib_cmd, uint32_t ib_len); 180 void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle); 181 bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev); 182 183 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid); 184 185 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev, 186 struct amdgpu_reset_context *reset_context); 187 188 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev); 189 190 void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev); 191 192 int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev, 193 int queue_bit); 194 195 struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context, 196 struct mm_struct *mm, 197 struct svm_range_bo *svm_bo, 198 u16 context_id); 199 200 int amdgpu_amdkfd_drm_client_create(struct amdgpu_device *adev); 201 #if defined(CONFIG_DEBUG_FS) 202 int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data); 203 #endif 204 #if IS_ENABLED(CONFIG_HSA_AMD) 205 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm); 206 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f); 207 void amdgpu_amdkfd_remove_all_eviction_fences(struct amdgpu_bo *bo); 208 int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni, 209 unsigned long cur_seq, struct kgd_mem *mem); 210 int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo, 211 uint32_t domain, 212 struct dma_fence *fence); 213 int amdgpu_amdkfd_set_sigbus_delay(struct task_struct *task, u32 ms); 214 #else 215 static inline 216 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm) 217 { 218 return false; 219 } 220 221 static inline 222 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f) 223 { 224 return NULL; 225 } 226 227 static inline 228 void amdgpu_amdkfd_remove_all_eviction_fences(struct amdgpu_bo *bo) 229 { 230 } 231 232 static inline 233 int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni, 234 unsigned long cur_seq, struct kgd_mem *mem) 235 { 236 return 0; 237 } 238 static inline 239 int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo, 240 uint32_t domain, 241 struct dma_fence *fence) 242 { 243 return 0; 244 } 245 static inline 246 int amdgpu_amdkfd_set_sigbus_delay(struct task_struct *task, u32 ms) 247 { 248 return -EOPNOTSUPP; 249 } 250 #endif 251 /* Shared API */ 252 int amdgpu_amdkfd_alloc_kernel_mem(struct amdgpu_device *adev, size_t size, 253 u32 domain, void **mem_obj, uint64_t *gpu_addr, 254 void **cpu_ptr, bool mqd_gfx9); 255 void amdgpu_amdkfd_free_kernel_mem(struct amdgpu_device *adev, void **mem_obj); 256 int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size, 257 void **mem_obj); 258 void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj); 259 int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem); 260 int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem); 261 uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev, 262 enum kgd_engine_type type); 263 void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev, 264 struct kfd_local_mem_info *mem_info, 265 struct amdgpu_xcp *xcp); 266 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev); 267 268 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev); 269 int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, 270 struct amdgpu_device **dmabuf_adev, 271 uint64_t *bo_size, void **metadata_buffer, 272 size_t buffer_size, uint32_t *metadata_size, 273 uint32_t *flags, int8_t *xcp_id); 274 int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min); 275 int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev, 276 uint32_t *payload); 277 int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off, 278 u32 inst); 279 int amdgpu_amdkfd_start_sched(struct amdgpu_device *adev, uint32_t node_id); 280 int amdgpu_amdkfd_stop_sched(struct amdgpu_device *adev, uint32_t node_id); 281 int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcp_id, 282 bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable); 283 bool amdgpu_amdkfd_compute_active(struct amdgpu_device *adev, uint32_t node_id); 284 int amdgpu_amdkfd_reset_mes_queue(struct amdgpu_device *adev, 285 uint32_t node_id, 286 int queue_type, 287 int pipe, int queue, 288 unsigned int db); 289 290 /* Read user wptr from a specified user address space with page fault 291 * disabled. The memory must be pinned and mapped to the hardware when 292 * this is called in hqd_load functions, so it should never fault in 293 * the first place. This resolves a circular lock dependency involving 294 * four locks, including the DQM lock and mmap_lock. 295 */ 296 #define read_user_wptr(mmptr, wptr, dst) \ 297 ({ \ 298 bool valid = false; \ 299 if ((mmptr) && (wptr)) { \ 300 pagefault_disable(); \ 301 if ((mmptr) == current->mm) { \ 302 valid = !get_user((dst), (wptr)); \ 303 } else if (current->flags & PF_KTHREAD) { \ 304 kthread_use_mm(mmptr); \ 305 valid = !get_user((dst), (wptr)); \ 306 kthread_unuse_mm(mmptr); \ 307 } \ 308 pagefault_enable(); \ 309 } \ 310 valid; \ 311 }) 312 313 /* GPUVM API */ 314 #define drm_priv_to_vm(drm_priv) \ 315 (&((struct amdgpu_fpriv *) \ 316 ((struct drm_file *)(drm_priv))->driver_priv)->vm) 317 318 int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev, 319 struct amdgpu_vm *avm, 320 void **process_info, 321 struct dma_fence **ef); 322 uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv); 323 size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev, 324 uint8_t xcp_id); 325 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( 326 struct amdgpu_device *adev, uint64_t va, uint64_t size, 327 void *drm_priv, struct kgd_mem **mem, 328 uint64_t *offset, uint32_t flags, bool criu_resume); 329 int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( 330 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv, 331 uint64_t *size); 332 int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(struct amdgpu_device *adev, 333 struct kgd_mem *mem, void *drm_priv); 334 int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( 335 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv); 336 int amdgpu_amdkfd_gpuvm_dmaunmap_mem(struct kgd_mem *mem, void *drm_priv); 337 int amdgpu_amdkfd_gpuvm_sync_memory( 338 struct amdgpu_device *adev, struct kgd_mem *mem, bool intr); 339 int amdgpu_amdkfd_gpuvm_map_bo_to_kernel(struct kgd_mem *mem, void **kptr, 340 u64 *size, u32 domain); 341 void amdgpu_amdkfd_gpuvm_unmap_bo_from_kernel(struct kgd_mem *mem); 342 343 int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_bo *bo, struct amdgpu_bo **bo_gart); 344 345 int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info, 346 struct dma_fence __rcu **ef); 347 int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev, 348 struct kfd_vm_fault_info *info); 349 int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd, 350 uint64_t va, void *drm_priv, 351 struct kgd_mem **mem, uint64_t *size, 352 uint64_t *mmap_offset); 353 int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, 354 struct dma_buf **dmabuf); 355 void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev); 356 int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, 357 struct tile_config *config); 358 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, 359 enum amdgpu_ras_block block, uint32_t reset); 360 361 void amdgpu_amdkfd_ras_pasid_poison_consumption_handler(struct amdgpu_device *adev, 362 enum amdgpu_ras_block block, uint16_t pasid, 363 pasid_notify pasid_fn, void *data, uint32_t reset); 364 365 bool amdgpu_amdkfd_is_fed(struct amdgpu_device *adev); 366 bool amdgpu_amdkfd_bo_mapped_to_dev(void *drm_priv, struct kgd_mem *mem); 367 void amdgpu_amdkfd_block_mmu_notifications(void *p); 368 int amdgpu_amdkfd_criu_resume(void *p); 369 int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev, 370 uint64_t size, u32 alloc_flag, int8_t xcp_id); 371 void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev, 372 uint64_t size, u32 alloc_flag, int8_t xcp_id); 373 void amdgpu_amdkfd_clear_kfd_mapping(struct amdgpu_device *adev); 374 375 u64 amdgpu_amdkfd_xcp_memory_size(struct amdgpu_device *adev, int xcp_id); 376 377 #define KFD_XCP_MEM_ID(adev, xcp_id) \ 378 ((adev)->xcp_mgr && (xcp_id) >= 0 ?\ 379 (adev)->xcp_mgr->xcp[(xcp_id)].mem_id : -1) 380 381 #define KFD_XCP_MEMORY_SIZE(adev, xcp_id) amdgpu_amdkfd_xcp_memory_size((adev), (xcp_id)) 382 383 384 #if IS_ENABLED(CONFIG_HSA_AMD) 385 void amdgpu_amdkfd_gpuvm_init_mem_limits(void); 386 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, 387 struct amdgpu_vm *vm); 388 389 /** 390 * @amdgpu_amdkfd_release_notify() - Notify KFD when GEM object is released 391 * 392 * Allows KFD to release its resources associated with the GEM object. 393 */ 394 void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo); 395 void amdgpu_amdkfd_reserve_system_mem(uint64_t size); 396 #else 397 static inline 398 void amdgpu_amdkfd_gpuvm_init_mem_limits(void) 399 { 400 } 401 402 static inline 403 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, 404 struct amdgpu_vm *vm) 405 { 406 } 407 408 static inline 409 void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo) 410 { 411 } 412 #endif 413 414 #if IS_ENABLED(CONFIG_HSA_AMD_SVM) 415 int kgd2kfd_init_zone_device(struct amdgpu_device *adev); 416 #else 417 static inline 418 int kgd2kfd_init_zone_device(struct amdgpu_device *adev) 419 { 420 return 0; 421 } 422 #endif 423 424 /* KGD2KFD callbacks */ 425 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger); 426 int kgd2kfd_resume_mm(struct mm_struct *mm); 427 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 428 u16 context_id, struct dma_fence *fence); 429 #if IS_ENABLED(CONFIG_HSA_AMD) 430 int kgd2kfd_init(void); 431 void kgd2kfd_exit(void); 432 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf); 433 bool kgd2kfd_device_init(struct kfd_dev *kfd, 434 const struct kgd2kfd_shared_resources *gpu_resources); 435 void kgd2kfd_device_exit(struct kfd_dev *kfd); 436 void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc); 437 int kgd2kfd_resume(struct kfd_dev *kfd, bool resume_proc); 438 void kgd2kfd_suspend_process(struct kfd_dev *kfd); 439 int kgd2kfd_resume_process(struct kfd_dev *kfd); 440 int kgd2kfd_pre_reset(struct kfd_dev *kfd, 441 struct amdgpu_reset_context *reset_context); 442 int kgd2kfd_post_reset(struct kfd_dev *kfd); 443 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry); 444 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd); 445 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask); 446 int kgd2kfd_check_and_lock_kfd(struct kfd_dev *kfd); 447 void kgd2kfd_unlock_kfd(struct kfd_dev *kfd); 448 int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id); 449 int kgd2kfd_start_sched_all_nodes(struct kfd_dev *kfd); 450 int amdgpu_amdkfd_start_sched_all(struct amdgpu_device *adev); 451 int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id); 452 int kgd2kfd_stop_sched_all_nodes(struct kfd_dev *kfd); 453 int amdgpu_amdkfd_stop_sched_all(struct amdgpu_device *adev); 454 bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id); 455 bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry, 456 bool retry_fault); 457 void kgd2kfd_lock_kfd(void); 458 void kgd2kfd_teardown_processes(struct amdgpu_device *adev); 459 int kgd2kfd_reset_mes_queue(struct kfd_dev *kfd, uint32_t node_id, 460 int queue_type, int pipe, int queue, 461 unsigned int db); 462 463 #else 464 static inline int kgd2kfd_init(void) 465 { 466 return -ENOENT; 467 } 468 469 static inline void kgd2kfd_exit(void) 470 { 471 } 472 473 static inline 474 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 475 { 476 return NULL; 477 } 478 479 static inline 480 bool kgd2kfd_device_init(struct kfd_dev *kfd, 481 const struct kgd2kfd_shared_resources *gpu_resources) 482 { 483 return false; 484 } 485 486 static inline void kgd2kfd_device_exit(struct kfd_dev *kfd) 487 { 488 } 489 490 static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc) 491 { 492 } 493 494 static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool resume_proc) 495 { 496 return 0; 497 } 498 499 static inline void kgd2kfd_suspend_process(struct kfd_dev *kfd) 500 { 501 } 502 503 static inline int kgd2kfd_resume_process(struct kfd_dev *kfd) 504 { 505 return 0; 506 } 507 508 static inline int kgd2kfd_pre_reset(struct kfd_dev *kfd, 509 struct amdgpu_reset_context *reset_context) 510 { 511 return 0; 512 } 513 514 static inline int kgd2kfd_post_reset(struct kfd_dev *kfd) 515 { 516 return 0; 517 } 518 519 static inline 520 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 521 { 522 } 523 524 static inline 525 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 526 { 527 } 528 529 static inline 530 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 531 { 532 } 533 534 static inline int kgd2kfd_check_and_lock_kfd(struct kfd_dev *kfd) 535 { 536 return 0; 537 } 538 539 static inline void kgd2kfd_unlock_kfd(struct kfd_dev *kfd) 540 { 541 } 542 543 static inline int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id) 544 { 545 return 0; 546 } 547 548 static inline int kgd2kfd_start_sched_all_nodes(struct kfd_dev *kfd) 549 { 550 return 0; 551 } 552 553 static inline int amdgpu_amdkfd_start_sched_all(struct amdgpu_device *adev) 554 { 555 return 0; 556 } 557 558 static inline int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id) 559 { 560 return 0; 561 } 562 563 static inline int kgd2kfd_stop_sched_all_nodes(struct kfd_dev *kfd) 564 { 565 return 0; 566 } 567 568 static inline int amdgpu_amdkfd_stop_sched_all(struct amdgpu_device *adev) 569 { 570 return 0; 571 } 572 573 static inline bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id) 574 { 575 return false; 576 } 577 578 static inline bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry, 579 bool retry_fault) 580 { 581 return false; 582 } 583 584 static inline void kgd2kfd_lock_kfd(void) 585 { 586 } 587 588 static inline void kgd2kfd_teardown_processes(struct amdgpu_device *adev) 589 { 590 } 591 592 static inline int kgd2kfd_reset_mes_queue(struct kfd_dev *kfd, uint32_t node_id, 593 int queue_type, int pipe, int queue, 594 unsigned int db) 595 { 596 return 0; 597 } 598 599 #endif 600 #endif /* AMDGPU_AMDKFD_H_INCLUDED */ 601