1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 /* amdgpu_amdkfd.h defines the private interface between amdgpu and amdkfd. */ 24 25 #ifndef AMDGPU_AMDKFD_H_INCLUDED 26 #define AMDGPU_AMDKFD_H_INCLUDED 27 28 #include <linux/list.h> 29 #include <linux/types.h> 30 #include <linux/mm.h> 31 #include <linux/kthread.h> 32 #include <linux/workqueue.h> 33 #include <linux/mmu_notifier.h> 34 #include <linux/memremap.h> 35 #include <kgd_kfd_interface.h> 36 #include <drm/drm_client.h> 37 #include "amdgpu_sync.h" 38 #include "amdgpu_vm.h" 39 #include "amdgpu_xcp.h" 40 #include "kfd_topology.h" 41 extern uint64_t amdgpu_amdkfd_total_mem_size; 42 43 enum TLB_FLUSH_TYPE { 44 TLB_FLUSH_LEGACY = 0, 45 TLB_FLUSH_LIGHTWEIGHT, 46 TLB_FLUSH_HEAVYWEIGHT 47 }; 48 49 struct amdgpu_device; 50 struct kfd_process_device; 51 struct amdgpu_reset_context; 52 53 enum kfd_mem_attachment_type { 54 KFD_MEM_ATT_SHARED, /* Share kgd_mem->bo or another attachment's */ 55 KFD_MEM_ATT_USERPTR, /* SG bo to DMA map pages from a userptr bo */ 56 KFD_MEM_ATT_DMABUF, /* DMAbuf to DMA map TTM BOs */ 57 KFD_MEM_ATT_SG /* Tag to DMA map SG BOs */ 58 }; 59 60 struct kfd_mem_attachment { 61 struct list_head list; 62 enum kfd_mem_attachment_type type; 63 bool is_mapped; 64 struct amdgpu_bo_va *bo_va; 65 struct amdgpu_device *adev; 66 uint64_t va; 67 uint64_t pte_flags; 68 }; 69 70 struct kgd_mem { 71 struct mutex lock; 72 struct amdgpu_bo *bo; 73 struct dma_buf *dmabuf; 74 struct amdgpu_hmm_range *range; 75 struct list_head attachments; 76 /* protected by amdkfd_process_info.lock */ 77 struct list_head validate_list; 78 uint32_t domain; 79 unsigned int mapped_to_gpu_memory; 80 uint64_t va; 81 82 uint32_t alloc_flags; 83 84 uint32_t invalid; 85 struct amdkfd_process_info *process_info; 86 87 struct amdgpu_sync sync; 88 89 uint32_t gem_handle; 90 bool aql_queue; 91 bool is_imported; 92 }; 93 94 /* KFD Memory Eviction */ 95 struct amdgpu_amdkfd_fence { 96 struct dma_fence base; 97 struct mm_struct *mm; 98 spinlock_t lock; 99 char timeline_name[TASK_COMM_LEN]; 100 struct svm_range_bo *svm_bo; 101 uint16_t context_id; 102 }; 103 104 struct amdgpu_kfd_dev { 105 struct kfd_dev *dev; 106 int64_t vram_used[MAX_XCP]; 107 uint64_t vram_used_aligned[MAX_XCP]; 108 bool init_complete; 109 struct work_struct reset_work; 110 111 /* Client for KFD BO GEM handle allocations */ 112 struct drm_client_dev client; 113 114 /* HMM page migration MEMORY_DEVICE_PRIVATE mapping 115 * Must be last --ends in a flexible-array member. 116 */ 117 struct dev_pagemap pgmap; 118 }; 119 120 enum kgd_engine_type { 121 KGD_ENGINE_PFP = 1, 122 KGD_ENGINE_ME, 123 KGD_ENGINE_CE, 124 KGD_ENGINE_MEC1, 125 KGD_ENGINE_MEC2, 126 KGD_ENGINE_RLC, 127 KGD_ENGINE_SDMA1, 128 KGD_ENGINE_SDMA2, 129 KGD_ENGINE_MAX 130 }; 131 132 133 struct amdkfd_process_info { 134 /* List head of all VMs that belong to a KFD process */ 135 struct list_head vm_list_head; 136 /* List head for all KFD BOs that belong to a KFD process. */ 137 struct list_head kfd_bo_list; 138 /* List of userptr BOs that are valid or invalid */ 139 struct list_head userptr_valid_list; 140 struct list_head userptr_inval_list; 141 /* Lock to protect kfd_bo_list */ 142 struct mutex lock; 143 144 /* Number of VMs */ 145 unsigned int n_vms; 146 /* Eviction Fence */ 147 struct amdgpu_amdkfd_fence *eviction_fence; 148 149 /* MMU-notifier related fields */ 150 struct mutex notifier_lock; 151 uint32_t evicted_bos; 152 /* kfd context id */ 153 u16 context_id; 154 struct delayed_work restore_userptr_work; 155 struct pid *pid; 156 bool block_mmu_notifications; 157 }; 158 159 int amdgpu_amdkfd_init(void); 160 void amdgpu_amdkfd_fini(void); 161 162 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool suspend_proc); 163 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool resume_proc); 164 void amdgpu_amdkfd_suspend_process(struct amdgpu_device *adev); 165 int amdgpu_amdkfd_resume_process(struct amdgpu_device *adev); 166 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, 167 const void *ih_ring_entry); 168 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev); 169 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev); 170 void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev); 171 int amdgpu_amdkfd_check_and_lock_kfd(struct amdgpu_device *adev); 172 void amdgpu_amdkfd_unlock_kfd(struct amdgpu_device *adev); 173 int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, 174 enum kgd_engine_type engine, 175 uint32_t vmid, uint64_t gpu_addr, 176 uint32_t *ib_cmd, uint32_t ib_len); 177 void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle); 178 bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev); 179 180 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid); 181 182 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev, 183 struct amdgpu_reset_context *reset_context); 184 185 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev); 186 187 void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev); 188 189 int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev, 190 int queue_bit); 191 192 struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context, 193 struct mm_struct *mm, 194 struct svm_range_bo *svm_bo, 195 u16 context_id); 196 197 int amdgpu_amdkfd_drm_client_create(struct amdgpu_device *adev); 198 #if defined(CONFIG_DEBUG_FS) 199 int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data); 200 #endif 201 #if IS_ENABLED(CONFIG_HSA_AMD) 202 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm); 203 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f); 204 void amdgpu_amdkfd_remove_all_eviction_fences(struct amdgpu_bo *bo); 205 int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni, 206 unsigned long cur_seq, struct kgd_mem *mem); 207 int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo, 208 uint32_t domain, 209 struct dma_fence *fence); 210 #else 211 static inline 212 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm) 213 { 214 return false; 215 } 216 217 static inline 218 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f) 219 { 220 return NULL; 221 } 222 223 static inline 224 void amdgpu_amdkfd_remove_all_eviction_fences(struct amdgpu_bo *bo) 225 { 226 } 227 228 static inline 229 int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni, 230 unsigned long cur_seq, struct kgd_mem *mem) 231 { 232 return 0; 233 } 234 static inline 235 int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo, 236 uint32_t domain, 237 struct dma_fence *fence) 238 { 239 return 0; 240 } 241 #endif 242 /* Shared API */ 243 int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size, 244 void **mem_obj, uint64_t *gpu_addr, 245 void **cpu_ptr, bool mqd_gfx9); 246 void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void **mem_obj); 247 int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size, 248 void **mem_obj); 249 void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj); 250 int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem); 251 int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem); 252 uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev, 253 enum kgd_engine_type type); 254 void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev, 255 struct kfd_local_mem_info *mem_info, 256 struct amdgpu_xcp *xcp); 257 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev); 258 259 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev); 260 int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, 261 struct amdgpu_device **dmabuf_adev, 262 uint64_t *bo_size, void *metadata_buffer, 263 size_t buffer_size, uint32_t *metadata_size, 264 uint32_t *flags, int8_t *xcp_id); 265 int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min); 266 int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev, 267 uint32_t *payload); 268 int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off, 269 u32 inst); 270 int amdgpu_amdkfd_start_sched(struct amdgpu_device *adev, uint32_t node_id); 271 int amdgpu_amdkfd_stop_sched(struct amdgpu_device *adev, uint32_t node_id); 272 int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcp_id, 273 bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable); 274 bool amdgpu_amdkfd_compute_active(struct amdgpu_device *adev, uint32_t node_id); 275 276 277 /* Read user wptr from a specified user address space with page fault 278 * disabled. The memory must be pinned and mapped to the hardware when 279 * this is called in hqd_load functions, so it should never fault in 280 * the first place. This resolves a circular lock dependency involving 281 * four locks, including the DQM lock and mmap_lock. 282 */ 283 #define read_user_wptr(mmptr, wptr, dst) \ 284 ({ \ 285 bool valid = false; \ 286 if ((mmptr) && (wptr)) { \ 287 pagefault_disable(); \ 288 if ((mmptr) == current->mm) { \ 289 valid = !get_user((dst), (wptr)); \ 290 } else if (current->flags & PF_KTHREAD) { \ 291 kthread_use_mm(mmptr); \ 292 valid = !get_user((dst), (wptr)); \ 293 kthread_unuse_mm(mmptr); \ 294 } \ 295 pagefault_enable(); \ 296 } \ 297 valid; \ 298 }) 299 300 /* GPUVM API */ 301 #define drm_priv_to_vm(drm_priv) \ 302 (&((struct amdgpu_fpriv *) \ 303 ((struct drm_file *)(drm_priv))->driver_priv)->vm) 304 305 int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev, 306 struct amdgpu_vm *avm, 307 void **process_info, 308 struct dma_fence **ef); 309 uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv); 310 size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev, 311 uint8_t xcp_id); 312 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( 313 struct amdgpu_device *adev, uint64_t va, uint64_t size, 314 void *drm_priv, struct kgd_mem **mem, 315 uint64_t *offset, uint32_t flags, bool criu_resume); 316 int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( 317 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv, 318 uint64_t *size); 319 int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(struct amdgpu_device *adev, 320 struct kgd_mem *mem, void *drm_priv); 321 int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( 322 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv); 323 int amdgpu_amdkfd_gpuvm_dmaunmap_mem(struct kgd_mem *mem, void *drm_priv); 324 int amdgpu_amdkfd_gpuvm_sync_memory( 325 struct amdgpu_device *adev, struct kgd_mem *mem, bool intr); 326 int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem, 327 void **kptr, uint64_t *size); 328 void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem); 329 330 int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_bo *bo, struct amdgpu_bo **bo_gart); 331 332 int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info, 333 struct dma_fence __rcu **ef); 334 int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev, 335 struct kfd_vm_fault_info *info); 336 int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd, 337 uint64_t va, void *drm_priv, 338 struct kgd_mem **mem, uint64_t *size, 339 uint64_t *mmap_offset); 340 int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, 341 struct dma_buf **dmabuf); 342 void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev); 343 int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, 344 struct tile_config *config); 345 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, 346 enum amdgpu_ras_block block, uint32_t reset); 347 348 void amdgpu_amdkfd_ras_pasid_poison_consumption_handler(struct amdgpu_device *adev, 349 enum amdgpu_ras_block block, uint16_t pasid, 350 pasid_notify pasid_fn, void *data, uint32_t reset); 351 352 bool amdgpu_amdkfd_is_fed(struct amdgpu_device *adev); 353 bool amdgpu_amdkfd_bo_mapped_to_dev(void *drm_priv, struct kgd_mem *mem); 354 void amdgpu_amdkfd_block_mmu_notifications(void *p); 355 int amdgpu_amdkfd_criu_resume(void *p); 356 int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev, 357 uint64_t size, u32 alloc_flag, int8_t xcp_id); 358 void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev, 359 uint64_t size, u32 alloc_flag, int8_t xcp_id); 360 361 u64 amdgpu_amdkfd_xcp_memory_size(struct amdgpu_device *adev, int xcp_id); 362 363 #define KFD_XCP_MEM_ID(adev, xcp_id) \ 364 ((adev)->xcp_mgr && (xcp_id) >= 0 ?\ 365 (adev)->xcp_mgr->xcp[(xcp_id)].mem_id : -1) 366 367 #define KFD_XCP_MEMORY_SIZE(adev, xcp_id) amdgpu_amdkfd_xcp_memory_size((adev), (xcp_id)) 368 369 370 #if IS_ENABLED(CONFIG_HSA_AMD) 371 void amdgpu_amdkfd_gpuvm_init_mem_limits(void); 372 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, 373 struct amdgpu_vm *vm); 374 375 /** 376 * @amdgpu_amdkfd_release_notify() - Notify KFD when GEM object is released 377 * 378 * Allows KFD to release its resources associated with the GEM object. 379 */ 380 void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo); 381 void amdgpu_amdkfd_reserve_system_mem(uint64_t size); 382 #else 383 static inline 384 void amdgpu_amdkfd_gpuvm_init_mem_limits(void) 385 { 386 } 387 388 static inline 389 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, 390 struct amdgpu_vm *vm) 391 { 392 } 393 394 static inline 395 void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo) 396 { 397 } 398 #endif 399 400 #if IS_ENABLED(CONFIG_HSA_AMD_SVM) 401 int kgd2kfd_init_zone_device(struct amdgpu_device *adev); 402 #else 403 static inline 404 int kgd2kfd_init_zone_device(struct amdgpu_device *adev) 405 { 406 return 0; 407 } 408 #endif 409 410 /* KGD2KFD callbacks */ 411 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger); 412 int kgd2kfd_resume_mm(struct mm_struct *mm); 413 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 414 u16 context_id, struct dma_fence *fence); 415 #if IS_ENABLED(CONFIG_HSA_AMD) 416 int kgd2kfd_init(void); 417 void kgd2kfd_exit(void); 418 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf); 419 bool kgd2kfd_device_init(struct kfd_dev *kfd, 420 const struct kgd2kfd_shared_resources *gpu_resources); 421 void kgd2kfd_device_exit(struct kfd_dev *kfd); 422 void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc); 423 int kgd2kfd_resume(struct kfd_dev *kfd, bool resume_proc); 424 void kgd2kfd_suspend_process(struct kfd_dev *kfd); 425 int kgd2kfd_resume_process(struct kfd_dev *kfd); 426 int kgd2kfd_pre_reset(struct kfd_dev *kfd, 427 struct amdgpu_reset_context *reset_context); 428 int kgd2kfd_post_reset(struct kfd_dev *kfd); 429 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry); 430 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd); 431 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask); 432 int kgd2kfd_check_and_lock_kfd(struct kfd_dev *kfd); 433 void kgd2kfd_unlock_kfd(struct kfd_dev *kfd); 434 int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id); 435 int kgd2kfd_start_sched_all_nodes(struct kfd_dev *kfd); 436 int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id); 437 int kgd2kfd_stop_sched_all_nodes(struct kfd_dev *kfd); 438 bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id); 439 bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry, 440 bool retry_fault); 441 442 #else 443 static inline int kgd2kfd_init(void) 444 { 445 return -ENOENT; 446 } 447 448 static inline void kgd2kfd_exit(void) 449 { 450 } 451 452 static inline 453 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 454 { 455 return NULL; 456 } 457 458 static inline 459 bool kgd2kfd_device_init(struct kfd_dev *kfd, 460 const struct kgd2kfd_shared_resources *gpu_resources) 461 { 462 return false; 463 } 464 465 static inline void kgd2kfd_device_exit(struct kfd_dev *kfd) 466 { 467 } 468 469 static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc) 470 { 471 } 472 473 static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool resume_proc) 474 { 475 return 0; 476 } 477 478 static inline void kgd2kfd_suspend_process(struct kfd_dev *kfd) 479 { 480 } 481 482 static inline int kgd2kfd_resume_process(struct kfd_dev *kfd) 483 { 484 return 0; 485 } 486 487 static inline int kgd2kfd_pre_reset(struct kfd_dev *kfd, 488 struct amdgpu_reset_context *reset_context) 489 { 490 return 0; 491 } 492 493 static inline int kgd2kfd_post_reset(struct kfd_dev *kfd) 494 { 495 return 0; 496 } 497 498 static inline 499 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 500 { 501 } 502 503 static inline 504 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 505 { 506 } 507 508 static inline 509 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 510 { 511 } 512 513 static inline int kgd2kfd_check_and_lock_kfd(struct kfd_dev *kfd) 514 { 515 return 0; 516 } 517 518 static inline void kgd2kfd_unlock_kfd(struct kfd_dev *kfd) 519 { 520 } 521 522 static inline int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id) 523 { 524 return 0; 525 } 526 527 static inline int kgd2kfd_start_sched_all_nodes(struct kfd_dev *kfd) 528 { 529 return 0; 530 } 531 532 static inline int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id) 533 { 534 return 0; 535 } 536 537 static inline int kgd2kfd_stop_sched_all_nodes(struct kfd_dev *kfd) 538 { 539 return 0; 540 } 541 542 static inline bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id) 543 { 544 return false; 545 } 546 547 static inline bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry, 548 bool retry_fault) 549 { 550 return false; 551 } 552 553 #endif 554 #endif /* AMDGPU_AMDKFD_H_INCLUDED */ 555