xref: /linux/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c (revision ec8a42e7343234802b9054874fe01810880289ce) 
1 /*
2  * Copyright 2014 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 
23 #include "amdgpu_amdkfd.h"
24 #include "amd_shared.h"
25 
26 #include "amdgpu.h"
27 #include "amdgpu_gfx.h"
28 #include "amdgpu_dma_buf.h"
29 #include <linux/module.h>
30 #include <linux/dma-buf.h>
31 #include "amdgpu_xgmi.h"
32 #include <uapi/linux/kfd_ioctl.h>
33 
34 /* Total memory size in system memory and all GPU VRAM. Used to
35  * estimate worst case amount of memory to reserve for page tables
36  */
37 uint64_t amdgpu_amdkfd_total_mem_size;
38 
39 static bool kfd_initialized;
40 
41 int amdgpu_amdkfd_init(void)
42 {
43 	struct sysinfo si;
44 	int ret;
45 
46 	si_meminfo(&si);
47 	amdgpu_amdkfd_total_mem_size = si.totalram - si.totalhigh;
48 	amdgpu_amdkfd_total_mem_size *= si.mem_unit;
49 
50 #ifdef CONFIG_HSA_AMD
51 	ret = kgd2kfd_init();
52 	amdgpu_amdkfd_gpuvm_init_mem_limits();
53 #else
54 	ret = -ENOENT;
55 #endif
56 	kfd_initialized = !ret;
57 
58 	return ret;
59 }
60 
61 void amdgpu_amdkfd_fini(void)
62 {
63 	if (kfd_initialized) {
64 		kgd2kfd_exit();
65 		kfd_initialized = false;
66 	}
67 }
68 
69 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
70 {
71 	bool vf = amdgpu_sriov_vf(adev);
72 
73 	if (!kfd_initialized)
74 		return;
75 
76 	adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev,
77 				      adev->pdev, adev->asic_type, vf);
78 
79 	if (adev->kfd.dev)
80 		amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size;
81 }
82 
83 /**
84  * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
85  *                                setup amdkfd
86  *
87  * @adev: amdgpu_device pointer
88  * @aperture_base: output returning doorbell aperture base physical address
89  * @aperture_size: output returning doorbell aperture size in bytes
90  * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
91  *
92  * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
93  * takes doorbells required for its own rings and reports the setup to amdkfd.
94  * amdgpu reserved doorbells are at the start of the doorbell aperture.
95  */
96 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
97 					 phys_addr_t *aperture_base,
98 					 size_t *aperture_size,
99 					 size_t *start_offset)
100 {
101 	/*
102 	 * The first num_doorbells are used by amdgpu.
103 	 * amdkfd takes whatever's left in the aperture.
104 	 */
105 	if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
106 		*aperture_base = adev->doorbell.base;
107 		*aperture_size = adev->doorbell.size;
108 		*start_offset = adev->doorbell.num_doorbells * sizeof(u32);
109 	} else {
110 		*aperture_base = 0;
111 		*aperture_size = 0;
112 		*start_offset = 0;
113 	}
114 }
115 
116 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
117 {
118 	int i;
119 	int last_valid_bit;
120 
121 	if (adev->kfd.dev) {
122 		struct kgd2kfd_shared_resources gpu_resources = {
123 			.compute_vmid_bitmap =
124 				((1 << AMDGPU_NUM_VMID) - 1) -
125 				((1 << adev->vm_manager.first_kfd_vmid) - 1),
126 			.num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
127 			.num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
128 			.gpuvm_size = min(adev->vm_manager.max_pfn
129 					  << AMDGPU_GPU_PAGE_SHIFT,
130 					  AMDGPU_GMC_HOLE_START),
131 			.drm_render_minor = adev_to_drm(adev)->render->index,
132 			.sdma_doorbell_idx = adev->doorbell_index.sdma_engine,
133 
134 		};
135 
136 		/* this is going to have a few of the MSBs set that we need to
137 		 * clear
138 		 */
139 		bitmap_complement(gpu_resources.cp_queue_bitmap,
140 				  adev->gfx.mec.queue_bitmap,
141 				  KGD_MAX_QUEUES);
142 
143 		/* According to linux/bitmap.h we shouldn't use bitmap_clear if
144 		 * nbits is not compile time constant
145 		 */
146 		last_valid_bit = 1 /* only first MEC can have compute queues */
147 				* adev->gfx.mec.num_pipe_per_mec
148 				* adev->gfx.mec.num_queue_per_pipe;
149 		for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i)
150 			clear_bit(i, gpu_resources.cp_queue_bitmap);
151 
152 		amdgpu_doorbell_get_kfd_info(adev,
153 				&gpu_resources.doorbell_physical_address,
154 				&gpu_resources.doorbell_aperture_size,
155 				&gpu_resources.doorbell_start_offset);
156 
157 		/* Since SOC15, BIF starts to statically use the
158 		 * lower 12 bits of doorbell addresses for routing
159 		 * based on settings in registers like
160 		 * SDMA0_DOORBELL_RANGE etc..
161 		 * In order to route a doorbell to CP engine, the lower
162 		 * 12 bits of its address has to be outside the range
163 		 * set for SDMA, VCN, and IH blocks.
164 		 */
165 		if (adev->asic_type >= CHIP_VEGA10) {
166 			gpu_resources.non_cp_doorbells_start =
167 					adev->doorbell_index.first_non_cp;
168 			gpu_resources.non_cp_doorbells_end =
169 					adev->doorbell_index.last_non_cp;
170 		}
171 
172 		kgd2kfd_device_init(adev->kfd.dev, adev_to_drm(adev), &gpu_resources);
173 	}
174 }
175 
176 void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev)
177 {
178 	if (adev->kfd.dev) {
179 		kgd2kfd_device_exit(adev->kfd.dev);
180 		adev->kfd.dev = NULL;
181 	}
182 }
183 
184 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
185 		const void *ih_ring_entry)
186 {
187 	if (adev->kfd.dev)
188 		kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry);
189 }
190 
191 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm)
192 {
193 	if (adev->kfd.dev)
194 		kgd2kfd_suspend(adev->kfd.dev, run_pm);
195 }
196 
197 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm)
198 {
199 	int r = 0;
200 
201 	if (adev->kfd.dev)
202 		r = kgd2kfd_resume(adev->kfd.dev, run_pm);
203 
204 	return r;
205 }
206 
207 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev)
208 {
209 	int r = 0;
210 
211 	if (adev->kfd.dev)
212 		r = kgd2kfd_pre_reset(adev->kfd.dev);
213 
214 	return r;
215 }
216 
217 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev)
218 {
219 	int r = 0;
220 
221 	if (adev->kfd.dev)
222 		r = kgd2kfd_post_reset(adev->kfd.dev);
223 
224 	return r;
225 }
226 
227 void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd)
228 {
229 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
230 
231 	if (amdgpu_device_should_recover_gpu(adev))
232 		amdgpu_device_gpu_recover(adev, NULL);
233 }
234 
235 int amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
236 				void **mem_obj, uint64_t *gpu_addr,
237 				void **cpu_ptr, bool cp_mqd_gfx9)
238 {
239 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
240 	struct amdgpu_bo *bo = NULL;
241 	struct amdgpu_bo_param bp;
242 	int r;
243 	void *cpu_ptr_tmp = NULL;
244 
245 	memset(&bp, 0, sizeof(bp));
246 	bp.size = size;
247 	bp.byte_align = PAGE_SIZE;
248 	bp.domain = AMDGPU_GEM_DOMAIN_GTT;
249 	bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
250 	bp.type = ttm_bo_type_kernel;
251 	bp.resv = NULL;
252 
253 	if (cp_mqd_gfx9)
254 		bp.flags |= AMDGPU_GEM_CREATE_CP_MQD_GFX9;
255 
256 	r = amdgpu_bo_create(adev, &bp, &bo);
257 	if (r) {
258 		dev_err(adev->dev,
259 			"failed to allocate BO for amdkfd (%d)\n", r);
260 		return r;
261 	}
262 
263 	/* map the buffer */
264 	r = amdgpu_bo_reserve(bo, true);
265 	if (r) {
266 		dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
267 		goto allocate_mem_reserve_bo_failed;
268 	}
269 
270 	r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
271 	if (r) {
272 		dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
273 		goto allocate_mem_pin_bo_failed;
274 	}
275 
276 	r = amdgpu_ttm_alloc_gart(&bo->tbo);
277 	if (r) {
278 		dev_err(adev->dev, "%p bind failed\n", bo);
279 		goto allocate_mem_kmap_bo_failed;
280 	}
281 
282 	r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp);
283 	if (r) {
284 		dev_err(adev->dev,
285 			"(%d) failed to map bo to kernel for amdkfd\n", r);
286 		goto allocate_mem_kmap_bo_failed;
287 	}
288 
289 	*mem_obj = bo;
290 	*gpu_addr = amdgpu_bo_gpu_offset(bo);
291 	*cpu_ptr = cpu_ptr_tmp;
292 
293 	amdgpu_bo_unreserve(bo);
294 
295 	return 0;
296 
297 allocate_mem_kmap_bo_failed:
298 	amdgpu_bo_unpin(bo);
299 allocate_mem_pin_bo_failed:
300 	amdgpu_bo_unreserve(bo);
301 allocate_mem_reserve_bo_failed:
302 	amdgpu_bo_unref(&bo);
303 
304 	return r;
305 }
306 
307 void amdgpu_amdkfd_free_gtt_mem(struct kgd_dev *kgd, void *mem_obj)
308 {
309 	struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj;
310 
311 	amdgpu_bo_reserve(bo, true);
312 	amdgpu_bo_kunmap(bo);
313 	amdgpu_bo_unpin(bo);
314 	amdgpu_bo_unreserve(bo);
315 	amdgpu_bo_unref(&(bo));
316 }
317 
318 int amdgpu_amdkfd_alloc_gws(struct kgd_dev *kgd, size_t size,
319 				void **mem_obj)
320 {
321 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
322 	struct amdgpu_bo *bo = NULL;
323 	struct amdgpu_bo_param bp;
324 	int r;
325 
326 	memset(&bp, 0, sizeof(bp));
327 	bp.size = size;
328 	bp.byte_align = 1;
329 	bp.domain = AMDGPU_GEM_DOMAIN_GWS;
330 	bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
331 	bp.type = ttm_bo_type_device;
332 	bp.resv = NULL;
333 
334 	r = amdgpu_bo_create(adev, &bp, &bo);
335 	if (r) {
336 		dev_err(adev->dev,
337 			"failed to allocate gws BO for amdkfd (%d)\n", r);
338 		return r;
339 	}
340 
341 	*mem_obj = bo;
342 	return 0;
343 }
344 
345 void amdgpu_amdkfd_free_gws(struct kgd_dev *kgd, void *mem_obj)
346 {
347 	struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj;
348 
349 	amdgpu_bo_unref(&bo);
350 }
351 
352 uint32_t amdgpu_amdkfd_get_fw_version(struct kgd_dev *kgd,
353 				      enum kgd_engine_type type)
354 {
355 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
356 
357 	switch (type) {
358 	case KGD_ENGINE_PFP:
359 		return adev->gfx.pfp_fw_version;
360 
361 	case KGD_ENGINE_ME:
362 		return adev->gfx.me_fw_version;
363 
364 	case KGD_ENGINE_CE:
365 		return adev->gfx.ce_fw_version;
366 
367 	case KGD_ENGINE_MEC1:
368 		return adev->gfx.mec_fw_version;
369 
370 	case KGD_ENGINE_MEC2:
371 		return adev->gfx.mec2_fw_version;
372 
373 	case KGD_ENGINE_RLC:
374 		return adev->gfx.rlc_fw_version;
375 
376 	case KGD_ENGINE_SDMA1:
377 		return adev->sdma.instance[0].fw_version;
378 
379 	case KGD_ENGINE_SDMA2:
380 		return adev->sdma.instance[1].fw_version;
381 
382 	default:
383 		return 0;
384 	}
385 
386 	return 0;
387 }
388 
389 void amdgpu_amdkfd_get_local_mem_info(struct kgd_dev *kgd,
390 				      struct kfd_local_mem_info *mem_info)
391 {
392 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
393 
394 	memset(mem_info, 0, sizeof(*mem_info));
395 
396 	mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
397 	mem_info->local_mem_size_private = adev->gmc.real_vram_size -
398 						adev->gmc.visible_vram_size;
399 
400 	mem_info->vram_width = adev->gmc.vram_width;
401 
402 	pr_debug("Address base: %pap public 0x%llx private 0x%llx\n",
403 			&adev->gmc.aper_base,
404 			mem_info->local_mem_size_public,
405 			mem_info->local_mem_size_private);
406 
407 	if (amdgpu_sriov_vf(adev))
408 		mem_info->mem_clk_max = adev->clock.default_mclk / 100;
409 	else if (adev->pm.dpm_enabled) {
410 		if (amdgpu_emu_mode == 1)
411 			mem_info->mem_clk_max = 0;
412 		else
413 			mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
414 	} else
415 		mem_info->mem_clk_max = 100;
416 }
417 
418 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct kgd_dev *kgd)
419 {
420 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
421 
422 	if (adev->gfx.funcs->get_gpu_clock_counter)
423 		return adev->gfx.funcs->get_gpu_clock_counter(adev);
424 	return 0;
425 }
426 
427 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
428 {
429 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
430 
431 	/* the sclk is in quantas of 10kHz */
432 	if (amdgpu_sriov_vf(adev))
433 		return adev->clock.default_sclk / 100;
434 	else if (adev->pm.dpm_enabled)
435 		return amdgpu_dpm_get_sclk(adev, false) / 100;
436 	else
437 		return 100;
438 }
439 
440 void amdgpu_amdkfd_get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info)
441 {
442 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
443 	struct amdgpu_cu_info acu_info = adev->gfx.cu_info;
444 
445 	memset(cu_info, 0, sizeof(*cu_info));
446 	if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap))
447 		return;
448 
449 	cu_info->cu_active_number = acu_info.number;
450 	cu_info->cu_ao_mask = acu_info.ao_cu_mask;
451 	memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0],
452 	       sizeof(acu_info.bitmap));
453 	cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;
454 	cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
455 	cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
456 	cu_info->simd_per_cu = acu_info.simd_per_cu;
457 	cu_info->max_waves_per_simd = acu_info.max_waves_per_simd;
458 	cu_info->wave_front_size = acu_info.wave_front_size;
459 	cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu;
460 	cu_info->lds_size = acu_info.lds_size;
461 }
462 
463 int amdgpu_amdkfd_get_dmabuf_info(struct kgd_dev *kgd, int dma_buf_fd,
464 				  struct kgd_dev **dma_buf_kgd,
465 				  uint64_t *bo_size, void *metadata_buffer,
466 				  size_t buffer_size, uint32_t *metadata_size,
467 				  uint32_t *flags)
468 {
469 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
470 	struct dma_buf *dma_buf;
471 	struct drm_gem_object *obj;
472 	struct amdgpu_bo *bo;
473 	uint64_t metadata_flags;
474 	int r = -EINVAL;
475 
476 	dma_buf = dma_buf_get(dma_buf_fd);
477 	if (IS_ERR(dma_buf))
478 		return PTR_ERR(dma_buf);
479 
480 	if (dma_buf->ops != &amdgpu_dmabuf_ops)
481 		/* Can't handle non-graphics buffers */
482 		goto out_put;
483 
484 	obj = dma_buf->priv;
485 	if (obj->dev->driver != adev_to_drm(adev)->driver)
486 		/* Can't handle buffers from different drivers */
487 		goto out_put;
488 
489 	adev = drm_to_adev(obj->dev);
490 	bo = gem_to_amdgpu_bo(obj);
491 	if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
492 				    AMDGPU_GEM_DOMAIN_GTT)))
493 		/* Only VRAM and GTT BOs are supported */
494 		goto out_put;
495 
496 	r = 0;
497 	if (dma_buf_kgd)
498 		*dma_buf_kgd = (struct kgd_dev *)adev;
499 	if (bo_size)
500 		*bo_size = amdgpu_bo_size(bo);
501 	if (metadata_size)
502 		*metadata_size = bo->metadata_size;
503 	if (metadata_buffer)
504 		r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size,
505 					   metadata_size, &metadata_flags);
506 	if (flags) {
507 		*flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
508 				KFD_IOC_ALLOC_MEM_FLAGS_VRAM
509 				: KFD_IOC_ALLOC_MEM_FLAGS_GTT;
510 
511 		if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
512 			*flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC;
513 	}
514 
515 out_put:
516 	dma_buf_put(dma_buf);
517 	return r;
518 }
519 
520 uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd)
521 {
522 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
523 	struct ttm_resource_manager *vram_man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
524 
525 	return amdgpu_vram_mgr_usage(vram_man);
526 }
527 
528 uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd)
529 {
530 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
531 
532 	return adev->gmc.xgmi.hive_id;
533 }
534 
535 uint64_t amdgpu_amdkfd_get_unique_id(struct kgd_dev *kgd)
536 {
537 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
538 
539 	return adev->unique_id;
540 }
541 
542 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *src)
543 {
544 	struct amdgpu_device *peer_adev = (struct amdgpu_device *)src;
545 	struct amdgpu_device *adev = (struct amdgpu_device *)dst;
546 	int ret = amdgpu_xgmi_get_hops_count(adev, peer_adev);
547 
548 	if (ret < 0) {
549 		DRM_ERROR("amdgpu: failed to get  xgmi hops count between node %d and %d. ret = %d\n",
550 			adev->gmc.xgmi.physical_node_id,
551 			peer_adev->gmc.xgmi.physical_node_id, ret);
552 		ret = 0;
553 	}
554 	return  (uint8_t)ret;
555 }
556 
557 uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd)
558 {
559 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
560 
561 	return adev->rmmio_remap.bus_addr;
562 }
563 
564 uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd)
565 {
566 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
567 
568 	return adev->gds.gws_size;
569 }
570 
571 uint32_t amdgpu_amdkfd_get_asic_rev_id(struct kgd_dev *kgd)
572 {
573 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
574 
575 	return adev->rev_id;
576 }
577 
578 int amdgpu_amdkfd_get_noretry(struct kgd_dev *kgd)
579 {
580 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
581 
582 	return adev->gmc.noretry;
583 }
584 
585 int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
586 				uint32_t vmid, uint64_t gpu_addr,
587 				uint32_t *ib_cmd, uint32_t ib_len)
588 {
589 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
590 	struct amdgpu_job *job;
591 	struct amdgpu_ib *ib;
592 	struct amdgpu_ring *ring;
593 	struct dma_fence *f = NULL;
594 	int ret;
595 
596 	switch (engine) {
597 	case KGD_ENGINE_MEC1:
598 		ring = &adev->gfx.compute_ring[0];
599 		break;
600 	case KGD_ENGINE_SDMA1:
601 		ring = &adev->sdma.instance[0].ring;
602 		break;
603 	case KGD_ENGINE_SDMA2:
604 		ring = &adev->sdma.instance[1].ring;
605 		break;
606 	default:
607 		pr_err("Invalid engine in IB submission: %d\n", engine);
608 		ret = -EINVAL;
609 		goto err;
610 	}
611 
612 	ret = amdgpu_job_alloc(adev, 1, &job, NULL);
613 	if (ret)
614 		goto err;
615 
616 	ib = &job->ibs[0];
617 	memset(ib, 0, sizeof(struct amdgpu_ib));
618 
619 	ib->gpu_addr = gpu_addr;
620 	ib->ptr = ib_cmd;
621 	ib->length_dw = ib_len;
622 	/* This works for NO_HWS. TODO: need to handle without knowing VMID */
623 	job->vmid = vmid;
624 
625 	ret = amdgpu_ib_schedule(ring, 1, ib, job, &f);
626 
627 	if (ret) {
628 		DRM_ERROR("amdgpu: failed to schedule IB.\n");
629 		goto err_ib_sched;
630 	}
631 
632 	ret = dma_fence_wait(f, false);
633 
634 err_ib_sched:
635 	dma_fence_put(f);
636 	amdgpu_job_free(job);
637 err:
638 	return ret;
639 }
640 
641 void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle)
642 {
643 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
644 
645 	/* Temp workaround to fix the soft hang observed in certain compute
646 	 * applications if GFXOFF is enabled.
647 	 */
648 	if (adev->asic_type == CHIP_SIENNA_CICHLID) {
649 		pr_debug("GFXOFF is %s\n", idle ? "enabled" : "disabled");
650 		amdgpu_gfx_off_ctrl(adev, idle);
651 	}
652 	amdgpu_dpm_switch_power_profile(adev,
653 					PP_SMC_POWER_PROFILE_COMPUTE,
654 					!idle);
655 }
656 
657 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
658 {
659 	if (adev->kfd.dev)
660 		return vmid >= adev->vm_manager.first_kfd_vmid;
661 
662 	return false;
663 }
664 
665 int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev *kgd, uint16_t vmid)
666 {
667 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
668 
669 	if (adev->family == AMDGPU_FAMILY_AI) {
670 		int i;
671 
672 		for (i = 0; i < adev->num_vmhubs; i++)
673 			amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0);
674 	} else {
675 		amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB_0, 0);
676 	}
677 
678 	return 0;
679 }
680 
681 int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t pasid)
682 {
683 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
684 	const uint32_t flush_type = 0;
685 	bool all_hub = false;
686 
687 	if (adev->family == AMDGPU_FAMILY_AI)
688 		all_hub = true;
689 
690 	return amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, flush_type, all_hub);
691 }
692 
693 bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd)
694 {
695 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
696 
697 	return adev->have_atomics_support;
698 }
699 
700 #ifndef CONFIG_HSA_AMD
701 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
702 {
703 	return false;
704 }
705 
706 void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo)
707 {
708 }
709 
710 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
711 {
712 	return 0;
713 }
714 
715 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
716 					struct amdgpu_vm *vm)
717 {
718 }
719 
720 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f)
721 {
722 	return NULL;
723 }
724 
725 int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm)
726 {
727 	return 0;
728 }
729 
730 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev,
731 			      unsigned int asic_type, bool vf)
732 {
733 	return NULL;
734 }
735 
736 bool kgd2kfd_device_init(struct kfd_dev *kfd,
737 			 struct drm_device *ddev,
738 			 const struct kgd2kfd_shared_resources *gpu_resources)
739 {
740 	return false;
741 }
742 
743 void kgd2kfd_device_exit(struct kfd_dev *kfd)
744 {
745 }
746 
747 void kgd2kfd_exit(void)
748 {
749 }
750 
751 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
752 {
753 }
754 
755 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
756 {
757 	return 0;
758 }
759 
760 int kgd2kfd_pre_reset(struct kfd_dev *kfd)
761 {
762 	return 0;
763 }
764 
765 int kgd2kfd_post_reset(struct kfd_dev *kfd)
766 {
767 	return 0;
768 }
769 
770 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
771 {
772 }
773 
774 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
775 {
776 }
777 
778 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint32_t throttle_bitmask)
779 {
780 }
781 #endif
782