1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2014 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include "amdgpu_amdkfd.h" 25 #include "amd_pcie.h" 26 #include "amd_shared.h" 27 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_dma_buf.h" 31 #include <drm/ttm/ttm_tt.h> 32 #include <linux/module.h> 33 #include <linux/dma-buf.h> 34 #include "amdgpu_xgmi.h" 35 #include <uapi/linux/kfd_ioctl.h> 36 #include "amdgpu_ras.h" 37 #include "amdgpu_umc.h" 38 #include "amdgpu_reset.h" 39 40 /* Total memory size in system memory and all GPU VRAM. Used to 41 * estimate worst case amount of memory to reserve for page tables 42 */ 43 uint64_t amdgpu_amdkfd_total_mem_size; 44 45 static bool kfd_initialized; 46 47 int amdgpu_amdkfd_init(void) 48 { 49 struct sysinfo si; 50 int ret; 51 52 si_meminfo(&si); 53 amdgpu_amdkfd_total_mem_size = si.freeram - si.freehigh; 54 amdgpu_amdkfd_total_mem_size *= si.mem_unit; 55 56 ret = kgd2kfd_init(); 57 kfd_initialized = !ret; 58 59 return ret; 60 } 61 62 void amdgpu_amdkfd_fini(void) 63 { 64 if (kfd_initialized) { 65 kgd2kfd_exit(); 66 kfd_initialized = false; 67 } 68 } 69 70 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) 71 { 72 bool vf = amdgpu_sriov_vf(adev); 73 74 if (!kfd_initialized) 75 return; 76 77 adev->kfd.dev = kgd2kfd_probe(adev, vf); 78 } 79 80 /** 81 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to 82 * setup amdkfd 83 * 84 * @adev: amdgpu_device pointer 85 * @aperture_base: output returning doorbell aperture base physical address 86 * @aperture_size: output returning doorbell aperture size in bytes 87 * @start_offset: output returning # of doorbell bytes reserved for amdgpu. 88 * 89 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, 90 * takes doorbells required for its own rings and reports the setup to amdkfd. 91 * amdgpu reserved doorbells are at the start of the doorbell aperture. 92 */ 93 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 94 phys_addr_t *aperture_base, 95 size_t *aperture_size, 96 size_t *start_offset) 97 { 98 /* 99 * The first num_kernel_doorbells are used by amdgpu. 100 * amdkfd takes whatever's left in the aperture. 101 */ 102 if (adev->enable_mes) { 103 /* 104 * With MES enabled, we only need to initialize 105 * the base address. The size and offset are 106 * not initialized as AMDGPU manages the whole 107 * doorbell space. 108 */ 109 *aperture_base = adev->doorbell.base; 110 *aperture_size = 0; 111 *start_offset = 0; 112 } else if (adev->doorbell.size > adev->doorbell.num_kernel_doorbells * 113 sizeof(u32)) { 114 *aperture_base = adev->doorbell.base; 115 *aperture_size = adev->doorbell.size; 116 *start_offset = adev->doorbell.num_kernel_doorbells * sizeof(u32); 117 } else { 118 *aperture_base = 0; 119 *aperture_size = 0; 120 *start_offset = 0; 121 } 122 } 123 124 125 static void amdgpu_amdkfd_reset_work(struct work_struct *work) 126 { 127 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 128 kfd.reset_work); 129 130 struct amdgpu_reset_context reset_context; 131 132 memset(&reset_context, 0, sizeof(reset_context)); 133 134 reset_context.method = AMD_RESET_METHOD_NONE; 135 reset_context.reset_req_dev = adev; 136 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 137 138 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 139 } 140 141 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) 142 { 143 int i; 144 int last_valid_bit; 145 int ret; 146 147 amdgpu_amdkfd_gpuvm_init_mem_limits(); 148 149 if (adev->kfd.dev) { 150 struct kgd2kfd_shared_resources gpu_resources = { 151 .compute_vmid_bitmap = 152 ((1 << AMDGPU_NUM_VMID) - 1) - 153 ((1 << adev->vm_manager.first_kfd_vmid) - 1), 154 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, 155 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, 156 .gpuvm_size = min(adev->vm_manager.max_pfn 157 << AMDGPU_GPU_PAGE_SHIFT, 158 AMDGPU_GMC_HOLE_START), 159 .drm_render_minor = adev_to_drm(adev)->render->index, 160 .sdma_doorbell_idx = adev->doorbell_index.sdma_engine, 161 .enable_mes = adev->enable_mes, 162 }; 163 164 ret = drm_client_init(&adev->ddev, &adev->kfd.client, "kfd", NULL); 165 if (ret) { 166 dev_err(adev->dev, "Failed to init DRM client: %d\n", ret); 167 return; 168 } 169 170 /* this is going to have a few of the MSBs set that we need to 171 * clear 172 */ 173 bitmap_complement(gpu_resources.cp_queue_bitmap, 174 adev->gfx.mec_bitmap[0].queue_bitmap, 175 AMDGPU_MAX_QUEUES); 176 177 /* According to linux/bitmap.h we shouldn't use bitmap_clear if 178 * nbits is not compile time constant 179 */ 180 last_valid_bit = 1 /* only first MEC can have compute queues */ 181 * adev->gfx.mec.num_pipe_per_mec 182 * adev->gfx.mec.num_queue_per_pipe; 183 for (i = last_valid_bit; i < AMDGPU_MAX_QUEUES; ++i) 184 clear_bit(i, gpu_resources.cp_queue_bitmap); 185 186 amdgpu_doorbell_get_kfd_info(adev, 187 &gpu_resources.doorbell_physical_address, 188 &gpu_resources.doorbell_aperture_size, 189 &gpu_resources.doorbell_start_offset); 190 191 /* Since SOC15, BIF starts to statically use the 192 * lower 12 bits of doorbell addresses for routing 193 * based on settings in registers like 194 * SDMA0_DOORBELL_RANGE etc.. 195 * In order to route a doorbell to CP engine, the lower 196 * 12 bits of its address has to be outside the range 197 * set for SDMA, VCN, and IH blocks. 198 */ 199 if (adev->asic_type >= CHIP_VEGA10) { 200 gpu_resources.non_cp_doorbells_start = 201 adev->doorbell_index.first_non_cp; 202 gpu_resources.non_cp_doorbells_end = 203 adev->doorbell_index.last_non_cp; 204 } 205 206 adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev, 207 &gpu_resources); 208 if (adev->kfd.init_complete) 209 drm_client_register(&adev->kfd.client); 210 else 211 drm_client_release(&adev->kfd.client); 212 213 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size; 214 215 INIT_WORK(&adev->kfd.reset_work, amdgpu_amdkfd_reset_work); 216 } 217 } 218 219 void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev) 220 { 221 if (adev->kfd.dev) { 222 kgd2kfd_device_exit(adev->kfd.dev); 223 adev->kfd.dev = NULL; 224 amdgpu_amdkfd_total_mem_size -= adev->gmc.real_vram_size; 225 } 226 } 227 228 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, 229 const void *ih_ring_entry) 230 { 231 if (adev->kfd.dev) 232 kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry); 233 } 234 235 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm) 236 { 237 if (adev->kfd.dev) 238 kgd2kfd_suspend(adev->kfd.dev, run_pm); 239 } 240 241 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm) 242 { 243 int r = 0; 244 245 if (adev->kfd.dev) 246 r = kgd2kfd_resume(adev->kfd.dev, run_pm); 247 248 return r; 249 } 250 251 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev) 252 { 253 int r = 0; 254 255 if (adev->kfd.dev) 256 r = kgd2kfd_pre_reset(adev->kfd.dev); 257 258 return r; 259 } 260 261 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev) 262 { 263 int r = 0; 264 265 if (adev->kfd.dev) 266 r = kgd2kfd_post_reset(adev->kfd.dev); 267 268 return r; 269 } 270 271 void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev) 272 { 273 if (amdgpu_device_should_recover_gpu(adev)) 274 amdgpu_reset_domain_schedule(adev->reset_domain, 275 &adev->kfd.reset_work); 276 } 277 278 int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size, 279 void **mem_obj, uint64_t *gpu_addr, 280 void **cpu_ptr, bool cp_mqd_gfx9) 281 { 282 struct amdgpu_bo *bo = NULL; 283 struct amdgpu_bo_param bp; 284 int r; 285 void *cpu_ptr_tmp = NULL; 286 287 memset(&bp, 0, sizeof(bp)); 288 bp.size = size; 289 bp.byte_align = PAGE_SIZE; 290 bp.domain = AMDGPU_GEM_DOMAIN_GTT; 291 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC; 292 bp.type = ttm_bo_type_kernel; 293 bp.resv = NULL; 294 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 295 296 if (cp_mqd_gfx9) 297 bp.flags |= AMDGPU_GEM_CREATE_CP_MQD_GFX9; 298 299 r = amdgpu_bo_create(adev, &bp, &bo); 300 if (r) { 301 dev_err(adev->dev, 302 "failed to allocate BO for amdkfd (%d)\n", r); 303 return r; 304 } 305 306 /* map the buffer */ 307 r = amdgpu_bo_reserve(bo, true); 308 if (r) { 309 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r); 310 goto allocate_mem_reserve_bo_failed; 311 } 312 313 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); 314 if (r) { 315 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r); 316 goto allocate_mem_pin_bo_failed; 317 } 318 319 r = amdgpu_ttm_alloc_gart(&bo->tbo); 320 if (r) { 321 dev_err(adev->dev, "%p bind failed\n", bo); 322 goto allocate_mem_kmap_bo_failed; 323 } 324 325 r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp); 326 if (r) { 327 dev_err(adev->dev, 328 "(%d) failed to map bo to kernel for amdkfd\n", r); 329 goto allocate_mem_kmap_bo_failed; 330 } 331 332 *mem_obj = bo; 333 *gpu_addr = amdgpu_bo_gpu_offset(bo); 334 *cpu_ptr = cpu_ptr_tmp; 335 336 amdgpu_bo_unreserve(bo); 337 338 return 0; 339 340 allocate_mem_kmap_bo_failed: 341 amdgpu_bo_unpin(bo); 342 allocate_mem_pin_bo_failed: 343 amdgpu_bo_unreserve(bo); 344 allocate_mem_reserve_bo_failed: 345 amdgpu_bo_unref(&bo); 346 347 return r; 348 } 349 350 void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void *mem_obj) 351 { 352 struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj; 353 354 amdgpu_bo_reserve(bo, true); 355 amdgpu_bo_kunmap(bo); 356 amdgpu_bo_unpin(bo); 357 amdgpu_bo_unreserve(bo); 358 amdgpu_bo_unref(&(bo)); 359 } 360 361 int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size, 362 void **mem_obj) 363 { 364 struct amdgpu_bo *bo = NULL; 365 struct amdgpu_bo_user *ubo; 366 struct amdgpu_bo_param bp; 367 int r; 368 369 memset(&bp, 0, sizeof(bp)); 370 bp.size = size; 371 bp.byte_align = 1; 372 bp.domain = AMDGPU_GEM_DOMAIN_GWS; 373 bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 374 bp.type = ttm_bo_type_device; 375 bp.resv = NULL; 376 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 377 378 r = amdgpu_bo_create_user(adev, &bp, &ubo); 379 if (r) { 380 dev_err(adev->dev, 381 "failed to allocate gws BO for amdkfd (%d)\n", r); 382 return r; 383 } 384 385 bo = &ubo->bo; 386 *mem_obj = bo; 387 return 0; 388 } 389 390 void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj) 391 { 392 struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj; 393 394 amdgpu_bo_unref(&bo); 395 } 396 397 uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev, 398 enum kgd_engine_type type) 399 { 400 switch (type) { 401 case KGD_ENGINE_PFP: 402 return adev->gfx.pfp_fw_version; 403 404 case KGD_ENGINE_ME: 405 return adev->gfx.me_fw_version; 406 407 case KGD_ENGINE_CE: 408 return adev->gfx.ce_fw_version; 409 410 case KGD_ENGINE_MEC1: 411 return adev->gfx.mec_fw_version; 412 413 case KGD_ENGINE_MEC2: 414 return adev->gfx.mec2_fw_version; 415 416 case KGD_ENGINE_RLC: 417 return adev->gfx.rlc_fw_version; 418 419 case KGD_ENGINE_SDMA1: 420 return adev->sdma.instance[0].fw_version; 421 422 case KGD_ENGINE_SDMA2: 423 return adev->sdma.instance[1].fw_version; 424 425 default: 426 return 0; 427 } 428 429 return 0; 430 } 431 432 void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev, 433 struct kfd_local_mem_info *mem_info, 434 struct amdgpu_xcp *xcp) 435 { 436 memset(mem_info, 0, sizeof(*mem_info)); 437 438 if (xcp) { 439 if (adev->gmc.real_vram_size == adev->gmc.visible_vram_size) 440 mem_info->local_mem_size_public = 441 KFD_XCP_MEMORY_SIZE(adev, xcp->id); 442 else 443 mem_info->local_mem_size_private = 444 KFD_XCP_MEMORY_SIZE(adev, xcp->id); 445 } else { 446 mem_info->local_mem_size_public = adev->gmc.visible_vram_size; 447 mem_info->local_mem_size_private = adev->gmc.real_vram_size - 448 adev->gmc.visible_vram_size; 449 } 450 mem_info->vram_width = adev->gmc.vram_width; 451 452 pr_debug("Address base: %pap public 0x%llx private 0x%llx\n", 453 &adev->gmc.aper_base, 454 mem_info->local_mem_size_public, 455 mem_info->local_mem_size_private); 456 457 if (adev->pm.dpm_enabled) { 458 if (amdgpu_emu_mode == 1) 459 mem_info->mem_clk_max = 0; 460 else 461 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100; 462 } else 463 mem_info->mem_clk_max = 100; 464 } 465 466 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev) 467 { 468 if (adev->gfx.funcs->get_gpu_clock_counter) 469 return adev->gfx.funcs->get_gpu_clock_counter(adev); 470 return 0; 471 } 472 473 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev) 474 { 475 /* the sclk is in quantas of 10kHz */ 476 if (adev->pm.dpm_enabled) 477 return amdgpu_dpm_get_sclk(adev, false) / 100; 478 else 479 return 100; 480 } 481 482 int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, 483 struct amdgpu_device **dmabuf_adev, 484 uint64_t *bo_size, void *metadata_buffer, 485 size_t buffer_size, uint32_t *metadata_size, 486 uint32_t *flags, int8_t *xcp_id) 487 { 488 struct dma_buf *dma_buf; 489 struct drm_gem_object *obj; 490 struct amdgpu_bo *bo; 491 uint64_t metadata_flags; 492 int r = -EINVAL; 493 494 dma_buf = dma_buf_get(dma_buf_fd); 495 if (IS_ERR(dma_buf)) 496 return PTR_ERR(dma_buf); 497 498 if (dma_buf->ops != &amdgpu_dmabuf_ops) 499 /* Can't handle non-graphics buffers */ 500 goto out_put; 501 502 obj = dma_buf->priv; 503 if (obj->dev->driver != adev_to_drm(adev)->driver) 504 /* Can't handle buffers from different drivers */ 505 goto out_put; 506 507 adev = drm_to_adev(obj->dev); 508 bo = gem_to_amdgpu_bo(obj); 509 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM | 510 AMDGPU_GEM_DOMAIN_GTT))) 511 /* Only VRAM and GTT BOs are supported */ 512 goto out_put; 513 514 r = 0; 515 if (dmabuf_adev) 516 *dmabuf_adev = adev; 517 if (bo_size) 518 *bo_size = amdgpu_bo_size(bo); 519 if (metadata_buffer) 520 r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size, 521 metadata_size, &metadata_flags); 522 if (flags) { 523 *flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ? 524 KFD_IOC_ALLOC_MEM_FLAGS_VRAM 525 : KFD_IOC_ALLOC_MEM_FLAGS_GTT; 526 527 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 528 *flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC; 529 } 530 if (xcp_id) 531 *xcp_id = bo->xcp_id; 532 533 out_put: 534 dma_buf_put(dma_buf); 535 return r; 536 } 537 538 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct amdgpu_device *dst, 539 struct amdgpu_device *src) 540 { 541 struct amdgpu_device *peer_adev = src; 542 struct amdgpu_device *adev = dst; 543 int ret = amdgpu_xgmi_get_hops_count(adev, peer_adev); 544 545 if (ret < 0) { 546 DRM_ERROR("amdgpu: failed to get xgmi hops count between node %d and %d. ret = %d\n", 547 adev->gmc.xgmi.physical_node_id, 548 peer_adev->gmc.xgmi.physical_node_id, ret); 549 ret = 0; 550 } 551 return (uint8_t)ret; 552 } 553 554 int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct amdgpu_device *dst, 555 struct amdgpu_device *src, 556 bool is_min) 557 { 558 struct amdgpu_device *adev = dst, *peer_adev; 559 int num_links; 560 561 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2)) 562 return 0; 563 564 if (src) 565 peer_adev = src; 566 567 /* num links returns 0 for indirect peers since indirect route is unknown. */ 568 num_links = is_min ? 1 : amdgpu_xgmi_get_num_links(adev, peer_adev); 569 if (num_links < 0) { 570 DRM_ERROR("amdgpu: failed to get xgmi num links between node %d and %d. ret = %d\n", 571 adev->gmc.xgmi.physical_node_id, 572 peer_adev->gmc.xgmi.physical_node_id, num_links); 573 num_links = 0; 574 } 575 576 /* Aldebaran xGMI DPM is defeatured so assume x16 x 25Gbps for bandwidth. */ 577 return (num_links * 16 * 25000)/BITS_PER_BYTE; 578 } 579 580 int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min) 581 { 582 int num_lanes_shift = (is_min ? ffs(adev->pm.pcie_mlw_mask) : 583 fls(adev->pm.pcie_mlw_mask)) - 1; 584 int gen_speed_shift = (is_min ? ffs(adev->pm.pcie_gen_mask & 585 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) : 586 fls(adev->pm.pcie_gen_mask & 587 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK)) - 1; 588 uint32_t num_lanes_mask = 1 << num_lanes_shift; 589 uint32_t gen_speed_mask = 1 << gen_speed_shift; 590 int num_lanes_factor = 0, gen_speed_mbits_factor = 0; 591 592 switch (num_lanes_mask) { 593 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1: 594 num_lanes_factor = 1; 595 break; 596 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2: 597 num_lanes_factor = 2; 598 break; 599 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4: 600 num_lanes_factor = 4; 601 break; 602 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8: 603 num_lanes_factor = 8; 604 break; 605 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12: 606 num_lanes_factor = 12; 607 break; 608 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16: 609 num_lanes_factor = 16; 610 break; 611 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32: 612 num_lanes_factor = 32; 613 break; 614 } 615 616 switch (gen_speed_mask) { 617 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1: 618 gen_speed_mbits_factor = 2500; 619 break; 620 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2: 621 gen_speed_mbits_factor = 5000; 622 break; 623 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3: 624 gen_speed_mbits_factor = 8000; 625 break; 626 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4: 627 gen_speed_mbits_factor = 16000; 628 break; 629 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5: 630 gen_speed_mbits_factor = 32000; 631 break; 632 } 633 634 return (num_lanes_factor * gen_speed_mbits_factor)/BITS_PER_BYTE; 635 } 636 637 int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, 638 enum kgd_engine_type engine, 639 uint32_t vmid, uint64_t gpu_addr, 640 uint32_t *ib_cmd, uint32_t ib_len) 641 { 642 struct amdgpu_job *job; 643 struct amdgpu_ib *ib; 644 struct amdgpu_ring *ring; 645 struct dma_fence *f = NULL; 646 int ret; 647 648 switch (engine) { 649 case KGD_ENGINE_MEC1: 650 ring = &adev->gfx.compute_ring[0]; 651 break; 652 case KGD_ENGINE_SDMA1: 653 ring = &adev->sdma.instance[0].ring; 654 break; 655 case KGD_ENGINE_SDMA2: 656 ring = &adev->sdma.instance[1].ring; 657 break; 658 default: 659 pr_err("Invalid engine in IB submission: %d\n", engine); 660 ret = -EINVAL; 661 goto err; 662 } 663 664 ret = amdgpu_job_alloc(adev, NULL, NULL, NULL, 1, &job); 665 if (ret) 666 goto err; 667 668 ib = &job->ibs[0]; 669 memset(ib, 0, sizeof(struct amdgpu_ib)); 670 671 ib->gpu_addr = gpu_addr; 672 ib->ptr = ib_cmd; 673 ib->length_dw = ib_len; 674 /* This works for NO_HWS. TODO: need to handle without knowing VMID */ 675 job->vmid = vmid; 676 job->num_ibs = 1; 677 678 ret = amdgpu_ib_schedule(ring, 1, ib, job, &f); 679 680 if (ret) { 681 DRM_ERROR("amdgpu: failed to schedule IB.\n"); 682 goto err_ib_sched; 683 } 684 685 /* Drop the initial kref_init count (see drm_sched_main as example) */ 686 dma_fence_put(f); 687 ret = dma_fence_wait(f, false); 688 689 err_ib_sched: 690 amdgpu_job_free(job); 691 err: 692 return ret; 693 } 694 695 void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle) 696 { 697 enum amd_powergating_state state = idle ? AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE; 698 /* Temporary workaround to fix issues observed in some 699 * compute applications when GFXOFF is enabled on GFX11. 700 */ 701 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 11) { 702 pr_debug("GFXOFF is %s\n", idle ? "enabled" : "disabled"); 703 amdgpu_gfx_off_ctrl(adev, idle); 704 } else if ((IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 9) && 705 (adev->flags & AMD_IS_APU)) { 706 /* Disable GFXOFF and PG. Temporary workaround 707 * to fix some compute applications issue on GFX9. 708 */ 709 adev->ip_blocks[AMD_IP_BLOCK_TYPE_GFX].version->funcs->set_powergating_state((void *)adev, state); 710 } 711 amdgpu_dpm_switch_power_profile(adev, 712 PP_SMC_POWER_PROFILE_COMPUTE, 713 !idle); 714 } 715 716 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid) 717 { 718 if (adev->kfd.dev) 719 return vmid >= adev->vm_manager.first_kfd_vmid; 720 721 return false; 722 } 723 724 bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev) 725 { 726 return adev->have_atomics_support; 727 } 728 729 void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev) 730 { 731 amdgpu_device_flush_hdp(adev, NULL); 732 } 733 734 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, bool reset) 735 { 736 amdgpu_umc_poison_handler(adev, reset); 737 } 738 739 int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev, 740 uint32_t *payload) 741 { 742 int ret; 743 744 /* Device or IH ring is not ready so bail. */ 745 ret = amdgpu_ih_wait_on_checkpoint_process_ts(adev, &adev->irq.ih); 746 if (ret) 747 return ret; 748 749 /* Send payload to fence KFD interrupts */ 750 amdgpu_amdkfd_interrupt(adev, payload); 751 752 return 0; 753 } 754 755 bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev) 756 { 757 if (adev->gfx.ras && adev->gfx.ras->query_utcl2_poison_status) 758 return adev->gfx.ras->query_utcl2_poison_status(adev); 759 else 760 return false; 761 } 762 763 int amdgpu_amdkfd_check_and_lock_kfd(struct amdgpu_device *adev) 764 { 765 return kgd2kfd_check_and_lock_kfd(); 766 } 767 768 void amdgpu_amdkfd_unlock_kfd(struct amdgpu_device *adev) 769 { 770 kgd2kfd_unlock_kfd(); 771 } 772 773 774 u64 amdgpu_amdkfd_xcp_memory_size(struct amdgpu_device *adev, int xcp_id) 775 { 776 s8 mem_id = KFD_XCP_MEM_ID(adev, xcp_id); 777 u64 tmp; 778 779 if (adev->gmc.num_mem_partitions && xcp_id >= 0 && mem_id >= 0) { 780 if (adev->gmc.is_app_apu && adev->gmc.num_mem_partitions == 1) { 781 /* In NPS1 mode, we should restrict the vram reporting 782 * tied to the ttm_pages_limit which is 1/2 of the system 783 * memory. For other partition modes, the HBM is uniformly 784 * divided already per numa node reported. If user wants to 785 * go beyond the default ttm limit and maximize the ROCm 786 * allocations, they can go up to max ttm and sysmem limits. 787 */ 788 789 tmp = (ttm_tt_pages_limit() << PAGE_SHIFT) / num_online_nodes(); 790 } else { 791 tmp = adev->gmc.mem_partitions[mem_id].size; 792 } 793 do_div(tmp, adev->xcp_mgr->num_xcp_per_mem_partition); 794 return ALIGN_DOWN(tmp, PAGE_SIZE); 795 } else { 796 return adev->gmc.real_vram_size; 797 } 798 } 799 800 int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off, 801 u32 inst) 802 { 803 struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst]; 804 struct amdgpu_ring *kiq_ring = &kiq->ring; 805 struct amdgpu_ring_funcs *ring_funcs; 806 struct amdgpu_ring *ring; 807 int r = 0; 808 809 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 810 return -EINVAL; 811 812 ring_funcs = kzalloc(sizeof(*ring_funcs), GFP_KERNEL); 813 if (!ring_funcs) 814 return -ENOMEM; 815 816 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 817 if (!ring) { 818 r = -ENOMEM; 819 goto free_ring_funcs; 820 } 821 822 ring_funcs->type = AMDGPU_RING_TYPE_COMPUTE; 823 ring->doorbell_index = doorbell_off; 824 ring->funcs = ring_funcs; 825 826 spin_lock(&kiq->ring_lock); 827 828 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 829 spin_unlock(&kiq->ring_lock); 830 r = -ENOMEM; 831 goto free_ring; 832 } 833 834 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 0, 0); 835 836 if (kiq_ring->sched.ready && !adev->job_hang) 837 r = amdgpu_ring_test_helper(kiq_ring); 838 839 spin_unlock(&kiq->ring_lock); 840 841 free_ring: 842 kfree(ring); 843 844 free_ring_funcs: 845 kfree(ring_funcs); 846 847 return r; 848 } 849