1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2014 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include "amdgpu_amdkfd.h" 25 #include "amd_pcie.h" 26 #include "amd_shared.h" 27 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_dma_buf.h" 31 #include <drm/ttm/ttm_tt.h> 32 #include <linux/module.h> 33 #include <linux/dma-buf.h> 34 #include "amdgpu_xgmi.h" 35 #include <uapi/linux/kfd_ioctl.h> 36 #include "amdgpu_ras.h" 37 #include "amdgpu_umc.h" 38 #include "amdgpu_reset.h" 39 40 /* Total memory size in system memory and all GPU VRAM. Used to 41 * estimate worst case amount of memory to reserve for page tables 42 */ 43 uint64_t amdgpu_amdkfd_total_mem_size; 44 45 static bool kfd_initialized; 46 47 int amdgpu_amdkfd_init(void) 48 { 49 struct sysinfo si; 50 int ret; 51 52 si_meminfo(&si); 53 amdgpu_amdkfd_total_mem_size = si.freeram - si.freehigh; 54 amdgpu_amdkfd_total_mem_size *= si.mem_unit; 55 56 ret = kgd2kfd_init(); 57 kfd_initialized = !ret; 58 59 return ret; 60 } 61 62 void amdgpu_amdkfd_fini(void) 63 { 64 if (kfd_initialized) { 65 kgd2kfd_exit(); 66 kfd_initialized = false; 67 } 68 } 69 70 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) 71 { 72 bool vf = amdgpu_sriov_vf(adev); 73 74 if (!kfd_initialized) 75 return; 76 77 adev->kfd.dev = kgd2kfd_probe(adev, vf); 78 } 79 80 /** 81 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to 82 * setup amdkfd 83 * 84 * @adev: amdgpu_device pointer 85 * @aperture_base: output returning doorbell aperture base physical address 86 * @aperture_size: output returning doorbell aperture size in bytes 87 * @start_offset: output returning # of doorbell bytes reserved for amdgpu. 88 * 89 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, 90 * takes doorbells required for its own rings and reports the setup to amdkfd. 91 * amdgpu reserved doorbells are at the start of the doorbell aperture. 92 */ 93 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 94 phys_addr_t *aperture_base, 95 size_t *aperture_size, 96 size_t *start_offset) 97 { 98 /* 99 * The first num_kernel_doorbells are used by amdgpu. 100 * amdkfd takes whatever's left in the aperture. 101 */ 102 if (adev->enable_mes) { 103 /* 104 * With MES enabled, we only need to initialize 105 * the base address. The size and offset are 106 * not initialized as AMDGPU manages the whole 107 * doorbell space. 108 */ 109 *aperture_base = adev->doorbell.base; 110 *aperture_size = 0; 111 *start_offset = 0; 112 } else if (adev->doorbell.size > adev->doorbell.num_kernel_doorbells * 113 sizeof(u32)) { 114 *aperture_base = adev->doorbell.base; 115 *aperture_size = adev->doorbell.size; 116 *start_offset = adev->doorbell.num_kernel_doorbells * sizeof(u32); 117 } else { 118 *aperture_base = 0; 119 *aperture_size = 0; 120 *start_offset = 0; 121 } 122 } 123 124 125 static void amdgpu_amdkfd_reset_work(struct work_struct *work) 126 { 127 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 128 kfd.reset_work); 129 130 struct amdgpu_reset_context reset_context; 131 132 memset(&reset_context, 0, sizeof(reset_context)); 133 134 reset_context.method = AMD_RESET_METHOD_NONE; 135 reset_context.reset_req_dev = adev; 136 reset_context.src = adev->enable_mes ? 137 AMDGPU_RESET_SRC_MES : 138 AMDGPU_RESET_SRC_HWS; 139 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 140 141 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 142 } 143 144 static const struct drm_client_funcs kfd_client_funcs = { 145 .unregister = drm_client_release, 146 }; 147 148 int amdgpu_amdkfd_drm_client_create(struct amdgpu_device *adev) 149 { 150 int ret; 151 152 if (!adev->kfd.init_complete || adev->kfd.client.dev) 153 return 0; 154 155 ret = drm_client_init(&adev->ddev, &adev->kfd.client, "kfd", 156 &kfd_client_funcs); 157 if (ret) { 158 dev_err(adev->dev, "Failed to init DRM client: %d\n", 159 ret); 160 return ret; 161 } 162 163 drm_client_register(&adev->kfd.client); 164 165 return 0; 166 } 167 168 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) 169 { 170 int i; 171 int last_valid_bit; 172 173 amdgpu_amdkfd_gpuvm_init_mem_limits(); 174 175 if (adev->kfd.dev) { 176 struct kgd2kfd_shared_resources gpu_resources = { 177 .compute_vmid_bitmap = 178 ((1 << AMDGPU_NUM_VMID) - 1) - 179 ((1 << adev->vm_manager.first_kfd_vmid) - 1), 180 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, 181 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, 182 .gpuvm_size = min(adev->vm_manager.max_pfn 183 << AMDGPU_GPU_PAGE_SHIFT, 184 AMDGPU_GMC_HOLE_START), 185 .drm_render_minor = adev_to_drm(adev)->render->index, 186 .sdma_doorbell_idx = adev->doorbell_index.sdma_engine, 187 .enable_mes = adev->enable_mes, 188 }; 189 190 /* this is going to have a few of the MSBs set that we need to 191 * clear 192 */ 193 bitmap_complement(gpu_resources.cp_queue_bitmap, 194 adev->gfx.mec_bitmap[0].queue_bitmap, 195 AMDGPU_MAX_QUEUES); 196 197 /* According to linux/bitmap.h we shouldn't use bitmap_clear if 198 * nbits is not compile time constant 199 */ 200 last_valid_bit = 1 /* only first MEC can have compute queues */ 201 * adev->gfx.mec.num_pipe_per_mec 202 * adev->gfx.mec.num_queue_per_pipe; 203 for (i = last_valid_bit; i < AMDGPU_MAX_QUEUES; ++i) 204 clear_bit(i, gpu_resources.cp_queue_bitmap); 205 206 amdgpu_doorbell_get_kfd_info(adev, 207 &gpu_resources.doorbell_physical_address, 208 &gpu_resources.doorbell_aperture_size, 209 &gpu_resources.doorbell_start_offset); 210 211 /* Since SOC15, BIF starts to statically use the 212 * lower 12 bits of doorbell addresses for routing 213 * based on settings in registers like 214 * SDMA0_DOORBELL_RANGE etc.. 215 * In order to route a doorbell to CP engine, the lower 216 * 12 bits of its address has to be outside the range 217 * set for SDMA, VCN, and IH blocks. 218 */ 219 if (adev->asic_type >= CHIP_VEGA10) { 220 gpu_resources.non_cp_doorbells_start = 221 adev->doorbell_index.first_non_cp; 222 gpu_resources.non_cp_doorbells_end = 223 adev->doorbell_index.last_non_cp; 224 } 225 226 adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev, 227 &gpu_resources); 228 229 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size; 230 231 INIT_WORK(&adev->kfd.reset_work, amdgpu_amdkfd_reset_work); 232 } 233 } 234 235 void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev) 236 { 237 if (adev->kfd.dev) { 238 kgd2kfd_device_exit(adev->kfd.dev); 239 adev->kfd.dev = NULL; 240 amdgpu_amdkfd_total_mem_size -= adev->gmc.real_vram_size; 241 } 242 } 243 244 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, 245 const void *ih_ring_entry) 246 { 247 if (adev->kfd.dev) 248 kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry); 249 } 250 251 void amdgpu_amdkfd_teardown_processes(struct amdgpu_device *adev) 252 { 253 kgd2kfd_teardown_processes(adev); 254 } 255 256 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool suspend_proc) 257 { 258 if (adev->kfd.dev) { 259 if (adev->in_s0ix) 260 kgd2kfd_stop_sched_all_nodes(adev->kfd.dev); 261 else 262 kgd2kfd_suspend(adev->kfd.dev, suspend_proc); 263 } 264 } 265 266 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool resume_proc) 267 { 268 int r = 0; 269 270 if (adev->kfd.dev) { 271 if (adev->in_s0ix) 272 r = kgd2kfd_start_sched_all_nodes(adev->kfd.dev); 273 else 274 r = kgd2kfd_resume(adev->kfd.dev, resume_proc); 275 } 276 277 return r; 278 } 279 280 void amdgpu_amdkfd_suspend_process(struct amdgpu_device *adev) 281 { 282 if (adev->kfd.dev) 283 kgd2kfd_suspend_process(adev->kfd.dev); 284 } 285 286 int amdgpu_amdkfd_resume_process(struct amdgpu_device *adev) 287 { 288 int r = 0; 289 290 if (adev->kfd.dev) 291 r = kgd2kfd_resume_process(adev->kfd.dev); 292 293 return r; 294 } 295 296 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev, 297 struct amdgpu_reset_context *reset_context) 298 { 299 int r = 0; 300 301 if (adev->kfd.dev) 302 r = kgd2kfd_pre_reset(adev->kfd.dev, reset_context); 303 304 return r; 305 } 306 307 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev) 308 { 309 int r = 0; 310 311 if (adev->kfd.dev) 312 r = kgd2kfd_post_reset(adev->kfd.dev); 313 314 return r; 315 } 316 317 void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev) 318 { 319 if (amdgpu_device_should_recover_gpu(adev)) 320 amdgpu_reset_domain_schedule(adev->reset_domain, 321 &adev->kfd.reset_work); 322 } 323 324 int amdgpu_amdkfd_alloc_kernel_mem(struct amdgpu_device *adev, size_t size, 325 u32 domain, void **mem_obj, uint64_t *gpu_addr, 326 void **cpu_ptr, bool cp_mqd_gfx9) 327 { 328 struct amdgpu_bo *bo = NULL; 329 struct amdgpu_bo_param bp; 330 int r; 331 void *cpu_ptr_tmp = NULL; 332 333 memset(&bp, 0, sizeof(bp)); 334 bp.size = size; 335 bp.byte_align = PAGE_SIZE; 336 bp.domain = domain; 337 bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | 338 AMDGPU_GEM_CREATE_CPU_GTT_USWC; 339 bp.type = ttm_bo_type_kernel; 340 bp.resv = NULL; 341 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 342 343 if (cp_mqd_gfx9) 344 bp.flags |= AMDGPU_GEM_CREATE_CP_MQD_GFX9; 345 346 r = amdgpu_bo_create(adev, &bp, &bo); 347 if (r) { 348 dev_err(adev->dev, 349 "failed to allocate BO for amdkfd (%d)\n", r); 350 return r; 351 } 352 353 /* map the buffer */ 354 r = amdgpu_bo_reserve(bo, true); 355 if (r) { 356 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r); 357 goto allocate_mem_reserve_bo_failed; 358 } 359 360 r = amdgpu_bo_pin(bo, domain); 361 if (r) { 362 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r); 363 goto allocate_mem_pin_bo_failed; 364 } 365 366 r = amdgpu_ttm_alloc_gart(&bo->tbo); 367 if (r) { 368 dev_err(adev->dev, "%p bind failed\n", bo); 369 goto allocate_mem_kmap_bo_failed; 370 } 371 372 r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp); 373 if (r) { 374 dev_err(adev->dev, 375 "(%d) failed to map bo to kernel for amdkfd\n", r); 376 goto allocate_mem_kmap_bo_failed; 377 } 378 379 *mem_obj = bo; 380 *gpu_addr = amdgpu_bo_gpu_offset(bo); 381 *cpu_ptr = cpu_ptr_tmp; 382 383 amdgpu_bo_unreserve(bo); 384 385 return 0; 386 387 allocate_mem_kmap_bo_failed: 388 amdgpu_bo_unpin(bo); 389 allocate_mem_pin_bo_failed: 390 amdgpu_bo_unreserve(bo); 391 allocate_mem_reserve_bo_failed: 392 amdgpu_bo_unref(&bo); 393 394 return r; 395 } 396 397 void amdgpu_amdkfd_free_kernel_mem(struct amdgpu_device *adev, void **mem_obj) 398 { 399 struct amdgpu_bo **bo = (struct amdgpu_bo **) mem_obj; 400 401 if (!bo || !*bo) 402 return; 403 404 (void)amdgpu_bo_reserve(*bo, true); 405 amdgpu_bo_kunmap(*bo); 406 amdgpu_bo_unpin(*bo); 407 amdgpu_bo_unreserve(*bo); 408 amdgpu_bo_unref(bo); 409 } 410 411 int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size, 412 void **mem_obj) 413 { 414 struct amdgpu_bo *bo = NULL; 415 struct amdgpu_bo_user *ubo; 416 struct amdgpu_bo_param bp; 417 int r; 418 419 memset(&bp, 0, sizeof(bp)); 420 bp.size = size; 421 bp.byte_align = 1; 422 bp.domain = AMDGPU_GEM_DOMAIN_GWS; 423 bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 424 bp.type = ttm_bo_type_device; 425 bp.resv = NULL; 426 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 427 428 r = amdgpu_bo_create_user(adev, &bp, &ubo); 429 if (r) { 430 dev_err(adev->dev, 431 "failed to allocate gws BO for amdkfd (%d)\n", r); 432 return r; 433 } 434 435 bo = &ubo->bo; 436 *mem_obj = bo; 437 return 0; 438 } 439 440 void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj) 441 { 442 struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj; 443 444 amdgpu_bo_unref(&bo); 445 } 446 447 uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev, 448 enum kgd_engine_type type) 449 { 450 switch (type) { 451 case KGD_ENGINE_PFP: 452 return adev->gfx.pfp_fw_version; 453 454 case KGD_ENGINE_ME: 455 return adev->gfx.me_fw_version; 456 457 case KGD_ENGINE_CE: 458 return adev->gfx.ce_fw_version; 459 460 case KGD_ENGINE_MEC1: 461 return adev->gfx.mec_fw_version; 462 463 case KGD_ENGINE_MEC2: 464 return adev->gfx.mec2_fw_version; 465 466 case KGD_ENGINE_RLC: 467 return adev->gfx.rlc_fw_version; 468 469 case KGD_ENGINE_SDMA1: 470 return adev->sdma.instance[0].fw_version; 471 472 case KGD_ENGINE_SDMA2: 473 return adev->sdma.instance[1].fw_version; 474 475 default: 476 return 0; 477 } 478 479 return 0; 480 } 481 482 void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev, 483 struct kfd_local_mem_info *mem_info, 484 struct amdgpu_xcp *xcp) 485 { 486 memset(mem_info, 0, sizeof(*mem_info)); 487 488 if (xcp) { 489 if (adev->gmc.real_vram_size == adev->gmc.visible_vram_size) 490 mem_info->local_mem_size_public = 491 KFD_XCP_MEMORY_SIZE(adev, xcp->id); 492 else 493 mem_info->local_mem_size_private = 494 KFD_XCP_MEMORY_SIZE(adev, xcp->id); 495 } else if (adev->apu_prefer_gtt) { 496 mem_info->local_mem_size_public = (ttm_tt_pages_limit() << PAGE_SHIFT); 497 mem_info->local_mem_size_private = 0; 498 } else { 499 mem_info->local_mem_size_public = adev->gmc.visible_vram_size; 500 mem_info->local_mem_size_private = adev->gmc.real_vram_size - 501 adev->gmc.visible_vram_size; 502 } 503 mem_info->vram_width = adev->gmc.vram_width; 504 505 pr_debug("Address base: %pap public 0x%llx private 0x%llx\n", 506 &adev->gmc.aper_base, 507 mem_info->local_mem_size_public, 508 mem_info->local_mem_size_private); 509 510 if (adev->pm.dpm_enabled) { 511 if (amdgpu_emu_mode == 1) 512 mem_info->mem_clk_max = 0; 513 else 514 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100; 515 } else 516 mem_info->mem_clk_max = 100; 517 } 518 519 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev) 520 { 521 if (adev->gfx.funcs->get_gpu_clock_counter) 522 return adev->gfx.funcs->get_gpu_clock_counter(adev); 523 return 0; 524 } 525 526 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev) 527 { 528 /* the sclk is in quantas of 10kHz */ 529 if (adev->pm.dpm_enabled) 530 return amdgpu_dpm_get_sclk(adev, false) / 100; 531 else 532 return 100; 533 } 534 535 int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, 536 struct amdgpu_device **dmabuf_adev, 537 uint64_t *bo_size, void *metadata_buffer, 538 size_t buffer_size, uint32_t *metadata_size, 539 uint32_t *flags, int8_t *xcp_id) 540 { 541 struct dma_buf *dma_buf; 542 struct drm_gem_object *obj; 543 struct amdgpu_bo *bo; 544 uint64_t metadata_flags; 545 int r = -EINVAL; 546 547 dma_buf = dma_buf_get(dma_buf_fd); 548 if (IS_ERR(dma_buf)) 549 return PTR_ERR(dma_buf); 550 551 if (dma_buf->ops != &amdgpu_dmabuf_ops) 552 /* Can't handle non-graphics buffers */ 553 goto out_put; 554 555 obj = dma_buf->priv; 556 if (obj->dev->driver != adev_to_drm(adev)->driver) 557 /* Can't handle buffers from different drivers */ 558 goto out_put; 559 560 adev = drm_to_adev(obj->dev); 561 bo = gem_to_amdgpu_bo(obj); 562 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM | 563 AMDGPU_GEM_DOMAIN_GTT))) 564 /* Only VRAM and GTT BOs are supported */ 565 goto out_put; 566 567 r = 0; 568 if (dmabuf_adev) 569 *dmabuf_adev = adev; 570 if (bo_size) 571 *bo_size = amdgpu_bo_size(bo); 572 if (metadata_buffer) 573 r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size, 574 metadata_size, &metadata_flags); 575 if (flags) { 576 *flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ? 577 KFD_IOC_ALLOC_MEM_FLAGS_VRAM 578 : KFD_IOC_ALLOC_MEM_FLAGS_GTT; 579 580 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 581 *flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC; 582 } 583 if (xcp_id) 584 *xcp_id = bo->xcp_id; 585 586 out_put: 587 dma_buf_put(dma_buf); 588 return r; 589 } 590 591 int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min) 592 { 593 int num_lanes_shift = (is_min ? ffs(adev->pm.pcie_mlw_mask) : 594 fls(adev->pm.pcie_mlw_mask)) - 1; 595 int gen_speed_shift = (is_min ? ffs(adev->pm.pcie_gen_mask & 596 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) : 597 fls(adev->pm.pcie_gen_mask & 598 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK)) - 1; 599 uint32_t num_lanes_mask = 1 << num_lanes_shift; 600 uint32_t gen_speed_mask = 1 << gen_speed_shift; 601 int num_lanes_factor = 0, gen_speed_mbits_factor = 0; 602 603 switch (num_lanes_mask) { 604 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1: 605 num_lanes_factor = 1; 606 break; 607 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2: 608 num_lanes_factor = 2; 609 break; 610 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4: 611 num_lanes_factor = 4; 612 break; 613 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8: 614 num_lanes_factor = 8; 615 break; 616 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12: 617 num_lanes_factor = 12; 618 break; 619 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16: 620 num_lanes_factor = 16; 621 break; 622 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32: 623 num_lanes_factor = 32; 624 break; 625 } 626 627 switch (gen_speed_mask) { 628 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1: 629 gen_speed_mbits_factor = 2500; 630 break; 631 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2: 632 gen_speed_mbits_factor = 5000; 633 break; 634 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3: 635 gen_speed_mbits_factor = 8000; 636 break; 637 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4: 638 gen_speed_mbits_factor = 16000; 639 break; 640 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5: 641 gen_speed_mbits_factor = 32000; 642 break; 643 } 644 645 return (num_lanes_factor * gen_speed_mbits_factor)/BITS_PER_BYTE; 646 } 647 648 int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, 649 enum kgd_engine_type engine, 650 uint32_t vmid, uint64_t gpu_addr, 651 uint32_t *ib_cmd, uint32_t ib_len) 652 { 653 struct amdgpu_job *job; 654 struct amdgpu_ib *ib; 655 struct amdgpu_ring *ring; 656 struct dma_fence *f = NULL; 657 int ret; 658 659 switch (engine) { 660 case KGD_ENGINE_MEC1: 661 ring = &adev->gfx.compute_ring[0]; 662 break; 663 case KGD_ENGINE_SDMA1: 664 ring = &adev->sdma.instance[0].ring; 665 break; 666 case KGD_ENGINE_SDMA2: 667 ring = &adev->sdma.instance[1].ring; 668 break; 669 default: 670 pr_err("Invalid engine in IB submission: %d\n", engine); 671 ret = -EINVAL; 672 goto err; 673 } 674 675 ret = amdgpu_job_alloc(adev, NULL, NULL, NULL, 1, &job, 0); 676 if (ret) 677 goto err; 678 679 ib = &job->ibs[0]; 680 memset(ib, 0, sizeof(struct amdgpu_ib)); 681 682 ib->gpu_addr = gpu_addr; 683 ib->ptr = ib_cmd; 684 ib->length_dw = ib_len; 685 /* This works for NO_HWS. TODO: need to handle without knowing VMID */ 686 job->vmid = vmid; 687 job->num_ibs = 1; 688 689 ret = amdgpu_ib_schedule(ring, 1, ib, job, &f); 690 691 if (ret) { 692 drm_err(adev_to_drm(adev), "failed to schedule IB.\n"); 693 goto err_ib_sched; 694 } 695 696 /* Drop the initial kref_init count (see drm_sched_main as example) */ 697 dma_fence_put(f); 698 ret = dma_fence_wait(f, false); 699 700 err_ib_sched: 701 amdgpu_job_free(job); 702 err: 703 return ret; 704 } 705 706 void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle) 707 { 708 enum amd_powergating_state state = idle ? AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE; 709 if ((IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 11 && 710 ((adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK) <= 64)) || 711 (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 12)) { 712 pr_debug("GFXOFF is %s\n", idle ? "enabled" : "disabled"); 713 amdgpu_gfx_off_ctrl(adev, idle); 714 } else if ((IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 9) && 715 (adev->flags & AMD_IS_APU)) { 716 /* Disable GFXOFF and PG. Temporary workaround 717 * to fix some compute applications issue on GFX9. 718 */ 719 struct amdgpu_ip_block *gfx_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); 720 if (gfx_block != NULL) 721 gfx_block->version->funcs->set_powergating_state((void *)gfx_block, state); 722 } 723 amdgpu_dpm_switch_power_profile(adev, 724 PP_SMC_POWER_PROFILE_COMPUTE, 725 !idle); 726 } 727 728 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid) 729 { 730 if (adev->kfd.dev) 731 return vmid >= adev->vm_manager.first_kfd_vmid; 732 733 return false; 734 } 735 736 bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev) 737 { 738 return adev->have_atomics_support; 739 } 740 741 void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev) 742 { 743 amdgpu_device_flush_hdp(adev, NULL); 744 } 745 746 bool amdgpu_amdkfd_is_fed(struct amdgpu_device *adev) 747 { 748 return amdgpu_ras_get_fed_status(adev); 749 } 750 751 void amdgpu_amdkfd_ras_pasid_poison_consumption_handler(struct amdgpu_device *adev, 752 enum amdgpu_ras_block block, uint16_t pasid, 753 pasid_notify pasid_fn, void *data, uint32_t reset) 754 { 755 amdgpu_umc_pasid_poison_handler(adev, block, pasid, pasid_fn, data, reset); 756 } 757 758 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, 759 enum amdgpu_ras_block block, uint32_t reset) 760 { 761 amdgpu_umc_pasid_poison_handler(adev, block, 0, NULL, NULL, reset); 762 } 763 764 int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev, 765 uint32_t *payload) 766 { 767 int ret; 768 769 /* Device or IH ring is not ready so bail. */ 770 ret = amdgpu_ih_wait_on_checkpoint_process_ts(adev, &adev->irq.ih); 771 if (ret) 772 return ret; 773 774 /* Send payload to fence KFD interrupts */ 775 amdgpu_amdkfd_interrupt(adev, payload); 776 777 return 0; 778 } 779 780 int amdgpu_amdkfd_check_and_lock_kfd(struct amdgpu_device *adev) 781 { 782 return kgd2kfd_check_and_lock_kfd(adev->kfd.dev); 783 } 784 785 void amdgpu_amdkfd_unlock_kfd(struct amdgpu_device *adev) 786 { 787 kgd2kfd_unlock_kfd(adev->kfd.dev); 788 } 789 790 791 u64 amdgpu_amdkfd_xcp_memory_size(struct amdgpu_device *adev, int xcp_id) 792 { 793 s8 mem_id = KFD_XCP_MEM_ID(adev, xcp_id); 794 u64 tmp; 795 796 if (adev->gmc.num_mem_partitions && xcp_id >= 0 && mem_id >= 0) { 797 if (adev->gmc.is_app_apu && adev->gmc.num_mem_partitions == 1) { 798 /* In NPS1 mode, we should restrict the vram reporting 799 * tied to the ttm_pages_limit which is 1/2 of the system 800 * memory. For other partition modes, the HBM is uniformly 801 * divided already per numa node reported. If user wants to 802 * go beyond the default ttm limit and maximize the ROCm 803 * allocations, they can go up to max ttm and sysmem limits. 804 */ 805 806 tmp = (ttm_tt_pages_limit() << PAGE_SHIFT) / num_online_nodes(); 807 } else { 808 tmp = adev->gmc.mem_partitions[mem_id].size; 809 } 810 do_div(tmp, adev->xcp_mgr->num_xcp_per_mem_partition); 811 return ALIGN_DOWN(tmp, PAGE_SIZE); 812 } else if (adev->apu_prefer_gtt) { 813 return (ttm_tt_pages_limit() << PAGE_SHIFT); 814 } else { 815 return adev->gmc.real_vram_size; 816 } 817 } 818 819 int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off, 820 u32 inst) 821 { 822 struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst]; 823 struct amdgpu_ring *kiq_ring = &kiq->ring; 824 struct amdgpu_ring_funcs *ring_funcs; 825 struct amdgpu_ring *ring; 826 int r = 0; 827 828 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 829 return -EINVAL; 830 831 if (!kiq_ring->sched.ready || amdgpu_in_reset(adev)) 832 return 0; 833 834 ring_funcs = kzalloc(sizeof(*ring_funcs), GFP_KERNEL); 835 if (!ring_funcs) 836 return -ENOMEM; 837 838 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 839 if (!ring) { 840 r = -ENOMEM; 841 goto free_ring_funcs; 842 } 843 844 ring_funcs->type = AMDGPU_RING_TYPE_COMPUTE; 845 ring->doorbell_index = doorbell_off; 846 ring->funcs = ring_funcs; 847 848 spin_lock(&kiq->ring_lock); 849 850 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 851 spin_unlock(&kiq->ring_lock); 852 r = -ENOMEM; 853 goto free_ring; 854 } 855 856 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 0, 0); 857 858 /* Submit unmap queue packet */ 859 amdgpu_ring_commit(kiq_ring); 860 /* 861 * Ring test will do a basic scratch register change check. Just run 862 * this to ensure that unmap queues that is submitted before got 863 * processed successfully before returning. 864 */ 865 r = amdgpu_ring_test_helper(kiq_ring); 866 867 spin_unlock(&kiq->ring_lock); 868 869 free_ring: 870 kfree(ring); 871 872 free_ring_funcs: 873 kfree(ring_funcs); 874 875 return r; 876 } 877 878 /* Stop scheduling on KFD */ 879 int amdgpu_amdkfd_stop_sched(struct amdgpu_device *adev, uint32_t node_id) 880 { 881 if (!adev->kfd.init_complete) 882 return 0; 883 884 return kgd2kfd_stop_sched(adev->kfd.dev, node_id); 885 } 886 887 /* Start scheduling on KFD */ 888 int amdgpu_amdkfd_start_sched(struct amdgpu_device *adev, uint32_t node_id) 889 { 890 if (!adev->kfd.init_complete) 891 return 0; 892 893 return kgd2kfd_start_sched(adev->kfd.dev, node_id); 894 } 895 896 /* check if there are KFD queues active */ 897 bool amdgpu_amdkfd_compute_active(struct amdgpu_device *adev, uint32_t node_id) 898 { 899 if (!adev->kfd.init_complete) 900 return false; 901 902 return kgd2kfd_compute_active(adev->kfd.dev, node_id); 903 } 904 905 /* Config CGTT_SQ_CLK_CTRL */ 906 int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcp_id, 907 bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable) 908 { 909 int r; 910 911 if (!adev->kfd.init_complete) 912 return 0; 913 914 r = psp_config_sq_perfmon(&adev->psp, xcp_id, core_override_enable, 915 reg_override_enable, perfmon_override_enable); 916 917 return r; 918 } 919