1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2014 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include "amdgpu_amdkfd.h" 25 #include "amd_pcie.h" 26 #include "amd_shared.h" 27 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_dma_buf.h" 31 #include <drm/ttm/ttm_tt.h> 32 #include <linux/module.h> 33 #include <linux/dma-buf.h> 34 #include "amdgpu_xgmi.h" 35 #include <uapi/linux/kfd_ioctl.h> 36 #include "amdgpu_ras.h" 37 #include "amdgpu_umc.h" 38 #include "amdgpu_reset.h" 39 40 /* Total memory size in system memory and all GPU VRAM. Used to 41 * estimate worst case amount of memory to reserve for page tables 42 */ 43 uint64_t amdgpu_amdkfd_total_mem_size; 44 45 static bool kfd_initialized; 46 47 int amdgpu_amdkfd_init(void) 48 { 49 struct sysinfo si; 50 int ret; 51 52 si_meminfo(&si); 53 amdgpu_amdkfd_total_mem_size = si.freeram - si.freehigh; 54 amdgpu_amdkfd_total_mem_size *= si.mem_unit; 55 56 ret = kgd2kfd_init(); 57 kfd_initialized = !ret; 58 59 return ret; 60 } 61 62 void amdgpu_amdkfd_fini(void) 63 { 64 if (kfd_initialized) { 65 kgd2kfd_exit(); 66 kfd_initialized = false; 67 } 68 } 69 70 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) 71 { 72 bool vf = amdgpu_sriov_vf(adev); 73 74 if (!kfd_initialized) 75 return; 76 77 adev->kfd.dev = kgd2kfd_probe(adev, vf); 78 } 79 80 /** 81 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to 82 * setup amdkfd 83 * 84 * @adev: amdgpu_device pointer 85 * @aperture_base: output returning doorbell aperture base physical address 86 * @aperture_size: output returning doorbell aperture size in bytes 87 * @start_offset: output returning # of doorbell bytes reserved for amdgpu. 88 * 89 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, 90 * takes doorbells required for its own rings and reports the setup to amdkfd. 91 * amdgpu reserved doorbells are at the start of the doorbell aperture. 92 */ 93 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 94 phys_addr_t *aperture_base, 95 size_t *aperture_size, 96 size_t *start_offset) 97 { 98 /* 99 * The first num_kernel_doorbells are used by amdgpu. 100 * amdkfd takes whatever's left in the aperture. 101 */ 102 if (adev->enable_mes) { 103 /* 104 * With MES enabled, we only need to initialize 105 * the base address. The size and offset are 106 * not initialized as AMDGPU manages the whole 107 * doorbell space. 108 */ 109 *aperture_base = adev->doorbell.base; 110 *aperture_size = 0; 111 *start_offset = 0; 112 } else if (adev->doorbell.size > adev->doorbell.num_kernel_doorbells * 113 sizeof(u32)) { 114 *aperture_base = adev->doorbell.base; 115 *aperture_size = adev->doorbell.size; 116 *start_offset = adev->doorbell.num_kernel_doorbells * sizeof(u32); 117 } else { 118 *aperture_base = 0; 119 *aperture_size = 0; 120 *start_offset = 0; 121 } 122 } 123 124 125 static void amdgpu_amdkfd_reset_work(struct work_struct *work) 126 { 127 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 128 kfd.reset_work); 129 130 struct amdgpu_reset_context reset_context; 131 132 memset(&reset_context, 0, sizeof(reset_context)); 133 134 reset_context.method = AMD_RESET_METHOD_NONE; 135 reset_context.reset_req_dev = adev; 136 reset_context.src = adev->enable_mes ? 137 AMDGPU_RESET_SRC_MES : 138 AMDGPU_RESET_SRC_HWS; 139 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 140 141 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 142 } 143 144 static const struct drm_client_funcs kfd_client_funcs = { 145 .unregister = drm_client_release, 146 }; 147 148 int amdgpu_amdkfd_drm_client_create(struct amdgpu_device *adev) 149 { 150 int ret; 151 152 if (!adev->kfd.init_complete || adev->kfd.client.dev) 153 return 0; 154 155 ret = drm_client_init(&adev->ddev, &adev->kfd.client, "kfd", 156 &kfd_client_funcs); 157 if (ret) { 158 dev_err(adev->dev, "Failed to init DRM client: %d\n", 159 ret); 160 return ret; 161 } 162 163 drm_client_register(&adev->kfd.client); 164 165 return 0; 166 } 167 168 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) 169 { 170 int i; 171 int last_valid_bit; 172 173 amdgpu_amdkfd_gpuvm_init_mem_limits(); 174 175 if (adev->kfd.dev) { 176 struct kgd2kfd_shared_resources gpu_resources = { 177 .compute_vmid_bitmap = 178 ((1 << AMDGPU_NUM_VMID) - 1) - 179 ((1 << adev->vm_manager.first_kfd_vmid) - 1), 180 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, 181 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, 182 .gpuvm_size = min(adev->vm_manager.max_pfn 183 << AMDGPU_GPU_PAGE_SHIFT, 184 AMDGPU_GMC_HOLE_START), 185 .drm_render_minor = adev_to_drm(adev)->render->index, 186 .sdma_doorbell_idx = adev->doorbell_index.sdma_engine, 187 .enable_mes = adev->enable_mes, 188 }; 189 190 /* this is going to have a few of the MSBs set that we need to 191 * clear 192 */ 193 bitmap_complement(gpu_resources.cp_queue_bitmap, 194 adev->gfx.mec_bitmap[0].queue_bitmap, 195 AMDGPU_MAX_QUEUES); 196 197 /* According to linux/bitmap.h we shouldn't use bitmap_clear if 198 * nbits is not compile time constant 199 */ 200 last_valid_bit = 1 /* only first MEC can have compute queues */ 201 * adev->gfx.mec.num_pipe_per_mec 202 * adev->gfx.mec.num_queue_per_pipe; 203 for (i = last_valid_bit; i < AMDGPU_MAX_QUEUES; ++i) 204 clear_bit(i, gpu_resources.cp_queue_bitmap); 205 206 amdgpu_doorbell_get_kfd_info(adev, 207 &gpu_resources.doorbell_physical_address, 208 &gpu_resources.doorbell_aperture_size, 209 &gpu_resources.doorbell_start_offset); 210 211 /* Since SOC15, BIF starts to statically use the 212 * lower 12 bits of doorbell addresses for routing 213 * based on settings in registers like 214 * SDMA0_DOORBELL_RANGE etc.. 215 * In order to route a doorbell to CP engine, the lower 216 * 12 bits of its address has to be outside the range 217 * set for SDMA, VCN, and IH blocks. 218 */ 219 if (adev->asic_type >= CHIP_VEGA10) { 220 gpu_resources.non_cp_doorbells_start = 221 adev->doorbell_index.first_non_cp; 222 gpu_resources.non_cp_doorbells_end = 223 adev->doorbell_index.last_non_cp; 224 } 225 226 adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev, 227 &gpu_resources); 228 229 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size; 230 231 INIT_WORK(&adev->kfd.reset_work, amdgpu_amdkfd_reset_work); 232 } 233 } 234 235 void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev) 236 { 237 if (adev->kfd.dev) { 238 kgd2kfd_device_exit(adev->kfd.dev); 239 adev->kfd.dev = NULL; 240 amdgpu_amdkfd_total_mem_size -= adev->gmc.real_vram_size; 241 } 242 } 243 244 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, 245 const void *ih_ring_entry) 246 { 247 if (adev->kfd.dev) 248 kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry); 249 } 250 251 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm) 252 { 253 if (adev->kfd.dev) 254 kgd2kfd_suspend(adev->kfd.dev, run_pm); 255 } 256 257 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm) 258 { 259 int r = 0; 260 261 if (adev->kfd.dev) 262 r = kgd2kfd_resume(adev->kfd.dev, run_pm); 263 264 return r; 265 } 266 267 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev, 268 struct amdgpu_reset_context *reset_context) 269 { 270 int r = 0; 271 272 if (adev->kfd.dev) 273 r = kgd2kfd_pre_reset(adev->kfd.dev, reset_context); 274 275 return r; 276 } 277 278 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev) 279 { 280 int r = 0; 281 282 if (adev->kfd.dev) 283 r = kgd2kfd_post_reset(adev->kfd.dev); 284 285 return r; 286 } 287 288 void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev) 289 { 290 if (amdgpu_device_should_recover_gpu(adev)) 291 amdgpu_reset_domain_schedule(adev->reset_domain, 292 &adev->kfd.reset_work); 293 } 294 295 int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size, 296 void **mem_obj, uint64_t *gpu_addr, 297 void **cpu_ptr, bool cp_mqd_gfx9) 298 { 299 struct amdgpu_bo *bo = NULL; 300 struct amdgpu_bo_param bp; 301 int r; 302 void *cpu_ptr_tmp = NULL; 303 304 memset(&bp, 0, sizeof(bp)); 305 bp.size = size; 306 bp.byte_align = PAGE_SIZE; 307 bp.domain = AMDGPU_GEM_DOMAIN_GTT; 308 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC; 309 bp.type = ttm_bo_type_kernel; 310 bp.resv = NULL; 311 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 312 313 if (cp_mqd_gfx9) 314 bp.flags |= AMDGPU_GEM_CREATE_CP_MQD_GFX9; 315 316 r = amdgpu_bo_create(adev, &bp, &bo); 317 if (r) { 318 dev_err(adev->dev, 319 "failed to allocate BO for amdkfd (%d)\n", r); 320 return r; 321 } 322 323 /* map the buffer */ 324 r = amdgpu_bo_reserve(bo, true); 325 if (r) { 326 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r); 327 goto allocate_mem_reserve_bo_failed; 328 } 329 330 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); 331 if (r) { 332 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r); 333 goto allocate_mem_pin_bo_failed; 334 } 335 336 r = amdgpu_ttm_alloc_gart(&bo->tbo); 337 if (r) { 338 dev_err(adev->dev, "%p bind failed\n", bo); 339 goto allocate_mem_kmap_bo_failed; 340 } 341 342 r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp); 343 if (r) { 344 dev_err(adev->dev, 345 "(%d) failed to map bo to kernel for amdkfd\n", r); 346 goto allocate_mem_kmap_bo_failed; 347 } 348 349 *mem_obj = bo; 350 *gpu_addr = amdgpu_bo_gpu_offset(bo); 351 *cpu_ptr = cpu_ptr_tmp; 352 353 amdgpu_bo_unreserve(bo); 354 355 return 0; 356 357 allocate_mem_kmap_bo_failed: 358 amdgpu_bo_unpin(bo); 359 allocate_mem_pin_bo_failed: 360 amdgpu_bo_unreserve(bo); 361 allocate_mem_reserve_bo_failed: 362 amdgpu_bo_unref(&bo); 363 364 return r; 365 } 366 367 void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void *mem_obj) 368 { 369 struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj; 370 371 amdgpu_bo_reserve(bo, true); 372 amdgpu_bo_kunmap(bo); 373 amdgpu_bo_unpin(bo); 374 amdgpu_bo_unreserve(bo); 375 amdgpu_bo_unref(&(bo)); 376 } 377 378 int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size, 379 void **mem_obj) 380 { 381 struct amdgpu_bo *bo = NULL; 382 struct amdgpu_bo_user *ubo; 383 struct amdgpu_bo_param bp; 384 int r; 385 386 memset(&bp, 0, sizeof(bp)); 387 bp.size = size; 388 bp.byte_align = 1; 389 bp.domain = AMDGPU_GEM_DOMAIN_GWS; 390 bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 391 bp.type = ttm_bo_type_device; 392 bp.resv = NULL; 393 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 394 395 r = amdgpu_bo_create_user(adev, &bp, &ubo); 396 if (r) { 397 dev_err(adev->dev, 398 "failed to allocate gws BO for amdkfd (%d)\n", r); 399 return r; 400 } 401 402 bo = &ubo->bo; 403 *mem_obj = bo; 404 return 0; 405 } 406 407 void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj) 408 { 409 struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj; 410 411 amdgpu_bo_unref(&bo); 412 } 413 414 uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev, 415 enum kgd_engine_type type) 416 { 417 switch (type) { 418 case KGD_ENGINE_PFP: 419 return adev->gfx.pfp_fw_version; 420 421 case KGD_ENGINE_ME: 422 return adev->gfx.me_fw_version; 423 424 case KGD_ENGINE_CE: 425 return adev->gfx.ce_fw_version; 426 427 case KGD_ENGINE_MEC1: 428 return adev->gfx.mec_fw_version; 429 430 case KGD_ENGINE_MEC2: 431 return adev->gfx.mec2_fw_version; 432 433 case KGD_ENGINE_RLC: 434 return adev->gfx.rlc_fw_version; 435 436 case KGD_ENGINE_SDMA1: 437 return adev->sdma.instance[0].fw_version; 438 439 case KGD_ENGINE_SDMA2: 440 return adev->sdma.instance[1].fw_version; 441 442 default: 443 return 0; 444 } 445 446 return 0; 447 } 448 449 void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev, 450 struct kfd_local_mem_info *mem_info, 451 struct amdgpu_xcp *xcp) 452 { 453 memset(mem_info, 0, sizeof(*mem_info)); 454 455 if (xcp) { 456 if (adev->gmc.real_vram_size == adev->gmc.visible_vram_size) 457 mem_info->local_mem_size_public = 458 KFD_XCP_MEMORY_SIZE(adev, xcp->id); 459 else 460 mem_info->local_mem_size_private = 461 KFD_XCP_MEMORY_SIZE(adev, xcp->id); 462 } else if (adev->flags & AMD_IS_APU) { 463 mem_info->local_mem_size_public = (ttm_tt_pages_limit() << PAGE_SHIFT); 464 mem_info->local_mem_size_private = 0; 465 } else { 466 mem_info->local_mem_size_public = adev->gmc.visible_vram_size; 467 mem_info->local_mem_size_private = adev->gmc.real_vram_size - 468 adev->gmc.visible_vram_size; 469 } 470 mem_info->vram_width = adev->gmc.vram_width; 471 472 pr_debug("Address base: %pap public 0x%llx private 0x%llx\n", 473 &adev->gmc.aper_base, 474 mem_info->local_mem_size_public, 475 mem_info->local_mem_size_private); 476 477 if (adev->pm.dpm_enabled) { 478 if (amdgpu_emu_mode == 1) 479 mem_info->mem_clk_max = 0; 480 else 481 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100; 482 } else 483 mem_info->mem_clk_max = 100; 484 } 485 486 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev) 487 { 488 if (adev->gfx.funcs->get_gpu_clock_counter) 489 return adev->gfx.funcs->get_gpu_clock_counter(adev); 490 return 0; 491 } 492 493 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev) 494 { 495 /* the sclk is in quantas of 10kHz */ 496 if (adev->pm.dpm_enabled) 497 return amdgpu_dpm_get_sclk(adev, false) / 100; 498 else 499 return 100; 500 } 501 502 int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, 503 struct amdgpu_device **dmabuf_adev, 504 uint64_t *bo_size, void *metadata_buffer, 505 size_t buffer_size, uint32_t *metadata_size, 506 uint32_t *flags, int8_t *xcp_id) 507 { 508 struct dma_buf *dma_buf; 509 struct drm_gem_object *obj; 510 struct amdgpu_bo *bo; 511 uint64_t metadata_flags; 512 int r = -EINVAL; 513 514 dma_buf = dma_buf_get(dma_buf_fd); 515 if (IS_ERR(dma_buf)) 516 return PTR_ERR(dma_buf); 517 518 if (dma_buf->ops != &amdgpu_dmabuf_ops) 519 /* Can't handle non-graphics buffers */ 520 goto out_put; 521 522 obj = dma_buf->priv; 523 if (obj->dev->driver != adev_to_drm(adev)->driver) 524 /* Can't handle buffers from different drivers */ 525 goto out_put; 526 527 adev = drm_to_adev(obj->dev); 528 bo = gem_to_amdgpu_bo(obj); 529 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM | 530 AMDGPU_GEM_DOMAIN_GTT))) 531 /* Only VRAM and GTT BOs are supported */ 532 goto out_put; 533 534 r = 0; 535 if (dmabuf_adev) 536 *dmabuf_adev = adev; 537 if (bo_size) 538 *bo_size = amdgpu_bo_size(bo); 539 if (metadata_buffer) 540 r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size, 541 metadata_size, &metadata_flags); 542 if (flags) { 543 *flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ? 544 KFD_IOC_ALLOC_MEM_FLAGS_VRAM 545 : KFD_IOC_ALLOC_MEM_FLAGS_GTT; 546 547 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 548 *flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC; 549 } 550 if (xcp_id) 551 *xcp_id = bo->xcp_id; 552 553 out_put: 554 dma_buf_put(dma_buf); 555 return r; 556 } 557 558 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct amdgpu_device *dst, 559 struct amdgpu_device *src) 560 { 561 struct amdgpu_device *peer_adev = src; 562 struct amdgpu_device *adev = dst; 563 int ret = amdgpu_xgmi_get_hops_count(adev, peer_adev); 564 565 if (ret < 0) { 566 DRM_ERROR("amdgpu: failed to get xgmi hops count between node %d and %d. ret = %d\n", 567 adev->gmc.xgmi.physical_node_id, 568 peer_adev->gmc.xgmi.physical_node_id, ret); 569 ret = 0; 570 } 571 return (uint8_t)ret; 572 } 573 574 int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct amdgpu_device *dst, 575 struct amdgpu_device *src, 576 bool is_min) 577 { 578 struct amdgpu_device *adev = dst, *peer_adev; 579 int num_links; 580 581 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2)) 582 return 0; 583 584 if (src) 585 peer_adev = src; 586 587 /* num links returns 0 for indirect peers since indirect route is unknown. */ 588 num_links = is_min ? 1 : amdgpu_xgmi_get_num_links(adev, peer_adev); 589 if (num_links < 0) { 590 DRM_ERROR("amdgpu: failed to get xgmi num links between node %d and %d. ret = %d\n", 591 adev->gmc.xgmi.physical_node_id, 592 peer_adev->gmc.xgmi.physical_node_id, num_links); 593 num_links = 0; 594 } 595 596 /* Aldebaran xGMI DPM is defeatured so assume x16 x 25Gbps for bandwidth. */ 597 return (num_links * 16 * 25000)/BITS_PER_BYTE; 598 } 599 600 int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min) 601 { 602 int num_lanes_shift = (is_min ? ffs(adev->pm.pcie_mlw_mask) : 603 fls(adev->pm.pcie_mlw_mask)) - 1; 604 int gen_speed_shift = (is_min ? ffs(adev->pm.pcie_gen_mask & 605 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) : 606 fls(adev->pm.pcie_gen_mask & 607 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK)) - 1; 608 uint32_t num_lanes_mask = 1 << num_lanes_shift; 609 uint32_t gen_speed_mask = 1 << gen_speed_shift; 610 int num_lanes_factor = 0, gen_speed_mbits_factor = 0; 611 612 switch (num_lanes_mask) { 613 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1: 614 num_lanes_factor = 1; 615 break; 616 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2: 617 num_lanes_factor = 2; 618 break; 619 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4: 620 num_lanes_factor = 4; 621 break; 622 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8: 623 num_lanes_factor = 8; 624 break; 625 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12: 626 num_lanes_factor = 12; 627 break; 628 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16: 629 num_lanes_factor = 16; 630 break; 631 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32: 632 num_lanes_factor = 32; 633 break; 634 } 635 636 switch (gen_speed_mask) { 637 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1: 638 gen_speed_mbits_factor = 2500; 639 break; 640 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2: 641 gen_speed_mbits_factor = 5000; 642 break; 643 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3: 644 gen_speed_mbits_factor = 8000; 645 break; 646 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4: 647 gen_speed_mbits_factor = 16000; 648 break; 649 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5: 650 gen_speed_mbits_factor = 32000; 651 break; 652 } 653 654 return (num_lanes_factor * gen_speed_mbits_factor)/BITS_PER_BYTE; 655 } 656 657 int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, 658 enum kgd_engine_type engine, 659 uint32_t vmid, uint64_t gpu_addr, 660 uint32_t *ib_cmd, uint32_t ib_len) 661 { 662 struct amdgpu_job *job; 663 struct amdgpu_ib *ib; 664 struct amdgpu_ring *ring; 665 struct dma_fence *f = NULL; 666 int ret; 667 668 switch (engine) { 669 case KGD_ENGINE_MEC1: 670 ring = &adev->gfx.compute_ring[0]; 671 break; 672 case KGD_ENGINE_SDMA1: 673 ring = &adev->sdma.instance[0].ring; 674 break; 675 case KGD_ENGINE_SDMA2: 676 ring = &adev->sdma.instance[1].ring; 677 break; 678 default: 679 pr_err("Invalid engine in IB submission: %d\n", engine); 680 ret = -EINVAL; 681 goto err; 682 } 683 684 ret = amdgpu_job_alloc(adev, NULL, NULL, NULL, 1, &job); 685 if (ret) 686 goto err; 687 688 ib = &job->ibs[0]; 689 memset(ib, 0, sizeof(struct amdgpu_ib)); 690 691 ib->gpu_addr = gpu_addr; 692 ib->ptr = ib_cmd; 693 ib->length_dw = ib_len; 694 /* This works for NO_HWS. TODO: need to handle without knowing VMID */ 695 job->vmid = vmid; 696 job->num_ibs = 1; 697 698 ret = amdgpu_ib_schedule(ring, 1, ib, job, &f); 699 700 if (ret) { 701 DRM_ERROR("amdgpu: failed to schedule IB.\n"); 702 goto err_ib_sched; 703 } 704 705 /* Drop the initial kref_init count (see drm_sched_main as example) */ 706 dma_fence_put(f); 707 ret = dma_fence_wait(f, false); 708 709 err_ib_sched: 710 amdgpu_job_free(job); 711 err: 712 return ret; 713 } 714 715 void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle) 716 { 717 enum amd_powergating_state state = idle ? AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE; 718 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 11 && 719 ((adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK) <= 64)) { 720 pr_debug("GFXOFF is %s\n", idle ? "enabled" : "disabled"); 721 amdgpu_gfx_off_ctrl(adev, idle); 722 } else if ((IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 9) && 723 (adev->flags & AMD_IS_APU)) { 724 /* Disable GFXOFF and PG. Temporary workaround 725 * to fix some compute applications issue on GFX9. 726 */ 727 adev->ip_blocks[AMD_IP_BLOCK_TYPE_GFX].version->funcs->set_powergating_state((void *)adev, state); 728 } 729 amdgpu_dpm_switch_power_profile(adev, 730 PP_SMC_POWER_PROFILE_COMPUTE, 731 !idle); 732 } 733 734 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid) 735 { 736 if (adev->kfd.dev) 737 return vmid >= adev->vm_manager.first_kfd_vmid; 738 739 return false; 740 } 741 742 bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev) 743 { 744 return adev->have_atomics_support; 745 } 746 747 void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev) 748 { 749 amdgpu_device_flush_hdp(adev, NULL); 750 } 751 752 bool amdgpu_amdkfd_is_fed(struct amdgpu_device *adev) 753 { 754 return amdgpu_ras_get_fed_status(adev); 755 } 756 757 void amdgpu_amdkfd_ras_pasid_poison_consumption_handler(struct amdgpu_device *adev, 758 enum amdgpu_ras_block block, uint16_t pasid, 759 pasid_notify pasid_fn, void *data, uint32_t reset) 760 { 761 amdgpu_umc_pasid_poison_handler(adev, block, pasid, pasid_fn, data, reset); 762 } 763 764 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, 765 enum amdgpu_ras_block block, uint32_t reset) 766 { 767 amdgpu_umc_pasid_poison_handler(adev, block, 0, NULL, NULL, reset); 768 } 769 770 int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev, 771 uint32_t *payload) 772 { 773 int ret; 774 775 /* Device or IH ring is not ready so bail. */ 776 ret = amdgpu_ih_wait_on_checkpoint_process_ts(adev, &adev->irq.ih); 777 if (ret) 778 return ret; 779 780 /* Send payload to fence KFD interrupts */ 781 amdgpu_amdkfd_interrupt(adev, payload); 782 783 return 0; 784 } 785 786 bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev, 787 int hub_inst, int hub_type) 788 { 789 if (!hub_type) { 790 if (adev->gfxhub.funcs->query_utcl2_poison_status) 791 return adev->gfxhub.funcs->query_utcl2_poison_status(adev, hub_inst); 792 else 793 return false; 794 } else { 795 if (adev->mmhub.funcs->query_utcl2_poison_status) 796 return adev->mmhub.funcs->query_utcl2_poison_status(adev, hub_inst); 797 else 798 return false; 799 } 800 } 801 802 int amdgpu_amdkfd_check_and_lock_kfd(struct amdgpu_device *adev) 803 { 804 return kgd2kfd_check_and_lock_kfd(); 805 } 806 807 void amdgpu_amdkfd_unlock_kfd(struct amdgpu_device *adev) 808 { 809 kgd2kfd_unlock_kfd(); 810 } 811 812 813 u64 amdgpu_amdkfd_xcp_memory_size(struct amdgpu_device *adev, int xcp_id) 814 { 815 s8 mem_id = KFD_XCP_MEM_ID(adev, xcp_id); 816 u64 tmp; 817 818 if (adev->gmc.num_mem_partitions && xcp_id >= 0 && mem_id >= 0) { 819 if (adev->gmc.is_app_apu && adev->gmc.num_mem_partitions == 1) { 820 /* In NPS1 mode, we should restrict the vram reporting 821 * tied to the ttm_pages_limit which is 1/2 of the system 822 * memory. For other partition modes, the HBM is uniformly 823 * divided already per numa node reported. If user wants to 824 * go beyond the default ttm limit and maximize the ROCm 825 * allocations, they can go up to max ttm and sysmem limits. 826 */ 827 828 tmp = (ttm_tt_pages_limit() << PAGE_SHIFT) / num_online_nodes(); 829 } else { 830 tmp = adev->gmc.mem_partitions[mem_id].size; 831 } 832 do_div(tmp, adev->xcp_mgr->num_xcp_per_mem_partition); 833 return ALIGN_DOWN(tmp, PAGE_SIZE); 834 } else if (adev->flags & AMD_IS_APU) { 835 return (ttm_tt_pages_limit() << PAGE_SHIFT); 836 } else { 837 return adev->gmc.real_vram_size; 838 } 839 } 840 841 int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off, 842 u32 inst) 843 { 844 struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst]; 845 struct amdgpu_ring *kiq_ring = &kiq->ring; 846 struct amdgpu_ring_funcs *ring_funcs; 847 struct amdgpu_ring *ring; 848 int r = 0; 849 850 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 851 return -EINVAL; 852 853 ring_funcs = kzalloc(sizeof(*ring_funcs), GFP_KERNEL); 854 if (!ring_funcs) 855 return -ENOMEM; 856 857 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 858 if (!ring) { 859 r = -ENOMEM; 860 goto free_ring_funcs; 861 } 862 863 ring_funcs->type = AMDGPU_RING_TYPE_COMPUTE; 864 ring->doorbell_index = doorbell_off; 865 ring->funcs = ring_funcs; 866 867 spin_lock(&kiq->ring_lock); 868 869 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 870 spin_unlock(&kiq->ring_lock); 871 r = -ENOMEM; 872 goto free_ring; 873 } 874 875 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 0, 0); 876 877 if (kiq_ring->sched.ready && !adev->job_hang) 878 r = amdgpu_ring_test_helper(kiq_ring); 879 880 spin_unlock(&kiq->ring_lock); 881 882 free_ring: 883 kfree(ring); 884 885 free_ring_funcs: 886 kfree(ring_funcs); 887 888 return r; 889 } 890