1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2014 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include "amdgpu_amdkfd.h" 25 #include "amd_pcie.h" 26 #include "amd_shared.h" 27 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_dma_buf.h" 31 #include <drm/ttm/ttm_tt.h> 32 #include <linux/module.h> 33 #include <linux/dma-buf.h> 34 #include "amdgpu_xgmi.h" 35 #include <uapi/linux/kfd_ioctl.h> 36 #include "amdgpu_ras.h" 37 #include "amdgpu_umc.h" 38 #include "amdgpu_reset.h" 39 #if IS_ENABLED(CONFIG_HSA_AMD) 40 #include "kfd_priv.h" 41 #endif 42 43 /* Total memory size in system memory and all GPU VRAM. Used to 44 * estimate worst case amount of memory to reserve for page tables 45 */ 46 uint64_t amdgpu_amdkfd_total_mem_size; 47 48 static bool kfd_initialized; 49 50 int amdgpu_amdkfd_init(void) 51 { 52 struct sysinfo si; 53 int ret; 54 55 si_meminfo(&si); 56 amdgpu_amdkfd_total_mem_size = si.freeram - si.freehigh; 57 amdgpu_amdkfd_total_mem_size *= si.mem_unit; 58 59 ret = kgd2kfd_init(); 60 kfd_initialized = !ret; 61 62 return ret; 63 } 64 65 void amdgpu_amdkfd_fini(void) 66 { 67 if (kfd_initialized) { 68 kgd2kfd_exit(); 69 kfd_initialized = false; 70 } 71 } 72 73 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) 74 { 75 bool vf = amdgpu_sriov_vf(adev); 76 77 if (!kfd_initialized) 78 return; 79 80 adev->kfd.dev = kgd2kfd_probe(adev, vf); 81 } 82 83 /** 84 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to 85 * setup amdkfd 86 * 87 * @adev: amdgpu_device pointer 88 * @aperture_base: output returning doorbell aperture base physical address 89 * @aperture_size: output returning doorbell aperture size in bytes 90 * @start_offset: output returning # of doorbell bytes reserved for amdgpu. 91 * 92 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, 93 * takes doorbells required for its own rings and reports the setup to amdkfd. 94 * amdgpu reserved doorbells are at the start of the doorbell aperture. 95 */ 96 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 97 phys_addr_t *aperture_base, 98 size_t *aperture_size, 99 size_t *start_offset) 100 { 101 /* 102 * The first num_kernel_doorbells are used by amdgpu. 103 * amdkfd takes whatever's left in the aperture. 104 */ 105 if (adev->enable_mes) { 106 /* 107 * With MES enabled, we only need to initialize 108 * the base address. The size and offset are 109 * not initialized as AMDGPU manages the whole 110 * doorbell space. 111 */ 112 *aperture_base = adev->doorbell.base; 113 *aperture_size = 0; 114 *start_offset = 0; 115 } else if (adev->doorbell.size > adev->doorbell.num_kernel_doorbells * 116 sizeof(u32)) { 117 *aperture_base = adev->doorbell.base; 118 *aperture_size = adev->doorbell.size; 119 *start_offset = adev->doorbell.num_kernel_doorbells * sizeof(u32); 120 } else { 121 *aperture_base = 0; 122 *aperture_size = 0; 123 *start_offset = 0; 124 } 125 } 126 127 128 static void amdgpu_amdkfd_reset_work(struct work_struct *work) 129 { 130 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 131 kfd.reset_work); 132 133 struct amdgpu_reset_context reset_context; 134 135 memset(&reset_context, 0, sizeof(reset_context)); 136 137 reset_context.method = AMD_RESET_METHOD_NONE; 138 reset_context.reset_req_dev = adev; 139 reset_context.src = adev->enable_mes ? 140 AMDGPU_RESET_SRC_MES : 141 AMDGPU_RESET_SRC_HWS; 142 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 143 144 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 145 } 146 147 static const struct drm_client_funcs kfd_client_funcs = { 148 .unregister = drm_client_release, 149 }; 150 151 int amdgpu_amdkfd_drm_client_create(struct amdgpu_device *adev) 152 { 153 int ret; 154 155 if (!adev->kfd.init_complete || adev->kfd.client.dev) 156 return 0; 157 158 ret = drm_client_init(&adev->ddev, &adev->kfd.client, "kfd", 159 &kfd_client_funcs); 160 if (ret) { 161 dev_err(adev->dev, "Failed to init DRM client: %d\n", 162 ret); 163 return ret; 164 } 165 166 drm_client_register(&adev->kfd.client); 167 168 return 0; 169 } 170 171 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) 172 { 173 int i; 174 int last_valid_bit; 175 176 amdgpu_amdkfd_gpuvm_init_mem_limits(); 177 178 if (adev->kfd.dev) { 179 struct kgd2kfd_shared_resources gpu_resources = { 180 .compute_vmid_bitmap = 181 ((1 << AMDGPU_NUM_VMID) - 1) - 182 ((1 << adev->vm_manager.first_kfd_vmid) - 1), 183 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, 184 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, 185 .gpuvm_size = min(adev->vm_manager.max_pfn 186 << AMDGPU_GPU_PAGE_SHIFT, 187 AMDGPU_GMC_HOLE_START), 188 .drm_render_minor = adev_to_drm(adev)->render->index, 189 .sdma_doorbell_idx = adev->doorbell_index.sdma_engine, 190 .enable_mes = adev->enable_mes, 191 }; 192 193 /* this is going to have a few of the MSBs set that we need to 194 * clear 195 */ 196 bitmap_complement(gpu_resources.cp_queue_bitmap, 197 adev->gfx.mec_bitmap[0].queue_bitmap, 198 AMDGPU_MAX_QUEUES); 199 200 /* According to linux/bitmap.h we shouldn't use bitmap_clear if 201 * nbits is not compile time constant 202 */ 203 last_valid_bit = 1 /* only first MEC can have compute queues */ 204 * adev->gfx.mec.num_pipe_per_mec 205 * adev->gfx.mec.num_queue_per_pipe; 206 for (i = last_valid_bit; i < AMDGPU_MAX_QUEUES; ++i) 207 clear_bit(i, gpu_resources.cp_queue_bitmap); 208 209 amdgpu_doorbell_get_kfd_info(adev, 210 &gpu_resources.doorbell_physical_address, 211 &gpu_resources.doorbell_aperture_size, 212 &gpu_resources.doorbell_start_offset); 213 214 /* Since SOC15, BIF starts to statically use the 215 * lower 12 bits of doorbell addresses for routing 216 * based on settings in registers like 217 * SDMA0_DOORBELL_RANGE etc.. 218 * In order to route a doorbell to CP engine, the lower 219 * 12 bits of its address has to be outside the range 220 * set for SDMA, VCN, and IH blocks. 221 */ 222 if (adev->asic_type >= CHIP_VEGA10) { 223 gpu_resources.non_cp_doorbells_start = 224 adev->doorbell_index.first_non_cp; 225 gpu_resources.non_cp_doorbells_end = 226 adev->doorbell_index.last_non_cp; 227 } 228 229 adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev, 230 &gpu_resources); 231 232 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size; 233 234 INIT_WORK(&adev->kfd.reset_work, amdgpu_amdkfd_reset_work); 235 } 236 } 237 238 void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev) 239 { 240 if (adev->kfd.dev) { 241 kgd2kfd_device_exit(adev->kfd.dev); 242 adev->kfd.dev = NULL; 243 amdgpu_amdkfd_total_mem_size -= adev->gmc.real_vram_size; 244 } 245 } 246 247 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, 248 const void *ih_ring_entry) 249 { 250 if (adev->kfd.dev) 251 kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry); 252 } 253 254 void amdgpu_amdkfd_teardown_processes(struct amdgpu_device *adev) 255 { 256 kgd2kfd_teardown_processes(adev); 257 } 258 259 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool suspend_proc) 260 { 261 if (adev->kfd.dev) { 262 if (adev->in_s0ix) 263 kgd2kfd_stop_sched_all_nodes(adev->kfd.dev); 264 else 265 kgd2kfd_suspend(adev->kfd.dev, suspend_proc); 266 } 267 } 268 269 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool resume_proc) 270 { 271 int r = 0; 272 273 if (adev->kfd.dev) { 274 if (adev->in_s0ix) 275 r = kgd2kfd_start_sched_all_nodes(adev->kfd.dev); 276 else 277 r = kgd2kfd_resume(adev->kfd.dev, resume_proc); 278 } 279 280 return r; 281 } 282 283 void amdgpu_amdkfd_suspend_process(struct amdgpu_device *adev) 284 { 285 if (adev->kfd.dev) 286 kgd2kfd_suspend_process(adev->kfd.dev); 287 } 288 289 int amdgpu_amdkfd_resume_process(struct amdgpu_device *adev) 290 { 291 int r = 0; 292 293 if (adev->kfd.dev) 294 r = kgd2kfd_resume_process(adev->kfd.dev); 295 296 return r; 297 } 298 299 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev, 300 struct amdgpu_reset_context *reset_context) 301 { 302 int r = 0; 303 304 if (adev->kfd.dev) 305 r = kgd2kfd_pre_reset(adev->kfd.dev, reset_context); 306 307 return r; 308 } 309 310 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev) 311 { 312 int r = 0; 313 314 if (adev->kfd.dev) 315 r = kgd2kfd_post_reset(adev->kfd.dev); 316 317 return r; 318 } 319 320 void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev) 321 { 322 if (amdgpu_device_should_recover_gpu(adev)) 323 (void)amdgpu_reset_domain_schedule(adev->reset_domain, &adev->kfd.reset_work); 324 } 325 326 void amdgpu_amdkfd_clear_kfd_mapping(struct amdgpu_device *adev) 327 { 328 #if IS_ENABLED(CONFIG_HSA_AMD) 329 struct kfd_dev *kfd = adev->kfd.dev; 330 unsigned int i; 331 332 if (!kfd) 333 return; 334 335 for (i = 0; i < kfd->num_nodes; i++) { 336 struct kfd_node *node = kfd->nodes[i]; 337 338 kfd_dev_unmap_mapping_range(KFD_MMAP_TYPE_DOORBELL | 339 KFD_MMAP_GPU_ID(node->id), 340 kfd_doorbell_process_slice(kfd)); 341 kfd_dev_unmap_mapping_range(KFD_MMAP_TYPE_MMIO | 342 KFD_MMAP_GPU_ID(node->id), 343 PAGE_SIZE); 344 } 345 #endif 346 } 347 348 int amdgpu_amdkfd_alloc_kernel_mem(struct amdgpu_device *adev, size_t size, 349 u32 domain, void **mem_obj, uint64_t *gpu_addr, 350 void **cpu_ptr, bool cp_mqd_gfx9) 351 { 352 struct amdgpu_bo *bo = NULL; 353 struct amdgpu_bo_param bp; 354 int r; 355 void *cpu_ptr_tmp = NULL; 356 357 memset(&bp, 0, sizeof(bp)); 358 bp.size = size; 359 bp.byte_align = PAGE_SIZE; 360 bp.domain = domain; 361 bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | 362 AMDGPU_GEM_CREATE_CPU_GTT_USWC; 363 bp.type = ttm_bo_type_kernel; 364 bp.resv = NULL; 365 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 366 367 if (cp_mqd_gfx9) 368 bp.flags |= AMDGPU_GEM_CREATE_CP_MQD_GFX9; 369 370 r = amdgpu_bo_create(adev, &bp, &bo); 371 if (r) { 372 dev_err(adev->dev, 373 "failed to allocate BO for amdkfd (%d)\n", r); 374 return r; 375 } 376 377 /* map the buffer */ 378 r = amdgpu_bo_reserve(bo, true); 379 if (r) { 380 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r); 381 goto allocate_mem_reserve_bo_failed; 382 } 383 384 r = amdgpu_bo_pin(bo, domain); 385 if (r) { 386 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r); 387 goto allocate_mem_pin_bo_failed; 388 } 389 390 r = amdgpu_ttm_alloc_gart(&bo->tbo); 391 if (r) { 392 dev_err(adev->dev, "%p bind failed\n", bo); 393 goto allocate_mem_kmap_bo_failed; 394 } 395 396 r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp); 397 if (r) { 398 dev_err(adev->dev, 399 "(%d) failed to map bo to kernel for amdkfd\n", r); 400 goto allocate_mem_kmap_bo_failed; 401 } 402 403 *mem_obj = bo; 404 *gpu_addr = amdgpu_bo_gpu_offset(bo); 405 *cpu_ptr = cpu_ptr_tmp; 406 407 amdgpu_bo_unreserve(bo); 408 409 return 0; 410 411 allocate_mem_kmap_bo_failed: 412 amdgpu_bo_unpin(bo); 413 allocate_mem_pin_bo_failed: 414 amdgpu_bo_unreserve(bo); 415 allocate_mem_reserve_bo_failed: 416 amdgpu_bo_unref(&bo); 417 418 return r; 419 } 420 421 void amdgpu_amdkfd_free_kernel_mem(struct amdgpu_device *adev, void **mem_obj) 422 { 423 struct amdgpu_bo **bo = (struct amdgpu_bo **) mem_obj; 424 425 if (!bo || !*bo) 426 return; 427 428 (void)amdgpu_bo_reserve(*bo, true); 429 amdgpu_bo_kunmap(*bo); 430 amdgpu_bo_unpin(*bo); 431 amdgpu_bo_unreserve(*bo); 432 amdgpu_bo_unref(bo); 433 } 434 435 int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size, 436 void **mem_obj) 437 { 438 struct amdgpu_bo *bo = NULL; 439 struct amdgpu_bo_user *ubo; 440 struct amdgpu_bo_param bp; 441 int r; 442 443 memset(&bp, 0, sizeof(bp)); 444 bp.size = size; 445 bp.byte_align = 1; 446 bp.domain = AMDGPU_GEM_DOMAIN_GWS; 447 bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 448 bp.type = ttm_bo_type_device; 449 bp.resv = NULL; 450 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 451 452 r = amdgpu_bo_create_user(adev, &bp, &ubo); 453 if (r) { 454 dev_err(adev->dev, 455 "failed to allocate gws BO for amdkfd (%d)\n", r); 456 return r; 457 } 458 459 bo = &ubo->bo; 460 *mem_obj = bo; 461 return 0; 462 } 463 464 void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj) 465 { 466 struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj; 467 468 amdgpu_bo_unref(&bo); 469 } 470 471 uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev, 472 enum kgd_engine_type type) 473 { 474 switch (type) { 475 case KGD_ENGINE_PFP: 476 return adev->gfx.pfp_fw_version; 477 478 case KGD_ENGINE_ME: 479 return adev->gfx.me_fw_version; 480 481 case KGD_ENGINE_CE: 482 return adev->gfx.ce_fw_version; 483 484 case KGD_ENGINE_MEC1: 485 return adev->gfx.mec_fw_version; 486 487 case KGD_ENGINE_MEC2: 488 return adev->gfx.mec2_fw_version; 489 490 case KGD_ENGINE_RLC: 491 return adev->gfx.rlc_fw_version; 492 493 case KGD_ENGINE_SDMA1: 494 return adev->sdma.instance[0].fw_version; 495 496 case KGD_ENGINE_SDMA2: 497 return adev->sdma.instance[1].fw_version; 498 499 default: 500 return 0; 501 } 502 503 return 0; 504 } 505 506 void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev, 507 struct kfd_local_mem_info *mem_info, 508 struct amdgpu_xcp *xcp) 509 { 510 memset(mem_info, 0, sizeof(*mem_info)); 511 512 if (xcp) { 513 if (adev->gmc.real_vram_size == adev->gmc.visible_vram_size) 514 mem_info->local_mem_size_public = 515 KFD_XCP_MEMORY_SIZE(adev, xcp->id); 516 else 517 mem_info->local_mem_size_private = 518 KFD_XCP_MEMORY_SIZE(adev, xcp->id); 519 } else if (adev->apu_prefer_gtt) { 520 mem_info->local_mem_size_public = (ttm_tt_pages_limit() << PAGE_SHIFT); 521 mem_info->local_mem_size_private = 0; 522 } else { 523 mem_info->local_mem_size_public = adev->gmc.visible_vram_size; 524 mem_info->local_mem_size_private = adev->gmc.real_vram_size - 525 adev->gmc.visible_vram_size; 526 } 527 mem_info->vram_width = adev->gmc.vram_width; 528 529 pr_debug("Address base: %pap public 0x%llx private 0x%llx\n", 530 &adev->gmc.aper_base, 531 mem_info->local_mem_size_public, 532 mem_info->local_mem_size_private); 533 534 if (adev->pm.dpm_enabled) { 535 if (amdgpu_emu_mode == 1) 536 mem_info->mem_clk_max = 0; 537 else 538 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100; 539 } else 540 mem_info->mem_clk_max = 100; 541 } 542 543 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev) 544 { 545 if (adev->gfx.funcs->get_gpu_clock_counter) 546 return adev->gfx.funcs->get_gpu_clock_counter(adev); 547 return 0; 548 } 549 550 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev) 551 { 552 /* the sclk is in quantas of 10kHz */ 553 if (adev->pm.dpm_enabled) 554 return amdgpu_dpm_get_sclk(adev, false) / 100; 555 else 556 return 100; 557 } 558 559 int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, 560 struct amdgpu_device **dmabuf_adev, 561 uint64_t *bo_size, void *metadata_buffer, 562 size_t buffer_size, uint32_t *metadata_size, 563 uint32_t *flags, int8_t *xcp_id) 564 { 565 struct dma_buf *dma_buf; 566 struct drm_gem_object *obj; 567 struct amdgpu_bo *bo; 568 uint64_t metadata_flags; 569 int r = -EINVAL; 570 571 dma_buf = dma_buf_get(dma_buf_fd); 572 if (IS_ERR(dma_buf)) 573 return PTR_ERR(dma_buf); 574 575 if (dma_buf->ops != &amdgpu_dmabuf_ops) 576 /* Can't handle non-graphics buffers */ 577 goto out_put; 578 579 obj = dma_buf->priv; 580 if (obj->dev->driver != adev_to_drm(adev)->driver) 581 /* Can't handle buffers from different drivers */ 582 goto out_put; 583 584 adev = drm_to_adev(obj->dev); 585 bo = gem_to_amdgpu_bo(obj); 586 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM | 587 AMDGPU_GEM_DOMAIN_GTT))) 588 /* Only VRAM and GTT BOs are supported */ 589 goto out_put; 590 591 r = 0; 592 if (dmabuf_adev) 593 *dmabuf_adev = adev; 594 if (bo_size) 595 *bo_size = amdgpu_bo_size(bo); 596 if (metadata_buffer) 597 r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size, 598 metadata_size, &metadata_flags); 599 if (flags) { 600 *flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ? 601 KFD_IOC_ALLOC_MEM_FLAGS_VRAM 602 : KFD_IOC_ALLOC_MEM_FLAGS_GTT; 603 604 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 605 *flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC; 606 } 607 if (xcp_id) 608 *xcp_id = bo->xcp_id; 609 610 out_put: 611 dma_buf_put(dma_buf); 612 return r; 613 } 614 615 int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min) 616 { 617 int num_lanes_shift = (is_min ? ffs(adev->pm.pcie_mlw_mask) : 618 fls(adev->pm.pcie_mlw_mask)) - 1; 619 int gen_speed_shift = (is_min ? ffs(adev->pm.pcie_gen_mask & 620 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) : 621 fls(adev->pm.pcie_gen_mask & 622 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK)) - 1; 623 uint32_t num_lanes_mask = 1 << num_lanes_shift; 624 uint32_t gen_speed_mask = 1 << gen_speed_shift; 625 int num_lanes_factor = 0, gen_speed_mbits_factor = 0; 626 627 switch (num_lanes_mask) { 628 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1: 629 num_lanes_factor = 1; 630 break; 631 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2: 632 num_lanes_factor = 2; 633 break; 634 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4: 635 num_lanes_factor = 4; 636 break; 637 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8: 638 num_lanes_factor = 8; 639 break; 640 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12: 641 num_lanes_factor = 12; 642 break; 643 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16: 644 num_lanes_factor = 16; 645 break; 646 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32: 647 num_lanes_factor = 32; 648 break; 649 } 650 651 switch (gen_speed_mask) { 652 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1: 653 gen_speed_mbits_factor = 2500; 654 break; 655 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2: 656 gen_speed_mbits_factor = 5000; 657 break; 658 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3: 659 gen_speed_mbits_factor = 8000; 660 break; 661 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4: 662 gen_speed_mbits_factor = 16000; 663 break; 664 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5: 665 gen_speed_mbits_factor = 32000; 666 break; 667 } 668 669 return (num_lanes_factor * gen_speed_mbits_factor)/BITS_PER_BYTE; 670 } 671 672 int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, 673 enum kgd_engine_type engine, 674 uint32_t vmid, uint64_t gpu_addr, 675 uint32_t *ib_cmd, uint32_t ib_len) 676 { 677 struct amdgpu_job *job; 678 struct amdgpu_ib *ib; 679 struct amdgpu_ring *ring; 680 struct dma_fence *f = NULL; 681 int ret; 682 683 switch (engine) { 684 case KGD_ENGINE_MEC1: 685 ring = &adev->gfx.compute_ring[0]; 686 break; 687 case KGD_ENGINE_SDMA1: 688 ring = &adev->sdma.instance[0].ring; 689 break; 690 case KGD_ENGINE_SDMA2: 691 ring = &adev->sdma.instance[1].ring; 692 break; 693 default: 694 pr_err("Invalid engine in IB submission: %d\n", engine); 695 ret = -EINVAL; 696 goto err; 697 } 698 699 ret = amdgpu_job_alloc(adev, NULL, NULL, NULL, 1, &job, 0); 700 if (ret) 701 goto err; 702 703 ib = &job->ibs[0]; 704 memset(ib, 0, sizeof(struct amdgpu_ib)); 705 706 ib->gpu_addr = gpu_addr; 707 ib->ptr = ib_cmd; 708 ib->length_dw = ib_len; 709 /* This works for NO_HWS. TODO: need to handle without knowing VMID */ 710 job->vmid = vmid; 711 job->num_ibs = 1; 712 713 ret = amdgpu_ib_schedule(ring, 1, ib, job, &f); 714 715 if (ret) { 716 drm_err(adev_to_drm(adev), "failed to schedule IB.\n"); 717 goto err_ib_sched; 718 } 719 720 ret = dma_fence_wait(f, false); 721 /* Drop the returned fence reference after the wait completes */ 722 dma_fence_put(f); 723 724 err_ib_sched: 725 amdgpu_job_free(job); 726 err: 727 return ret; 728 } 729 730 void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle) 731 { 732 enum amd_powergating_state state = idle ? AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE; 733 if ((IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 11 && 734 ((adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK) <= 64)) || 735 (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 12)) { 736 pr_debug("GFXOFF is %s\n", idle ? "enabled" : "disabled"); 737 amdgpu_gfx_off_ctrl(adev, idle); 738 } else if ((IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 9) && 739 (adev->flags & AMD_IS_APU)) { 740 /* Disable GFXOFF and PG. Temporary workaround 741 * to fix some compute applications issue on GFX9. 742 */ 743 struct amdgpu_ip_block *gfx_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); 744 if (gfx_block != NULL) 745 gfx_block->version->funcs->set_powergating_state((void *)gfx_block, state); 746 } 747 (void)amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_COMPUTE, !idle); 748 749 } 750 751 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid) 752 { 753 if (adev->kfd.dev) 754 return vmid >= adev->vm_manager.first_kfd_vmid; 755 756 return false; 757 } 758 759 bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev) 760 { 761 return adev->have_atomics_support; 762 } 763 764 void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev) 765 { 766 amdgpu_device_flush_hdp(adev, NULL); 767 } 768 769 bool amdgpu_amdkfd_is_fed(struct amdgpu_device *adev) 770 { 771 return amdgpu_ras_get_fed_status(adev); 772 } 773 774 void amdgpu_amdkfd_ras_pasid_poison_consumption_handler(struct amdgpu_device *adev, 775 enum amdgpu_ras_block block, uint16_t pasid, 776 pasid_notify pasid_fn, void *data, uint32_t reset) 777 { 778 amdgpu_umc_pasid_poison_handler(adev, block, pasid, pasid_fn, data, reset); 779 } 780 781 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, 782 enum amdgpu_ras_block block, uint32_t reset) 783 { 784 amdgpu_umc_pasid_poison_handler(adev, block, 0, NULL, NULL, reset); 785 } 786 787 int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev, 788 uint32_t *payload) 789 { 790 int ret; 791 792 /* Device or IH ring is not ready so bail. */ 793 ret = amdgpu_ih_wait_on_checkpoint_process_ts(adev, &adev->irq.ih); 794 if (ret) 795 return ret; 796 797 /* Send payload to fence KFD interrupts */ 798 amdgpu_amdkfd_interrupt(adev, payload); 799 800 return 0; 801 } 802 803 int amdgpu_amdkfd_check_and_lock_kfd(struct amdgpu_device *adev) 804 { 805 return kgd2kfd_check_and_lock_kfd(adev->kfd.dev); 806 } 807 808 void amdgpu_amdkfd_unlock_kfd(struct amdgpu_device *adev) 809 { 810 kgd2kfd_unlock_kfd(adev->kfd.dev); 811 } 812 813 814 u64 amdgpu_amdkfd_xcp_memory_size(struct amdgpu_device *adev, int xcp_id) 815 { 816 s8 mem_id = KFD_XCP_MEM_ID(adev, xcp_id); 817 u64 tmp; 818 819 if (adev->gmc.num_mem_partitions && xcp_id >= 0 && mem_id >= 0) { 820 if (adev->gmc.is_app_apu && adev->gmc.num_mem_partitions == 1) { 821 /* In NPS1 mode, we should restrict the vram reporting 822 * tied to the ttm_pages_limit which is 1/2 of the system 823 * memory. For other partition modes, the HBM is uniformly 824 * divided already per numa node reported. If user wants to 825 * go beyond the default ttm limit and maximize the ROCm 826 * allocations, they can go up to max ttm and sysmem limits. 827 */ 828 829 tmp = (ttm_tt_pages_limit() << PAGE_SHIFT) / num_online_nodes(); 830 } else { 831 tmp = adev->gmc.mem_partitions[mem_id].size; 832 } 833 834 if (adev->xcp_mgr->mem_alloc_mode == AMDGPU_PARTITION_MEM_CAPPING_EVEN) 835 do_div(tmp, adev->xcp_mgr->num_xcp_per_mem_partition); 836 837 return ALIGN_DOWN(tmp, PAGE_SIZE); 838 } else if (adev->apu_prefer_gtt) { 839 return (ttm_tt_pages_limit() << PAGE_SHIFT); 840 } else { 841 return adev->gmc.real_vram_size; 842 } 843 } 844 845 int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off, 846 u32 inst) 847 { 848 struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst]; 849 struct amdgpu_ring *kiq_ring = &kiq->ring; 850 struct amdgpu_ring_funcs *ring_funcs; 851 struct amdgpu_ring *ring; 852 int r = 0; 853 854 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 855 return -EINVAL; 856 857 if (!kiq_ring->sched.ready || amdgpu_in_reset(adev)) 858 return 0; 859 860 ring_funcs = kzalloc_obj(*ring_funcs); 861 if (!ring_funcs) 862 return -ENOMEM; 863 864 ring = kzalloc_obj(*ring); 865 if (!ring) { 866 r = -ENOMEM; 867 goto free_ring_funcs; 868 } 869 870 ring_funcs->type = AMDGPU_RING_TYPE_COMPUTE; 871 ring->doorbell_index = doorbell_off; 872 ring->funcs = ring_funcs; 873 874 spin_lock(&kiq->ring_lock); 875 876 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 877 spin_unlock(&kiq->ring_lock); 878 r = -ENOMEM; 879 goto free_ring; 880 } 881 882 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 0, 0); 883 884 /* Submit unmap queue packet */ 885 amdgpu_ring_commit(kiq_ring); 886 /* 887 * Ring test will do a basic scratch register change check. Just run 888 * this to ensure that unmap queues that is submitted before got 889 * processed successfully before returning. 890 */ 891 r = amdgpu_ring_test_helper(kiq_ring); 892 893 spin_unlock(&kiq->ring_lock); 894 895 free_ring: 896 kfree(ring); 897 898 free_ring_funcs: 899 kfree(ring_funcs); 900 901 return r; 902 } 903 904 /* Stop scheduling on KFD */ 905 int amdgpu_amdkfd_stop_sched(struct amdgpu_device *adev, uint32_t node_id) 906 { 907 if (!adev->kfd.init_complete) 908 return 0; 909 910 return kgd2kfd_stop_sched(adev->kfd.dev, node_id); 911 } 912 913 /* Start scheduling on KFD */ 914 int amdgpu_amdkfd_start_sched(struct amdgpu_device *adev, uint32_t node_id) 915 { 916 if (!adev->kfd.init_complete) 917 return 0; 918 919 return kgd2kfd_start_sched(adev->kfd.dev, node_id); 920 } 921 922 /* check if there are KFD queues active */ 923 bool amdgpu_amdkfd_compute_active(struct amdgpu_device *adev, uint32_t node_id) 924 { 925 if (!adev->kfd.init_complete) 926 return false; 927 928 return kgd2kfd_compute_active(adev->kfd.dev, node_id); 929 } 930 931 /* Config CGTT_SQ_CLK_CTRL */ 932 int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcp_id, 933 bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable) 934 { 935 int r; 936 937 if (!adev->kfd.init_complete) 938 return 0; 939 940 r = psp_config_sq_perfmon(&adev->psp, xcp_id, core_override_enable, 941 reg_override_enable, perfmon_override_enable); 942 943 return r; 944 } 945