1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2014 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include "amdgpu_amdkfd.h" 25 #include "amd_pcie.h" 26 #include "amd_shared.h" 27 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_dma_buf.h" 31 #include <drm/ttm/ttm_tt.h> 32 #include <linux/module.h> 33 #include <linux/dma-buf.h> 34 #include "amdgpu_xgmi.h" 35 #include <uapi/linux/kfd_ioctl.h> 36 #include "amdgpu_ras.h" 37 #include "amdgpu_umc.h" 38 #include "amdgpu_reset.h" 39 40 /* Total memory size in system memory and all GPU VRAM. Used to 41 * estimate worst case amount of memory to reserve for page tables 42 */ 43 uint64_t amdgpu_amdkfd_total_mem_size; 44 45 static bool kfd_initialized; 46 47 int amdgpu_amdkfd_init(void) 48 { 49 struct sysinfo si; 50 int ret; 51 52 si_meminfo(&si); 53 amdgpu_amdkfd_total_mem_size = si.freeram - si.freehigh; 54 amdgpu_amdkfd_total_mem_size *= si.mem_unit; 55 56 ret = kgd2kfd_init(); 57 kfd_initialized = !ret; 58 59 return ret; 60 } 61 62 void amdgpu_amdkfd_fini(void) 63 { 64 if (kfd_initialized) { 65 kgd2kfd_exit(); 66 kfd_initialized = false; 67 } 68 } 69 70 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) 71 { 72 bool vf = amdgpu_sriov_vf(adev); 73 74 if (!kfd_initialized) 75 return; 76 77 adev->kfd.dev = kgd2kfd_probe(adev, vf); 78 } 79 80 /** 81 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to 82 * setup amdkfd 83 * 84 * @adev: amdgpu_device pointer 85 * @aperture_base: output returning doorbell aperture base physical address 86 * @aperture_size: output returning doorbell aperture size in bytes 87 * @start_offset: output returning # of doorbell bytes reserved for amdgpu. 88 * 89 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, 90 * takes doorbells required for its own rings and reports the setup to amdkfd. 91 * amdgpu reserved doorbells are at the start of the doorbell aperture. 92 */ 93 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 94 phys_addr_t *aperture_base, 95 size_t *aperture_size, 96 size_t *start_offset) 97 { 98 /* 99 * The first num_kernel_doorbells are used by amdgpu. 100 * amdkfd takes whatever's left in the aperture. 101 */ 102 if (adev->enable_mes) { 103 /* 104 * With MES enabled, we only need to initialize 105 * the base address. The size and offset are 106 * not initialized as AMDGPU manages the whole 107 * doorbell space. 108 */ 109 *aperture_base = adev->doorbell.base; 110 *aperture_size = 0; 111 *start_offset = 0; 112 } else if (adev->doorbell.size > adev->doorbell.num_kernel_doorbells * 113 sizeof(u32)) { 114 *aperture_base = adev->doorbell.base; 115 *aperture_size = adev->doorbell.size; 116 *start_offset = adev->doorbell.num_kernel_doorbells * sizeof(u32); 117 } else { 118 *aperture_base = 0; 119 *aperture_size = 0; 120 *start_offset = 0; 121 } 122 } 123 124 125 static void amdgpu_amdkfd_reset_work(struct work_struct *work) 126 { 127 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 128 kfd.reset_work); 129 130 struct amdgpu_reset_context reset_context; 131 132 memset(&reset_context, 0, sizeof(reset_context)); 133 134 reset_context.method = AMD_RESET_METHOD_NONE; 135 reset_context.reset_req_dev = adev; 136 reset_context.src = adev->enable_mes ? 137 AMDGPU_RESET_SRC_MES : 138 AMDGPU_RESET_SRC_HWS; 139 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 140 141 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 142 } 143 144 static const struct drm_client_funcs kfd_client_funcs = { 145 .unregister = drm_client_release, 146 }; 147 148 int amdgpu_amdkfd_drm_client_create(struct amdgpu_device *adev) 149 { 150 int ret; 151 152 if (!adev->kfd.init_complete || adev->kfd.client.dev) 153 return 0; 154 155 ret = drm_client_init(&adev->ddev, &adev->kfd.client, "kfd", 156 &kfd_client_funcs); 157 if (ret) { 158 dev_err(adev->dev, "Failed to init DRM client: %d\n", 159 ret); 160 return ret; 161 } 162 163 drm_client_register(&adev->kfd.client); 164 165 return 0; 166 } 167 168 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) 169 { 170 int i; 171 int last_valid_bit; 172 173 amdgpu_amdkfd_gpuvm_init_mem_limits(); 174 175 if (adev->kfd.dev) { 176 struct kgd2kfd_shared_resources gpu_resources = { 177 .compute_vmid_bitmap = 178 ((1 << AMDGPU_NUM_VMID) - 1) - 179 ((1 << adev->vm_manager.first_kfd_vmid) - 1), 180 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, 181 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, 182 .gpuvm_size = min(adev->vm_manager.max_pfn 183 << AMDGPU_GPU_PAGE_SHIFT, 184 AMDGPU_GMC_HOLE_START), 185 .drm_render_minor = adev_to_drm(adev)->render->index, 186 .sdma_doorbell_idx = adev->doorbell_index.sdma_engine, 187 .enable_mes = adev->enable_mes, 188 }; 189 190 /* this is going to have a few of the MSBs set that we need to 191 * clear 192 */ 193 bitmap_complement(gpu_resources.cp_queue_bitmap, 194 adev->gfx.mec_bitmap[0].queue_bitmap, 195 AMDGPU_MAX_QUEUES); 196 197 /* According to linux/bitmap.h we shouldn't use bitmap_clear if 198 * nbits is not compile time constant 199 */ 200 last_valid_bit = 1 /* only first MEC can have compute queues */ 201 * adev->gfx.mec.num_pipe_per_mec 202 * adev->gfx.mec.num_queue_per_pipe; 203 for (i = last_valid_bit; i < AMDGPU_MAX_QUEUES; ++i) 204 clear_bit(i, gpu_resources.cp_queue_bitmap); 205 206 amdgpu_doorbell_get_kfd_info(adev, 207 &gpu_resources.doorbell_physical_address, 208 &gpu_resources.doorbell_aperture_size, 209 &gpu_resources.doorbell_start_offset); 210 211 /* Since SOC15, BIF starts to statically use the 212 * lower 12 bits of doorbell addresses for routing 213 * based on settings in registers like 214 * SDMA0_DOORBELL_RANGE etc.. 215 * In order to route a doorbell to CP engine, the lower 216 * 12 bits of its address has to be outside the range 217 * set for SDMA, VCN, and IH blocks. 218 */ 219 if (adev->asic_type >= CHIP_VEGA10) { 220 gpu_resources.non_cp_doorbells_start = 221 adev->doorbell_index.first_non_cp; 222 gpu_resources.non_cp_doorbells_end = 223 adev->doorbell_index.last_non_cp; 224 } 225 226 adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev, 227 &gpu_resources); 228 229 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size; 230 231 INIT_WORK(&adev->kfd.reset_work, amdgpu_amdkfd_reset_work); 232 } 233 } 234 235 void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev) 236 { 237 if (adev->kfd.dev) { 238 kgd2kfd_device_exit(adev->kfd.dev); 239 adev->kfd.dev = NULL; 240 amdgpu_amdkfd_total_mem_size -= adev->gmc.real_vram_size; 241 } 242 } 243 244 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, 245 const void *ih_ring_entry) 246 { 247 if (adev->kfd.dev) 248 kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry); 249 } 250 251 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool suspend_proc) 252 { 253 if (adev->kfd.dev) 254 kgd2kfd_suspend(adev->kfd.dev, suspend_proc); 255 } 256 257 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool resume_proc) 258 { 259 int r = 0; 260 261 if (adev->kfd.dev) 262 r = kgd2kfd_resume(adev->kfd.dev, resume_proc); 263 264 return r; 265 } 266 267 void amdgpu_amdkfd_suspend_process(struct amdgpu_device *adev) 268 { 269 if (adev->kfd.dev) 270 kgd2kfd_suspend_process(adev->kfd.dev); 271 } 272 273 int amdgpu_amdkfd_resume_process(struct amdgpu_device *adev) 274 { 275 int r = 0; 276 277 if (adev->kfd.dev) 278 r = kgd2kfd_resume_process(adev->kfd.dev); 279 280 return r; 281 } 282 283 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev, 284 struct amdgpu_reset_context *reset_context) 285 { 286 int r = 0; 287 288 if (adev->kfd.dev) 289 r = kgd2kfd_pre_reset(adev->kfd.dev, reset_context); 290 291 return r; 292 } 293 294 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev) 295 { 296 int r = 0; 297 298 if (adev->kfd.dev) 299 r = kgd2kfd_post_reset(adev->kfd.dev); 300 301 return r; 302 } 303 304 void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev) 305 { 306 if (amdgpu_device_should_recover_gpu(adev)) 307 amdgpu_reset_domain_schedule(adev->reset_domain, 308 &adev->kfd.reset_work); 309 } 310 311 int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size, 312 void **mem_obj, uint64_t *gpu_addr, 313 void **cpu_ptr, bool cp_mqd_gfx9) 314 { 315 struct amdgpu_bo *bo = NULL; 316 struct amdgpu_bo_param bp; 317 int r; 318 void *cpu_ptr_tmp = NULL; 319 320 memset(&bp, 0, sizeof(bp)); 321 bp.size = size; 322 bp.byte_align = PAGE_SIZE; 323 bp.domain = AMDGPU_GEM_DOMAIN_GTT; 324 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC; 325 bp.type = ttm_bo_type_kernel; 326 bp.resv = NULL; 327 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 328 329 if (cp_mqd_gfx9) 330 bp.flags |= AMDGPU_GEM_CREATE_CP_MQD_GFX9; 331 332 r = amdgpu_bo_create(adev, &bp, &bo); 333 if (r) { 334 dev_err(adev->dev, 335 "failed to allocate BO for amdkfd (%d)\n", r); 336 return r; 337 } 338 339 /* map the buffer */ 340 r = amdgpu_bo_reserve(bo, true); 341 if (r) { 342 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r); 343 goto allocate_mem_reserve_bo_failed; 344 } 345 346 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); 347 if (r) { 348 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r); 349 goto allocate_mem_pin_bo_failed; 350 } 351 352 r = amdgpu_ttm_alloc_gart(&bo->tbo); 353 if (r) { 354 dev_err(adev->dev, "%p bind failed\n", bo); 355 goto allocate_mem_kmap_bo_failed; 356 } 357 358 r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp); 359 if (r) { 360 dev_err(adev->dev, 361 "(%d) failed to map bo to kernel for amdkfd\n", r); 362 goto allocate_mem_kmap_bo_failed; 363 } 364 365 *mem_obj = bo; 366 *gpu_addr = amdgpu_bo_gpu_offset(bo); 367 *cpu_ptr = cpu_ptr_tmp; 368 369 amdgpu_bo_unreserve(bo); 370 371 return 0; 372 373 allocate_mem_kmap_bo_failed: 374 amdgpu_bo_unpin(bo); 375 allocate_mem_pin_bo_failed: 376 amdgpu_bo_unreserve(bo); 377 allocate_mem_reserve_bo_failed: 378 amdgpu_bo_unref(&bo); 379 380 return r; 381 } 382 383 void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void **mem_obj) 384 { 385 struct amdgpu_bo **bo = (struct amdgpu_bo **) mem_obj; 386 387 if (!bo || !*bo) 388 return; 389 390 (void)amdgpu_bo_reserve(*bo, true); 391 amdgpu_bo_kunmap(*bo); 392 amdgpu_bo_unpin(*bo); 393 amdgpu_bo_unreserve(*bo); 394 amdgpu_bo_unref(bo); 395 } 396 397 int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size, 398 void **mem_obj) 399 { 400 struct amdgpu_bo *bo = NULL; 401 struct amdgpu_bo_user *ubo; 402 struct amdgpu_bo_param bp; 403 int r; 404 405 memset(&bp, 0, sizeof(bp)); 406 bp.size = size; 407 bp.byte_align = 1; 408 bp.domain = AMDGPU_GEM_DOMAIN_GWS; 409 bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 410 bp.type = ttm_bo_type_device; 411 bp.resv = NULL; 412 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 413 414 r = amdgpu_bo_create_user(adev, &bp, &ubo); 415 if (r) { 416 dev_err(adev->dev, 417 "failed to allocate gws BO for amdkfd (%d)\n", r); 418 return r; 419 } 420 421 bo = &ubo->bo; 422 *mem_obj = bo; 423 return 0; 424 } 425 426 void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj) 427 { 428 struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj; 429 430 amdgpu_bo_unref(&bo); 431 } 432 433 uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev, 434 enum kgd_engine_type type) 435 { 436 switch (type) { 437 case KGD_ENGINE_PFP: 438 return adev->gfx.pfp_fw_version; 439 440 case KGD_ENGINE_ME: 441 return adev->gfx.me_fw_version; 442 443 case KGD_ENGINE_CE: 444 return adev->gfx.ce_fw_version; 445 446 case KGD_ENGINE_MEC1: 447 return adev->gfx.mec_fw_version; 448 449 case KGD_ENGINE_MEC2: 450 return adev->gfx.mec2_fw_version; 451 452 case KGD_ENGINE_RLC: 453 return adev->gfx.rlc_fw_version; 454 455 case KGD_ENGINE_SDMA1: 456 return adev->sdma.instance[0].fw_version; 457 458 case KGD_ENGINE_SDMA2: 459 return adev->sdma.instance[1].fw_version; 460 461 default: 462 return 0; 463 } 464 465 return 0; 466 } 467 468 void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev, 469 struct kfd_local_mem_info *mem_info, 470 struct amdgpu_xcp *xcp) 471 { 472 memset(mem_info, 0, sizeof(*mem_info)); 473 474 if (xcp) { 475 if (adev->gmc.real_vram_size == adev->gmc.visible_vram_size) 476 mem_info->local_mem_size_public = 477 KFD_XCP_MEMORY_SIZE(adev, xcp->id); 478 else 479 mem_info->local_mem_size_private = 480 KFD_XCP_MEMORY_SIZE(adev, xcp->id); 481 } else if (adev->apu_prefer_gtt) { 482 mem_info->local_mem_size_public = (ttm_tt_pages_limit() << PAGE_SHIFT); 483 mem_info->local_mem_size_private = 0; 484 } else { 485 mem_info->local_mem_size_public = adev->gmc.visible_vram_size; 486 mem_info->local_mem_size_private = adev->gmc.real_vram_size - 487 adev->gmc.visible_vram_size; 488 } 489 mem_info->vram_width = adev->gmc.vram_width; 490 491 pr_debug("Address base: %pap public 0x%llx private 0x%llx\n", 492 &adev->gmc.aper_base, 493 mem_info->local_mem_size_public, 494 mem_info->local_mem_size_private); 495 496 if (adev->pm.dpm_enabled) { 497 if (amdgpu_emu_mode == 1) 498 mem_info->mem_clk_max = 0; 499 else 500 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100; 501 } else 502 mem_info->mem_clk_max = 100; 503 } 504 505 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev) 506 { 507 if (adev->gfx.funcs->get_gpu_clock_counter) 508 return adev->gfx.funcs->get_gpu_clock_counter(adev); 509 return 0; 510 } 511 512 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev) 513 { 514 /* the sclk is in quantas of 10kHz */ 515 if (adev->pm.dpm_enabled) 516 return amdgpu_dpm_get_sclk(adev, false) / 100; 517 else 518 return 100; 519 } 520 521 int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, 522 struct amdgpu_device **dmabuf_adev, 523 uint64_t *bo_size, void *metadata_buffer, 524 size_t buffer_size, uint32_t *metadata_size, 525 uint32_t *flags, int8_t *xcp_id) 526 { 527 struct dma_buf *dma_buf; 528 struct drm_gem_object *obj; 529 struct amdgpu_bo *bo; 530 uint64_t metadata_flags; 531 int r = -EINVAL; 532 533 dma_buf = dma_buf_get(dma_buf_fd); 534 if (IS_ERR(dma_buf)) 535 return PTR_ERR(dma_buf); 536 537 if (dma_buf->ops != &amdgpu_dmabuf_ops) 538 /* Can't handle non-graphics buffers */ 539 goto out_put; 540 541 obj = dma_buf->priv; 542 if (obj->dev->driver != adev_to_drm(adev)->driver) 543 /* Can't handle buffers from different drivers */ 544 goto out_put; 545 546 adev = drm_to_adev(obj->dev); 547 bo = gem_to_amdgpu_bo(obj); 548 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM | 549 AMDGPU_GEM_DOMAIN_GTT))) 550 /* Only VRAM and GTT BOs are supported */ 551 goto out_put; 552 553 r = 0; 554 if (dmabuf_adev) 555 *dmabuf_adev = adev; 556 if (bo_size) 557 *bo_size = amdgpu_bo_size(bo); 558 if (metadata_buffer) 559 r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size, 560 metadata_size, &metadata_flags); 561 if (flags) { 562 *flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ? 563 KFD_IOC_ALLOC_MEM_FLAGS_VRAM 564 : KFD_IOC_ALLOC_MEM_FLAGS_GTT; 565 566 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 567 *flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC; 568 } 569 if (xcp_id) 570 *xcp_id = bo->xcp_id; 571 572 out_put: 573 dma_buf_put(dma_buf); 574 return r; 575 } 576 577 int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min) 578 { 579 int num_lanes_shift = (is_min ? ffs(adev->pm.pcie_mlw_mask) : 580 fls(adev->pm.pcie_mlw_mask)) - 1; 581 int gen_speed_shift = (is_min ? ffs(adev->pm.pcie_gen_mask & 582 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) : 583 fls(adev->pm.pcie_gen_mask & 584 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK)) - 1; 585 uint32_t num_lanes_mask = 1 << num_lanes_shift; 586 uint32_t gen_speed_mask = 1 << gen_speed_shift; 587 int num_lanes_factor = 0, gen_speed_mbits_factor = 0; 588 589 switch (num_lanes_mask) { 590 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1: 591 num_lanes_factor = 1; 592 break; 593 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2: 594 num_lanes_factor = 2; 595 break; 596 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4: 597 num_lanes_factor = 4; 598 break; 599 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8: 600 num_lanes_factor = 8; 601 break; 602 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12: 603 num_lanes_factor = 12; 604 break; 605 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16: 606 num_lanes_factor = 16; 607 break; 608 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32: 609 num_lanes_factor = 32; 610 break; 611 } 612 613 switch (gen_speed_mask) { 614 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1: 615 gen_speed_mbits_factor = 2500; 616 break; 617 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2: 618 gen_speed_mbits_factor = 5000; 619 break; 620 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3: 621 gen_speed_mbits_factor = 8000; 622 break; 623 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4: 624 gen_speed_mbits_factor = 16000; 625 break; 626 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5: 627 gen_speed_mbits_factor = 32000; 628 break; 629 } 630 631 return (num_lanes_factor * gen_speed_mbits_factor)/BITS_PER_BYTE; 632 } 633 634 int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, 635 enum kgd_engine_type engine, 636 uint32_t vmid, uint64_t gpu_addr, 637 uint32_t *ib_cmd, uint32_t ib_len) 638 { 639 struct amdgpu_job *job; 640 struct amdgpu_ib *ib; 641 struct amdgpu_ring *ring; 642 struct dma_fence *f = NULL; 643 int ret; 644 645 switch (engine) { 646 case KGD_ENGINE_MEC1: 647 ring = &adev->gfx.compute_ring[0]; 648 break; 649 case KGD_ENGINE_SDMA1: 650 ring = &adev->sdma.instance[0].ring; 651 break; 652 case KGD_ENGINE_SDMA2: 653 ring = &adev->sdma.instance[1].ring; 654 break; 655 default: 656 pr_err("Invalid engine in IB submission: %d\n", engine); 657 ret = -EINVAL; 658 goto err; 659 } 660 661 ret = amdgpu_job_alloc(adev, NULL, NULL, NULL, 1, &job, 0); 662 if (ret) 663 goto err; 664 665 ib = &job->ibs[0]; 666 memset(ib, 0, sizeof(struct amdgpu_ib)); 667 668 ib->gpu_addr = gpu_addr; 669 ib->ptr = ib_cmd; 670 ib->length_dw = ib_len; 671 /* This works for NO_HWS. TODO: need to handle without knowing VMID */ 672 job->vmid = vmid; 673 job->num_ibs = 1; 674 675 ret = amdgpu_ib_schedule(ring, 1, ib, job, &f); 676 677 if (ret) { 678 DRM_ERROR("amdgpu: failed to schedule IB.\n"); 679 goto err_ib_sched; 680 } 681 682 /* Drop the initial kref_init count (see drm_sched_main as example) */ 683 dma_fence_put(f); 684 ret = dma_fence_wait(f, false); 685 686 err_ib_sched: 687 amdgpu_job_free(job); 688 err: 689 return ret; 690 } 691 692 void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle) 693 { 694 enum amd_powergating_state state = idle ? AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE; 695 if ((IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 11 && 696 ((adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK) <= 64)) || 697 (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 12)) { 698 pr_debug("GFXOFF is %s\n", idle ? "enabled" : "disabled"); 699 amdgpu_gfx_off_ctrl(adev, idle); 700 } else if ((IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 9) && 701 (adev->flags & AMD_IS_APU)) { 702 /* Disable GFXOFF and PG. Temporary workaround 703 * to fix some compute applications issue on GFX9. 704 */ 705 struct amdgpu_ip_block *gfx_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); 706 if (gfx_block != NULL) 707 gfx_block->version->funcs->set_powergating_state((void *)gfx_block, state); 708 } 709 amdgpu_dpm_switch_power_profile(adev, 710 PP_SMC_POWER_PROFILE_COMPUTE, 711 !idle); 712 } 713 714 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid) 715 { 716 if (adev->kfd.dev) 717 return vmid >= adev->vm_manager.first_kfd_vmid; 718 719 return false; 720 } 721 722 bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev) 723 { 724 return adev->have_atomics_support; 725 } 726 727 void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev) 728 { 729 amdgpu_device_flush_hdp(adev, NULL); 730 } 731 732 bool amdgpu_amdkfd_is_fed(struct amdgpu_device *adev) 733 { 734 return amdgpu_ras_get_fed_status(adev); 735 } 736 737 void amdgpu_amdkfd_ras_pasid_poison_consumption_handler(struct amdgpu_device *adev, 738 enum amdgpu_ras_block block, uint16_t pasid, 739 pasid_notify pasid_fn, void *data, uint32_t reset) 740 { 741 amdgpu_umc_pasid_poison_handler(adev, block, pasid, pasid_fn, data, reset); 742 } 743 744 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, 745 enum amdgpu_ras_block block, uint32_t reset) 746 { 747 amdgpu_umc_pasid_poison_handler(adev, block, 0, NULL, NULL, reset); 748 } 749 750 int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev, 751 uint32_t *payload) 752 { 753 int ret; 754 755 /* Device or IH ring is not ready so bail. */ 756 ret = amdgpu_ih_wait_on_checkpoint_process_ts(adev, &adev->irq.ih); 757 if (ret) 758 return ret; 759 760 /* Send payload to fence KFD interrupts */ 761 amdgpu_amdkfd_interrupt(adev, payload); 762 763 return 0; 764 } 765 766 int amdgpu_amdkfd_check_and_lock_kfd(struct amdgpu_device *adev) 767 { 768 return kgd2kfd_check_and_lock_kfd(adev->kfd.dev); 769 } 770 771 void amdgpu_amdkfd_unlock_kfd(struct amdgpu_device *adev) 772 { 773 kgd2kfd_unlock_kfd(adev->kfd.dev); 774 } 775 776 777 u64 amdgpu_amdkfd_xcp_memory_size(struct amdgpu_device *adev, int xcp_id) 778 { 779 s8 mem_id = KFD_XCP_MEM_ID(adev, xcp_id); 780 u64 tmp; 781 782 if (adev->gmc.num_mem_partitions && xcp_id >= 0 && mem_id >= 0) { 783 if (adev->gmc.is_app_apu && adev->gmc.num_mem_partitions == 1) { 784 /* In NPS1 mode, we should restrict the vram reporting 785 * tied to the ttm_pages_limit which is 1/2 of the system 786 * memory. For other partition modes, the HBM is uniformly 787 * divided already per numa node reported. If user wants to 788 * go beyond the default ttm limit and maximize the ROCm 789 * allocations, they can go up to max ttm and sysmem limits. 790 */ 791 792 tmp = (ttm_tt_pages_limit() << PAGE_SHIFT) / num_online_nodes(); 793 } else { 794 tmp = adev->gmc.mem_partitions[mem_id].size; 795 } 796 do_div(tmp, adev->xcp_mgr->num_xcp_per_mem_partition); 797 return ALIGN_DOWN(tmp, PAGE_SIZE); 798 } else if (adev->apu_prefer_gtt) { 799 return (ttm_tt_pages_limit() << PAGE_SHIFT); 800 } else { 801 return adev->gmc.real_vram_size; 802 } 803 } 804 805 int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off, 806 u32 inst) 807 { 808 struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst]; 809 struct amdgpu_ring *kiq_ring = &kiq->ring; 810 struct amdgpu_ring_funcs *ring_funcs; 811 struct amdgpu_ring *ring; 812 int r = 0; 813 814 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 815 return -EINVAL; 816 817 if (!kiq_ring->sched.ready || amdgpu_in_reset(adev)) 818 return 0; 819 820 ring_funcs = kzalloc(sizeof(*ring_funcs), GFP_KERNEL); 821 if (!ring_funcs) 822 return -ENOMEM; 823 824 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 825 if (!ring) { 826 r = -ENOMEM; 827 goto free_ring_funcs; 828 } 829 830 ring_funcs->type = AMDGPU_RING_TYPE_COMPUTE; 831 ring->doorbell_index = doorbell_off; 832 ring->funcs = ring_funcs; 833 834 spin_lock(&kiq->ring_lock); 835 836 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 837 spin_unlock(&kiq->ring_lock); 838 r = -ENOMEM; 839 goto free_ring; 840 } 841 842 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 0, 0); 843 844 /* Submit unmap queue packet */ 845 amdgpu_ring_commit(kiq_ring); 846 /* 847 * Ring test will do a basic scratch register change check. Just run 848 * this to ensure that unmap queues that is submitted before got 849 * processed successfully before returning. 850 */ 851 r = amdgpu_ring_test_helper(kiq_ring); 852 853 spin_unlock(&kiq->ring_lock); 854 855 free_ring: 856 kfree(ring); 857 858 free_ring_funcs: 859 kfree(ring_funcs); 860 861 return r; 862 } 863 864 /* Stop scheduling on KFD */ 865 int amdgpu_amdkfd_stop_sched(struct amdgpu_device *adev, uint32_t node_id) 866 { 867 if (!adev->kfd.init_complete) 868 return 0; 869 870 return kgd2kfd_stop_sched(adev->kfd.dev, node_id); 871 } 872 873 /* Start scheduling on KFD */ 874 int amdgpu_amdkfd_start_sched(struct amdgpu_device *adev, uint32_t node_id) 875 { 876 if (!adev->kfd.init_complete) 877 return 0; 878 879 return kgd2kfd_start_sched(adev->kfd.dev, node_id); 880 } 881 882 /* check if there are KFD queues active */ 883 bool amdgpu_amdkfd_compute_active(struct amdgpu_device *adev, uint32_t node_id) 884 { 885 if (!adev->kfd.init_complete) 886 return false; 887 888 return kgd2kfd_compute_active(adev->kfd.dev, node_id); 889 } 890 891 /* Config CGTT_SQ_CLK_CTRL */ 892 int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcp_id, 893 bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable) 894 { 895 int r; 896 897 if (!adev->kfd.init_complete) 898 return 0; 899 900 r = psp_config_sq_perfmon(&adev->psp, xcp_id, core_override_enable, 901 reg_override_enable, perfmon_override_enable); 902 903 return r; 904 } 905