1 /* SPDX-License-Identifier: GPL-2.0 OR MIT 2 * 3 * Copyright 2026 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef __AMDGPU_ACPI_H__ 24 #define __AMDGPU_ACPI_H__ 25 26 #include <linux/types.h> 27 #include <linux/mutex_types.h> 28 29 struct amdgpu_device; 30 struct acpi_device; 31 struct amdgpu_dm_backlight_caps; 32 33 #define MAX_UMA_OPTION_NAME 28 34 #define MAX_UMA_OPTION_ENTRIES 19 35 36 #define AMDGPU_UMA_FLAG_AUTO BIT(1) 37 #define AMDGPU_UMA_FLAG_CUSTOM BIT(0) 38 39 /* ATCS Device/Driver State */ 40 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 41 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 42 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 43 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 44 45 enum amdgpu_ss { 46 AMDGPU_SS_DRV_LOAD, 47 AMDGPU_SS_DEV_D0, 48 AMDGPU_SS_DEV_D3, 49 AMDGPU_SS_DRV_UNLOAD 50 }; 51 52 /** 53 * struct amdgpu_uma_carveout_option - single UMA carveout option 54 * @name: Name of the carveout option 55 * @memory_carved_mb: Amount of memory carved in MB 56 * @flags: ATCS flags supported by this option 57 */ 58 struct amdgpu_uma_carveout_option { 59 char name[MAX_UMA_OPTION_NAME]; 60 uint32_t memory_carved_mb; 61 uint8_t flags; 62 }; 63 64 /** 65 * struct amdgpu_uma_carveout_info - table of available UMA carveout options 66 * @num_entries: Number of available options 67 * @uma_option_index: The index of the option currently applied 68 * @update_lock: Lock to serialize changes to the option 69 * @entries: The array of carveout options 70 */ 71 struct amdgpu_uma_carveout_info { 72 uint8_t num_entries; 73 uint8_t uma_option_index; 74 struct mutex update_lock; 75 struct amdgpu_uma_carveout_option entries[MAX_UMA_OPTION_ENTRIES]; 76 }; 77 78 struct amdgpu_numa_info { 79 uint64_t size; 80 int pxm; 81 int nid; 82 }; 83 84 #if defined(CONFIG_ACPI) 85 int amdgpu_acpi_init(struct amdgpu_device *adev); 86 void amdgpu_acpi_fini(struct amdgpu_device *adev); 87 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 88 bool amdgpu_acpi_is_power_shift_control_supported(void); 89 bool amdgpu_acpi_is_set_uma_allocation_size_supported(void); 90 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 91 u8 perf_req, bool advertise); 92 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 93 u8 dev_state, bool drv_state); 94 int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev, 95 enum amdgpu_ss ss_state); 96 int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type); 97 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 98 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, 99 u64 *tmr_size); 100 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, 101 struct amdgpu_numa_info *numa_info); 102 103 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 104 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 105 void amdgpu_acpi_detect(void); 106 void amdgpu_acpi_release(void); 107 #else 108 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 109 static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, 110 u64 *tmr_offset, u64 *tmr_size) 111 { 112 return -EINVAL; 113 } 114 static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, 115 int xcc_id, 116 struct amdgpu_numa_info *numa_info) 117 { 118 return -EINVAL; 119 } 120 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 121 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 122 static inline void amdgpu_acpi_detect(void) { } 123 static inline void amdgpu_acpi_release(void) { } 124 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 125 static inline bool amdgpu_acpi_is_set_uma_allocation_size_supported(void) { return false; } 126 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 127 u8 dev_state, bool drv_state) { return 0; } 128 static inline int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev, 129 enum amdgpu_ss ss_state) 130 { 131 return 0; 132 } 133 static inline int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type) 134 { 135 return -EINVAL; 136 } 137 static inline void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps) { } 138 #endif 139 140 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 141 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 142 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 143 #else 144 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 145 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 146 #endif 147 148 #if defined(CONFIG_DRM_AMD_ISP) 149 int amdgpu_acpi_get_isp4_dev(struct acpi_device **dev); 150 #endif 151 #endif /* __AMDGPU_ACPI_H__ */ 152