1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/irqdomain.h> 27 #include <linux/pci.h> 28 #include <linux/pm_domain.h> 29 #include <linux/platform_device.h> 30 #include <sound/designware_i2s.h> 31 #include <sound/pcm.h> 32 #include <linux/acpi.h> 33 #include <linux/dmi.h> 34 35 #include "amdgpu.h" 36 #include "atom.h" 37 #include "amdgpu_acp.h" 38 39 #include "acp_gfx_if.h" 40 41 #define ST_JADEITE 1 42 #define ACP_TILE_ON_MASK 0x03 43 #define ACP_TILE_OFF_MASK 0x02 44 #define ACP_TILE_ON_RETAIN_REG_MASK 0x1f 45 #define ACP_TILE_OFF_RETAIN_REG_MASK 0x20 46 47 #define ACP_TILE_P1_MASK 0x3e 48 #define ACP_TILE_P2_MASK 0x3d 49 #define ACP_TILE_DSP0_MASK 0x3b 50 #define ACP_TILE_DSP1_MASK 0x37 51 52 #define ACP_TILE_DSP2_MASK 0x2f 53 54 #define ACP_DMA_REGS_END 0x146c0 55 #define ACP_I2S_PLAY_REGS_START 0x14840 56 #define ACP_I2S_PLAY_REGS_END 0x148b4 57 #define ACP_I2S_CAP_REGS_START 0x148b8 58 #define ACP_I2S_CAP_REGS_END 0x1496c 59 60 #define ACP_I2S_COMP1_CAP_REG_OFFSET 0xac 61 #define ACP_I2S_COMP2_CAP_REG_OFFSET 0xa8 62 #define ACP_I2S_COMP1_PLAY_REG_OFFSET 0x6c 63 #define ACP_I2S_COMP2_PLAY_REG_OFFSET 0x68 64 #define ACP_BT_PLAY_REGS_START 0x14970 65 #define ACP_BT_PLAY_REGS_END 0x14a24 66 #define ACP_BT_COMP1_REG_OFFSET 0xac 67 #define ACP_BT_COMP2_REG_OFFSET 0xa8 68 69 #define mmACP_PGFSM_RETAIN_REG 0x51c9 70 #define mmACP_PGFSM_CONFIG_REG 0x51ca 71 #define mmACP_PGFSM_READ_REG_0 0x51cc 72 73 #define mmACP_MEM_SHUT_DOWN_REQ_LO 0x51f8 74 #define mmACP_MEM_SHUT_DOWN_REQ_HI 0x51f9 75 #define mmACP_MEM_SHUT_DOWN_STS_LO 0x51fa 76 #define mmACP_MEM_SHUT_DOWN_STS_HI 0x51fb 77 78 #define mmACP_CONTROL 0x5131 79 #define mmACP_STATUS 0x5133 80 #define mmACP_SOFT_RESET 0x5134 81 #define ACP_CONTROL__ClkEn_MASK 0x1 82 #define ACP_SOFT_RESET__SoftResetAud_MASK 0x100 83 #define ACP_SOFT_RESET__SoftResetAudDone_MASK 0x1000000 84 #define ACP_CLOCK_EN_TIME_OUT_VALUE 0x000000FF 85 #define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE 0x000000FF 86 87 #define ACP_TIMEOUT_LOOP 0x000000FF 88 #define ACP_DEVS 4 89 #define ACP_SRC_ID 162 90 91 static unsigned long acp_machine_id; 92 93 enum { 94 ACP_TILE_P1 = 0, 95 ACP_TILE_P2, 96 ACP_TILE_DSP0, 97 ACP_TILE_DSP1, 98 ACP_TILE_DSP2, 99 }; 100 101 static int acp_sw_init(struct amdgpu_ip_block *ip_block) 102 { 103 struct amdgpu_device *adev = ip_block->adev; 104 105 adev->acp.parent = adev->dev; 106 107 adev->acp.cgs_device = 108 amdgpu_cgs_create_device(adev); 109 if (!adev->acp.cgs_device) 110 return -EINVAL; 111 112 return 0; 113 } 114 115 static int acp_sw_fini(struct amdgpu_ip_block *ip_block) 116 { 117 struct amdgpu_device *adev = ip_block->adev; 118 119 if (adev->acp.cgs_device) 120 amdgpu_cgs_destroy_device(adev->acp.cgs_device); 121 122 return 0; 123 } 124 125 struct acp_pm_domain { 126 void *adev; 127 struct generic_pm_domain gpd; 128 }; 129 130 static int acp_poweroff(struct generic_pm_domain *genpd) 131 { 132 struct acp_pm_domain *apd; 133 struct amdgpu_device *adev; 134 135 apd = container_of(genpd, struct acp_pm_domain, gpd); 136 adev = apd->adev; 137 /* call smu to POWER GATE ACP block 138 * smu will 139 * 1. turn off the acp clock 140 * 2. power off the acp tiles 141 * 3. check and enter ulv state 142 */ 143 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true, 0); 144 return 0; 145 } 146 147 static int acp_poweron(struct generic_pm_domain *genpd) 148 { 149 struct acp_pm_domain *apd; 150 struct amdgpu_device *adev; 151 152 apd = container_of(genpd, struct acp_pm_domain, gpd); 153 adev = apd->adev; 154 /* call smu to UNGATE ACP block 155 * smu will 156 * 1. exit ulv 157 * 2. turn on acp clock 158 * 3. power on acp tiles 159 */ 160 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false, 0); 161 return 0; 162 } 163 164 static int acp_genpd_add_device(struct device *dev, void *data) 165 { 166 struct generic_pm_domain *gpd = data; 167 int ret; 168 169 ret = pm_genpd_add_device(gpd, dev); 170 if (ret) 171 dev_err(dev, "Failed to add dev to genpd %d\n", ret); 172 173 return ret; 174 } 175 176 static int acp_genpd_remove_device(struct device *dev, void *data) 177 { 178 int ret; 179 180 ret = pm_genpd_remove_device(dev); 181 if (ret) 182 dev_err(dev, "Failed to remove dev from genpd %d\n", ret); 183 184 /* Continue to remove */ 185 return 0; 186 } 187 188 static int acp_quirk_cb(const struct dmi_system_id *id) 189 { 190 acp_machine_id = ST_JADEITE; 191 return 1; 192 } 193 194 static const struct dmi_system_id acp_quirk_table[] = { 195 { 196 .callback = acp_quirk_cb, 197 .matches = { 198 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMD"), 199 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Jadeite"), 200 } 201 }, 202 { 203 .callback = acp_quirk_cb, 204 .matches = { 205 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "IP3 Technology CO.,Ltd."), 206 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "ASN1D"), 207 }, 208 }, 209 { 210 .callback = acp_quirk_cb, 211 .matches = { 212 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "Standard"), 213 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "ASN10"), 214 }, 215 }, 216 {} 217 }; 218 219 /** 220 * acp_hw_init - start and test ACP block 221 * 222 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 223 * 224 */ 225 static int acp_hw_init(struct amdgpu_ip_block *ip_block) 226 { 227 int r; 228 u64 acp_base; 229 u32 val = 0; 230 u32 count = 0; 231 struct i2s_platform_data *i2s_pdata = NULL; 232 233 struct amdgpu_device *adev = ip_block->adev; 234 235 r = amd_acp_hw_init(adev->acp.cgs_device, 236 ip_block->version->major, ip_block->version->minor); 237 /* -ENODEV means board uses AZ rather than ACP */ 238 if (r == -ENODEV) { 239 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true, 0); 240 return 0; 241 } else if (r) { 242 return r; 243 } 244 245 if (adev->rmmio_size == 0 || adev->rmmio_size < 0x5289) 246 return -EINVAL; 247 248 acp_base = adev->rmmio_base; 249 adev->acp.acp_genpd = kzalloc_obj(struct acp_pm_domain); 250 if (!adev->acp.acp_genpd) 251 return -ENOMEM; 252 253 adev->acp.acp_genpd->gpd.name = "ACP_AUDIO"; 254 adev->acp.acp_genpd->gpd.power_off = acp_poweroff; 255 adev->acp.acp_genpd->gpd.power_on = acp_poweron; 256 adev->acp.acp_genpd->adev = adev; 257 258 pm_genpd_init(&adev->acp.acp_genpd->gpd, NULL, false); 259 dmi_check_system(acp_quirk_table); 260 switch (acp_machine_id) { 261 case ST_JADEITE: 262 { 263 adev->acp.acp_cell = kzalloc_objs(struct mfd_cell, 2); 264 if (!adev->acp.acp_cell) { 265 r = -ENOMEM; 266 goto failure; 267 } 268 269 adev->acp.acp_res = kzalloc_objs(struct resource, 3); 270 if (!adev->acp.acp_res) { 271 r = -ENOMEM; 272 goto failure; 273 } 274 275 i2s_pdata = kzalloc_objs(struct i2s_platform_data, 1); 276 if (!i2s_pdata) { 277 r = -ENOMEM; 278 goto failure; 279 } 280 281 i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | 282 DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; 283 i2s_pdata[0].cap = DWC_I2S_PLAY | DWC_I2S_RECORD; 284 i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000; 285 i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET; 286 i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET; 287 288 adev->acp.acp_res[0].name = "acp2x_dma"; 289 adev->acp.acp_res[0].flags = IORESOURCE_MEM; 290 adev->acp.acp_res[0].start = acp_base; 291 adev->acp.acp_res[0].end = acp_base + ACP_DMA_REGS_END; 292 293 adev->acp.acp_res[1].name = "acp2x_dw_i2s_play_cap"; 294 adev->acp.acp_res[1].flags = IORESOURCE_MEM; 295 adev->acp.acp_res[1].start = acp_base + ACP_I2S_CAP_REGS_START; 296 adev->acp.acp_res[1].end = acp_base + ACP_I2S_CAP_REGS_END; 297 298 adev->acp.acp_res[2].name = "acp2x_dma_irq"; 299 adev->acp.acp_res[2].flags = IORESOURCE_IRQ; 300 adev->acp.acp_res[2].start = amdgpu_irq_create_mapping(adev, 162); 301 adev->acp.acp_res[2].end = adev->acp.acp_res[2].start; 302 303 adev->acp.acp_cell[0].name = "acp_audio_dma"; 304 adev->acp.acp_cell[0].id = 0; 305 adev->acp.acp_cell[0].num_resources = 3; 306 adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0]; 307 adev->acp.acp_cell[0].platform_data = &adev->asic_type; 308 adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type); 309 310 adev->acp.acp_cell[1].name = "designware-i2s"; 311 adev->acp.acp_cell[1].id = 1; 312 adev->acp.acp_cell[1].num_resources = 1; 313 adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1]; 314 adev->acp.acp_cell[1].platform_data = &i2s_pdata[0]; 315 adev->acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data); 316 r = mfd_add_devices(adev->acp.parent, 0, adev->acp.acp_cell, 2, NULL, 0, NULL); 317 if (r) 318 goto failure; 319 r = device_for_each_child(adev->acp.parent, &adev->acp.acp_genpd->gpd, 320 acp_genpd_add_device); 321 if (r) 322 goto failure; 323 break; 324 } 325 default: 326 adev->acp.acp_cell = kzalloc_objs(struct mfd_cell, ACP_DEVS); 327 328 if (!adev->acp.acp_cell) { 329 r = -ENOMEM; 330 goto failure; 331 } 332 333 adev->acp.acp_res = kzalloc_objs(struct resource, 5); 334 if (!adev->acp.acp_res) { 335 r = -ENOMEM; 336 goto failure; 337 } 338 339 i2s_pdata = kzalloc_objs(struct i2s_platform_data, 3); 340 if (!i2s_pdata) { 341 r = -ENOMEM; 342 goto failure; 343 } 344 345 switch (adev->asic_type) { 346 case CHIP_STONEY: 347 i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | 348 DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; 349 break; 350 default: 351 i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET; 352 } 353 i2s_pdata[0].cap = DWC_I2S_PLAY; 354 i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000; 355 i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET; 356 i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET; 357 switch (adev->asic_type) { 358 case CHIP_STONEY: 359 i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | 360 DW_I2S_QUIRK_COMP_PARAM1 | 361 DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; 362 break; 363 default: 364 i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | 365 DW_I2S_QUIRK_COMP_PARAM1; 366 } 367 368 i2s_pdata[1].cap = DWC_I2S_RECORD; 369 i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000; 370 i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET; 371 i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET; 372 373 i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET; 374 switch (adev->asic_type) { 375 case CHIP_STONEY: 376 i2s_pdata[2].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; 377 break; 378 default: 379 break; 380 } 381 382 i2s_pdata[2].cap = DWC_I2S_PLAY | DWC_I2S_RECORD; 383 i2s_pdata[2].snd_rates = SNDRV_PCM_RATE_8000_96000; 384 i2s_pdata[2].i2s_reg_comp1 = ACP_BT_COMP1_REG_OFFSET; 385 i2s_pdata[2].i2s_reg_comp2 = ACP_BT_COMP2_REG_OFFSET; 386 387 adev->acp.acp_res[0].name = "acp2x_dma"; 388 adev->acp.acp_res[0].flags = IORESOURCE_MEM; 389 adev->acp.acp_res[0].start = acp_base; 390 adev->acp.acp_res[0].end = acp_base + ACP_DMA_REGS_END; 391 392 adev->acp.acp_res[1].name = "acp2x_dw_i2s_play"; 393 adev->acp.acp_res[1].flags = IORESOURCE_MEM; 394 adev->acp.acp_res[1].start = acp_base + ACP_I2S_PLAY_REGS_START; 395 adev->acp.acp_res[1].end = acp_base + ACP_I2S_PLAY_REGS_END; 396 397 adev->acp.acp_res[2].name = "acp2x_dw_i2s_cap"; 398 adev->acp.acp_res[2].flags = IORESOURCE_MEM; 399 adev->acp.acp_res[2].start = acp_base + ACP_I2S_CAP_REGS_START; 400 adev->acp.acp_res[2].end = acp_base + ACP_I2S_CAP_REGS_END; 401 402 adev->acp.acp_res[3].name = "acp2x_dw_bt_i2s_play_cap"; 403 adev->acp.acp_res[3].flags = IORESOURCE_MEM; 404 adev->acp.acp_res[3].start = acp_base + ACP_BT_PLAY_REGS_START; 405 adev->acp.acp_res[3].end = acp_base + ACP_BT_PLAY_REGS_END; 406 407 adev->acp.acp_res[4].name = "acp2x_dma_irq"; 408 adev->acp.acp_res[4].flags = IORESOURCE_IRQ; 409 adev->acp.acp_res[4].start = amdgpu_irq_create_mapping(adev, 162); 410 adev->acp.acp_res[4].end = adev->acp.acp_res[4].start; 411 412 adev->acp.acp_cell[0].name = "acp_audio_dma"; 413 adev->acp.acp_cell[0].id = 0; 414 adev->acp.acp_cell[0].num_resources = 5; 415 adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0]; 416 adev->acp.acp_cell[0].platform_data = &adev->asic_type; 417 adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type); 418 419 adev->acp.acp_cell[1].name = "designware-i2s"; 420 adev->acp.acp_cell[1].id = 1; 421 adev->acp.acp_cell[1].num_resources = 1; 422 adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1]; 423 adev->acp.acp_cell[1].platform_data = &i2s_pdata[0]; 424 adev->acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data); 425 426 adev->acp.acp_cell[2].name = "designware-i2s"; 427 adev->acp.acp_cell[2].id = 2; 428 adev->acp.acp_cell[2].num_resources = 1; 429 adev->acp.acp_cell[2].resources = &adev->acp.acp_res[2]; 430 adev->acp.acp_cell[2].platform_data = &i2s_pdata[1]; 431 adev->acp.acp_cell[2].pdata_size = sizeof(struct i2s_platform_data); 432 433 adev->acp.acp_cell[3].name = "designware-i2s"; 434 adev->acp.acp_cell[3].id = 3; 435 adev->acp.acp_cell[3].num_resources = 1; 436 adev->acp.acp_cell[3].resources = &adev->acp.acp_res[3]; 437 adev->acp.acp_cell[3].platform_data = &i2s_pdata[2]; 438 adev->acp.acp_cell[3].pdata_size = sizeof(struct i2s_platform_data); 439 440 r = mfd_add_devices(adev->acp.parent, 0, adev->acp.acp_cell, ACP_DEVS, NULL, 0, NULL); 441 if (r) 442 goto failure; 443 444 r = device_for_each_child(adev->acp.parent, &adev->acp.acp_genpd->gpd, 445 acp_genpd_add_device); 446 if (r) 447 goto failure; 448 } 449 450 /* Assert Soft reset of ACP */ 451 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 452 453 val |= ACP_SOFT_RESET__SoftResetAud_MASK; 454 cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val); 455 456 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 457 while (true) { 458 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 459 if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 460 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 461 break; 462 if (--count == 0) { 463 dev_err(&adev->pdev->dev, "Failed to reset ACP\n"); 464 r = -ETIMEDOUT; 465 goto failure; 466 } 467 udelay(100); 468 } 469 /* Enable clock to ACP and wait until the clock is enabled */ 470 val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL); 471 val = val | ACP_CONTROL__ClkEn_MASK; 472 cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val); 473 474 count = ACP_CLOCK_EN_TIME_OUT_VALUE; 475 476 while (true) { 477 val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS); 478 if (val & (u32) 0x1) 479 break; 480 if (--count == 0) { 481 dev_err(&adev->pdev->dev, "Failed to reset ACP\n"); 482 r = -ETIMEDOUT; 483 goto failure; 484 } 485 udelay(100); 486 } 487 /* Deassert the SOFT RESET flags */ 488 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 489 val &= ~ACP_SOFT_RESET__SoftResetAud_MASK; 490 cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val); 491 return 0; 492 493 failure: 494 kfree(i2s_pdata); 495 kfree(adev->acp.acp_res); 496 kfree(adev->acp.acp_cell); 497 kfree(adev->acp.acp_genpd); 498 return r; 499 } 500 501 /** 502 * acp_hw_fini - stop the hardware block 503 * 504 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 505 * 506 */ 507 static int acp_hw_fini(struct amdgpu_ip_block *ip_block) 508 { 509 u32 val = 0; 510 u32 count = 0; 511 struct amdgpu_device *adev = ip_block->adev; 512 513 /* return early if no ACP */ 514 if (!adev->acp.acp_genpd) { 515 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false, 0); 516 return 0; 517 } 518 519 /* Assert Soft reset of ACP */ 520 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 521 522 val |= ACP_SOFT_RESET__SoftResetAud_MASK; 523 cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val); 524 525 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 526 while (true) { 527 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 528 if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 529 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 530 break; 531 if (--count == 0) { 532 dev_err(&adev->pdev->dev, "Failed to reset ACP\n"); 533 return -ETIMEDOUT; 534 } 535 udelay(100); 536 } 537 /* Disable ACP clock */ 538 val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL); 539 val &= ~ACP_CONTROL__ClkEn_MASK; 540 cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val); 541 542 count = ACP_CLOCK_EN_TIME_OUT_VALUE; 543 544 while (true) { 545 val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS); 546 if (val & (u32) 0x1) 547 break; 548 if (--count == 0) { 549 dev_err(&adev->pdev->dev, "Failed to reset ACP\n"); 550 return -ETIMEDOUT; 551 } 552 udelay(100); 553 } 554 555 device_for_each_child(adev->acp.parent, NULL, 556 acp_genpd_remove_device); 557 558 mfd_remove_devices(adev->acp.parent); 559 kfree(adev->acp.acp_res); 560 kfree(adev->acp.acp_genpd); 561 kfree(adev->acp.acp_cell); 562 563 return 0; 564 } 565 566 static int acp_suspend(struct amdgpu_ip_block *ip_block) 567 { 568 struct amdgpu_device *adev = ip_block->adev; 569 570 /* power up on suspend */ 571 if (!adev->acp.acp_cell) 572 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false, 0); 573 return 0; 574 } 575 576 static int acp_resume(struct amdgpu_ip_block *ip_block) 577 { 578 struct amdgpu_device *adev = ip_block->adev; 579 580 /* power down again on resume */ 581 if (!adev->acp.acp_cell) 582 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true, 0); 583 return 0; 584 } 585 586 static bool acp_is_idle(struct amdgpu_ip_block *ip_block) 587 { 588 return true; 589 } 590 591 static int acp_set_clockgating_state(struct amdgpu_ip_block *ip_block, 592 enum amd_clockgating_state state) 593 { 594 return 0; 595 } 596 597 static int acp_set_powergating_state(struct amdgpu_ip_block *ip_block, 598 enum amd_powergating_state state) 599 { 600 struct amdgpu_device *adev = ip_block->adev; 601 bool enable = (state == AMD_PG_STATE_GATE); 602 603 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable, 0); 604 605 return 0; 606 } 607 608 static const struct amd_ip_funcs acp_ip_funcs = { 609 .name = "acp_ip", 610 .sw_init = acp_sw_init, 611 .sw_fini = acp_sw_fini, 612 .hw_init = acp_hw_init, 613 .hw_fini = acp_hw_fini, 614 .suspend = acp_suspend, 615 .resume = acp_resume, 616 .is_idle = acp_is_idle, 617 .set_clockgating_state = acp_set_clockgating_state, 618 .set_powergating_state = acp_set_powergating_state, 619 }; 620 621 const struct amdgpu_ip_block_version acp_ip_block = { 622 .type = AMD_IP_BLOCK_TYPE_ACP, 623 .major = 2, 624 .minor = 2, 625 .rev = 0, 626 .funcs = &acp_ip_funcs, 627 }; 628