1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/list.h> 25 #include "amdgpu.h" 26 #include "amdgpu_aca.h" 27 #include "amdgpu_ras.h" 28 29 #define ACA_BANK_HWID(type, hwid, mcatype) [ACA_HWIP_TYPE_##type] = {hwid, mcatype} 30 31 typedef int bank_handler_t(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type, void *data); 32 33 static struct aca_hwip aca_hwid_mcatypes[ACA_HWIP_TYPE_COUNT] = { 34 ACA_BANK_HWID(SMU, 0x01, 0x01), 35 ACA_BANK_HWID(PCS_XGMI, 0x50, 0x00), 36 ACA_BANK_HWID(UMC, 0x96, 0x00), 37 }; 38 39 static void aca_banks_init(struct aca_banks *banks) 40 { 41 if (!banks) 42 return; 43 44 memset(banks, 0, sizeof(*banks)); 45 INIT_LIST_HEAD(&banks->list); 46 } 47 48 static int aca_banks_add_bank(struct aca_banks *banks, struct aca_bank *bank) 49 { 50 struct aca_bank_node *node; 51 52 if (!bank) 53 return -EINVAL; 54 55 node = kvzalloc(sizeof(*node), GFP_KERNEL); 56 if (!node) 57 return -ENOMEM; 58 59 memcpy(&node->bank, bank, sizeof(*bank)); 60 61 INIT_LIST_HEAD(&node->node); 62 list_add_tail(&node->node, &banks->list); 63 64 banks->nr_banks++; 65 66 return 0; 67 } 68 69 static void aca_banks_release(struct aca_banks *banks) 70 { 71 struct aca_bank_node *node, *tmp; 72 73 if (list_empty(&banks->list)) 74 return; 75 76 list_for_each_entry_safe(node, tmp, &banks->list, node) { 77 list_del(&node->node); 78 kvfree(node); 79 } 80 } 81 82 static int aca_smu_get_valid_aca_count(struct amdgpu_device *adev, enum aca_smu_type type, u32 *count) 83 { 84 struct amdgpu_aca *aca = &adev->aca; 85 const struct aca_smu_funcs *smu_funcs = aca->smu_funcs; 86 87 if (!count) 88 return -EINVAL; 89 90 if (!smu_funcs || !smu_funcs->get_valid_aca_count) 91 return -EOPNOTSUPP; 92 93 return smu_funcs->get_valid_aca_count(adev, type, count); 94 } 95 96 static struct aca_regs_dump { 97 const char *name; 98 int reg_idx; 99 } aca_regs[] = { 100 {"CONTROL", ACA_REG_IDX_CTL}, 101 {"STATUS", ACA_REG_IDX_STATUS}, 102 {"ADDR", ACA_REG_IDX_ADDR}, 103 {"MISC", ACA_REG_IDX_MISC0}, 104 {"CONFIG", ACA_REG_IDX_CONFIG}, 105 {"IPID", ACA_REG_IDX_IPID}, 106 {"SYND", ACA_REG_IDX_SYND}, 107 {"DESTAT", ACA_REG_IDX_DESTAT}, 108 {"DEADDR", ACA_REG_IDX_DEADDR}, 109 {"CONTROL_MASK", ACA_REG_IDX_CTL_MASK}, 110 }; 111 112 static void aca_smu_bank_dump(struct amdgpu_device *adev, int idx, int total, struct aca_bank *bank, 113 struct ras_query_context *qctx) 114 { 115 u64 event_id = qctx ? qctx->evid.event_id : RAS_EVENT_INVALID_ID; 116 int i; 117 118 RAS_EVENT_LOG(adev, event_id, HW_ERR "Accelerator Check Architecture events logged\n"); 119 /* plus 1 for output format, e.g: ACA[08/08]: xxxx */ 120 for (i = 0; i < ARRAY_SIZE(aca_regs); i++) 121 RAS_EVENT_LOG(adev, event_id, HW_ERR "ACA[%02d/%02d].%s=0x%016llx\n", 122 idx + 1, total, aca_regs[i].name, bank->regs[aca_regs[i].reg_idx]); 123 } 124 125 static int aca_smu_get_valid_aca_banks(struct amdgpu_device *adev, enum aca_smu_type type, 126 int start, int count, 127 struct aca_banks *banks, struct ras_query_context *qctx) 128 { 129 struct amdgpu_aca *aca = &adev->aca; 130 const struct aca_smu_funcs *smu_funcs = aca->smu_funcs; 131 struct aca_bank bank; 132 int i, max_count, ret; 133 134 if (!count) 135 return 0; 136 137 if (!smu_funcs || !smu_funcs->get_valid_aca_bank) 138 return -EOPNOTSUPP; 139 140 switch (type) { 141 case ACA_SMU_TYPE_UE: 142 max_count = smu_funcs->max_ue_bank_count; 143 break; 144 case ACA_SMU_TYPE_CE: 145 max_count = smu_funcs->max_ce_bank_count; 146 break; 147 default: 148 return -EINVAL; 149 } 150 151 if (start + count > max_count) 152 return -EINVAL; 153 154 count = min_t(int, count, max_count); 155 for (i = 0; i < count; i++) { 156 memset(&bank, 0, sizeof(bank)); 157 ret = smu_funcs->get_valid_aca_bank(adev, type, start + i, &bank); 158 if (ret) 159 return ret; 160 161 bank.smu_err_type = type; 162 163 aca_smu_bank_dump(adev, i, count, &bank, qctx); 164 165 ret = aca_banks_add_bank(banks, &bank); 166 if (ret) 167 return ret; 168 } 169 170 return 0; 171 } 172 173 static bool aca_bank_hwip_is_matched(struct aca_bank *bank, enum aca_hwip_type type) 174 { 175 176 struct aca_hwip *hwip; 177 int hwid, mcatype; 178 u64 ipid; 179 180 if (!bank || type == ACA_HWIP_TYPE_UNKNOW) 181 return false; 182 183 hwip = &aca_hwid_mcatypes[type]; 184 if (!hwip->hwid) 185 return false; 186 187 ipid = bank->regs[ACA_REG_IDX_IPID]; 188 hwid = ACA_REG__IPID__HARDWAREID(ipid); 189 mcatype = ACA_REG__IPID__MCATYPE(ipid); 190 191 return hwip->hwid == hwid && hwip->mcatype == mcatype; 192 } 193 194 static bool aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type) 195 { 196 const struct aca_bank_ops *bank_ops = handle->bank_ops; 197 198 if (!aca_bank_hwip_is_matched(bank, handle->hwip)) 199 return false; 200 201 if (!bank_ops->aca_bank_is_valid) 202 return true; 203 204 return bank_ops->aca_bank_is_valid(handle, bank, type, handle->data); 205 } 206 207 static struct aca_bank_error *new_bank_error(struct aca_error *aerr, struct aca_bank_info *info) 208 { 209 struct aca_bank_error *bank_error; 210 211 bank_error = kvzalloc(sizeof(*bank_error), GFP_KERNEL); 212 if (!bank_error) 213 return NULL; 214 215 INIT_LIST_HEAD(&bank_error->node); 216 memcpy(&bank_error->info, info, sizeof(*info)); 217 218 mutex_lock(&aerr->lock); 219 list_add_tail(&bank_error->node, &aerr->list); 220 mutex_unlock(&aerr->lock); 221 222 return bank_error; 223 } 224 225 static struct aca_bank_error *find_bank_error(struct aca_error *aerr, struct aca_bank_info *info) 226 { 227 struct aca_bank_error *bank_error = NULL; 228 struct aca_bank_info *tmp_info; 229 bool found = false; 230 231 mutex_lock(&aerr->lock); 232 list_for_each_entry(bank_error, &aerr->list, node) { 233 tmp_info = &bank_error->info; 234 if (tmp_info->socket_id == info->socket_id && 235 tmp_info->die_id == info->die_id) { 236 found = true; 237 goto out_unlock; 238 } 239 } 240 241 out_unlock: 242 mutex_unlock(&aerr->lock); 243 244 return found ? bank_error : NULL; 245 } 246 247 static void aca_bank_error_remove(struct aca_error *aerr, struct aca_bank_error *bank_error) 248 { 249 if (!aerr || !bank_error) 250 return; 251 252 list_del(&bank_error->node); 253 aerr->nr_errors--; 254 255 kvfree(bank_error); 256 } 257 258 static struct aca_bank_error *get_bank_error(struct aca_error *aerr, struct aca_bank_info *info) 259 { 260 struct aca_bank_error *bank_error; 261 262 if (!aerr || !info) 263 return NULL; 264 265 bank_error = find_bank_error(aerr, info); 266 if (bank_error) 267 return bank_error; 268 269 return new_bank_error(aerr, info); 270 } 271 272 int aca_error_cache_log_bank_error(struct aca_handle *handle, struct aca_bank_info *info, 273 enum aca_error_type type, u64 count) 274 { 275 struct aca_error_cache *error_cache = &handle->error_cache; 276 struct aca_bank_error *bank_error; 277 struct aca_error *aerr; 278 279 if (!handle || !info || type >= ACA_ERROR_TYPE_COUNT) 280 return -EINVAL; 281 282 if (!count) 283 return 0; 284 285 aerr = &error_cache->errors[type]; 286 bank_error = get_bank_error(aerr, info); 287 if (!bank_error) 288 return -ENOMEM; 289 290 bank_error->count += count; 291 292 return 0; 293 } 294 295 static int aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type) 296 { 297 const struct aca_bank_ops *bank_ops = handle->bank_ops; 298 299 if (!bank) 300 return -EINVAL; 301 302 if (!bank_ops->aca_bank_parser) 303 return -EOPNOTSUPP; 304 305 return bank_ops->aca_bank_parser(handle, bank, type, 306 handle->data); 307 } 308 309 static int handler_aca_log_bank_error(struct aca_handle *handle, struct aca_bank *bank, 310 enum aca_smu_type type, void *data) 311 { 312 int ret; 313 314 ret = aca_bank_parser(handle, bank, type); 315 if (ret) 316 return ret; 317 318 return 0; 319 } 320 321 static int aca_dispatch_bank(struct aca_handle_manager *mgr, struct aca_bank *bank, 322 enum aca_smu_type type, bank_handler_t handler, void *data) 323 { 324 struct aca_handle *handle; 325 int ret; 326 327 if (list_empty(&mgr->list)) 328 return 0; 329 330 list_for_each_entry(handle, &mgr->list, node) { 331 if (!aca_bank_is_valid(handle, bank, type)) 332 continue; 333 334 ret = handler(handle, bank, type, data); 335 if (ret) 336 return ret; 337 } 338 339 return 0; 340 } 341 342 static int aca_dispatch_banks(struct aca_handle_manager *mgr, struct aca_banks *banks, 343 enum aca_smu_type type, bank_handler_t handler, void *data) 344 { 345 struct aca_bank_node *node; 346 struct aca_bank *bank; 347 int ret; 348 349 if (!mgr || !banks) 350 return -EINVAL; 351 352 /* pre check to avoid unnecessary operations */ 353 if (list_empty(&mgr->list) || list_empty(&banks->list)) 354 return 0; 355 356 list_for_each_entry(node, &banks->list, node) { 357 bank = &node->bank; 358 359 ret = aca_dispatch_bank(mgr, bank, type, handler, data); 360 if (ret) 361 return ret; 362 } 363 364 return 0; 365 } 366 367 static bool aca_bank_should_update(struct amdgpu_device *adev, enum aca_smu_type type) 368 { 369 struct amdgpu_aca *aca = &adev->aca; 370 bool ret = true; 371 372 /* 373 * Because the UE Valid MCA count will only be cleared after reset, 374 * in order to avoid repeated counting of the error count, 375 * the aca bank is only updated once during the gpu recovery stage. 376 */ 377 if (type == ACA_SMU_TYPE_UE) { 378 if (amdgpu_ras_intr_triggered()) 379 ret = atomic_cmpxchg(&aca->ue_update_flag, 0, 1) == 0; 380 else 381 atomic_set(&aca->ue_update_flag, 0); 382 } 383 384 return ret; 385 } 386 387 static void aca_banks_generate_cper(struct amdgpu_device *adev, 388 enum aca_smu_type type, 389 struct aca_banks *banks, 390 int count) 391 { 392 struct aca_bank_node *node; 393 struct aca_bank *bank; 394 395 if (!adev || !banks || !count) { 396 dev_warn(adev->dev, "fail to generate cper records\n"); 397 return; 398 } 399 400 /* UEs must be encoded into separate CPER entries */ 401 if (type == ACA_SMU_TYPE_UE) { 402 list_for_each_entry(node, &banks->list, node) { 403 bank = &node->bank; 404 if (amdgpu_cper_generate_ue_record(adev, bank)) 405 dev_warn(adev->dev, "fail to generate ue cper records\n"); 406 } 407 } else { 408 /* 409 * SMU_TYPE_CE banks are combined into 1 CPER entries, 410 * they could be CEs or DEs or both 411 */ 412 if (amdgpu_cper_generate_ce_records(adev, banks, count)) 413 dev_warn(adev->dev, "fail to generate ce cper records\n"); 414 } 415 } 416 417 static int aca_banks_update(struct amdgpu_device *adev, enum aca_smu_type type, 418 bank_handler_t handler, struct ras_query_context *qctx, void *data) 419 { 420 struct amdgpu_aca *aca = &adev->aca; 421 struct aca_banks banks; 422 u32 count = 0; 423 int ret; 424 425 if (list_empty(&aca->mgr.list)) 426 return 0; 427 428 if (!aca_bank_should_update(adev, type)) 429 return 0; 430 431 ret = aca_smu_get_valid_aca_count(adev, type, &count); 432 if (ret) 433 return ret; 434 435 if (!count) 436 return 0; 437 438 aca_banks_init(&banks); 439 440 ret = aca_smu_get_valid_aca_banks(adev, type, 0, count, &banks, qctx); 441 if (ret) 442 goto err_release_banks; 443 444 if (list_empty(&banks.list)) { 445 ret = 0; 446 goto err_release_banks; 447 } 448 449 ret = aca_dispatch_banks(&aca->mgr, &banks, type, 450 handler, data); 451 if (ret) 452 goto err_release_banks; 453 454 aca_banks_generate_cper(adev, type, &banks, count); 455 456 err_release_banks: 457 aca_banks_release(&banks); 458 459 return ret; 460 } 461 462 static int aca_log_aca_error_data(struct aca_bank_error *bank_error, enum aca_error_type type, struct ras_err_data *err_data) 463 { 464 struct aca_bank_info *info; 465 struct amdgpu_smuio_mcm_config_info mcm_info; 466 u64 count; 467 468 if (type >= ACA_ERROR_TYPE_COUNT) 469 return -EINVAL; 470 471 count = bank_error->count; 472 if (!count) 473 return 0; 474 475 info = &bank_error->info; 476 mcm_info.die_id = info->die_id; 477 mcm_info.socket_id = info->socket_id; 478 479 switch (type) { 480 case ACA_ERROR_TYPE_UE: 481 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, count); 482 break; 483 case ACA_ERROR_TYPE_CE: 484 amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, count); 485 break; 486 case ACA_ERROR_TYPE_DEFERRED: 487 amdgpu_ras_error_statistic_de_count(err_data, &mcm_info, count); 488 break; 489 default: 490 break; 491 } 492 493 return 0; 494 } 495 496 static int aca_log_aca_error(struct aca_handle *handle, enum aca_error_type type, struct ras_err_data *err_data) 497 { 498 struct aca_error_cache *error_cache = &handle->error_cache; 499 struct aca_error *aerr = &error_cache->errors[type]; 500 struct aca_bank_error *bank_error, *tmp; 501 502 mutex_lock(&aerr->lock); 503 504 if (list_empty(&aerr->list)) 505 goto out_unlock; 506 507 list_for_each_entry_safe(bank_error, tmp, &aerr->list, node) { 508 aca_log_aca_error_data(bank_error, type, err_data); 509 aca_bank_error_remove(aerr, bank_error); 510 } 511 512 out_unlock: 513 mutex_unlock(&aerr->lock); 514 515 return 0; 516 } 517 518 static int __aca_get_error_data(struct amdgpu_device *adev, struct aca_handle *handle, enum aca_error_type type, 519 struct ras_err_data *err_data, struct ras_query_context *qctx) 520 { 521 enum aca_smu_type smu_type; 522 int ret; 523 524 switch (type) { 525 case ACA_ERROR_TYPE_UE: 526 smu_type = ACA_SMU_TYPE_UE; 527 break; 528 case ACA_ERROR_TYPE_CE: 529 case ACA_ERROR_TYPE_DEFERRED: 530 smu_type = ACA_SMU_TYPE_CE; 531 break; 532 default: 533 return -EINVAL; 534 } 535 536 /* update aca bank to aca source error_cache first */ 537 ret = aca_banks_update(adev, smu_type, handler_aca_log_bank_error, qctx, NULL); 538 if (ret) 539 return ret; 540 541 return aca_log_aca_error(handle, type, err_data); 542 } 543 544 static bool aca_handle_is_valid(struct aca_handle *handle) 545 { 546 if (!handle->mask || !list_empty(&handle->node)) 547 return false; 548 549 return true; 550 } 551 552 int amdgpu_aca_get_error_data(struct amdgpu_device *adev, struct aca_handle *handle, 553 enum aca_error_type type, struct ras_err_data *err_data, 554 struct ras_query_context *qctx) 555 { 556 if (!handle || !err_data) 557 return -EINVAL; 558 559 if (aca_handle_is_valid(handle)) 560 return -EOPNOTSUPP; 561 562 if ((type < 0) || (!(BIT(type) & handle->mask))) 563 return 0; 564 565 return __aca_get_error_data(adev, handle, type, err_data, qctx); 566 } 567 568 static void aca_error_init(struct aca_error *aerr, enum aca_error_type type) 569 { 570 mutex_init(&aerr->lock); 571 INIT_LIST_HEAD(&aerr->list); 572 aerr->type = type; 573 aerr->nr_errors = 0; 574 } 575 576 static void aca_init_error_cache(struct aca_handle *handle) 577 { 578 struct aca_error_cache *error_cache = &handle->error_cache; 579 int type; 580 581 for (type = ACA_ERROR_TYPE_UE; type < ACA_ERROR_TYPE_COUNT; type++) 582 aca_error_init(&error_cache->errors[type], type); 583 } 584 585 static void aca_error_fini(struct aca_error *aerr) 586 { 587 struct aca_bank_error *bank_error, *tmp; 588 589 mutex_lock(&aerr->lock); 590 if (list_empty(&aerr->list)) 591 goto out_unlock; 592 593 list_for_each_entry_safe(bank_error, tmp, &aerr->list, node) 594 aca_bank_error_remove(aerr, bank_error); 595 596 out_unlock: 597 mutex_destroy(&aerr->lock); 598 } 599 600 static void aca_fini_error_cache(struct aca_handle *handle) 601 { 602 struct aca_error_cache *error_cache = &handle->error_cache; 603 int type; 604 605 for (type = ACA_ERROR_TYPE_UE; type < ACA_ERROR_TYPE_COUNT; type++) 606 aca_error_fini(&error_cache->errors[type]); 607 } 608 609 static int add_aca_handle(struct amdgpu_device *adev, struct aca_handle_manager *mgr, struct aca_handle *handle, 610 const char *name, const struct aca_info *ras_info, void *data) 611 { 612 memset(handle, 0, sizeof(*handle)); 613 614 handle->adev = adev; 615 handle->mgr = mgr; 616 handle->name = name; 617 handle->hwip = ras_info->hwip; 618 handle->mask = ras_info->mask; 619 handle->bank_ops = ras_info->bank_ops; 620 handle->data = data; 621 aca_init_error_cache(handle); 622 623 INIT_LIST_HEAD(&handle->node); 624 list_add_tail(&handle->node, &mgr->list); 625 mgr->nr_handles++; 626 627 return 0; 628 } 629 630 static ssize_t aca_sysfs_read(struct device *dev, 631 struct device_attribute *attr, char *buf) 632 { 633 struct aca_handle *handle = container_of(attr, struct aca_handle, aca_attr); 634 635 /* NOTE: the aca cache will be auto cleared once read, 636 * So the driver should unify the query entry point, forward request to ras query interface directly */ 637 return amdgpu_ras_aca_sysfs_read(dev, attr, handle, buf, handle->data); 638 } 639 640 static int add_aca_sysfs(struct amdgpu_device *adev, struct aca_handle *handle) 641 { 642 struct device_attribute *aca_attr = &handle->aca_attr; 643 644 snprintf(handle->attr_name, sizeof(handle->attr_name) - 1, "aca_%s", handle->name); 645 aca_attr->show = aca_sysfs_read; 646 aca_attr->attr.name = handle->attr_name; 647 aca_attr->attr.mode = S_IRUGO; 648 sysfs_attr_init(&aca_attr->attr); 649 650 return sysfs_add_file_to_group(&adev->dev->kobj, 651 &aca_attr->attr, 652 "ras"); 653 } 654 655 int amdgpu_aca_add_handle(struct amdgpu_device *adev, struct aca_handle *handle, 656 const char *name, const struct aca_info *ras_info, void *data) 657 { 658 struct amdgpu_aca *aca = &adev->aca; 659 int ret; 660 661 if (!amdgpu_aca_is_enabled(adev)) 662 return 0; 663 664 ret = add_aca_handle(adev, &aca->mgr, handle, name, ras_info, data); 665 if (ret) 666 return ret; 667 668 return add_aca_sysfs(adev, handle); 669 } 670 671 static void remove_aca_handle(struct aca_handle *handle) 672 { 673 struct aca_handle_manager *mgr = handle->mgr; 674 675 aca_fini_error_cache(handle); 676 list_del(&handle->node); 677 mgr->nr_handles--; 678 } 679 680 static void remove_aca_sysfs(struct aca_handle *handle) 681 { 682 struct amdgpu_device *adev = handle->adev; 683 struct device_attribute *aca_attr = &handle->aca_attr; 684 685 if (adev->dev->kobj.sd) 686 sysfs_remove_file_from_group(&adev->dev->kobj, 687 &aca_attr->attr, 688 "ras"); 689 } 690 691 void amdgpu_aca_remove_handle(struct aca_handle *handle) 692 { 693 if (!handle || list_empty(&handle->node)) 694 return; 695 696 remove_aca_sysfs(handle); 697 remove_aca_handle(handle); 698 } 699 700 static int aca_manager_init(struct aca_handle_manager *mgr) 701 { 702 INIT_LIST_HEAD(&mgr->list); 703 mgr->nr_handles = 0; 704 705 return 0; 706 } 707 708 static void aca_manager_fini(struct aca_handle_manager *mgr) 709 { 710 struct aca_handle *handle, *tmp; 711 712 if (list_empty(&mgr->list)) 713 return; 714 715 list_for_each_entry_safe(handle, tmp, &mgr->list, node) 716 amdgpu_aca_remove_handle(handle); 717 } 718 719 bool amdgpu_aca_is_enabled(struct amdgpu_device *adev) 720 { 721 return (adev->aca.is_enabled || 722 adev->debug_enable_ras_aca); 723 } 724 725 int amdgpu_aca_init(struct amdgpu_device *adev) 726 { 727 struct amdgpu_aca *aca = &adev->aca; 728 int ret; 729 730 atomic_set(&aca->ue_update_flag, 0); 731 732 ret = aca_manager_init(&aca->mgr); 733 if (ret) 734 return ret; 735 736 return 0; 737 } 738 739 void amdgpu_aca_fini(struct amdgpu_device *adev) 740 { 741 struct amdgpu_aca *aca = &adev->aca; 742 743 aca_manager_fini(&aca->mgr); 744 745 atomic_set(&aca->ue_update_flag, 0); 746 } 747 748 int amdgpu_aca_reset(struct amdgpu_device *adev) 749 { 750 struct amdgpu_aca *aca = &adev->aca; 751 752 atomic_set(&aca->ue_update_flag, 0); 753 754 return 0; 755 } 756 757 void amdgpu_aca_set_smu_funcs(struct amdgpu_device *adev, const struct aca_smu_funcs *smu_funcs) 758 { 759 struct amdgpu_aca *aca = &adev->aca; 760 761 WARN_ON(aca->smu_funcs); 762 aca->smu_funcs = smu_funcs; 763 } 764 765 int aca_bank_info_decode(struct aca_bank *bank, struct aca_bank_info *info) 766 { 767 u64 ipid; 768 u32 instidhi, instidlo; 769 770 if (!bank || !info) 771 return -EINVAL; 772 773 ipid = bank->regs[ACA_REG_IDX_IPID]; 774 info->hwid = ACA_REG__IPID__HARDWAREID(ipid); 775 info->mcatype = ACA_REG__IPID__MCATYPE(ipid); 776 /* 777 * Unfied DieID Format: SAASS. A:AID, S:Socket. 778 * Unfied DieID[4:4] = InstanceId[0:0] 779 * Unfied DieID[0:3] = InstanceIdHi[0:3] 780 */ 781 instidhi = ACA_REG__IPID__INSTANCEIDHI(ipid); 782 instidlo = ACA_REG__IPID__INSTANCEIDLO(ipid); 783 info->die_id = ((instidhi >> 2) & 0x03); 784 info->socket_id = ((instidlo & 0x1) << 2) | (instidhi & 0x03); 785 786 return 0; 787 } 788 789 static int aca_bank_get_error_code(struct amdgpu_device *adev, struct aca_bank *bank) 790 { 791 struct amdgpu_aca *aca = &adev->aca; 792 const struct aca_smu_funcs *smu_funcs = aca->smu_funcs; 793 794 if (!smu_funcs || !smu_funcs->parse_error_code) 795 return -EOPNOTSUPP; 796 797 return smu_funcs->parse_error_code(adev, bank); 798 } 799 800 int aca_bank_check_error_codes(struct amdgpu_device *adev, struct aca_bank *bank, int *err_codes, int size) 801 { 802 int i, error_code; 803 804 if (!bank || !err_codes) 805 return -EINVAL; 806 807 error_code = aca_bank_get_error_code(adev, bank); 808 if (error_code < 0) 809 return error_code; 810 811 for (i = 0; i < size; i++) { 812 if (err_codes[i] == error_code) 813 return 0; 814 } 815 816 return -EINVAL; 817 } 818 819 int amdgpu_aca_smu_set_debug_mode(struct amdgpu_device *adev, bool en) 820 { 821 struct amdgpu_aca *aca = &adev->aca; 822 const struct aca_smu_funcs *smu_funcs = aca->smu_funcs; 823 824 if (!smu_funcs || !smu_funcs->set_debug_mode) 825 return -EOPNOTSUPP; 826 827 return smu_funcs->set_debug_mode(adev, en); 828 } 829 830 #if defined(CONFIG_DEBUG_FS) 831 static int amdgpu_aca_smu_debug_mode_set(void *data, u64 val) 832 { 833 struct amdgpu_device *adev = (struct amdgpu_device *)data; 834 int ret; 835 836 ret = amdgpu_ras_set_aca_debug_mode(adev, val ? true : false); 837 if (ret) 838 return ret; 839 840 dev_info(adev->dev, "amdgpu set smu aca debug mode %s success\n", val ? "on" : "off"); 841 842 return 0; 843 } 844 845 static void aca_dump_entry(struct seq_file *m, struct aca_bank *bank, enum aca_smu_type type, int idx) 846 { 847 struct aca_bank_info info; 848 int i, ret; 849 850 ret = aca_bank_info_decode(bank, &info); 851 if (ret) 852 return; 853 854 seq_printf(m, "aca entry[%d].type: %s\n", idx, type == ACA_SMU_TYPE_UE ? "UE" : "CE"); 855 seq_printf(m, "aca entry[%d].info: socketid:%d aid:%d hwid:0x%03x mcatype:0x%04x\n", 856 idx, info.socket_id, info.die_id, info.hwid, info.mcatype); 857 858 for (i = 0; i < ARRAY_SIZE(aca_regs); i++) 859 seq_printf(m, "aca entry[%d].regs[%d]: 0x%016llx\n", idx, aca_regs[i].reg_idx, bank->regs[aca_regs[i].reg_idx]); 860 } 861 862 struct aca_dump_context { 863 struct seq_file *m; 864 int idx; 865 }; 866 867 static int handler_aca_bank_dump(struct aca_handle *handle, struct aca_bank *bank, 868 enum aca_smu_type type, void *data) 869 { 870 struct aca_dump_context *ctx = (struct aca_dump_context *)data; 871 872 aca_dump_entry(ctx->m, bank, type, ctx->idx++); 873 874 return handler_aca_log_bank_error(handle, bank, type, NULL); 875 } 876 877 static int aca_dump_show(struct seq_file *m, enum aca_smu_type type) 878 { 879 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 880 struct aca_dump_context context = { 881 .m = m, 882 .idx = 0, 883 }; 884 885 return aca_banks_update(adev, type, handler_aca_bank_dump, NULL, (void *)&context); 886 } 887 888 static int aca_dump_ce_show(struct seq_file *m, void *unused) 889 { 890 return aca_dump_show(m, ACA_SMU_TYPE_CE); 891 } 892 893 static int aca_dump_ce_open(struct inode *inode, struct file *file) 894 { 895 return single_open(file, aca_dump_ce_show, inode->i_private); 896 } 897 898 static const struct file_operations aca_ce_dump_debug_fops = { 899 .owner = THIS_MODULE, 900 .open = aca_dump_ce_open, 901 .read = seq_read, 902 .llseek = seq_lseek, 903 .release = single_release, 904 }; 905 906 static int aca_dump_ue_show(struct seq_file *m, void *unused) 907 { 908 return aca_dump_show(m, ACA_SMU_TYPE_UE); 909 } 910 911 static int aca_dump_ue_open(struct inode *inode, struct file *file) 912 { 913 return single_open(file, aca_dump_ue_show, inode->i_private); 914 } 915 916 static const struct file_operations aca_ue_dump_debug_fops = { 917 .owner = THIS_MODULE, 918 .open = aca_dump_ue_open, 919 .read = seq_read, 920 .llseek = seq_lseek, 921 .release = single_release, 922 }; 923 924 DEFINE_DEBUGFS_ATTRIBUTE(aca_debug_mode_fops, NULL, amdgpu_aca_smu_debug_mode_set, "%llu\n"); 925 #endif 926 927 void amdgpu_aca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root) 928 { 929 #if defined(CONFIG_DEBUG_FS) 930 if (!root) 931 return; 932 933 debugfs_create_file("aca_debug_mode", 0200, root, adev, &aca_debug_mode_fops); 934 debugfs_create_file("aca_ue_dump", 0400, root, adev, &aca_ue_dump_debug_fops); 935 debugfs_create_file("aca_ce_dump", 0400, root, adev, &aca_ce_dump_debug_fops); 936 #endif 937 } 938