xref: /linux/drivers/gpu/drm/amd/amdgpu/amdgpu.h (revision fd7d598270724cc787982ea48bbe17ad383a8b7f)
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #ifndef __AMDGPU_H__
29 #define __AMDGPU_H__
30 
31 #ifdef pr_fmt
32 #undef pr_fmt
33 #endif
34 
35 #define pr_fmt(fmt) "amdgpu: " fmt
36 
37 #ifdef dev_fmt
38 #undef dev_fmt
39 #endif
40 
41 #define dev_fmt(fmt) "amdgpu: " fmt
42 
43 #include "amdgpu_ctx.h"
44 
45 #include <linux/atomic.h>
46 #include <linux/wait.h>
47 #include <linux/list.h>
48 #include <linux/kref.h>
49 #include <linux/rbtree.h>
50 #include <linux/hashtable.h>
51 #include <linux/dma-fence.h>
52 #include <linux/pci.h>
53 
54 #include <drm/ttm/ttm_bo.h>
55 #include <drm/ttm/ttm_placement.h>
56 
57 #include <drm/amdgpu_drm.h>
58 #include <drm/drm_gem.h>
59 #include <drm/drm_ioctl.h>
60 
61 #include <kgd_kfd_interface.h>
62 #include "dm_pp_interface.h"
63 #include "kgd_pp_interface.h"
64 
65 #include "amd_shared.h"
66 #include "amdgpu_mode.h"
67 #include "amdgpu_ih.h"
68 #include "amdgpu_irq.h"
69 #include "amdgpu_ucode.h"
70 #include "amdgpu_ttm.h"
71 #include "amdgpu_psp.h"
72 #include "amdgpu_gds.h"
73 #include "amdgpu_sync.h"
74 #include "amdgpu_ring.h"
75 #include "amdgpu_vm.h"
76 #include "amdgpu_dpm.h"
77 #include "amdgpu_acp.h"
78 #include "amdgpu_uvd.h"
79 #include "amdgpu_vce.h"
80 #include "amdgpu_vcn.h"
81 #include "amdgpu_jpeg.h"
82 #include "amdgpu_vpe.h"
83 #include "amdgpu_umsch_mm.h"
84 #include "amdgpu_gmc.h"
85 #include "amdgpu_gfx.h"
86 #include "amdgpu_sdma.h"
87 #include "amdgpu_lsdma.h"
88 #include "amdgpu_nbio.h"
89 #include "amdgpu_hdp.h"
90 #include "amdgpu_dm.h"
91 #include "amdgpu_virt.h"
92 #include "amdgpu_csa.h"
93 #include "amdgpu_mes_ctx.h"
94 #include "amdgpu_gart.h"
95 #include "amdgpu_debugfs.h"
96 #include "amdgpu_job.h"
97 #include "amdgpu_bo_list.h"
98 #include "amdgpu_gem.h"
99 #include "amdgpu_doorbell.h"
100 #include "amdgpu_amdkfd.h"
101 #include "amdgpu_discovery.h"
102 #include "amdgpu_mes.h"
103 #include "amdgpu_umc.h"
104 #include "amdgpu_mmhub.h"
105 #include "amdgpu_gfxhub.h"
106 #include "amdgpu_df.h"
107 #include "amdgpu_smuio.h"
108 #include "amdgpu_fdinfo.h"
109 #include "amdgpu_mca.h"
110 #include "amdgpu_ras.h"
111 #include "amdgpu_xcp.h"
112 
113 #define MAX_GPU_INSTANCE		64
114 
115 struct amdgpu_gpu_instance
116 {
117 	struct amdgpu_device		*adev;
118 	int				mgpu_fan_enabled;
119 };
120 
121 struct amdgpu_mgpu_info
122 {
123 	struct amdgpu_gpu_instance	gpu_ins[MAX_GPU_INSTANCE];
124 	struct mutex			mutex;
125 	uint32_t			num_gpu;
126 	uint32_t			num_dgpu;
127 	uint32_t			num_apu;
128 
129 	/* delayed reset_func for XGMI configuration if necessary */
130 	struct delayed_work		delayed_reset_work;
131 	bool				pending_reset;
132 };
133 
134 enum amdgpu_ss {
135 	AMDGPU_SS_DRV_LOAD,
136 	AMDGPU_SS_DEV_D0,
137 	AMDGPU_SS_DEV_D3,
138 	AMDGPU_SS_DRV_UNLOAD
139 };
140 
141 struct amdgpu_watchdog_timer
142 {
143 	bool timeout_fatal_disable;
144 	uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */
145 };
146 
147 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH	256
148 
149 /*
150  * Modules parameters.
151  */
152 extern int amdgpu_modeset;
153 extern unsigned int amdgpu_vram_limit;
154 extern int amdgpu_vis_vram_limit;
155 extern int amdgpu_gart_size;
156 extern int amdgpu_gtt_size;
157 extern int amdgpu_moverate;
158 extern int amdgpu_audio;
159 extern int amdgpu_disp_priority;
160 extern int amdgpu_hw_i2c;
161 extern int amdgpu_pcie_gen2;
162 extern int amdgpu_msi;
163 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
164 extern int amdgpu_dpm;
165 extern int amdgpu_fw_load_type;
166 extern int amdgpu_aspm;
167 extern int amdgpu_runtime_pm;
168 extern uint amdgpu_ip_block_mask;
169 extern int amdgpu_bapm;
170 extern int amdgpu_deep_color;
171 extern int amdgpu_vm_size;
172 extern int amdgpu_vm_block_size;
173 extern int amdgpu_vm_fragment_size;
174 extern int amdgpu_vm_fault_stop;
175 extern int amdgpu_vm_debug;
176 extern int amdgpu_vm_update_mode;
177 extern int amdgpu_exp_hw_support;
178 extern int amdgpu_dc;
179 extern int amdgpu_sched_jobs;
180 extern int amdgpu_sched_hw_submission;
181 extern uint amdgpu_pcie_gen_cap;
182 extern uint amdgpu_pcie_lane_cap;
183 extern u64 amdgpu_cg_mask;
184 extern uint amdgpu_pg_mask;
185 extern uint amdgpu_sdma_phase_quantum;
186 extern char *amdgpu_disable_cu;
187 extern char *amdgpu_virtual_display;
188 extern uint amdgpu_pp_feature_mask;
189 extern uint amdgpu_force_long_training;
190 extern int amdgpu_lbpw;
191 extern int amdgpu_compute_multipipe;
192 extern int amdgpu_gpu_recovery;
193 extern int amdgpu_emu_mode;
194 extern uint amdgpu_smu_memory_pool_size;
195 extern int amdgpu_smu_pptable_id;
196 extern uint amdgpu_dc_feature_mask;
197 extern uint amdgpu_dc_debug_mask;
198 extern uint amdgpu_dc_visual_confirm;
199 extern uint amdgpu_dm_abm_level;
200 extern int amdgpu_backlight;
201 extern struct amdgpu_mgpu_info mgpu_info;
202 extern int amdgpu_ras_enable;
203 extern uint amdgpu_ras_mask;
204 extern int amdgpu_bad_page_threshold;
205 extern bool amdgpu_ignore_bad_page_threshold;
206 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer;
207 extern int amdgpu_async_gfx_ring;
208 extern int amdgpu_mcbp;
209 extern int amdgpu_discovery;
210 extern int amdgpu_mes;
211 extern int amdgpu_mes_kiq;
212 extern int amdgpu_noretry;
213 extern int amdgpu_force_asic_type;
214 extern int amdgpu_smartshift_bias;
215 extern int amdgpu_use_xgmi_p2p;
216 extern int amdgpu_mtype_local;
217 extern bool enforce_isolation;
218 #ifdef CONFIG_HSA_AMD
219 extern int sched_policy;
220 extern bool debug_evictions;
221 extern bool no_system_mem_limit;
222 extern int halt_if_hws_hang;
223 #else
224 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;
225 static const bool __maybe_unused debug_evictions; /* = false */
226 static const bool __maybe_unused no_system_mem_limit;
227 static const int __maybe_unused halt_if_hws_hang;
228 #endif
229 #ifdef CONFIG_HSA_AMD_P2P
230 extern bool pcie_p2p;
231 #endif
232 
233 extern int amdgpu_tmz;
234 extern int amdgpu_reset_method;
235 
236 #ifdef CONFIG_DRM_AMDGPU_SI
237 extern int amdgpu_si_support;
238 #endif
239 #ifdef CONFIG_DRM_AMDGPU_CIK
240 extern int amdgpu_cik_support;
241 #endif
242 extern int amdgpu_num_kcq;
243 
244 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)
245 extern int amdgpu_vcnfw_log;
246 extern int amdgpu_sg_display;
247 extern int amdgpu_umsch_mm;
248 extern int amdgpu_seamless;
249 
250 extern int amdgpu_user_partt_mode;
251 
252 #define AMDGPU_VM_MAX_NUM_CTX			4096
253 #define AMDGPU_SG_THRESHOLD			(256*1024*1024)
254 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS	        3000
255 #define AMDGPU_MAX_USEC_TIMEOUT			100000	/* 100 ms */
256 #define AMDGPU_FENCE_JIFFIES_TIMEOUT		(HZ / 2)
257 #define AMDGPU_DEBUGFS_MAX_COMPONENTS		32
258 #define AMDGPUFB_CONN_LIMIT			4
259 #define AMDGPU_BIOS_NUM_SCRATCH			16
260 
261 #define AMDGPU_VBIOS_VGA_ALLOCATION		(9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */
262 
263 /* hard reset data */
264 #define AMDGPU_ASIC_RESET_DATA                  0x39d5e86b
265 
266 /* reset flags */
267 #define AMDGPU_RESET_GFX			(1 << 0)
268 #define AMDGPU_RESET_COMPUTE			(1 << 1)
269 #define AMDGPU_RESET_DMA			(1 << 2)
270 #define AMDGPU_RESET_CP				(1 << 3)
271 #define AMDGPU_RESET_GRBM			(1 << 4)
272 #define AMDGPU_RESET_DMA1			(1 << 5)
273 #define AMDGPU_RESET_RLC			(1 << 6)
274 #define AMDGPU_RESET_SEM			(1 << 7)
275 #define AMDGPU_RESET_IH				(1 << 8)
276 #define AMDGPU_RESET_VMC			(1 << 9)
277 #define AMDGPU_RESET_MC				(1 << 10)
278 #define AMDGPU_RESET_DISPLAY			(1 << 11)
279 #define AMDGPU_RESET_UVD			(1 << 12)
280 #define AMDGPU_RESET_VCE			(1 << 13)
281 #define AMDGPU_RESET_VCE1			(1 << 14)
282 
283 /* max cursor sizes (in pixels) */
284 #define CIK_CURSOR_WIDTH 128
285 #define CIK_CURSOR_HEIGHT 128
286 
287 /* smart shift bias level limits */
288 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
289 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
290 
291 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */
292 #define AMDGPU_SWCTF_EXTRA_DELAY		50
293 
294 struct amdgpu_xcp_mgr;
295 struct amdgpu_device;
296 struct amdgpu_irq_src;
297 struct amdgpu_fpriv;
298 struct amdgpu_bo_va_mapping;
299 struct kfd_vm_fault_info;
300 struct amdgpu_hive_info;
301 struct amdgpu_reset_context;
302 struct amdgpu_reset_control;
303 
304 enum amdgpu_cp_irq {
305 	AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
306 	AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
307 	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
308 	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
309 	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
310 	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
311 	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
312 	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
313 	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
314 	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
315 
316 	AMDGPU_CP_IRQ_LAST
317 };
318 
319 enum amdgpu_thermal_irq {
320 	AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
321 	AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
322 
323 	AMDGPU_THERMAL_IRQ_LAST
324 };
325 
326 enum amdgpu_kiq_irq {
327 	AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
328 	AMDGPU_CP_KIQ_IRQ_LAST
329 };
330 #define SRIOV_USEC_TIMEOUT  1200000 /* wait 12 * 100ms for SRIOV */
331 #define MAX_KIQ_REG_WAIT       5000 /* in usecs, 5ms */
332 #define MAX_KIQ_REG_BAILOUT_INTERVAL   5 /* in msecs, 5ms */
333 #define MAX_KIQ_REG_TRY 1000
334 
335 int amdgpu_device_ip_set_clockgating_state(void *dev,
336 					   enum amd_ip_block_type block_type,
337 					   enum amd_clockgating_state state);
338 int amdgpu_device_ip_set_powergating_state(void *dev,
339 					   enum amd_ip_block_type block_type,
340 					   enum amd_powergating_state state);
341 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
342 					    u64 *flags);
343 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
344 				   enum amd_ip_block_type block_type);
345 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
346 			      enum amd_ip_block_type block_type);
347 
348 #define AMDGPU_MAX_IP_NUM 16
349 
350 struct amdgpu_ip_block_status {
351 	bool valid;
352 	bool sw;
353 	bool hw;
354 	bool late_initialized;
355 	bool hang;
356 };
357 
358 struct amdgpu_ip_block_version {
359 	const enum amd_ip_block_type type;
360 	const u32 major;
361 	const u32 minor;
362 	const u32 rev;
363 	const struct amd_ip_funcs *funcs;
364 };
365 
366 #define HW_REV(_Major, _Minor, _Rev) \
367 	((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev)))
368 
369 struct amdgpu_ip_block {
370 	struct amdgpu_ip_block_status status;
371 	const struct amdgpu_ip_block_version *version;
372 };
373 
374 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
375 				       enum amd_ip_block_type type,
376 				       u32 major, u32 minor);
377 
378 struct amdgpu_ip_block *
379 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
380 			      enum amd_ip_block_type type);
381 
382 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
383 			       const struct amdgpu_ip_block_version *ip_block_version);
384 
385 /*
386  * BIOS.
387  */
388 bool amdgpu_get_bios(struct amdgpu_device *adev);
389 bool amdgpu_read_bios(struct amdgpu_device *adev);
390 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,
391 				     u8 *bios, u32 length_bytes);
392 /*
393  * Clocks
394  */
395 
396 #define AMDGPU_MAX_PPLL 3
397 
398 struct amdgpu_clock {
399 	struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
400 	struct amdgpu_pll spll;
401 	struct amdgpu_pll mpll;
402 	/* 10 Khz units */
403 	uint32_t default_mclk;
404 	uint32_t default_sclk;
405 	uint32_t default_dispclk;
406 	uint32_t current_dispclk;
407 	uint32_t dp_extclk;
408 	uint32_t max_pixel_clock;
409 };
410 
411 /* sub-allocation manager, it has to be protected by another lock.
412  * By conception this is an helper for other part of the driver
413  * like the indirect buffer or semaphore, which both have their
414  * locking.
415  *
416  * Principe is simple, we keep a list of sub allocation in offset
417  * order (first entry has offset == 0, last entry has the highest
418  * offset).
419  *
420  * When allocating new object we first check if there is room at
421  * the end total_size - (last_object_offset + last_object_size) >=
422  * alloc_size. If so we allocate new object there.
423  *
424  * When there is not enough room at the end, we start waiting for
425  * each sub object until we reach object_offset+object_size >=
426  * alloc_size, this object then become the sub object we return.
427  *
428  * Alignment can't be bigger than page size.
429  *
430  * Hole are not considered for allocation to keep things simple.
431  * Assumption is that there won't be hole (all object on same
432  * alignment).
433  */
434 
435 struct amdgpu_sa_manager {
436 	struct drm_suballoc_manager	base;
437 	struct amdgpu_bo		*bo;
438 	uint64_t			gpu_addr;
439 	void				*cpu_ptr;
440 };
441 
442 int amdgpu_fence_slab_init(void);
443 void amdgpu_fence_slab_fini(void);
444 
445 /*
446  * IRQS.
447  */
448 
449 struct amdgpu_flip_work {
450 	struct delayed_work		flip_work;
451 	struct work_struct		unpin_work;
452 	struct amdgpu_device		*adev;
453 	int				crtc_id;
454 	u32				target_vblank;
455 	uint64_t			base;
456 	struct drm_pending_vblank_event *event;
457 	struct amdgpu_bo		*old_abo;
458 	unsigned			shared_count;
459 	struct dma_fence		**shared;
460 	struct dma_fence_cb		cb;
461 	bool				async;
462 };
463 
464 
465 /*
466  * file private structure
467  */
468 
469 struct amdgpu_fpriv {
470 	struct amdgpu_vm	vm;
471 	struct amdgpu_bo_va	*prt_va;
472 	struct amdgpu_bo_va	*csa_va;
473 	struct mutex		bo_list_lock;
474 	struct idr		bo_list_handles;
475 	struct amdgpu_ctx_mgr	ctx_mgr;
476 	/** GPU partition selection */
477 	uint32_t		xcp_id;
478 };
479 
480 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
481 
482 /*
483  * Writeback
484  */
485 #define AMDGPU_MAX_WB 1024	/* Reserve at most 1024 WB slots for amdgpu-owned rings. */
486 
487 struct amdgpu_wb {
488 	struct amdgpu_bo	*wb_obj;
489 	volatile uint32_t	*wb;
490 	uint64_t		gpu_addr;
491 	u32			num_wb;	/* Number of wb slots actually reserved for amdgpu. */
492 	unsigned long		used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
493 };
494 
495 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
496 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
497 
498 /*
499  * Benchmarking
500  */
501 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
502 
503 /*
504  * ASIC specific register table accessible by UMD
505  */
506 struct amdgpu_allowed_register_entry {
507 	uint32_t reg_offset;
508 	bool grbm_indexed;
509 };
510 
511 enum amd_reset_method {
512 	AMD_RESET_METHOD_NONE = -1,
513 	AMD_RESET_METHOD_LEGACY = 0,
514 	AMD_RESET_METHOD_MODE0,
515 	AMD_RESET_METHOD_MODE1,
516 	AMD_RESET_METHOD_MODE2,
517 	AMD_RESET_METHOD_BACO,
518 	AMD_RESET_METHOD_PCI,
519 };
520 
521 struct amdgpu_video_codec_info {
522 	u32 codec_type;
523 	u32 max_width;
524 	u32 max_height;
525 	u32 max_pixels_per_frame;
526 	u32 max_level;
527 };
528 
529 #define codec_info_build(type, width, height, level) \
530 			 .codec_type = type,\
531 			 .max_width = width,\
532 			 .max_height = height,\
533 			 .max_pixels_per_frame = height * width,\
534 			 .max_level = level,
535 
536 struct amdgpu_video_codecs {
537 	const u32 codec_count;
538 	const struct amdgpu_video_codec_info *codec_array;
539 };
540 
541 /*
542  * ASIC specific functions.
543  */
544 struct amdgpu_asic_funcs {
545 	bool (*read_disabled_bios)(struct amdgpu_device *adev);
546 	bool (*read_bios_from_rom)(struct amdgpu_device *adev,
547 				   u8 *bios, u32 length_bytes);
548 	int (*read_register)(struct amdgpu_device *adev, u32 se_num,
549 			     u32 sh_num, u32 reg_offset, u32 *value);
550 	void (*set_vga_state)(struct amdgpu_device *adev, bool state);
551 	int (*reset)(struct amdgpu_device *adev);
552 	enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
553 	/* get the reference clock */
554 	u32 (*get_xclk)(struct amdgpu_device *adev);
555 	/* MM block clocks */
556 	int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
557 	int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
558 	/* static power management */
559 	int (*get_pcie_lanes)(struct amdgpu_device *adev);
560 	void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
561 	/* get config memsize register */
562 	u32 (*get_config_memsize)(struct amdgpu_device *adev);
563 	/* flush hdp write queue */
564 	void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
565 	/* invalidate hdp read cache */
566 	void (*invalidate_hdp)(struct amdgpu_device *adev,
567 			       struct amdgpu_ring *ring);
568 	/* check if the asic needs a full reset of if soft reset will work */
569 	bool (*need_full_reset)(struct amdgpu_device *adev);
570 	/* initialize doorbell layout for specific asic*/
571 	void (*init_doorbell_index)(struct amdgpu_device *adev);
572 	/* PCIe bandwidth usage */
573 	void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
574 			       uint64_t *count1);
575 	/* do we need to reset the asic at init time (e.g., kexec) */
576 	bool (*need_reset_on_init)(struct amdgpu_device *adev);
577 	/* PCIe replay counter */
578 	uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
579 	/* device supports BACO */
580 	bool (*supports_baco)(struct amdgpu_device *adev);
581 	/* pre asic_init quirks */
582 	void (*pre_asic_init)(struct amdgpu_device *adev);
583 	/* enter/exit umd stable pstate */
584 	int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
585 	/* query video codecs */
586 	int (*query_video_codecs)(struct amdgpu_device *adev, bool encode,
587 				  const struct amdgpu_video_codecs **codecs);
588 	/* encode "> 32bits" smn addressing */
589 	u64 (*encode_ext_smn_addressing)(int ext_id);
590 };
591 
592 /*
593  * IOCTL.
594  */
595 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
596 				struct drm_file *filp);
597 
598 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
599 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
600 				    struct drm_file *filp);
601 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
602 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
603 				struct drm_file *filp);
604 
605 /* VRAM scratch page for HDP bug, default vram page */
606 struct amdgpu_mem_scratch {
607 	struct amdgpu_bo		*robj;
608 	volatile uint32_t		*ptr;
609 	u64				gpu_addr;
610 };
611 
612 /*
613  * CGS
614  */
615 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
616 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
617 
618 /*
619  * Core structure, functions and helpers.
620  */
621 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
622 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
623 
624 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t);
625 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t);
626 
627 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
628 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
629 
630 typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device*, uint64_t);
631 typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device*, uint64_t, uint64_t);
632 
633 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
634 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
635 
636 struct amdgpu_mmio_remap {
637 	u32 reg_offset;
638 	resource_size_t bus_addr;
639 };
640 
641 /* Define the HW IP blocks will be used in driver , add more if necessary */
642 enum amd_hw_ip_block_type {
643 	GC_HWIP = 1,
644 	HDP_HWIP,
645 	SDMA0_HWIP,
646 	SDMA1_HWIP,
647 	SDMA2_HWIP,
648 	SDMA3_HWIP,
649 	SDMA4_HWIP,
650 	SDMA5_HWIP,
651 	SDMA6_HWIP,
652 	SDMA7_HWIP,
653 	LSDMA_HWIP,
654 	MMHUB_HWIP,
655 	ATHUB_HWIP,
656 	NBIO_HWIP,
657 	MP0_HWIP,
658 	MP1_HWIP,
659 	UVD_HWIP,
660 	VCN_HWIP = UVD_HWIP,
661 	JPEG_HWIP = VCN_HWIP,
662 	VCN1_HWIP,
663 	VCE_HWIP,
664 	VPE_HWIP,
665 	DF_HWIP,
666 	DCE_HWIP,
667 	OSSSYS_HWIP,
668 	SMUIO_HWIP,
669 	PWR_HWIP,
670 	NBIF_HWIP,
671 	THM_HWIP,
672 	CLK_HWIP,
673 	UMC_HWIP,
674 	RSMU_HWIP,
675 	XGMI_HWIP,
676 	DCI_HWIP,
677 	PCIE_HWIP,
678 	MAX_HWIP
679 };
680 
681 #define HWIP_MAX_INSTANCE	44
682 
683 #define HW_ID_MAX		300
684 #define IP_VERSION_FULL(mj, mn, rv, var, srev) \
685 	(((mj) << 24) | ((mn) << 16) | ((rv) << 8) | ((var) << 4) | (srev))
686 #define IP_VERSION(mj, mn, rv)		IP_VERSION_FULL(mj, mn, rv, 0, 0)
687 #define IP_VERSION_MAJ(ver)		((ver) >> 24)
688 #define IP_VERSION_MIN(ver)		(((ver) >> 16) & 0xFF)
689 #define IP_VERSION_REV(ver)		(((ver) >> 8) & 0xFF)
690 #define IP_VERSION_VARIANT(ver)		(((ver) >> 4) & 0xF)
691 #define IP_VERSION_SUBREV(ver)		((ver) & 0xF)
692 #define IP_VERSION_MAJ_MIN_REV(ver)	((ver) >> 8)
693 
694 struct amdgpu_ip_map_info {
695 	/* Map of logical to actual dev instances/mask */
696 	uint32_t 		dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE];
697 	int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev,
698 				      enum amd_hw_ip_block_type block,
699 				      int8_t inst);
700 	uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev,
701 					enum amd_hw_ip_block_type block,
702 					uint32_t mask);
703 };
704 
705 struct amd_powerplay {
706 	void *pp_handle;
707 	const struct amd_pm_funcs *pp_funcs;
708 };
709 
710 struct ip_discovery_top;
711 
712 /* polaris10 kickers */
713 #define ASICID_IS_P20(did, rid)		(((did == 0x67DF) && \
714 					 ((rid == 0xE3) || \
715 					  (rid == 0xE4) || \
716 					  (rid == 0xE5) || \
717 					  (rid == 0xE7) || \
718 					  (rid == 0xEF))) || \
719 					 ((did == 0x6FDF) && \
720 					 ((rid == 0xE7) || \
721 					  (rid == 0xEF) || \
722 					  (rid == 0xFF))))
723 
724 #define ASICID_IS_P30(did, rid)		((did == 0x67DF) && \
725 					((rid == 0xE1) || \
726 					 (rid == 0xF7)))
727 
728 /* polaris11 kickers */
729 #define ASICID_IS_P21(did, rid)		(((did == 0x67EF) && \
730 					 ((rid == 0xE0) || \
731 					  (rid == 0xE5))) || \
732 					 ((did == 0x67FF) && \
733 					 ((rid == 0xCF) || \
734 					  (rid == 0xEF) || \
735 					  (rid == 0xFF))))
736 
737 #define ASICID_IS_P31(did, rid)		((did == 0x67EF) && \
738 					((rid == 0xE2)))
739 
740 /* polaris12 kickers */
741 #define ASICID_IS_P23(did, rid)		(((did == 0x6987) && \
742 					 ((rid == 0xC0) || \
743 					  (rid == 0xC1) || \
744 					  (rid == 0xC3) || \
745 					  (rid == 0xC7))) || \
746 					 ((did == 0x6981) && \
747 					 ((rid == 0x00) || \
748 					  (rid == 0x01) || \
749 					  (rid == 0x10))))
750 
751 struct amdgpu_mqd_prop {
752 	uint64_t mqd_gpu_addr;
753 	uint64_t hqd_base_gpu_addr;
754 	uint64_t rptr_gpu_addr;
755 	uint64_t wptr_gpu_addr;
756 	uint32_t queue_size;
757 	bool use_doorbell;
758 	uint32_t doorbell_index;
759 	uint64_t eop_gpu_addr;
760 	uint32_t hqd_pipe_priority;
761 	uint32_t hqd_queue_priority;
762 	bool hqd_active;
763 };
764 
765 struct amdgpu_mqd {
766 	unsigned mqd_size;
767 	int (*init_mqd)(struct amdgpu_device *adev, void *mqd,
768 			struct amdgpu_mqd_prop *p);
769 };
770 
771 #define AMDGPU_RESET_MAGIC_NUM 64
772 #define AMDGPU_MAX_DF_PERFMONS 4
773 struct amdgpu_reset_domain;
774 struct amdgpu_fru_info;
775 
776 struct amdgpu_reset_info {
777 	/* reset dump register */
778 	u32 *reset_dump_reg_list;
779 	u32 *reset_dump_reg_value;
780 	int num_regs;
781 
782 #ifdef CONFIG_DEV_COREDUMP
783 	struct amdgpu_coredump_info *coredump_info;
784 #endif
785 };
786 
787 /*
788  * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise.
789  */
790 #define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size)
791 
792 struct amdgpu_device {
793 	struct device			*dev;
794 	struct pci_dev			*pdev;
795 	struct drm_device		ddev;
796 
797 #ifdef CONFIG_DRM_AMD_ACP
798 	struct amdgpu_acp		acp;
799 #endif
800 	struct amdgpu_hive_info *hive;
801 	struct amdgpu_xcp_mgr *xcp_mgr;
802 	/* ASIC */
803 	enum amd_asic_type		asic_type;
804 	uint32_t			family;
805 	uint32_t			rev_id;
806 	uint32_t			external_rev_id;
807 	unsigned long			flags;
808 	unsigned long			apu_flags;
809 	int				usec_timeout;
810 	const struct amdgpu_asic_funcs	*asic_funcs;
811 	bool				shutdown;
812 	bool				need_swiotlb;
813 	bool				accel_working;
814 	struct notifier_block		acpi_nb;
815 	struct amdgpu_i2c_chan		*i2c_bus[AMDGPU_MAX_I2C_BUS];
816 	struct debugfs_blob_wrapper     debugfs_vbios_blob;
817 	struct debugfs_blob_wrapper     debugfs_discovery_blob;
818 	struct mutex			srbm_mutex;
819 	/* GRBM index mutex. Protects concurrent access to GRBM index */
820 	struct mutex                    grbm_idx_mutex;
821 	struct dev_pm_domain		vga_pm_domain;
822 	bool				have_disp_power_ref;
823 	bool                            have_atomics_support;
824 
825 	/* BIOS */
826 	bool				is_atom_fw;
827 	uint8_t				*bios;
828 	uint32_t			bios_size;
829 	uint32_t			bios_scratch_reg_offset;
830 	uint32_t			bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
831 
832 	/* Register/doorbell mmio */
833 	resource_size_t			rmmio_base;
834 	resource_size_t			rmmio_size;
835 	void __iomem			*rmmio;
836 	/* protects concurrent MM_INDEX/DATA based register access */
837 	spinlock_t mmio_idx_lock;
838 	struct amdgpu_mmio_remap        rmmio_remap;
839 	/* protects concurrent SMC based register access */
840 	spinlock_t smc_idx_lock;
841 	amdgpu_rreg_t			smc_rreg;
842 	amdgpu_wreg_t			smc_wreg;
843 	/* protects concurrent PCIE register access */
844 	spinlock_t pcie_idx_lock;
845 	amdgpu_rreg_t			pcie_rreg;
846 	amdgpu_wreg_t			pcie_wreg;
847 	amdgpu_rreg_t			pciep_rreg;
848 	amdgpu_wreg_t			pciep_wreg;
849 	amdgpu_rreg_ext_t		pcie_rreg_ext;
850 	amdgpu_wreg_ext_t		pcie_wreg_ext;
851 	amdgpu_rreg64_t			pcie_rreg64;
852 	amdgpu_wreg64_t			pcie_wreg64;
853 	amdgpu_rreg64_ext_t			pcie_rreg64_ext;
854 	amdgpu_wreg64_ext_t			pcie_wreg64_ext;
855 	/* protects concurrent UVD register access */
856 	spinlock_t uvd_ctx_idx_lock;
857 	amdgpu_rreg_t			uvd_ctx_rreg;
858 	amdgpu_wreg_t			uvd_ctx_wreg;
859 	/* protects concurrent DIDT register access */
860 	spinlock_t didt_idx_lock;
861 	amdgpu_rreg_t			didt_rreg;
862 	amdgpu_wreg_t			didt_wreg;
863 	/* protects concurrent gc_cac register access */
864 	spinlock_t gc_cac_idx_lock;
865 	amdgpu_rreg_t			gc_cac_rreg;
866 	amdgpu_wreg_t			gc_cac_wreg;
867 	/* protects concurrent se_cac register access */
868 	spinlock_t se_cac_idx_lock;
869 	amdgpu_rreg_t			se_cac_rreg;
870 	amdgpu_wreg_t			se_cac_wreg;
871 	/* protects concurrent ENDPOINT (audio) register access */
872 	spinlock_t audio_endpt_idx_lock;
873 	amdgpu_block_rreg_t		audio_endpt_rreg;
874 	amdgpu_block_wreg_t		audio_endpt_wreg;
875 	struct amdgpu_doorbell		doorbell;
876 
877 	/* clock/pll info */
878 	struct amdgpu_clock            clock;
879 
880 	/* MC */
881 	struct amdgpu_gmc		gmc;
882 	struct amdgpu_gart		gart;
883 	dma_addr_t			dummy_page_addr;
884 	struct amdgpu_vm_manager	vm_manager;
885 	struct amdgpu_vmhub             vmhub[AMDGPU_MAX_VMHUBS];
886 	DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS);
887 
888 	/* memory management */
889 	struct amdgpu_mman		mman;
890 	struct amdgpu_mem_scratch	mem_scratch;
891 	struct amdgpu_wb		wb;
892 	atomic64_t			num_bytes_moved;
893 	atomic64_t			num_evictions;
894 	atomic64_t			num_vram_cpu_page_faults;
895 	atomic_t			gpu_reset_counter;
896 	atomic_t			vram_lost_counter;
897 
898 	/* data for buffer migration throttling */
899 	struct {
900 		spinlock_t		lock;
901 		s64			last_update_us;
902 		s64			accum_us; /* accumulated microseconds */
903 		s64			accum_us_vis; /* for visible VRAM */
904 		u32			log2_max_MBps;
905 	} mm_stats;
906 
907 	/* display */
908 	bool				enable_virtual_display;
909 	struct amdgpu_vkms_output       *amdgpu_vkms_output;
910 	struct amdgpu_mode_info		mode_info;
911 	/* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
912 	struct delayed_work         hotplug_work;
913 	struct amdgpu_irq_src		crtc_irq;
914 	struct amdgpu_irq_src		vline0_irq;
915 	struct amdgpu_irq_src		vupdate_irq;
916 	struct amdgpu_irq_src		pageflip_irq;
917 	struct amdgpu_irq_src		hpd_irq;
918 	struct amdgpu_irq_src		dmub_trace_irq;
919 	struct amdgpu_irq_src		dmub_outbox_irq;
920 
921 	/* rings */
922 	u64				fence_context;
923 	unsigned			num_rings;
924 	struct amdgpu_ring		*rings[AMDGPU_MAX_RINGS];
925 	struct dma_fence __rcu		*gang_submit;
926 	bool				ib_pool_ready;
927 	struct amdgpu_sa_manager	ib_pools[AMDGPU_IB_POOL_MAX];
928 	struct amdgpu_sched		gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
929 
930 	/* interrupts */
931 	struct amdgpu_irq		irq;
932 
933 	/* powerplay */
934 	struct amd_powerplay		powerplay;
935 	struct amdgpu_pm		pm;
936 	u64				cg_flags;
937 	u32				pg_flags;
938 
939 	/* nbio */
940 	struct amdgpu_nbio		nbio;
941 
942 	/* hdp */
943 	struct amdgpu_hdp		hdp;
944 
945 	/* smuio */
946 	struct amdgpu_smuio		smuio;
947 
948 	/* mmhub */
949 	struct amdgpu_mmhub		mmhub;
950 
951 	/* gfxhub */
952 	struct amdgpu_gfxhub		gfxhub;
953 
954 	/* gfx */
955 	struct amdgpu_gfx		gfx;
956 
957 	/* sdma */
958 	struct amdgpu_sdma		sdma;
959 
960 	/* lsdma */
961 	struct amdgpu_lsdma		lsdma;
962 
963 	/* uvd */
964 	struct amdgpu_uvd		uvd;
965 
966 	/* vce */
967 	struct amdgpu_vce		vce;
968 
969 	/* vcn */
970 	struct amdgpu_vcn		vcn;
971 
972 	/* jpeg */
973 	struct amdgpu_jpeg		jpeg;
974 
975 	/* vpe */
976 	struct amdgpu_vpe		vpe;
977 
978 	/* umsch */
979 	struct amdgpu_umsch_mm		umsch_mm;
980 	bool				enable_umsch_mm;
981 
982 	/* firmwares */
983 	struct amdgpu_firmware		firmware;
984 
985 	/* PSP */
986 	struct psp_context		psp;
987 
988 	/* GDS */
989 	struct amdgpu_gds		gds;
990 
991 	/* KFD */
992 	struct amdgpu_kfd_dev		kfd;
993 
994 	/* UMC */
995 	struct amdgpu_umc		umc;
996 
997 	/* display related functionality */
998 	struct amdgpu_display_manager dm;
999 
1000 	/* mes */
1001 	bool                            enable_mes;
1002 	bool                            enable_mes_kiq;
1003 	struct amdgpu_mes               mes;
1004 	struct amdgpu_mqd               mqds[AMDGPU_HW_IP_NUM];
1005 
1006 	/* df */
1007 	struct amdgpu_df                df;
1008 
1009 	/* MCA */
1010 	struct amdgpu_mca               mca;
1011 
1012 	struct amdgpu_ip_block          ip_blocks[AMDGPU_MAX_IP_NUM];
1013 	uint32_t		        harvest_ip_mask;
1014 	int				num_ip_blocks;
1015 	struct mutex	mn_lock;
1016 	DECLARE_HASHTABLE(mn_hash, 7);
1017 
1018 	/* tracking pinned memory */
1019 	atomic64_t vram_pin_size;
1020 	atomic64_t visible_pin_size;
1021 	atomic64_t gart_pin_size;
1022 
1023 	/* soc15 register offset based on ip, instance and  segment */
1024 	uint32_t		*reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
1025 	struct amdgpu_ip_map_info	ip_map;
1026 
1027 	/* delayed work_func for deferring clockgating during resume */
1028 	struct delayed_work     delayed_init_work;
1029 
1030 	struct amdgpu_virt	virt;
1031 
1032 	/* link all shadow bo */
1033 	struct list_head                shadow_list;
1034 	struct mutex                    shadow_list_lock;
1035 
1036 	/* record hw reset is performed */
1037 	bool has_hw_reset;
1038 	u8				reset_magic[AMDGPU_RESET_MAGIC_NUM];
1039 
1040 	/* s3/s4 mask */
1041 	bool                            in_suspend;
1042 	bool				in_s3;
1043 	bool				in_s4;
1044 	bool				in_s0ix;
1045 
1046 	enum pp_mp1_state               mp1_state;
1047 	struct amdgpu_doorbell_index doorbell_index;
1048 
1049 	struct mutex			notifier_lock;
1050 
1051 	int asic_reset_res;
1052 	struct work_struct		xgmi_reset_work;
1053 	struct list_head		reset_list;
1054 
1055 	long				gfx_timeout;
1056 	long				sdma_timeout;
1057 	long				video_timeout;
1058 	long				compute_timeout;
1059 
1060 	uint64_t			unique_id;
1061 	uint64_t	df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
1062 
1063 	/* enable runtime pm on the device */
1064 	bool                            in_runpm;
1065 	bool                            has_pr3;
1066 
1067 	bool                            ucode_sysfs_en;
1068 
1069 	struct amdgpu_fru_info		*fru_info;
1070 	atomic_t			throttling_logging_enabled;
1071 	struct ratelimit_state		throttling_logging_rs;
1072 	uint32_t                        ras_hw_enabled;
1073 	uint32_t                        ras_enabled;
1074 
1075 	bool                            no_hw_access;
1076 	struct pci_saved_state          *pci_state;
1077 	pci_channel_state_t		pci_channel_state;
1078 
1079 	/* Track auto wait count on s_barrier settings */
1080 	bool				barrier_has_auto_waitcnt;
1081 
1082 	struct amdgpu_reset_control     *reset_cntl;
1083 	uint32_t                        ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE];
1084 
1085 	bool				ram_is_direct_mapped;
1086 
1087 	struct list_head                ras_list;
1088 
1089 	struct ip_discovery_top         *ip_top;
1090 
1091 	struct amdgpu_reset_domain	*reset_domain;
1092 
1093 	struct mutex			benchmark_mutex;
1094 
1095 	struct amdgpu_reset_info	reset_info;
1096 
1097 	bool                            scpm_enabled;
1098 	uint32_t                        scpm_status;
1099 
1100 	struct work_struct		reset_work;
1101 
1102 	bool                            job_hang;
1103 	bool                            dc_enabled;
1104 	/* Mask of active clusters */
1105 	uint32_t			aid_mask;
1106 
1107 	/* Debug */
1108 	bool                            debug_vm;
1109 	bool                            debug_largebar;
1110 	bool                            debug_disable_soft_recovery;
1111 };
1112 
1113 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev,
1114 					 uint8_t ip, uint8_t inst)
1115 {
1116 	/* This considers only major/minor/rev and ignores
1117 	 * subrevision/variant fields.
1118 	 */
1119 	return adev->ip_versions[ip][inst] & ~0xFFU;
1120 }
1121 
1122 static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev,
1123 					      uint8_t ip, uint8_t inst)
1124 {
1125 	/* This returns full version - major/minor/rev/variant/subrevision */
1126 	return adev->ip_versions[ip][inst];
1127 }
1128 
1129 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
1130 {
1131 	return container_of(ddev, struct amdgpu_device, ddev);
1132 }
1133 
1134 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev)
1135 {
1136 	return &adev->ddev;
1137 }
1138 
1139 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev)
1140 {
1141 	return container_of(bdev, struct amdgpu_device, mman.bdev);
1142 }
1143 
1144 int amdgpu_device_init(struct amdgpu_device *adev,
1145 		       uint32_t flags);
1146 void amdgpu_device_fini_hw(struct amdgpu_device *adev);
1147 void amdgpu_device_fini_sw(struct amdgpu_device *adev);
1148 
1149 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1150 
1151 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
1152 			     void *buf, size_t size, bool write);
1153 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
1154 				 void *buf, size_t size, bool write);
1155 
1156 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1157 			       void *buf, size_t size, bool write);
1158 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev,
1159 			    uint32_t inst, uint32_t reg_addr, char reg_name[],
1160 			    uint32_t expected_value, uint32_t mask);
1161 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
1162 			    uint32_t reg, uint32_t acc_flags);
1163 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev,
1164 				    u64 reg_addr);
1165 void amdgpu_device_wreg(struct amdgpu_device *adev,
1166 			uint32_t reg, uint32_t v,
1167 			uint32_t acc_flags);
1168 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev,
1169 				     u64 reg_addr, u32 reg_data);
1170 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
1171 			     uint32_t reg, uint32_t v, uint32_t xcc_id);
1172 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1173 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1174 
1175 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
1176 				u32 reg_addr);
1177 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
1178 				  u32 reg_addr);
1179 u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev,
1180 				  u64 reg_addr);
1181 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
1182 				 u32 reg_addr, u32 reg_data);
1183 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
1184 				   u32 reg_addr, u64 reg_data);
1185 void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev,
1186 				   u64 reg_addr, u64 reg_data);
1187 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev);
1188 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1189 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1190 
1191 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev);
1192 
1193 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
1194 				 struct amdgpu_reset_context *reset_context);
1195 
1196 int amdgpu_do_asic_reset(struct list_head *device_list_handle,
1197 			 struct amdgpu_reset_context *reset_context);
1198 
1199 int emu_soc_asic_init(struct amdgpu_device *adev);
1200 
1201 /*
1202  * Registers read & write functions.
1203  */
1204 #define AMDGPU_REGS_NO_KIQ    (1<<1)
1205 #define AMDGPU_REGS_RLC	(1<<2)
1206 
1207 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1208 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1209 
1210 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))
1211 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))
1212 
1213 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1214 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1215 
1216 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
1217 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
1218 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
1219 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1220 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1221 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1222 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1223 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1224 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1225 #define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg))
1226 #define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v))
1227 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1228 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1229 #define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg))
1230 #define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v))
1231 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1232 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1233 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1234 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1235 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1236 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1237 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1238 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1239 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1240 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1241 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1242 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1243 #define WREG32_P(reg, val, mask)				\
1244 	do {							\
1245 		uint32_t tmp_ = RREG32(reg);			\
1246 		tmp_ &= (mask);					\
1247 		tmp_ |= ((val) & ~(mask));			\
1248 		WREG32(reg, tmp_);				\
1249 	} while (0)
1250 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1251 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1252 #define WREG32_PLL_P(reg, val, mask)				\
1253 	do {							\
1254 		uint32_t tmp_ = RREG32_PLL(reg);		\
1255 		tmp_ &= (mask);					\
1256 		tmp_ |= ((val) & ~(mask));			\
1257 		WREG32_PLL(reg, tmp_);				\
1258 	} while (0)
1259 
1260 #define WREG32_SMC_P(_Reg, _Val, _Mask)                         \
1261 	do {                                                    \
1262 		u32 tmp = RREG32_SMC(_Reg);                     \
1263 		tmp &= (_Mask);                                 \
1264 		tmp |= ((_Val) & ~(_Mask));                     \
1265 		WREG32_SMC(_Reg, tmp);                          \
1266 	} while (0)
1267 
1268 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
1269 
1270 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1271 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1272 
1273 #define REG_SET_FIELD(orig_val, reg, field, field_val)			\
1274 	(((orig_val) & ~REG_FIELD_MASK(reg, field)) |			\
1275 	 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1276 
1277 #define REG_GET_FIELD(value, reg, field)				\
1278 	(((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1279 
1280 #define WREG32_FIELD(reg, field, val)	\
1281 	WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1282 
1283 #define WREG32_FIELD_OFFSET(reg, offset, field, val)	\
1284 	WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1285 
1286 /*
1287  * BIOS helpers.
1288  */
1289 #define RBIOS8(i) (adev->bios[i])
1290 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1291 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1292 
1293 /*
1294  * ASICs macro.
1295  */
1296 #define amdgpu_asic_set_vga_state(adev, state) \
1297     ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0)
1298 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1299 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1300 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1301 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1302 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1303 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1304 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1305 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1306 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1307 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1308 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1309 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1310 #define amdgpu_asic_flush_hdp(adev, r) \
1311 	((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r)))
1312 #define amdgpu_asic_invalidate_hdp(adev, r) \
1313 	((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \
1314 	 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0))
1315 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1316 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1317 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1318 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1319 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1320 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
1321 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
1322 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
1323 	((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
1324 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c))
1325 
1326 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter))
1327 
1328 #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i))
1329 #define for_each_inst(i, inst_mask)        \
1330 	for (i = ffs(inst_mask); i-- != 0; \
1331 	     i = ffs(inst_mask & BIT_MASK_UPPER(i + 1)))
1332 
1333 /* Common functions */
1334 bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
1335 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1336 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1337 			      struct amdgpu_job *job,
1338 			      struct amdgpu_reset_context *reset_context);
1339 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1340 int amdgpu_device_pci_reset(struct amdgpu_device *adev);
1341 bool amdgpu_device_need_post(struct amdgpu_device *adev);
1342 bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev);
1343 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);
1344 
1345 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1346 				  u64 num_vis_bytes);
1347 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1348 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1349 					     const u32 *registers,
1350 					     const u32 array_size);
1351 
1352 int amdgpu_device_mode1_reset(struct amdgpu_device *adev);
1353 bool amdgpu_device_supports_atpx(struct drm_device *dev);
1354 bool amdgpu_device_supports_px(struct drm_device *dev);
1355 bool amdgpu_device_supports_boco(struct drm_device *dev);
1356 bool amdgpu_device_supports_smart_shift(struct drm_device *dev);
1357 bool amdgpu_device_supports_baco(struct drm_device *dev);
1358 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1359 				      struct amdgpu_device *peer_adev);
1360 int amdgpu_device_baco_enter(struct drm_device *dev);
1361 int amdgpu_device_baco_exit(struct drm_device *dev);
1362 
1363 void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
1364 		struct amdgpu_ring *ring);
1365 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
1366 		struct amdgpu_ring *ring);
1367 
1368 void amdgpu_device_halt(struct amdgpu_device *adev);
1369 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
1370 				u32 reg);
1371 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
1372 				u32 reg, u32 v);
1373 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
1374 					    struct dma_fence *gang);
1375 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev);
1376 
1377 /* atpx handler */
1378 #if defined(CONFIG_VGA_SWITCHEROO)
1379 void amdgpu_register_atpx_handler(void);
1380 void amdgpu_unregister_atpx_handler(void);
1381 bool amdgpu_has_atpx_dgpu_power_cntl(void);
1382 bool amdgpu_is_atpx_hybrid(void);
1383 bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1384 bool amdgpu_has_atpx(void);
1385 #else
1386 static inline void amdgpu_register_atpx_handler(void) {}
1387 static inline void amdgpu_unregister_atpx_handler(void) {}
1388 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1389 static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1390 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
1391 static inline bool amdgpu_has_atpx(void) { return false; }
1392 #endif
1393 
1394 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1395 void *amdgpu_atpx_get_dhandle(void);
1396 #else
1397 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1398 #endif
1399 
1400 /*
1401  * KMS
1402  */
1403 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1404 extern const int amdgpu_max_kms_ioctl;
1405 
1406 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags);
1407 void amdgpu_driver_unload_kms(struct drm_device *dev);
1408 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1409 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1410 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1411 				 struct drm_file *file_priv);
1412 void amdgpu_driver_release_kms(struct drm_device *dev);
1413 
1414 int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1415 int amdgpu_device_prepare(struct drm_device *dev);
1416 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
1417 int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
1418 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
1419 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
1420 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
1421 int amdgpu_info_ioctl(struct drm_device *dev, void *data,
1422 		      struct drm_file *filp);
1423 
1424 /*
1425  * functions used by amdgpu_encoder.c
1426  */
1427 struct amdgpu_afmt_acr {
1428 	u32 clock;
1429 
1430 	int n_32khz;
1431 	int cts_32khz;
1432 
1433 	int n_44_1khz;
1434 	int cts_44_1khz;
1435 
1436 	int n_48khz;
1437 	int cts_48khz;
1438 
1439 };
1440 
1441 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1442 
1443 /* amdgpu_acpi.c */
1444 
1445 struct amdgpu_numa_info {
1446 	uint64_t size;
1447 	int pxm;
1448 	int nid;
1449 };
1450 
1451 /* ATCS Device/Driver State */
1452 #define AMDGPU_ATCS_PSC_DEV_STATE_D0		0
1453 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT	3
1454 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR		0
1455 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR	1
1456 
1457 #if defined(CONFIG_ACPI)
1458 int amdgpu_acpi_init(struct amdgpu_device *adev);
1459 void amdgpu_acpi_fini(struct amdgpu_device *adev);
1460 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1461 bool amdgpu_acpi_is_power_shift_control_supported(void);
1462 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1463 						u8 perf_req, bool advertise);
1464 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1465 				    u8 dev_state, bool drv_state);
1466 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state);
1467 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1468 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset,
1469 			     u64 *tmr_size);
1470 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id,
1471 			     struct amdgpu_numa_info *numa_info);
1472 
1473 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
1474 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev);
1475 void amdgpu_acpi_detect(void);
1476 void amdgpu_acpi_release(void);
1477 #else
1478 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1479 static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev,
1480 					   u64 *tmr_offset, u64 *tmr_size)
1481 {
1482 	return -EINVAL;
1483 }
1484 static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev,
1485 					   int xcc_id,
1486 					   struct amdgpu_numa_info *numa_info)
1487 {
1488 	return -EINVAL;
1489 }
1490 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1491 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; }
1492 static inline void amdgpu_acpi_detect(void) { }
1493 static inline void amdgpu_acpi_release(void) { }
1494 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
1495 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1496 						  u8 dev_state, bool drv_state) { return 0; }
1497 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev,
1498 						 enum amdgpu_ss ss_state) { return 0; }
1499 #endif
1500 
1501 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND)
1502 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);
1503 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
1504 #else
1505 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }
1506 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }
1507 #endif
1508 
1509 #if defined(CONFIG_DRM_AMD_DC)
1510 int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1511 #else
1512 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1513 #endif
1514 
1515 
1516 void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1517 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1518 
1519 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev,
1520 					   pci_channel_state_t state);
1521 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev);
1522 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev);
1523 void amdgpu_pci_resume(struct pci_dev *pdev);
1524 
1525 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);
1526 bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
1527 
1528 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev);
1529 
1530 int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1531 			       enum amd_clockgating_state state);
1532 int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
1533 			       enum amd_powergating_state state);
1534 
1535 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev)
1536 {
1537 	return amdgpu_gpu_recovery != 0 &&
1538 		adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT &&
1539 		adev->compute_timeout != MAX_SCHEDULE_TIMEOUT &&
1540 		adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT &&
1541 		adev->video_timeout != MAX_SCHEDULE_TIMEOUT;
1542 }
1543 
1544 #include "amdgpu_object.h"
1545 
1546 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
1547 {
1548        return adev->gmc.tmz_enabled;
1549 }
1550 
1551 int amdgpu_in_reset(struct amdgpu_device *adev);
1552 
1553 extern const struct attribute_group amdgpu_vram_mgr_attr_group;
1554 extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
1555 extern const struct attribute_group amdgpu_flash_attr_group;
1556 
1557 #endif
1558