1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include <linux/atomic.h> 32 #include <linux/wait.h> 33 #include <linux/list.h> 34 #include <linux/kref.h> 35 #include <linux/rbtree.h> 36 #include <linux/hashtable.h> 37 #include <linux/dma-fence.h> 38 39 #include <drm/ttm/ttm_bo_api.h> 40 #include <drm/ttm/ttm_bo_driver.h> 41 #include <drm/ttm/ttm_placement.h> 42 #include <drm/ttm/ttm_module.h> 43 #include <drm/ttm/ttm_execbuf_util.h> 44 45 #include <drm/drmP.h> 46 #include <drm/drm_gem.h> 47 #include <drm/amdgpu_drm.h> 48 49 #include <kgd_kfd_interface.h> 50 51 #include "amd_shared.h" 52 #include "amdgpu_mode.h" 53 #include "amdgpu_ih.h" 54 #include "amdgpu_irq.h" 55 #include "amdgpu_ucode.h" 56 #include "amdgpu_ttm.h" 57 #include "amdgpu_psp.h" 58 #include "amdgpu_gds.h" 59 #include "amdgpu_sync.h" 60 #include "amdgpu_ring.h" 61 #include "amdgpu_vm.h" 62 #include "amd_powerplay.h" 63 #include "amdgpu_dpm.h" 64 #include "amdgpu_acp.h" 65 #include "amdgpu_uvd.h" 66 #include "amdgpu_vce.h" 67 #include "amdgpu_vcn.h" 68 #include "amdgpu_mn.h" 69 #include "amdgpu_dm.h" 70 71 #include "gpu_scheduler.h" 72 #include "amdgpu_virt.h" 73 #include "amdgpu_gart.h" 74 75 /* 76 * Modules parameters. 77 */ 78 extern int amdgpu_modeset; 79 extern int amdgpu_vram_limit; 80 extern int amdgpu_vis_vram_limit; 81 extern int amdgpu_gart_size; 82 extern int amdgpu_gtt_size; 83 extern int amdgpu_moverate; 84 extern int amdgpu_benchmarking; 85 extern int amdgpu_testing; 86 extern int amdgpu_audio; 87 extern int amdgpu_disp_priority; 88 extern int amdgpu_hw_i2c; 89 extern int amdgpu_pcie_gen2; 90 extern int amdgpu_msi; 91 extern int amdgpu_lockup_timeout; 92 extern int amdgpu_dpm; 93 extern int amdgpu_fw_load_type; 94 extern int amdgpu_aspm; 95 extern int amdgpu_runtime_pm; 96 extern uint amdgpu_ip_block_mask; 97 extern int amdgpu_bapm; 98 extern int amdgpu_deep_color; 99 extern int amdgpu_vm_size; 100 extern int amdgpu_vm_block_size; 101 extern int amdgpu_vm_fragment_size; 102 extern int amdgpu_vm_fault_stop; 103 extern int amdgpu_vm_debug; 104 extern int amdgpu_vm_update_mode; 105 extern int amdgpu_dc; 106 extern int amdgpu_sched_jobs; 107 extern int amdgpu_sched_hw_submission; 108 extern int amdgpu_no_evict; 109 extern int amdgpu_direct_gma_size; 110 extern uint amdgpu_pcie_gen_cap; 111 extern uint amdgpu_pcie_lane_cap; 112 extern uint amdgpu_cg_mask; 113 extern uint amdgpu_pg_mask; 114 extern uint amdgpu_sdma_phase_quantum; 115 extern char *amdgpu_disable_cu; 116 extern char *amdgpu_virtual_display; 117 extern uint amdgpu_pp_feature_mask; 118 extern int amdgpu_vram_page_split; 119 extern int amdgpu_ngg; 120 extern int amdgpu_prim_buf_per_se; 121 extern int amdgpu_pos_buf_per_se; 122 extern int amdgpu_cntl_sb_buf_per_se; 123 extern int amdgpu_param_buf_per_se; 124 extern int amdgpu_job_hang_limit; 125 extern int amdgpu_lbpw; 126 127 #ifdef CONFIG_DRM_AMDGPU_SI 128 extern int amdgpu_si_support; 129 #endif 130 #ifdef CONFIG_DRM_AMDGPU_CIK 131 extern int amdgpu_cik_support; 132 #endif 133 134 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 135 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 136 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 137 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 138 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 139 #define AMDGPU_IB_POOL_SIZE 16 140 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 141 #define AMDGPUFB_CONN_LIMIT 4 142 #define AMDGPU_BIOS_NUM_SCRATCH 16 143 144 /* max number of IP instances */ 145 #define AMDGPU_MAX_SDMA_INSTANCES 2 146 147 /* hard reset data */ 148 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 149 150 /* reset flags */ 151 #define AMDGPU_RESET_GFX (1 << 0) 152 #define AMDGPU_RESET_COMPUTE (1 << 1) 153 #define AMDGPU_RESET_DMA (1 << 2) 154 #define AMDGPU_RESET_CP (1 << 3) 155 #define AMDGPU_RESET_GRBM (1 << 4) 156 #define AMDGPU_RESET_DMA1 (1 << 5) 157 #define AMDGPU_RESET_RLC (1 << 6) 158 #define AMDGPU_RESET_SEM (1 << 7) 159 #define AMDGPU_RESET_IH (1 << 8) 160 #define AMDGPU_RESET_VMC (1 << 9) 161 #define AMDGPU_RESET_MC (1 << 10) 162 #define AMDGPU_RESET_DISPLAY (1 << 11) 163 #define AMDGPU_RESET_UVD (1 << 12) 164 #define AMDGPU_RESET_VCE (1 << 13) 165 #define AMDGPU_RESET_VCE1 (1 << 14) 166 167 /* GFX current status */ 168 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 169 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 170 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 171 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 172 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 173 174 /* max cursor sizes (in pixels) */ 175 #define CIK_CURSOR_WIDTH 128 176 #define CIK_CURSOR_HEIGHT 128 177 178 struct amdgpu_device; 179 struct amdgpu_ib; 180 struct amdgpu_cs_parser; 181 struct amdgpu_job; 182 struct amdgpu_irq_src; 183 struct amdgpu_fpriv; 184 struct amdgpu_bo_va_mapping; 185 186 enum amdgpu_cp_irq { 187 AMDGPU_CP_IRQ_GFX_EOP = 0, 188 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 189 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 190 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 191 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 192 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 193 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 194 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 195 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 196 197 AMDGPU_CP_IRQ_LAST 198 }; 199 200 enum amdgpu_sdma_irq { 201 AMDGPU_SDMA_IRQ_TRAP0 = 0, 202 AMDGPU_SDMA_IRQ_TRAP1, 203 204 AMDGPU_SDMA_IRQ_LAST 205 }; 206 207 enum amdgpu_thermal_irq { 208 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 209 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 210 211 AMDGPU_THERMAL_IRQ_LAST 212 }; 213 214 enum amdgpu_kiq_irq { 215 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 216 AMDGPU_CP_KIQ_IRQ_LAST 217 }; 218 219 int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 220 enum amd_ip_block_type block_type, 221 enum amd_clockgating_state state); 222 int amdgpu_set_powergating_state(struct amdgpu_device *adev, 223 enum amd_ip_block_type block_type, 224 enum amd_powergating_state state); 225 void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags); 226 int amdgpu_wait_for_idle(struct amdgpu_device *adev, 227 enum amd_ip_block_type block_type); 228 bool amdgpu_is_idle(struct amdgpu_device *adev, 229 enum amd_ip_block_type block_type); 230 231 #define AMDGPU_MAX_IP_NUM 16 232 233 struct amdgpu_ip_block_status { 234 bool valid; 235 bool sw; 236 bool hw; 237 bool late_initialized; 238 bool hang; 239 }; 240 241 struct amdgpu_ip_block_version { 242 const enum amd_ip_block_type type; 243 const u32 major; 244 const u32 minor; 245 const u32 rev; 246 const struct amd_ip_funcs *funcs; 247 }; 248 249 struct amdgpu_ip_block { 250 struct amdgpu_ip_block_status status; 251 const struct amdgpu_ip_block_version *version; 252 }; 253 254 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 255 enum amd_ip_block_type type, 256 u32 major, u32 minor); 257 258 struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, 259 enum amd_ip_block_type type); 260 261 int amdgpu_ip_block_add(struct amdgpu_device *adev, 262 const struct amdgpu_ip_block_version *ip_block_version); 263 264 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 265 struct amdgpu_buffer_funcs { 266 /* maximum bytes in a single operation */ 267 uint32_t copy_max_bytes; 268 269 /* number of dw to reserve per operation */ 270 unsigned copy_num_dw; 271 272 /* used for buffer migration */ 273 void (*emit_copy_buffer)(struct amdgpu_ib *ib, 274 /* src addr in bytes */ 275 uint64_t src_offset, 276 /* dst addr in bytes */ 277 uint64_t dst_offset, 278 /* number of byte to transfer */ 279 uint32_t byte_count); 280 281 /* maximum bytes in a single operation */ 282 uint32_t fill_max_bytes; 283 284 /* number of dw to reserve per operation */ 285 unsigned fill_num_dw; 286 287 /* used for buffer clearing */ 288 void (*emit_fill_buffer)(struct amdgpu_ib *ib, 289 /* value to write to memory */ 290 uint32_t src_data, 291 /* dst addr in bytes */ 292 uint64_t dst_offset, 293 /* number of byte to fill */ 294 uint32_t byte_count); 295 }; 296 297 /* provided by hw blocks that can write ptes, e.g., sdma */ 298 struct amdgpu_vm_pte_funcs { 299 /* number of dw to reserve per operation */ 300 unsigned copy_pte_num_dw; 301 302 /* copy pte entries from GART */ 303 void (*copy_pte)(struct amdgpu_ib *ib, 304 uint64_t pe, uint64_t src, 305 unsigned count); 306 307 /* write pte one entry at a time with addr mapping */ 308 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, 309 uint64_t value, unsigned count, 310 uint32_t incr); 311 312 /* maximum nums of PTEs/PDEs in a single operation */ 313 uint32_t set_max_nums_pte_pde; 314 315 /* number of dw to reserve per operation */ 316 unsigned set_pte_pde_num_dw; 317 318 /* for linear pte/pde updates without addr mapping */ 319 void (*set_pte_pde)(struct amdgpu_ib *ib, 320 uint64_t pe, 321 uint64_t addr, unsigned count, 322 uint32_t incr, uint64_t flags); 323 }; 324 325 /* provided by the gmc block */ 326 struct amdgpu_gart_funcs { 327 /* flush the vm tlb via mmio */ 328 void (*flush_gpu_tlb)(struct amdgpu_device *adev, 329 uint32_t vmid); 330 /* write pte/pde updates using the cpu */ 331 int (*set_pte_pde)(struct amdgpu_device *adev, 332 void *cpu_pt_addr, /* cpu addr of page table */ 333 uint32_t gpu_page_idx, /* pte/pde to update */ 334 uint64_t addr, /* addr to write into pte/pde */ 335 uint64_t flags); /* access flags */ 336 /* enable/disable PRT support */ 337 void (*set_prt)(struct amdgpu_device *adev, bool enable); 338 /* set pte flags based per asic */ 339 uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev, 340 uint32_t flags); 341 /* get the pde for a given mc addr */ 342 u64 (*get_vm_pde)(struct amdgpu_device *adev, u64 addr); 343 uint32_t (*get_invalidate_req)(unsigned int vm_id); 344 }; 345 346 /* provided by the ih block */ 347 struct amdgpu_ih_funcs { 348 /* ring read/write ptr handling, called from interrupt context */ 349 u32 (*get_wptr)(struct amdgpu_device *adev); 350 bool (*prescreen_iv)(struct amdgpu_device *adev); 351 void (*decode_iv)(struct amdgpu_device *adev, 352 struct amdgpu_iv_entry *entry); 353 void (*set_rptr)(struct amdgpu_device *adev); 354 }; 355 356 /* 357 * BIOS. 358 */ 359 bool amdgpu_get_bios(struct amdgpu_device *adev); 360 bool amdgpu_read_bios(struct amdgpu_device *adev); 361 362 /* 363 * Dummy page 364 */ 365 struct amdgpu_dummy_page { 366 struct page *page; 367 dma_addr_t addr; 368 }; 369 int amdgpu_dummy_page_init(struct amdgpu_device *adev); 370 void amdgpu_dummy_page_fini(struct amdgpu_device *adev); 371 372 373 /* 374 * Clocks 375 */ 376 377 #define AMDGPU_MAX_PPLL 3 378 379 struct amdgpu_clock { 380 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 381 struct amdgpu_pll spll; 382 struct amdgpu_pll mpll; 383 /* 10 Khz units */ 384 uint32_t default_mclk; 385 uint32_t default_sclk; 386 uint32_t default_dispclk; 387 uint32_t current_dispclk; 388 uint32_t dp_extclk; 389 uint32_t max_pixel_clock; 390 }; 391 392 /* 393 * GEM. 394 */ 395 396 #define AMDGPU_GEM_DOMAIN_MAX 0x3 397 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) 398 399 void amdgpu_gem_object_free(struct drm_gem_object *obj); 400 int amdgpu_gem_object_open(struct drm_gem_object *obj, 401 struct drm_file *file_priv); 402 void amdgpu_gem_object_close(struct drm_gem_object *obj, 403 struct drm_file *file_priv); 404 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 405 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); 406 struct drm_gem_object * 407 amdgpu_gem_prime_import_sg_table(struct drm_device *dev, 408 struct dma_buf_attachment *attach, 409 struct sg_table *sg); 410 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, 411 struct drm_gem_object *gobj, 412 int flags); 413 int amdgpu_gem_prime_pin(struct drm_gem_object *obj); 414 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); 415 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); 416 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); 417 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 418 int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); 419 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); 420 421 /* sub-allocation manager, it has to be protected by another lock. 422 * By conception this is an helper for other part of the driver 423 * like the indirect buffer or semaphore, which both have their 424 * locking. 425 * 426 * Principe is simple, we keep a list of sub allocation in offset 427 * order (first entry has offset == 0, last entry has the highest 428 * offset). 429 * 430 * When allocating new object we first check if there is room at 431 * the end total_size - (last_object_offset + last_object_size) >= 432 * alloc_size. If so we allocate new object there. 433 * 434 * When there is not enough room at the end, we start waiting for 435 * each sub object until we reach object_offset+object_size >= 436 * alloc_size, this object then become the sub object we return. 437 * 438 * Alignment can't be bigger than page size. 439 * 440 * Hole are not considered for allocation to keep things simple. 441 * Assumption is that there won't be hole (all object on same 442 * alignment). 443 */ 444 445 #define AMDGPU_SA_NUM_FENCE_LISTS 32 446 447 struct amdgpu_sa_manager { 448 wait_queue_head_t wq; 449 struct amdgpu_bo *bo; 450 struct list_head *hole; 451 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 452 struct list_head olist; 453 unsigned size; 454 uint64_t gpu_addr; 455 void *cpu_ptr; 456 uint32_t domain; 457 uint32_t align; 458 }; 459 460 /* sub-allocation buffer */ 461 struct amdgpu_sa_bo { 462 struct list_head olist; 463 struct list_head flist; 464 struct amdgpu_sa_manager *manager; 465 unsigned soffset; 466 unsigned eoffset; 467 struct dma_fence *fence; 468 }; 469 470 /* 471 * GEM objects. 472 */ 473 void amdgpu_gem_force_release(struct amdgpu_device *adev); 474 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 475 int alignment, u32 initial_domain, 476 u64 flags, bool kernel, 477 struct reservation_object *resv, 478 struct drm_gem_object **obj); 479 480 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 481 struct drm_device *dev, 482 struct drm_mode_create_dumb *args); 483 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 484 struct drm_device *dev, 485 uint32_t handle, uint64_t *offset_p); 486 int amdgpu_fence_slab_init(void); 487 void amdgpu_fence_slab_fini(void); 488 489 /* 490 * VMHUB structures, functions & helpers 491 */ 492 struct amdgpu_vmhub { 493 uint32_t ctx0_ptb_addr_lo32; 494 uint32_t ctx0_ptb_addr_hi32; 495 uint32_t vm_inv_eng0_req; 496 uint32_t vm_inv_eng0_ack; 497 uint32_t vm_context0_cntl; 498 uint32_t vm_l2_pro_fault_status; 499 uint32_t vm_l2_pro_fault_cntl; 500 }; 501 502 /* 503 * GPU MC structures, functions & helpers 504 */ 505 struct amdgpu_mc { 506 resource_size_t aper_size; 507 resource_size_t aper_base; 508 resource_size_t agp_base; 509 /* for some chips with <= 32MB we need to lie 510 * about vram size near mc fb location */ 511 u64 mc_vram_size; 512 u64 visible_vram_size; 513 u64 gart_size; 514 u64 gart_start; 515 u64 gart_end; 516 u64 vram_start; 517 u64 vram_end; 518 unsigned vram_width; 519 u64 real_vram_size; 520 int vram_mtrr; 521 u64 mc_mask; 522 const struct firmware *fw; /* MC firmware */ 523 uint32_t fw_version; 524 struct amdgpu_irq_src vm_fault; 525 uint32_t vram_type; 526 uint32_t srbm_soft_reset; 527 bool prt_warning; 528 uint64_t stolen_size; 529 /* apertures */ 530 u64 shared_aperture_start; 531 u64 shared_aperture_end; 532 u64 private_aperture_start; 533 u64 private_aperture_end; 534 /* protects concurrent invalidation */ 535 spinlock_t invalidate_lock; 536 }; 537 538 /* 539 * GPU doorbell structures, functions & helpers 540 */ 541 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 542 { 543 AMDGPU_DOORBELL_KIQ = 0x000, 544 AMDGPU_DOORBELL_HIQ = 0x001, 545 AMDGPU_DOORBELL_DIQ = 0x002, 546 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 547 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 548 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 549 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 550 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 551 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 552 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 553 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 554 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 555 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 556 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 557 AMDGPU_DOORBELL_IH = 0x1E8, 558 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 559 AMDGPU_DOORBELL_INVALID = 0xFFFF 560 } AMDGPU_DOORBELL_ASSIGNMENT; 561 562 struct amdgpu_doorbell { 563 /* doorbell mmio */ 564 resource_size_t base; 565 resource_size_t size; 566 u32 __iomem *ptr; 567 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 568 }; 569 570 /* 571 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space 572 */ 573 typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT 574 { 575 /* 576 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in 577 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range. 578 * Compute related doorbells are allocated from 0x00 to 0x8a 579 */ 580 581 582 /* kernel scheduling */ 583 AMDGPU_DOORBELL64_KIQ = 0x00, 584 585 /* HSA interface queue and debug queue */ 586 AMDGPU_DOORBELL64_HIQ = 0x01, 587 AMDGPU_DOORBELL64_DIQ = 0x02, 588 589 /* Compute engines */ 590 AMDGPU_DOORBELL64_MEC_RING0 = 0x03, 591 AMDGPU_DOORBELL64_MEC_RING1 = 0x04, 592 AMDGPU_DOORBELL64_MEC_RING2 = 0x05, 593 AMDGPU_DOORBELL64_MEC_RING3 = 0x06, 594 AMDGPU_DOORBELL64_MEC_RING4 = 0x07, 595 AMDGPU_DOORBELL64_MEC_RING5 = 0x08, 596 AMDGPU_DOORBELL64_MEC_RING6 = 0x09, 597 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a, 598 599 /* User queue doorbell range (128 doorbells) */ 600 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b, 601 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a, 602 603 /* Graphics engine */ 604 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b, 605 606 /* 607 * Other graphics doorbells can be allocated here: from 0x8c to 0xef 608 * Graphics voltage island aperture 1 609 * default non-graphics QWORD index is 0xF0 - 0xFF inclusive 610 */ 611 612 /* sDMA engines */ 613 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0, 614 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1, 615 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2, 616 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3, 617 618 /* Interrupt handler */ 619 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */ 620 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */ 621 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */ 622 623 /* VCN engine use 32 bits doorbell */ 624 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ 625 AMDGPU_DOORBELL64_VCN2_3 = 0xF9, 626 AMDGPU_DOORBELL64_VCN4_5 = 0xFA, 627 AMDGPU_DOORBELL64_VCN6_7 = 0xFB, 628 629 /* overlap the doorbell assignment with VCN as they are mutually exclusive 630 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD 631 */ 632 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8, 633 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9, 634 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA, 635 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB, 636 637 AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC, 638 AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD, 639 AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE, 640 AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF, 641 642 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF, 643 AMDGPU_DOORBELL64_INVALID = 0xFFFF 644 } AMDGPU_DOORBELL64_ASSIGNMENT; 645 646 647 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 648 phys_addr_t *aperture_base, 649 size_t *aperture_size, 650 size_t *start_offset); 651 652 /* 653 * IRQS. 654 */ 655 656 struct amdgpu_flip_work { 657 struct delayed_work flip_work; 658 struct work_struct unpin_work; 659 struct amdgpu_device *adev; 660 int crtc_id; 661 u32 target_vblank; 662 uint64_t base; 663 struct drm_pending_vblank_event *event; 664 struct amdgpu_bo *old_abo; 665 struct dma_fence *excl; 666 unsigned shared_count; 667 struct dma_fence **shared; 668 struct dma_fence_cb cb; 669 bool async; 670 }; 671 672 673 /* 674 * CP & rings. 675 */ 676 677 struct amdgpu_ib { 678 struct amdgpu_sa_bo *sa_bo; 679 uint32_t length_dw; 680 uint64_t gpu_addr; 681 uint32_t *ptr; 682 uint32_t flags; 683 }; 684 685 extern const struct amd_sched_backend_ops amdgpu_sched_ops; 686 687 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, 688 struct amdgpu_job **job, struct amdgpu_vm *vm); 689 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, 690 struct amdgpu_job **job); 691 692 void amdgpu_job_free_resources(struct amdgpu_job *job); 693 void amdgpu_job_free(struct amdgpu_job *job); 694 int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, 695 struct amd_sched_entity *entity, void *owner, 696 struct dma_fence **f); 697 698 /* 699 * Queue manager 700 */ 701 struct amdgpu_queue_mapper { 702 int hw_ip; 703 struct mutex lock; 704 /* protected by lock */ 705 struct amdgpu_ring *queue_map[AMDGPU_MAX_RINGS]; 706 }; 707 708 struct amdgpu_queue_mgr { 709 struct amdgpu_queue_mapper mapper[AMDGPU_MAX_IP_NUM]; 710 }; 711 712 int amdgpu_queue_mgr_init(struct amdgpu_device *adev, 713 struct amdgpu_queue_mgr *mgr); 714 int amdgpu_queue_mgr_fini(struct amdgpu_device *adev, 715 struct amdgpu_queue_mgr *mgr); 716 int amdgpu_queue_mgr_map(struct amdgpu_device *adev, 717 struct amdgpu_queue_mgr *mgr, 718 int hw_ip, int instance, int ring, 719 struct amdgpu_ring **out_ring); 720 721 /* 722 * context related structures 723 */ 724 725 struct amdgpu_ctx_ring { 726 uint64_t sequence; 727 struct dma_fence **fences; 728 struct amd_sched_entity entity; 729 }; 730 731 struct amdgpu_ctx { 732 struct kref refcount; 733 struct amdgpu_device *adev; 734 struct amdgpu_queue_mgr queue_mgr; 735 unsigned reset_counter; 736 spinlock_t ring_lock; 737 struct dma_fence **fences; 738 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; 739 bool preamble_presented; 740 }; 741 742 struct amdgpu_ctx_mgr { 743 struct amdgpu_device *adev; 744 struct mutex lock; 745 /* protected by lock */ 746 struct idr ctx_handles; 747 }; 748 749 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 750 int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 751 752 int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 753 struct dma_fence *fence, uint64_t *seq); 754 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 755 struct amdgpu_ring *ring, uint64_t seq); 756 757 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 758 struct drm_file *filp); 759 760 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 761 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 762 763 /* 764 * file private structure 765 */ 766 767 struct amdgpu_fpriv { 768 struct amdgpu_vm vm; 769 struct amdgpu_bo_va *prt_va; 770 struct amdgpu_bo_va *csa_va; 771 struct mutex bo_list_lock; 772 struct idr bo_list_handles; 773 struct amdgpu_ctx_mgr ctx_mgr; 774 u32 vram_lost_counter; 775 }; 776 777 /* 778 * residency list 779 */ 780 struct amdgpu_bo_list_entry { 781 struct amdgpu_bo *robj; 782 struct ttm_validate_buffer tv; 783 struct amdgpu_bo_va *bo_va; 784 uint32_t priority; 785 struct page **user_pages; 786 int user_invalidated; 787 }; 788 789 struct amdgpu_bo_list { 790 struct mutex lock; 791 struct rcu_head rhead; 792 struct kref refcount; 793 struct amdgpu_bo *gds_obj; 794 struct amdgpu_bo *gws_obj; 795 struct amdgpu_bo *oa_obj; 796 unsigned first_userptr; 797 unsigned num_entries; 798 struct amdgpu_bo_list_entry *array; 799 }; 800 801 struct amdgpu_bo_list * 802 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); 803 void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list, 804 struct list_head *validated); 805 void amdgpu_bo_list_put(struct amdgpu_bo_list *list); 806 void amdgpu_bo_list_free(struct amdgpu_bo_list *list); 807 808 /* 809 * GFX stuff 810 */ 811 #include "clearstate_defs.h" 812 813 struct amdgpu_rlc_funcs { 814 void (*enter_safe_mode)(struct amdgpu_device *adev); 815 void (*exit_safe_mode)(struct amdgpu_device *adev); 816 }; 817 818 struct amdgpu_rlc { 819 /* for power gating */ 820 struct amdgpu_bo *save_restore_obj; 821 uint64_t save_restore_gpu_addr; 822 volatile uint32_t *sr_ptr; 823 const u32 *reg_list; 824 u32 reg_list_size; 825 /* for clear state */ 826 struct amdgpu_bo *clear_state_obj; 827 uint64_t clear_state_gpu_addr; 828 volatile uint32_t *cs_ptr; 829 const struct cs_section_def *cs_data; 830 u32 clear_state_size; 831 /* for cp tables */ 832 struct amdgpu_bo *cp_table_obj; 833 uint64_t cp_table_gpu_addr; 834 volatile uint32_t *cp_table_ptr; 835 u32 cp_table_size; 836 837 /* safe mode for updating CG/PG state */ 838 bool in_safe_mode; 839 const struct amdgpu_rlc_funcs *funcs; 840 841 /* for firmware data */ 842 u32 save_and_restore_offset; 843 u32 clear_state_descriptor_offset; 844 u32 avail_scratch_ram_locations; 845 u32 reg_restore_list_size; 846 u32 reg_list_format_start; 847 u32 reg_list_format_separate_start; 848 u32 starting_offsets_start; 849 u32 reg_list_format_size_bytes; 850 u32 reg_list_size_bytes; 851 852 u32 *register_list_format; 853 u32 *register_restore; 854 }; 855 856 #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES 857 858 struct amdgpu_mec { 859 struct amdgpu_bo *hpd_eop_obj; 860 u64 hpd_eop_gpu_addr; 861 struct amdgpu_bo *mec_fw_obj; 862 u64 mec_fw_gpu_addr; 863 u32 num_mec; 864 u32 num_pipe_per_mec; 865 u32 num_queue_per_pipe; 866 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1]; 867 868 /* These are the resources for which amdgpu takes ownership */ 869 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 870 }; 871 872 struct amdgpu_kiq { 873 u64 eop_gpu_addr; 874 struct amdgpu_bo *eop_obj; 875 struct mutex ring_mutex; 876 struct amdgpu_ring ring; 877 struct amdgpu_irq_src irq; 878 }; 879 880 /* 881 * GPU scratch registers structures, functions & helpers 882 */ 883 struct amdgpu_scratch { 884 unsigned num_reg; 885 uint32_t reg_base; 886 uint32_t free_mask; 887 }; 888 889 /* 890 * GFX configurations 891 */ 892 #define AMDGPU_GFX_MAX_SE 4 893 #define AMDGPU_GFX_MAX_SH_PER_SE 2 894 895 struct amdgpu_rb_config { 896 uint32_t rb_backend_disable; 897 uint32_t user_rb_backend_disable; 898 uint32_t raster_config; 899 uint32_t raster_config_1; 900 }; 901 902 struct gb_addr_config { 903 uint16_t pipe_interleave_size; 904 uint8_t num_pipes; 905 uint8_t max_compress_frags; 906 uint8_t num_banks; 907 uint8_t num_se; 908 uint8_t num_rb_per_se; 909 }; 910 911 struct amdgpu_gfx_config { 912 unsigned max_shader_engines; 913 unsigned max_tile_pipes; 914 unsigned max_cu_per_sh; 915 unsigned max_sh_per_se; 916 unsigned max_backends_per_se; 917 unsigned max_texture_channel_caches; 918 unsigned max_gprs; 919 unsigned max_gs_threads; 920 unsigned max_hw_contexts; 921 unsigned sc_prim_fifo_size_frontend; 922 unsigned sc_prim_fifo_size_backend; 923 unsigned sc_hiz_tile_fifo_size; 924 unsigned sc_earlyz_tile_fifo_size; 925 926 unsigned num_tile_pipes; 927 unsigned backend_enable_mask; 928 unsigned mem_max_burst_length_bytes; 929 unsigned mem_row_size_in_kb; 930 unsigned shader_engine_tile_size; 931 unsigned num_gpus; 932 unsigned multi_gpu_tile_size; 933 unsigned mc_arb_ramcfg; 934 unsigned gb_addr_config; 935 unsigned num_rbs; 936 unsigned gs_vgt_table_depth; 937 unsigned gs_prim_buffer_depth; 938 939 uint32_t tile_mode_array[32]; 940 uint32_t macrotile_mode_array[16]; 941 942 struct gb_addr_config gb_addr_config_fields; 943 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; 944 945 /* gfx configure feature */ 946 uint32_t double_offchip_lds_buf; 947 }; 948 949 struct amdgpu_cu_info { 950 uint32_t max_waves_per_simd; 951 uint32_t wave_front_size; 952 uint32_t max_scratch_slots_per_cu; 953 uint32_t lds_size; 954 955 /* total active CU number */ 956 uint32_t number; 957 uint32_t ao_cu_mask; 958 uint32_t ao_cu_bitmap[4][4]; 959 uint32_t bitmap[4][4]; 960 }; 961 962 struct amdgpu_gfx_funcs { 963 /* get the gpu clock counter */ 964 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 965 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); 966 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields); 967 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst); 968 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst); 969 }; 970 971 struct amdgpu_ngg_buf { 972 struct amdgpu_bo *bo; 973 uint64_t gpu_addr; 974 uint32_t size; 975 uint32_t bo_size; 976 }; 977 978 enum { 979 NGG_PRIM = 0, 980 NGG_POS, 981 NGG_CNTL, 982 NGG_PARAM, 983 NGG_BUF_MAX 984 }; 985 986 struct amdgpu_ngg { 987 struct amdgpu_ngg_buf buf[NGG_BUF_MAX]; 988 uint32_t gds_reserve_addr; 989 uint32_t gds_reserve_size; 990 bool init; 991 }; 992 993 struct amdgpu_gfx { 994 struct mutex gpu_clock_mutex; 995 struct amdgpu_gfx_config config; 996 struct amdgpu_rlc rlc; 997 struct amdgpu_mec mec; 998 struct amdgpu_kiq kiq; 999 struct amdgpu_scratch scratch; 1000 const struct firmware *me_fw; /* ME firmware */ 1001 uint32_t me_fw_version; 1002 const struct firmware *pfp_fw; /* PFP firmware */ 1003 uint32_t pfp_fw_version; 1004 const struct firmware *ce_fw; /* CE firmware */ 1005 uint32_t ce_fw_version; 1006 const struct firmware *rlc_fw; /* RLC firmware */ 1007 uint32_t rlc_fw_version; 1008 const struct firmware *mec_fw; /* MEC firmware */ 1009 uint32_t mec_fw_version; 1010 const struct firmware *mec2_fw; /* MEC2 firmware */ 1011 uint32_t mec2_fw_version; 1012 uint32_t me_feature_version; 1013 uint32_t ce_feature_version; 1014 uint32_t pfp_feature_version; 1015 uint32_t rlc_feature_version; 1016 uint32_t mec_feature_version; 1017 uint32_t mec2_feature_version; 1018 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 1019 unsigned num_gfx_rings; 1020 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 1021 unsigned num_compute_rings; 1022 struct amdgpu_irq_src eop_irq; 1023 struct amdgpu_irq_src priv_reg_irq; 1024 struct amdgpu_irq_src priv_inst_irq; 1025 /* gfx status */ 1026 uint32_t gfx_current_status; 1027 /* ce ram size*/ 1028 unsigned ce_ram_size; 1029 struct amdgpu_cu_info cu_info; 1030 const struct amdgpu_gfx_funcs *funcs; 1031 1032 /* reset mask */ 1033 uint32_t grbm_soft_reset; 1034 uint32_t srbm_soft_reset; 1035 /* s3/s4 mask */ 1036 bool in_suspend; 1037 /* NGG */ 1038 struct amdgpu_ngg ngg; 1039 }; 1040 1041 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 1042 unsigned size, struct amdgpu_ib *ib); 1043 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 1044 struct dma_fence *f); 1045 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 1046 struct amdgpu_ib *ibs, struct amdgpu_job *job, 1047 struct dma_fence **f); 1048 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 1049 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 1050 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 1051 1052 /* 1053 * CS. 1054 */ 1055 struct amdgpu_cs_chunk { 1056 uint32_t chunk_id; 1057 uint32_t length_dw; 1058 void *kdata; 1059 }; 1060 1061 struct amdgpu_cs_parser { 1062 struct amdgpu_device *adev; 1063 struct drm_file *filp; 1064 struct amdgpu_ctx *ctx; 1065 1066 /* chunks */ 1067 unsigned nchunks; 1068 struct amdgpu_cs_chunk *chunks; 1069 1070 /* scheduler job object */ 1071 struct amdgpu_job *job; 1072 1073 /* buffer objects */ 1074 struct ww_acquire_ctx ticket; 1075 struct amdgpu_bo_list *bo_list; 1076 struct amdgpu_mn *mn; 1077 struct amdgpu_bo_list_entry vm_pd; 1078 struct list_head validated; 1079 struct dma_fence *fence; 1080 uint64_t bytes_moved_threshold; 1081 uint64_t bytes_moved_vis_threshold; 1082 uint64_t bytes_moved; 1083 uint64_t bytes_moved_vis; 1084 struct amdgpu_bo_list_entry *evictable; 1085 1086 /* user fence */ 1087 struct amdgpu_bo_list_entry uf_entry; 1088 1089 unsigned num_post_dep_syncobjs; 1090 struct drm_syncobj **post_dep_syncobjs; 1091 }; 1092 1093 #define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */ 1094 #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */ 1095 #define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */ 1096 1097 struct amdgpu_job { 1098 struct amd_sched_job base; 1099 struct amdgpu_device *adev; 1100 struct amdgpu_vm *vm; 1101 struct amdgpu_ring *ring; 1102 struct amdgpu_sync sync; 1103 struct amdgpu_sync dep_sync; 1104 struct amdgpu_sync sched_sync; 1105 struct amdgpu_ib *ibs; 1106 struct dma_fence *fence; /* the hw fence */ 1107 uint32_t preamble_status; 1108 uint32_t num_ibs; 1109 void *owner; 1110 uint64_t fence_ctx; /* the fence_context this job uses */ 1111 bool vm_needs_flush; 1112 unsigned vm_id; 1113 uint64_t vm_pd_addr; 1114 uint32_t gds_base, gds_size; 1115 uint32_t gws_base, gws_size; 1116 uint32_t oa_base, oa_size; 1117 1118 /* user fence handling */ 1119 uint64_t uf_addr; 1120 uint64_t uf_sequence; 1121 1122 }; 1123 #define to_amdgpu_job(sched_job) \ 1124 container_of((sched_job), struct amdgpu_job, base) 1125 1126 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 1127 uint32_t ib_idx, int idx) 1128 { 1129 return p->job->ibs[ib_idx].ptr[idx]; 1130 } 1131 1132 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 1133 uint32_t ib_idx, int idx, 1134 uint32_t value) 1135 { 1136 p->job->ibs[ib_idx].ptr[idx] = value; 1137 } 1138 1139 /* 1140 * Writeback 1141 */ 1142 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 1143 1144 struct amdgpu_wb { 1145 struct amdgpu_bo *wb_obj; 1146 volatile uint32_t *wb; 1147 uint64_t gpu_addr; 1148 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 1149 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 1150 }; 1151 1152 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); 1153 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); 1154 1155 void amdgpu_get_pcie_info(struct amdgpu_device *adev); 1156 1157 /* 1158 * SDMA 1159 */ 1160 struct amdgpu_sdma_instance { 1161 /* SDMA firmware */ 1162 const struct firmware *fw; 1163 uint32_t fw_version; 1164 uint32_t feature_version; 1165 1166 struct amdgpu_ring ring; 1167 bool burst_nop; 1168 }; 1169 1170 struct amdgpu_sdma { 1171 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 1172 #ifdef CONFIG_DRM_AMDGPU_SI 1173 //SI DMA has a difference trap irq number for the second engine 1174 struct amdgpu_irq_src trap_irq_1; 1175 #endif 1176 struct amdgpu_irq_src trap_irq; 1177 struct amdgpu_irq_src illegal_inst_irq; 1178 int num_instances; 1179 uint32_t srbm_soft_reset; 1180 }; 1181 1182 /* 1183 * Firmware 1184 */ 1185 enum amdgpu_firmware_load_type { 1186 AMDGPU_FW_LOAD_DIRECT = 0, 1187 AMDGPU_FW_LOAD_SMU, 1188 AMDGPU_FW_LOAD_PSP, 1189 }; 1190 1191 struct amdgpu_firmware { 1192 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 1193 enum amdgpu_firmware_load_type load_type; 1194 struct amdgpu_bo *fw_buf; 1195 unsigned int fw_size; 1196 unsigned int max_ucodes; 1197 /* firmwares are loaded by psp instead of smu from vega10 */ 1198 const struct amdgpu_psp_funcs *funcs; 1199 struct amdgpu_bo *rbuf; 1200 struct mutex mutex; 1201 1202 /* gpu info firmware data pointer */ 1203 const struct firmware *gpu_info_fw; 1204 1205 void *fw_buf_ptr; 1206 uint64_t fw_buf_mc; 1207 }; 1208 1209 /* 1210 * Benchmarking 1211 */ 1212 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 1213 1214 1215 /* 1216 * Testing 1217 */ 1218 void amdgpu_test_moves(struct amdgpu_device *adev); 1219 1220 /* 1221 * Debugfs 1222 */ 1223 struct amdgpu_debugfs { 1224 const struct drm_info_list *files; 1225 unsigned num_files; 1226 }; 1227 1228 int amdgpu_debugfs_add_files(struct amdgpu_device *adev, 1229 const struct drm_info_list *files, 1230 unsigned nfiles); 1231 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); 1232 1233 #if defined(CONFIG_DEBUG_FS) 1234 int amdgpu_debugfs_init(struct drm_minor *minor); 1235 #endif 1236 1237 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev); 1238 1239 /* 1240 * amdgpu smumgr functions 1241 */ 1242 struct amdgpu_smumgr_funcs { 1243 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 1244 int (*request_smu_load_fw)(struct amdgpu_device *adev); 1245 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 1246 }; 1247 1248 /* 1249 * amdgpu smumgr 1250 */ 1251 struct amdgpu_smumgr { 1252 struct amdgpu_bo *toc_buf; 1253 struct amdgpu_bo *smu_buf; 1254 /* asic priv smu data */ 1255 void *priv; 1256 spinlock_t smu_lock; 1257 /* smumgr functions */ 1258 const struct amdgpu_smumgr_funcs *smumgr_funcs; 1259 /* ucode loading complete flag */ 1260 uint32_t fw_flags; 1261 }; 1262 1263 /* 1264 * ASIC specific register table accessible by UMD 1265 */ 1266 struct amdgpu_allowed_register_entry { 1267 uint32_t reg_offset; 1268 bool grbm_indexed; 1269 }; 1270 1271 /* 1272 * ASIC specific functions. 1273 */ 1274 struct amdgpu_asic_funcs { 1275 bool (*read_disabled_bios)(struct amdgpu_device *adev); 1276 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 1277 u8 *bios, u32 length_bytes); 1278 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 1279 u32 sh_num, u32 reg_offset, u32 *value); 1280 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 1281 int (*reset)(struct amdgpu_device *adev); 1282 /* get the reference clock */ 1283 u32 (*get_xclk)(struct amdgpu_device *adev); 1284 /* MM block clocks */ 1285 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 1286 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 1287 /* static power management */ 1288 int (*get_pcie_lanes)(struct amdgpu_device *adev); 1289 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 1290 /* get config memsize register */ 1291 u32 (*get_config_memsize)(struct amdgpu_device *adev); 1292 }; 1293 1294 /* 1295 * IOCTL. 1296 */ 1297 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 1298 struct drm_file *filp); 1299 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 1300 struct drm_file *filp); 1301 1302 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 1303 struct drm_file *filp); 1304 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 1305 struct drm_file *filp); 1306 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 1307 struct drm_file *filp); 1308 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1309 struct drm_file *filp); 1310 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 1311 struct drm_file *filp); 1312 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 1313 struct drm_file *filp); 1314 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1315 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1316 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 1317 struct drm_file *filp); 1318 1319 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 1320 struct drm_file *filp); 1321 1322 /* VRAM scratch page for HDP bug, default vram page */ 1323 struct amdgpu_vram_scratch { 1324 struct amdgpu_bo *robj; 1325 volatile uint32_t *ptr; 1326 u64 gpu_addr; 1327 }; 1328 1329 /* 1330 * ACPI 1331 */ 1332 struct amdgpu_atif_notification_cfg { 1333 bool enabled; 1334 int command_code; 1335 }; 1336 1337 struct amdgpu_atif_notifications { 1338 bool display_switch; 1339 bool expansion_mode_change; 1340 bool thermal_state; 1341 bool forced_power_state; 1342 bool system_power_state; 1343 bool display_conf_change; 1344 bool px_gfx_switch; 1345 bool brightness_change; 1346 bool dgpu_display_event; 1347 }; 1348 1349 struct amdgpu_atif_functions { 1350 bool system_params; 1351 bool sbios_requests; 1352 bool select_active_disp; 1353 bool lid_state; 1354 bool get_tv_standard; 1355 bool set_tv_standard; 1356 bool get_panel_expansion_mode; 1357 bool set_panel_expansion_mode; 1358 bool temperature_change; 1359 bool graphics_device_types; 1360 }; 1361 1362 struct amdgpu_atif { 1363 struct amdgpu_atif_notifications notifications; 1364 struct amdgpu_atif_functions functions; 1365 struct amdgpu_atif_notification_cfg notification_cfg; 1366 struct amdgpu_encoder *encoder_for_bl; 1367 }; 1368 1369 struct amdgpu_atcs_functions { 1370 bool get_ext_state; 1371 bool pcie_perf_req; 1372 bool pcie_dev_rdy; 1373 bool pcie_bus_width; 1374 }; 1375 1376 struct amdgpu_atcs { 1377 struct amdgpu_atcs_functions functions; 1378 }; 1379 1380 /* 1381 * CGS 1382 */ 1383 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1384 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 1385 1386 /* 1387 * Core structure, functions and helpers. 1388 */ 1389 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 1390 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1391 1392 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1393 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 1394 1395 #define AMDGPU_RESET_MAGIC_NUM 64 1396 struct amdgpu_device { 1397 struct device *dev; 1398 struct drm_device *ddev; 1399 struct pci_dev *pdev; 1400 1401 #ifdef CONFIG_DRM_AMD_ACP 1402 struct amdgpu_acp acp; 1403 #endif 1404 1405 /* ASIC */ 1406 enum amd_asic_type asic_type; 1407 uint32_t family; 1408 uint32_t rev_id; 1409 uint32_t external_rev_id; 1410 unsigned long flags; 1411 int usec_timeout; 1412 const struct amdgpu_asic_funcs *asic_funcs; 1413 bool shutdown; 1414 bool need_dma32; 1415 bool accel_working; 1416 struct work_struct reset_work; 1417 struct notifier_block acpi_nb; 1418 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 1419 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1420 unsigned debugfs_count; 1421 #if defined(CONFIG_DEBUG_FS) 1422 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1423 #endif 1424 struct amdgpu_atif atif; 1425 struct amdgpu_atcs atcs; 1426 struct mutex srbm_mutex; 1427 /* GRBM index mutex. Protects concurrent access to GRBM index */ 1428 struct mutex grbm_idx_mutex; 1429 struct dev_pm_domain vga_pm_domain; 1430 bool have_disp_power_ref; 1431 1432 /* BIOS */ 1433 bool is_atom_fw; 1434 uint8_t *bios; 1435 uint32_t bios_size; 1436 struct amdgpu_bo *stolen_vga_memory; 1437 uint32_t bios_scratch_reg_offset; 1438 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 1439 1440 /* Register/doorbell mmio */ 1441 resource_size_t rmmio_base; 1442 resource_size_t rmmio_size; 1443 void __iomem *rmmio; 1444 /* protects concurrent MM_INDEX/DATA based register access */ 1445 spinlock_t mmio_idx_lock; 1446 /* protects concurrent SMC based register access */ 1447 spinlock_t smc_idx_lock; 1448 amdgpu_rreg_t smc_rreg; 1449 amdgpu_wreg_t smc_wreg; 1450 /* protects concurrent PCIE register access */ 1451 spinlock_t pcie_idx_lock; 1452 amdgpu_rreg_t pcie_rreg; 1453 amdgpu_wreg_t pcie_wreg; 1454 amdgpu_rreg_t pciep_rreg; 1455 amdgpu_wreg_t pciep_wreg; 1456 /* protects concurrent UVD register access */ 1457 spinlock_t uvd_ctx_idx_lock; 1458 amdgpu_rreg_t uvd_ctx_rreg; 1459 amdgpu_wreg_t uvd_ctx_wreg; 1460 /* protects concurrent DIDT register access */ 1461 spinlock_t didt_idx_lock; 1462 amdgpu_rreg_t didt_rreg; 1463 amdgpu_wreg_t didt_wreg; 1464 /* protects concurrent gc_cac register access */ 1465 spinlock_t gc_cac_idx_lock; 1466 amdgpu_rreg_t gc_cac_rreg; 1467 amdgpu_wreg_t gc_cac_wreg; 1468 /* protects concurrent se_cac register access */ 1469 spinlock_t se_cac_idx_lock; 1470 amdgpu_rreg_t se_cac_rreg; 1471 amdgpu_wreg_t se_cac_wreg; 1472 /* protects concurrent ENDPOINT (audio) register access */ 1473 spinlock_t audio_endpt_idx_lock; 1474 amdgpu_block_rreg_t audio_endpt_rreg; 1475 amdgpu_block_wreg_t audio_endpt_wreg; 1476 void __iomem *rio_mem; 1477 resource_size_t rio_mem_size; 1478 struct amdgpu_doorbell doorbell; 1479 1480 /* clock/pll info */ 1481 struct amdgpu_clock clock; 1482 1483 /* MC */ 1484 struct amdgpu_mc mc; 1485 struct amdgpu_gart gart; 1486 struct amdgpu_dummy_page dummy_page; 1487 struct amdgpu_vm_manager vm_manager; 1488 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 1489 1490 /* memory management */ 1491 struct amdgpu_mman mman; 1492 struct amdgpu_vram_scratch vram_scratch; 1493 struct amdgpu_wb wb; 1494 atomic64_t num_bytes_moved; 1495 atomic64_t num_evictions; 1496 atomic64_t num_vram_cpu_page_faults; 1497 atomic_t gpu_reset_counter; 1498 atomic_t vram_lost_counter; 1499 1500 /* data for buffer migration throttling */ 1501 struct { 1502 spinlock_t lock; 1503 s64 last_update_us; 1504 s64 accum_us; /* accumulated microseconds */ 1505 s64 accum_us_vis; /* for visible VRAM */ 1506 u32 log2_max_MBps; 1507 } mm_stats; 1508 1509 /* display */ 1510 bool enable_virtual_display; 1511 struct amdgpu_mode_info mode_info; 1512 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 1513 struct work_struct hotplug_work; 1514 struct amdgpu_irq_src crtc_irq; 1515 struct amdgpu_irq_src pageflip_irq; 1516 struct amdgpu_irq_src hpd_irq; 1517 1518 /* rings */ 1519 u64 fence_context; 1520 unsigned num_rings; 1521 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 1522 bool ib_pool_ready; 1523 struct amdgpu_sa_manager ring_tmp_bo; 1524 1525 /* interrupts */ 1526 struct amdgpu_irq irq; 1527 1528 /* powerplay */ 1529 struct amd_powerplay powerplay; 1530 bool pp_enabled; 1531 bool pp_force_state_enabled; 1532 1533 /* dpm */ 1534 struct amdgpu_pm pm; 1535 u32 cg_flags; 1536 u32 pg_flags; 1537 1538 /* amdgpu smumgr */ 1539 struct amdgpu_smumgr smu; 1540 1541 /* gfx */ 1542 struct amdgpu_gfx gfx; 1543 1544 /* sdma */ 1545 struct amdgpu_sdma sdma; 1546 1547 union { 1548 struct { 1549 /* uvd */ 1550 struct amdgpu_uvd uvd; 1551 1552 /* vce */ 1553 struct amdgpu_vce vce; 1554 }; 1555 1556 /* vcn */ 1557 struct amdgpu_vcn vcn; 1558 }; 1559 1560 /* firmwares */ 1561 struct amdgpu_firmware firmware; 1562 1563 /* PSP */ 1564 struct psp_context psp; 1565 1566 /* GDS */ 1567 struct amdgpu_gds gds; 1568 1569 /* display related functionality */ 1570 struct amdgpu_display_manager dm; 1571 1572 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1573 int num_ip_blocks; 1574 struct mutex mn_lock; 1575 DECLARE_HASHTABLE(mn_hash, 7); 1576 1577 /* tracking pinned memory */ 1578 u64 vram_pin_size; 1579 u64 invisible_pin_size; 1580 u64 gart_pin_size; 1581 1582 /* amdkfd interface */ 1583 struct kfd_dev *kfd; 1584 1585 /* delayed work_func for deferring clockgating during resume */ 1586 struct delayed_work late_init_work; 1587 1588 struct amdgpu_virt virt; 1589 1590 /* link all shadow bo */ 1591 struct list_head shadow_list; 1592 struct mutex shadow_list_lock; 1593 /* link all gtt */ 1594 spinlock_t gtt_list_lock; 1595 struct list_head gtt_list; 1596 /* keep an lru list of rings by HW IP */ 1597 struct list_head ring_lru_list; 1598 spinlock_t ring_lru_list_lock; 1599 1600 /* record hw reset is performed */ 1601 bool has_hw_reset; 1602 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1603 1604 /* record last mm index being written through WREG32*/ 1605 unsigned long last_mm_index; 1606 bool in_sriov_reset; 1607 }; 1608 1609 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1610 { 1611 return container_of(bdev, struct amdgpu_device, mman.bdev); 1612 } 1613 1614 int amdgpu_device_init(struct amdgpu_device *adev, 1615 struct drm_device *ddev, 1616 struct pci_dev *pdev, 1617 uint32_t flags); 1618 void amdgpu_device_fini(struct amdgpu_device *adev); 1619 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1620 1621 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 1622 uint32_t acc_flags); 1623 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 1624 uint32_t acc_flags); 1625 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1626 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1627 1628 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 1629 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 1630 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index); 1631 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v); 1632 1633 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1634 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1635 1636 /* 1637 * Registers read & write functions. 1638 */ 1639 1640 #define AMDGPU_REGS_IDX (1<<0) 1641 #define AMDGPU_REGS_NO_KIQ (1<<1) 1642 1643 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1644 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1645 1646 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 1647 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) 1648 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 1649 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 1650 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) 1651 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1652 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1653 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1654 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1655 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1656 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1657 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1658 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1659 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1660 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1661 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1662 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1663 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1664 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1665 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1666 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1667 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1668 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1669 #define WREG32_P(reg, val, mask) \ 1670 do { \ 1671 uint32_t tmp_ = RREG32(reg); \ 1672 tmp_ &= (mask); \ 1673 tmp_ |= ((val) & ~(mask)); \ 1674 WREG32(reg, tmp_); \ 1675 } while (0) 1676 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1677 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1678 #define WREG32_PLL_P(reg, val, mask) \ 1679 do { \ 1680 uint32_t tmp_ = RREG32_PLL(reg); \ 1681 tmp_ &= (mask); \ 1682 tmp_ |= ((val) & ~(mask)); \ 1683 WREG32_PLL(reg, tmp_); \ 1684 } while (0) 1685 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 1686 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1687 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1688 1689 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 1690 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 1691 #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index)) 1692 #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v)) 1693 1694 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1695 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1696 1697 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1698 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1699 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1700 1701 #define REG_GET_FIELD(value, reg, field) \ 1702 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1703 1704 #define WREG32_FIELD(reg, field, val) \ 1705 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1706 1707 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1708 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1709 1710 /* 1711 * BIOS helpers. 1712 */ 1713 #define RBIOS8(i) (adev->bios[i]) 1714 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1715 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1716 1717 static inline struct amdgpu_sdma_instance * 1718 amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 1719 { 1720 struct amdgpu_device *adev = ring->adev; 1721 int i; 1722 1723 for (i = 0; i < adev->sdma.num_instances; i++) 1724 if (&adev->sdma.instance[i].ring == ring) 1725 break; 1726 1727 if (i < AMDGPU_MAX_SDMA_INSTANCES) 1728 return &adev->sdma.instance[i]; 1729 else 1730 return NULL; 1731 } 1732 1733 /* 1734 * ASICs macro. 1735 */ 1736 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1737 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1738 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1739 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1740 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1741 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1742 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1743 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1744 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1745 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1746 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1747 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1748 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) 1749 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) 1750 #define amdgpu_gart_get_vm_pde(adev, addr) (adev)->gart.gart_funcs->get_vm_pde((adev), (addr)) 1751 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 1752 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) 1753 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 1754 #define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags)) 1755 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 1756 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 1757 #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t)) 1758 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 1759 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 1760 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 1761 #define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c)) 1762 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) 1763 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 1764 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 1765 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 1766 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 1767 #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r)) 1768 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r)) 1769 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d)) 1770 #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d)) 1771 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) 1772 #define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b)) 1773 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) 1774 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) 1775 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) 1776 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) 1777 #define amdgpu_ih_prescreen_iv(adev) (adev)->irq.ih_funcs->prescreen_iv((adev)) 1778 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) 1779 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) 1780 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 1781 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) 1782 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 1783 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 1784 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 1785 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) 1786 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) 1787 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) 1788 #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async)) 1789 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) 1790 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) 1791 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) 1792 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 1793 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 1794 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 1795 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) 1796 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) 1797 #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i)) 1798 1799 /* Common functions */ 1800 int amdgpu_gpu_reset(struct amdgpu_device *adev); 1801 bool amdgpu_need_backup(struct amdgpu_device *adev); 1802 void amdgpu_pci_config_reset(struct amdgpu_device *adev); 1803 bool amdgpu_need_post(struct amdgpu_device *adev); 1804 void amdgpu_update_display_priority(struct amdgpu_device *adev); 1805 1806 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1807 u64 num_vis_bytes); 1808 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain); 1809 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 1810 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); 1811 void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); 1812 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); 1813 int amdgpu_ttm_init(struct amdgpu_device *adev); 1814 void amdgpu_ttm_fini(struct amdgpu_device *adev); 1815 void amdgpu_program_register_sequence(struct amdgpu_device *adev, 1816 const u32 *registers, 1817 const u32 array_size); 1818 1819 bool amdgpu_device_is_px(struct drm_device *dev); 1820 /* atpx handler */ 1821 #if defined(CONFIG_VGA_SWITCHEROO) 1822 void amdgpu_register_atpx_handler(void); 1823 void amdgpu_unregister_atpx_handler(void); 1824 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1825 bool amdgpu_is_atpx_hybrid(void); 1826 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1827 bool amdgpu_has_atpx(void); 1828 #else 1829 static inline void amdgpu_register_atpx_handler(void) {} 1830 static inline void amdgpu_unregister_atpx_handler(void) {} 1831 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1832 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1833 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1834 static inline bool amdgpu_has_atpx(void) { return false; } 1835 #endif 1836 1837 /* 1838 * KMS 1839 */ 1840 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1841 extern const int amdgpu_max_kms_ioctl; 1842 1843 bool amdgpu_kms_vram_lost(struct amdgpu_device *adev, 1844 struct amdgpu_fpriv *fpriv); 1845 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1846 void amdgpu_driver_unload_kms(struct drm_device *dev); 1847 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1848 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1849 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1850 struct drm_file *file_priv); 1851 int amdgpu_suspend(struct amdgpu_device *adev); 1852 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); 1853 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); 1854 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 1855 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1856 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1857 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1858 unsigned long arg); 1859 1860 /* 1861 * functions used by amdgpu_encoder.c 1862 */ 1863 struct amdgpu_afmt_acr { 1864 u32 clock; 1865 1866 int n_32khz; 1867 int cts_32khz; 1868 1869 int n_44_1khz; 1870 int cts_44_1khz; 1871 1872 int n_48khz; 1873 int cts_48khz; 1874 1875 }; 1876 1877 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1878 1879 /* amdgpu_acpi.c */ 1880 #if defined(CONFIG_ACPI) 1881 int amdgpu_acpi_init(struct amdgpu_device *adev); 1882 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1883 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1884 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1885 u8 perf_req, bool advertise); 1886 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1887 #else 1888 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1889 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1890 #endif 1891 1892 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1893 uint64_t addr, struct amdgpu_bo **bo, 1894 struct amdgpu_bo_va_mapping **mapping); 1895 1896 #if defined(CONFIG_DRM_AMD_DC) 1897 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1898 #else 1899 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1900 #endif 1901 1902 #include "amdgpu_object.h" 1903 #endif 1904