1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include <linux/atomic.h> 32 #include <linux/wait.h> 33 #include <linux/list.h> 34 #include <linux/kref.h> 35 #include <linux/interval_tree.h> 36 #include <linux/hashtable.h> 37 #include <linux/fence.h> 38 39 #include <ttm/ttm_bo_api.h> 40 #include <ttm/ttm_bo_driver.h> 41 #include <ttm/ttm_placement.h> 42 #include <ttm/ttm_module.h> 43 #include <ttm/ttm_execbuf_util.h> 44 45 #include <drm/drmP.h> 46 #include <drm/drm_gem.h> 47 #include <drm/amdgpu_drm.h> 48 49 #include "amd_shared.h" 50 #include "amdgpu_mode.h" 51 #include "amdgpu_ih.h" 52 #include "amdgpu_irq.h" 53 #include "amdgpu_ucode.h" 54 #include "amdgpu_gds.h" 55 56 #include "gpu_scheduler.h" 57 58 /* 59 * Modules parameters. 60 */ 61 extern int amdgpu_modeset; 62 extern int amdgpu_vram_limit; 63 extern int amdgpu_gart_size; 64 extern int amdgpu_benchmarking; 65 extern int amdgpu_testing; 66 extern int amdgpu_audio; 67 extern int amdgpu_disp_priority; 68 extern int amdgpu_hw_i2c; 69 extern int amdgpu_pcie_gen2; 70 extern int amdgpu_msi; 71 extern int amdgpu_lockup_timeout; 72 extern int amdgpu_dpm; 73 extern int amdgpu_smc_load_fw; 74 extern int amdgpu_aspm; 75 extern int amdgpu_runtime_pm; 76 extern int amdgpu_hard_reset; 77 extern unsigned amdgpu_ip_block_mask; 78 extern int amdgpu_bapm; 79 extern int amdgpu_deep_color; 80 extern int amdgpu_vm_size; 81 extern int amdgpu_vm_block_size; 82 extern int amdgpu_vm_fault_stop; 83 extern int amdgpu_vm_debug; 84 extern int amdgpu_enable_scheduler; 85 extern int amdgpu_sched_jobs; 86 extern int amdgpu_sched_hw_submission; 87 extern int amdgpu_enable_semaphores; 88 89 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 90 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 91 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 92 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 93 #define AMDGPU_IB_POOL_SIZE 16 94 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 95 #define AMDGPUFB_CONN_LIMIT 4 96 #define AMDGPU_BIOS_NUM_SCRATCH 8 97 98 /* max number of rings */ 99 #define AMDGPU_MAX_RINGS 16 100 #define AMDGPU_MAX_GFX_RINGS 1 101 #define AMDGPU_MAX_COMPUTE_RINGS 8 102 #define AMDGPU_MAX_VCE_RINGS 2 103 104 /* max number of IP instances */ 105 #define AMDGPU_MAX_SDMA_INSTANCES 2 106 107 /* number of hw syncs before falling back on blocking */ 108 #define AMDGPU_NUM_SYNCS 4 109 110 /* hardcode that limit for now */ 111 #define AMDGPU_VA_RESERVED_SIZE (8 << 20) 112 113 /* hard reset data */ 114 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 115 116 /* reset flags */ 117 #define AMDGPU_RESET_GFX (1 << 0) 118 #define AMDGPU_RESET_COMPUTE (1 << 1) 119 #define AMDGPU_RESET_DMA (1 << 2) 120 #define AMDGPU_RESET_CP (1 << 3) 121 #define AMDGPU_RESET_GRBM (1 << 4) 122 #define AMDGPU_RESET_DMA1 (1 << 5) 123 #define AMDGPU_RESET_RLC (1 << 6) 124 #define AMDGPU_RESET_SEM (1 << 7) 125 #define AMDGPU_RESET_IH (1 << 8) 126 #define AMDGPU_RESET_VMC (1 << 9) 127 #define AMDGPU_RESET_MC (1 << 10) 128 #define AMDGPU_RESET_DISPLAY (1 << 11) 129 #define AMDGPU_RESET_UVD (1 << 12) 130 #define AMDGPU_RESET_VCE (1 << 13) 131 #define AMDGPU_RESET_VCE1 (1 << 14) 132 133 /* CG block flags */ 134 #define AMDGPU_CG_BLOCK_GFX (1 << 0) 135 #define AMDGPU_CG_BLOCK_MC (1 << 1) 136 #define AMDGPU_CG_BLOCK_SDMA (1 << 2) 137 #define AMDGPU_CG_BLOCK_UVD (1 << 3) 138 #define AMDGPU_CG_BLOCK_VCE (1 << 4) 139 #define AMDGPU_CG_BLOCK_HDP (1 << 5) 140 #define AMDGPU_CG_BLOCK_BIF (1 << 6) 141 142 /* CG flags */ 143 #define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0) 144 #define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1) 145 #define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2) 146 #define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3) 147 #define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4) 148 #define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 149 #define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6) 150 #define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7) 151 #define AMDGPU_CG_SUPPORT_MC_LS (1 << 8) 152 #define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9) 153 #define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10) 154 #define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11) 155 #define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12) 156 #define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13) 157 #define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14) 158 #define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15) 159 #define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16) 160 161 /* PG flags */ 162 #define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0) 163 #define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1) 164 #define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2) 165 #define AMDGPU_PG_SUPPORT_UVD (1 << 3) 166 #define AMDGPU_PG_SUPPORT_VCE (1 << 4) 167 #define AMDGPU_PG_SUPPORT_CP (1 << 5) 168 #define AMDGPU_PG_SUPPORT_GDS (1 << 6) 169 #define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7) 170 #define AMDGPU_PG_SUPPORT_SDMA (1 << 8) 171 #define AMDGPU_PG_SUPPORT_ACP (1 << 9) 172 #define AMDGPU_PG_SUPPORT_SAMU (1 << 10) 173 174 /* GFX current status */ 175 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 176 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 177 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 178 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 179 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 180 181 /* max cursor sizes (in pixels) */ 182 #define CIK_CURSOR_WIDTH 128 183 #define CIK_CURSOR_HEIGHT 128 184 185 struct amdgpu_device; 186 struct amdgpu_fence; 187 struct amdgpu_ib; 188 struct amdgpu_vm; 189 struct amdgpu_ring; 190 struct amdgpu_semaphore; 191 struct amdgpu_cs_parser; 192 struct amdgpu_job; 193 struct amdgpu_irq_src; 194 struct amdgpu_fpriv; 195 196 enum amdgpu_cp_irq { 197 AMDGPU_CP_IRQ_GFX_EOP = 0, 198 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 199 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 200 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 201 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 202 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 203 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 204 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 205 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 206 207 AMDGPU_CP_IRQ_LAST 208 }; 209 210 enum amdgpu_sdma_irq { 211 AMDGPU_SDMA_IRQ_TRAP0 = 0, 212 AMDGPU_SDMA_IRQ_TRAP1, 213 214 AMDGPU_SDMA_IRQ_LAST 215 }; 216 217 enum amdgpu_thermal_irq { 218 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 219 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 220 221 AMDGPU_THERMAL_IRQ_LAST 222 }; 223 224 int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 225 enum amd_ip_block_type block_type, 226 enum amd_clockgating_state state); 227 int amdgpu_set_powergating_state(struct amdgpu_device *adev, 228 enum amd_ip_block_type block_type, 229 enum amd_powergating_state state); 230 231 struct amdgpu_ip_block_version { 232 enum amd_ip_block_type type; 233 u32 major; 234 u32 minor; 235 u32 rev; 236 const struct amd_ip_funcs *funcs; 237 }; 238 239 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 240 enum amd_ip_block_type type, 241 u32 major, u32 minor); 242 243 const struct amdgpu_ip_block_version * amdgpu_get_ip_block( 244 struct amdgpu_device *adev, 245 enum amd_ip_block_type type); 246 247 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 248 struct amdgpu_buffer_funcs { 249 /* maximum bytes in a single operation */ 250 uint32_t copy_max_bytes; 251 252 /* number of dw to reserve per operation */ 253 unsigned copy_num_dw; 254 255 /* used for buffer migration */ 256 void (*emit_copy_buffer)(struct amdgpu_ib *ib, 257 /* src addr in bytes */ 258 uint64_t src_offset, 259 /* dst addr in bytes */ 260 uint64_t dst_offset, 261 /* number of byte to transfer */ 262 uint32_t byte_count); 263 264 /* maximum bytes in a single operation */ 265 uint32_t fill_max_bytes; 266 267 /* number of dw to reserve per operation */ 268 unsigned fill_num_dw; 269 270 /* used for buffer clearing */ 271 void (*emit_fill_buffer)(struct amdgpu_ib *ib, 272 /* value to write to memory */ 273 uint32_t src_data, 274 /* dst addr in bytes */ 275 uint64_t dst_offset, 276 /* number of byte to fill */ 277 uint32_t byte_count); 278 }; 279 280 /* provided by hw blocks that can write ptes, e.g., sdma */ 281 struct amdgpu_vm_pte_funcs { 282 /* copy pte entries from GART */ 283 void (*copy_pte)(struct amdgpu_ib *ib, 284 uint64_t pe, uint64_t src, 285 unsigned count); 286 /* write pte one entry at a time with addr mapping */ 287 void (*write_pte)(struct amdgpu_ib *ib, 288 uint64_t pe, 289 uint64_t addr, unsigned count, 290 uint32_t incr, uint32_t flags); 291 /* for linear pte/pde updates without addr mapping */ 292 void (*set_pte_pde)(struct amdgpu_ib *ib, 293 uint64_t pe, 294 uint64_t addr, unsigned count, 295 uint32_t incr, uint32_t flags); 296 /* pad the indirect buffer to the necessary number of dw */ 297 void (*pad_ib)(struct amdgpu_ib *ib); 298 }; 299 300 /* provided by the gmc block */ 301 struct amdgpu_gart_funcs { 302 /* flush the vm tlb via mmio */ 303 void (*flush_gpu_tlb)(struct amdgpu_device *adev, 304 uint32_t vmid); 305 /* write pte/pde updates using the cpu */ 306 int (*set_pte_pde)(struct amdgpu_device *adev, 307 void *cpu_pt_addr, /* cpu addr of page table */ 308 uint32_t gpu_page_idx, /* pte/pde to update */ 309 uint64_t addr, /* addr to write into pte/pde */ 310 uint32_t flags); /* access flags */ 311 }; 312 313 /* provided by the ih block */ 314 struct amdgpu_ih_funcs { 315 /* ring read/write ptr handling, called from interrupt context */ 316 u32 (*get_wptr)(struct amdgpu_device *adev); 317 void (*decode_iv)(struct amdgpu_device *adev, 318 struct amdgpu_iv_entry *entry); 319 void (*set_rptr)(struct amdgpu_device *adev); 320 }; 321 322 /* provided by hw blocks that expose a ring buffer for commands */ 323 struct amdgpu_ring_funcs { 324 /* ring read/write ptr handling */ 325 u32 (*get_rptr)(struct amdgpu_ring *ring); 326 u32 (*get_wptr)(struct amdgpu_ring *ring); 327 void (*set_wptr)(struct amdgpu_ring *ring); 328 /* validating and patching of IBs */ 329 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); 330 /* command emit functions */ 331 void (*emit_ib)(struct amdgpu_ring *ring, 332 struct amdgpu_ib *ib); 333 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 334 uint64_t seq, unsigned flags); 335 bool (*emit_semaphore)(struct amdgpu_ring *ring, 336 struct amdgpu_semaphore *semaphore, 337 bool emit_wait); 338 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id, 339 uint64_t pd_addr); 340 void (*emit_hdp_flush)(struct amdgpu_ring *ring); 341 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, 342 uint32_t gds_base, uint32_t gds_size, 343 uint32_t gws_base, uint32_t gws_size, 344 uint32_t oa_base, uint32_t oa_size); 345 /* testing functions */ 346 int (*test_ring)(struct amdgpu_ring *ring); 347 int (*test_ib)(struct amdgpu_ring *ring); 348 /* insert NOP packets */ 349 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); 350 }; 351 352 /* 353 * BIOS. 354 */ 355 bool amdgpu_get_bios(struct amdgpu_device *adev); 356 bool amdgpu_read_bios(struct amdgpu_device *adev); 357 358 /* 359 * Dummy page 360 */ 361 struct amdgpu_dummy_page { 362 struct page *page; 363 dma_addr_t addr; 364 }; 365 int amdgpu_dummy_page_init(struct amdgpu_device *adev); 366 void amdgpu_dummy_page_fini(struct amdgpu_device *adev); 367 368 369 /* 370 * Clocks 371 */ 372 373 #define AMDGPU_MAX_PPLL 3 374 375 struct amdgpu_clock { 376 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 377 struct amdgpu_pll spll; 378 struct amdgpu_pll mpll; 379 /* 10 Khz units */ 380 uint32_t default_mclk; 381 uint32_t default_sclk; 382 uint32_t default_dispclk; 383 uint32_t current_dispclk; 384 uint32_t dp_extclk; 385 uint32_t max_pixel_clock; 386 }; 387 388 /* 389 * Fences. 390 */ 391 struct amdgpu_fence_driver { 392 struct amdgpu_ring *ring; 393 uint64_t gpu_addr; 394 volatile uint32_t *cpu_addr; 395 /* sync_seq is protected by ring emission lock */ 396 uint64_t sync_seq[AMDGPU_MAX_RINGS]; 397 atomic64_t last_seq; 398 bool initialized; 399 struct amdgpu_irq_src *irq_src; 400 unsigned irq_type; 401 struct delayed_work lockup_work; 402 wait_queue_head_t fence_queue; 403 }; 404 405 /* some special values for the owner field */ 406 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul) 407 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul) 408 #define AMDGPU_FENCE_OWNER_MOVE ((void*)2ul) 409 410 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) 411 #define AMDGPU_FENCE_FLAG_INT (1 << 1) 412 413 struct amdgpu_fence { 414 struct fence base; 415 416 /* RB, DMA, etc. */ 417 struct amdgpu_ring *ring; 418 uint64_t seq; 419 420 /* filp or special value for fence creator */ 421 void *owner; 422 423 wait_queue_t fence_wake; 424 }; 425 426 struct amdgpu_user_fence { 427 /* write-back bo */ 428 struct amdgpu_bo *bo; 429 /* write-back address offset to bo start */ 430 uint32_t offset; 431 }; 432 433 int amdgpu_fence_driver_init(struct amdgpu_device *adev); 434 void amdgpu_fence_driver_fini(struct amdgpu_device *adev); 435 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev); 436 437 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring); 438 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 439 struct amdgpu_irq_src *irq_src, 440 unsigned irq_type); 441 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev); 442 void amdgpu_fence_driver_resume(struct amdgpu_device *adev); 443 int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner, 444 struct amdgpu_fence **fence); 445 void amdgpu_fence_process(struct amdgpu_ring *ring); 446 int amdgpu_fence_wait_next(struct amdgpu_ring *ring); 447 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 448 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 449 450 signed long amdgpu_fence_wait_any(struct fence **array, 451 uint32_t count, 452 bool intr, 453 signed long t); 454 struct amdgpu_fence *amdgpu_fence_ref(struct amdgpu_fence *fence); 455 void amdgpu_fence_unref(struct amdgpu_fence **fence); 456 457 bool amdgpu_fence_need_sync(struct amdgpu_fence *fence, 458 struct amdgpu_ring *ring); 459 void amdgpu_fence_note_sync(struct amdgpu_fence *fence, 460 struct amdgpu_ring *ring); 461 462 static inline struct amdgpu_fence *amdgpu_fence_later(struct amdgpu_fence *a, 463 struct amdgpu_fence *b) 464 { 465 if (!a) { 466 return b; 467 } 468 469 if (!b) { 470 return a; 471 } 472 473 BUG_ON(a->ring != b->ring); 474 475 if (a->seq > b->seq) { 476 return a; 477 } else { 478 return b; 479 } 480 } 481 482 static inline bool amdgpu_fence_is_earlier(struct amdgpu_fence *a, 483 struct amdgpu_fence *b) 484 { 485 if (!a) { 486 return false; 487 } 488 489 if (!b) { 490 return true; 491 } 492 493 BUG_ON(a->ring != b->ring); 494 495 return a->seq < b->seq; 496 } 497 498 int amdgpu_user_fence_emit(struct amdgpu_ring *ring, struct amdgpu_user_fence *user, 499 void *owner, struct amdgpu_fence **fence); 500 501 /* 502 * TTM. 503 */ 504 struct amdgpu_mman { 505 struct ttm_bo_global_ref bo_global_ref; 506 struct drm_global_reference mem_global_ref; 507 struct ttm_bo_device bdev; 508 bool mem_global_referenced; 509 bool initialized; 510 511 #if defined(CONFIG_DEBUG_FS) 512 struct dentry *vram; 513 struct dentry *gtt; 514 #endif 515 516 /* buffer handling */ 517 const struct amdgpu_buffer_funcs *buffer_funcs; 518 struct amdgpu_ring *buffer_funcs_ring; 519 }; 520 521 int amdgpu_copy_buffer(struct amdgpu_ring *ring, 522 uint64_t src_offset, 523 uint64_t dst_offset, 524 uint32_t byte_count, 525 struct reservation_object *resv, 526 struct fence **fence); 527 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); 528 529 struct amdgpu_bo_list_entry { 530 struct amdgpu_bo *robj; 531 struct ttm_validate_buffer tv; 532 struct amdgpu_bo_va *bo_va; 533 unsigned prefered_domains; 534 unsigned allowed_domains; 535 uint32_t priority; 536 }; 537 538 struct amdgpu_bo_va_mapping { 539 struct list_head list; 540 struct interval_tree_node it; 541 uint64_t offset; 542 uint32_t flags; 543 }; 544 545 /* bo virtual addresses in a specific vm */ 546 struct amdgpu_bo_va { 547 /* protected by bo being reserved */ 548 struct list_head bo_list; 549 struct fence *last_pt_update; 550 unsigned ref_count; 551 552 /* protected by vm mutex and spinlock */ 553 struct list_head vm_status; 554 555 /* mappings for this bo_va */ 556 struct list_head invalids; 557 struct list_head valids; 558 559 /* constant after initialization */ 560 struct amdgpu_vm *vm; 561 struct amdgpu_bo *bo; 562 }; 563 564 #define AMDGPU_GEM_DOMAIN_MAX 0x3 565 566 struct amdgpu_bo { 567 /* Protected by gem.mutex */ 568 struct list_head list; 569 /* Protected by tbo.reserved */ 570 u32 initial_domain; 571 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 572 struct ttm_placement placement; 573 struct ttm_buffer_object tbo; 574 struct ttm_bo_kmap_obj kmap; 575 u64 flags; 576 unsigned pin_count; 577 void *kptr; 578 u64 tiling_flags; 579 u64 metadata_flags; 580 void *metadata; 581 u32 metadata_size; 582 /* list of all virtual address to which this bo 583 * is associated to 584 */ 585 struct list_head va; 586 /* Constant after initialization */ 587 struct amdgpu_device *adev; 588 struct drm_gem_object gem_base; 589 590 struct ttm_bo_kmap_obj dma_buf_vmap; 591 pid_t pid; 592 struct amdgpu_mn *mn; 593 struct list_head mn_list; 594 }; 595 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) 596 597 void amdgpu_gem_object_free(struct drm_gem_object *obj); 598 int amdgpu_gem_object_open(struct drm_gem_object *obj, 599 struct drm_file *file_priv); 600 void amdgpu_gem_object_close(struct drm_gem_object *obj, 601 struct drm_file *file_priv); 602 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 603 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); 604 struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev, 605 struct dma_buf_attachment *attach, 606 struct sg_table *sg); 607 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, 608 struct drm_gem_object *gobj, 609 int flags); 610 int amdgpu_gem_prime_pin(struct drm_gem_object *obj); 611 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); 612 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); 613 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); 614 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 615 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); 616 617 /* sub-allocation manager, it has to be protected by another lock. 618 * By conception this is an helper for other part of the driver 619 * like the indirect buffer or semaphore, which both have their 620 * locking. 621 * 622 * Principe is simple, we keep a list of sub allocation in offset 623 * order (first entry has offset == 0, last entry has the highest 624 * offset). 625 * 626 * When allocating new object we first check if there is room at 627 * the end total_size - (last_object_offset + last_object_size) >= 628 * alloc_size. If so we allocate new object there. 629 * 630 * When there is not enough room at the end, we start waiting for 631 * each sub object until we reach object_offset+object_size >= 632 * alloc_size, this object then become the sub object we return. 633 * 634 * Alignment can't be bigger than page size. 635 * 636 * Hole are not considered for allocation to keep things simple. 637 * Assumption is that there won't be hole (all object on same 638 * alignment). 639 */ 640 struct amdgpu_sa_manager { 641 wait_queue_head_t wq; 642 struct amdgpu_bo *bo; 643 struct list_head *hole; 644 struct list_head flist[AMDGPU_MAX_RINGS]; 645 struct list_head olist; 646 unsigned size; 647 uint64_t gpu_addr; 648 void *cpu_ptr; 649 uint32_t domain; 650 uint32_t align; 651 }; 652 653 struct amdgpu_sa_bo; 654 655 /* sub-allocation buffer */ 656 struct amdgpu_sa_bo { 657 struct list_head olist; 658 struct list_head flist; 659 struct amdgpu_sa_manager *manager; 660 unsigned soffset; 661 unsigned eoffset; 662 struct fence *fence; 663 }; 664 665 /* 666 * GEM objects. 667 */ 668 struct amdgpu_gem { 669 struct mutex mutex; 670 struct list_head objects; 671 }; 672 673 int amdgpu_gem_init(struct amdgpu_device *adev); 674 void amdgpu_gem_fini(struct amdgpu_device *adev); 675 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 676 int alignment, u32 initial_domain, 677 u64 flags, bool kernel, 678 struct drm_gem_object **obj); 679 680 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 681 struct drm_device *dev, 682 struct drm_mode_create_dumb *args); 683 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 684 struct drm_device *dev, 685 uint32_t handle, uint64_t *offset_p); 686 687 /* 688 * Semaphores. 689 */ 690 struct amdgpu_semaphore { 691 struct amdgpu_sa_bo *sa_bo; 692 signed waiters; 693 uint64_t gpu_addr; 694 }; 695 696 int amdgpu_semaphore_create(struct amdgpu_device *adev, 697 struct amdgpu_semaphore **semaphore); 698 bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring, 699 struct amdgpu_semaphore *semaphore); 700 bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring, 701 struct amdgpu_semaphore *semaphore); 702 void amdgpu_semaphore_free(struct amdgpu_device *adev, 703 struct amdgpu_semaphore **semaphore, 704 struct fence *fence); 705 706 /* 707 * Synchronization 708 */ 709 struct amdgpu_sync { 710 struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS]; 711 struct amdgpu_fence *sync_to[AMDGPU_MAX_RINGS]; 712 DECLARE_HASHTABLE(fences, 4); 713 struct fence *last_vm_update; 714 }; 715 716 void amdgpu_sync_create(struct amdgpu_sync *sync); 717 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, 718 struct fence *f); 719 int amdgpu_sync_resv(struct amdgpu_device *adev, 720 struct amdgpu_sync *sync, 721 struct reservation_object *resv, 722 void *owner); 723 int amdgpu_sync_rings(struct amdgpu_sync *sync, 724 struct amdgpu_ring *ring); 725 struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync); 726 int amdgpu_sync_wait(struct amdgpu_sync *sync); 727 void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync, 728 struct fence *fence); 729 730 /* 731 * GART structures, functions & helpers 732 */ 733 struct amdgpu_mc; 734 735 #define AMDGPU_GPU_PAGE_SIZE 4096 736 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) 737 #define AMDGPU_GPU_PAGE_SHIFT 12 738 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) 739 740 struct amdgpu_gart { 741 dma_addr_t table_addr; 742 struct amdgpu_bo *robj; 743 void *ptr; 744 unsigned num_gpu_pages; 745 unsigned num_cpu_pages; 746 unsigned table_size; 747 struct page **pages; 748 dma_addr_t *pages_addr; 749 bool ready; 750 const struct amdgpu_gart_funcs *gart_funcs; 751 }; 752 753 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); 754 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); 755 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); 756 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); 757 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); 758 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); 759 int amdgpu_gart_init(struct amdgpu_device *adev); 760 void amdgpu_gart_fini(struct amdgpu_device *adev); 761 void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset, 762 int pages); 763 int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset, 764 int pages, struct page **pagelist, 765 dma_addr_t *dma_addr, uint32_t flags); 766 767 /* 768 * GPU MC structures, functions & helpers 769 */ 770 struct amdgpu_mc { 771 resource_size_t aper_size; 772 resource_size_t aper_base; 773 resource_size_t agp_base; 774 /* for some chips with <= 32MB we need to lie 775 * about vram size near mc fb location */ 776 u64 mc_vram_size; 777 u64 visible_vram_size; 778 u64 gtt_size; 779 u64 gtt_start; 780 u64 gtt_end; 781 u64 vram_start; 782 u64 vram_end; 783 unsigned vram_width; 784 u64 real_vram_size; 785 int vram_mtrr; 786 u64 gtt_base_align; 787 u64 mc_mask; 788 const struct firmware *fw; /* MC firmware */ 789 uint32_t fw_version; 790 struct amdgpu_irq_src vm_fault; 791 uint32_t vram_type; 792 }; 793 794 /* 795 * GPU doorbell structures, functions & helpers 796 */ 797 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 798 { 799 AMDGPU_DOORBELL_KIQ = 0x000, 800 AMDGPU_DOORBELL_HIQ = 0x001, 801 AMDGPU_DOORBELL_DIQ = 0x002, 802 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 803 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 804 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 805 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 806 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 807 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 808 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 809 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 810 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 811 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 812 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 813 AMDGPU_DOORBELL_IH = 0x1E8, 814 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 815 AMDGPU_DOORBELL_INVALID = 0xFFFF 816 } AMDGPU_DOORBELL_ASSIGNMENT; 817 818 struct amdgpu_doorbell { 819 /* doorbell mmio */ 820 resource_size_t base; 821 resource_size_t size; 822 u32 __iomem *ptr; 823 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 824 }; 825 826 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 827 phys_addr_t *aperture_base, 828 size_t *aperture_size, 829 size_t *start_offset); 830 831 /* 832 * IRQS. 833 */ 834 835 struct amdgpu_flip_work { 836 struct work_struct flip_work; 837 struct work_struct unpin_work; 838 struct amdgpu_device *adev; 839 int crtc_id; 840 uint64_t base; 841 struct drm_pending_vblank_event *event; 842 struct amdgpu_bo *old_rbo; 843 struct fence *excl; 844 unsigned shared_count; 845 struct fence **shared; 846 }; 847 848 849 /* 850 * CP & rings. 851 */ 852 853 struct amdgpu_ib { 854 struct amdgpu_sa_bo *sa_bo; 855 uint32_t length_dw; 856 uint64_t gpu_addr; 857 uint32_t *ptr; 858 struct amdgpu_ring *ring; 859 struct amdgpu_fence *fence; 860 struct amdgpu_user_fence *user; 861 struct amdgpu_vm *vm; 862 struct amdgpu_ctx *ctx; 863 struct amdgpu_sync sync; 864 uint32_t gds_base, gds_size; 865 uint32_t gws_base, gws_size; 866 uint32_t oa_base, oa_size; 867 uint32_t flags; 868 /* resulting sequence number */ 869 uint64_t sequence; 870 }; 871 872 enum amdgpu_ring_type { 873 AMDGPU_RING_TYPE_GFX, 874 AMDGPU_RING_TYPE_COMPUTE, 875 AMDGPU_RING_TYPE_SDMA, 876 AMDGPU_RING_TYPE_UVD, 877 AMDGPU_RING_TYPE_VCE 878 }; 879 880 extern struct amd_sched_backend_ops amdgpu_sched_ops; 881 882 int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev, 883 struct amdgpu_ring *ring, 884 struct amdgpu_ib *ibs, 885 unsigned num_ibs, 886 int (*free_job)(struct amdgpu_job *), 887 void *owner, 888 struct fence **fence); 889 890 struct amdgpu_ring { 891 struct amdgpu_device *adev; 892 const struct amdgpu_ring_funcs *funcs; 893 struct amdgpu_fence_driver fence_drv; 894 struct amd_gpu_scheduler sched; 895 896 spinlock_t fence_lock; 897 struct mutex *ring_lock; 898 struct amdgpu_bo *ring_obj; 899 volatile uint32_t *ring; 900 unsigned rptr_offs; 901 u64 next_rptr_gpu_addr; 902 volatile u32 *next_rptr_cpu_addr; 903 unsigned wptr; 904 unsigned wptr_old; 905 unsigned ring_size; 906 unsigned ring_free_dw; 907 int count_dw; 908 uint64_t gpu_addr; 909 uint32_t align_mask; 910 uint32_t ptr_mask; 911 bool ready; 912 u32 nop; 913 u32 idx; 914 u64 last_semaphore_signal_addr; 915 u64 last_semaphore_wait_addr; 916 u32 me; 917 u32 pipe; 918 u32 queue; 919 struct amdgpu_bo *mqd_obj; 920 u32 doorbell_index; 921 bool use_doorbell; 922 unsigned wptr_offs; 923 unsigned next_rptr_offs; 924 unsigned fence_offs; 925 struct amdgpu_ctx *current_ctx; 926 enum amdgpu_ring_type type; 927 char name[16]; 928 bool is_pte_ring; 929 }; 930 931 /* 932 * VM 933 */ 934 935 /* maximum number of VMIDs */ 936 #define AMDGPU_NUM_VM 16 937 938 /* number of entries in page table */ 939 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size) 940 941 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 942 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768 943 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1) 944 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK) 945 946 #define AMDGPU_PTE_VALID (1 << 0) 947 #define AMDGPU_PTE_SYSTEM (1 << 1) 948 #define AMDGPU_PTE_SNOOPED (1 << 2) 949 950 /* VI only */ 951 #define AMDGPU_PTE_EXECUTABLE (1 << 4) 952 953 #define AMDGPU_PTE_READABLE (1 << 5) 954 #define AMDGPU_PTE_WRITEABLE (1 << 6) 955 956 /* PTE (Page Table Entry) fragment field for different page sizes */ 957 #define AMDGPU_PTE_FRAG_4KB (0 << 7) 958 #define AMDGPU_PTE_FRAG_64KB (4 << 7) 959 #define AMDGPU_LOG2_PAGES_PER_FRAG 4 960 961 /* How to programm VM fault handling */ 962 #define AMDGPU_VM_FAULT_STOP_NEVER 0 963 #define AMDGPU_VM_FAULT_STOP_FIRST 1 964 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 965 966 struct amdgpu_vm_pt { 967 struct amdgpu_bo *bo; 968 uint64_t addr; 969 }; 970 971 struct amdgpu_vm_id { 972 unsigned id; 973 uint64_t pd_gpu_addr; 974 /* last flushed PD/PT update */ 975 struct fence *flushed_updates; 976 /* last use of vmid */ 977 struct amdgpu_fence *last_id_use; 978 }; 979 980 struct amdgpu_vm { 981 struct mutex mutex; 982 983 struct rb_root va; 984 985 /* protecting invalidated */ 986 spinlock_t status_lock; 987 988 /* BOs moved, but not yet updated in the PT */ 989 struct list_head invalidated; 990 991 /* BOs cleared in the PT because of a move */ 992 struct list_head cleared; 993 994 /* BO mappings freed, but not yet updated in the PT */ 995 struct list_head freed; 996 997 /* contains the page directory */ 998 struct amdgpu_bo *page_directory; 999 unsigned max_pde_used; 1000 struct fence *page_directory_fence; 1001 1002 /* array of page tables, one for each page directory entry */ 1003 struct amdgpu_vm_pt *page_tables; 1004 1005 /* for id and flush management per ring */ 1006 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS]; 1007 }; 1008 1009 struct amdgpu_vm_manager { 1010 struct amdgpu_fence *active[AMDGPU_NUM_VM]; 1011 uint32_t max_pfn; 1012 /* number of VMIDs */ 1013 unsigned nvm; 1014 /* vram base address for page table entry */ 1015 u64 vram_base_offset; 1016 /* is vm enabled? */ 1017 bool enabled; 1018 /* for hw to save the PD addr on suspend/resume */ 1019 uint32_t saved_table_addr[AMDGPU_NUM_VM]; 1020 /* vm pte handling */ 1021 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 1022 struct amdgpu_ring *vm_pte_funcs_ring; 1023 }; 1024 1025 /* 1026 * context related structures 1027 */ 1028 1029 #define AMDGPU_CTX_MAX_CS_PENDING 16 1030 1031 struct amdgpu_ctx_ring { 1032 uint64_t sequence; 1033 struct fence *fences[AMDGPU_CTX_MAX_CS_PENDING]; 1034 struct amd_sched_entity entity; 1035 }; 1036 1037 struct amdgpu_ctx { 1038 struct kref refcount; 1039 struct amdgpu_device *adev; 1040 unsigned reset_counter; 1041 spinlock_t ring_lock; 1042 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; 1043 }; 1044 1045 struct amdgpu_ctx_mgr { 1046 struct amdgpu_device *adev; 1047 struct mutex lock; 1048 /* protected by lock */ 1049 struct idr ctx_handles; 1050 }; 1051 1052 int amdgpu_ctx_init(struct amdgpu_device *adev, bool kernel, 1053 struct amdgpu_ctx *ctx); 1054 void amdgpu_ctx_fini(struct amdgpu_ctx *ctx); 1055 1056 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 1057 int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 1058 1059 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 1060 struct fence *fence); 1061 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 1062 struct amdgpu_ring *ring, uint64_t seq); 1063 1064 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 1065 struct drm_file *filp); 1066 1067 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 1068 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 1069 1070 /* 1071 * file private structure 1072 */ 1073 1074 struct amdgpu_fpriv { 1075 struct amdgpu_vm vm; 1076 struct mutex bo_list_lock; 1077 struct idr bo_list_handles; 1078 struct amdgpu_ctx_mgr ctx_mgr; 1079 }; 1080 1081 /* 1082 * residency list 1083 */ 1084 1085 struct amdgpu_bo_list { 1086 struct mutex lock; 1087 struct amdgpu_bo *gds_obj; 1088 struct amdgpu_bo *gws_obj; 1089 struct amdgpu_bo *oa_obj; 1090 bool has_userptr; 1091 unsigned num_entries; 1092 struct amdgpu_bo_list_entry *array; 1093 }; 1094 1095 struct amdgpu_bo_list * 1096 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); 1097 void amdgpu_bo_list_put(struct amdgpu_bo_list *list); 1098 void amdgpu_bo_list_free(struct amdgpu_bo_list *list); 1099 1100 /* 1101 * GFX stuff 1102 */ 1103 #include "clearstate_defs.h" 1104 1105 struct amdgpu_rlc { 1106 /* for power gating */ 1107 struct amdgpu_bo *save_restore_obj; 1108 uint64_t save_restore_gpu_addr; 1109 volatile uint32_t *sr_ptr; 1110 const u32 *reg_list; 1111 u32 reg_list_size; 1112 /* for clear state */ 1113 struct amdgpu_bo *clear_state_obj; 1114 uint64_t clear_state_gpu_addr; 1115 volatile uint32_t *cs_ptr; 1116 const struct cs_section_def *cs_data; 1117 u32 clear_state_size; 1118 /* for cp tables */ 1119 struct amdgpu_bo *cp_table_obj; 1120 uint64_t cp_table_gpu_addr; 1121 volatile uint32_t *cp_table_ptr; 1122 u32 cp_table_size; 1123 }; 1124 1125 struct amdgpu_mec { 1126 struct amdgpu_bo *hpd_eop_obj; 1127 u64 hpd_eop_gpu_addr; 1128 u32 num_pipe; 1129 u32 num_mec; 1130 u32 num_queue; 1131 }; 1132 1133 /* 1134 * GPU scratch registers structures, functions & helpers 1135 */ 1136 struct amdgpu_scratch { 1137 unsigned num_reg; 1138 uint32_t reg_base; 1139 bool free[32]; 1140 uint32_t reg[32]; 1141 }; 1142 1143 /* 1144 * GFX configurations 1145 */ 1146 struct amdgpu_gca_config { 1147 unsigned max_shader_engines; 1148 unsigned max_tile_pipes; 1149 unsigned max_cu_per_sh; 1150 unsigned max_sh_per_se; 1151 unsigned max_backends_per_se; 1152 unsigned max_texture_channel_caches; 1153 unsigned max_gprs; 1154 unsigned max_gs_threads; 1155 unsigned max_hw_contexts; 1156 unsigned sc_prim_fifo_size_frontend; 1157 unsigned sc_prim_fifo_size_backend; 1158 unsigned sc_hiz_tile_fifo_size; 1159 unsigned sc_earlyz_tile_fifo_size; 1160 1161 unsigned num_tile_pipes; 1162 unsigned backend_enable_mask; 1163 unsigned mem_max_burst_length_bytes; 1164 unsigned mem_row_size_in_kb; 1165 unsigned shader_engine_tile_size; 1166 unsigned num_gpus; 1167 unsigned multi_gpu_tile_size; 1168 unsigned mc_arb_ramcfg; 1169 unsigned gb_addr_config; 1170 1171 uint32_t tile_mode_array[32]; 1172 uint32_t macrotile_mode_array[16]; 1173 }; 1174 1175 struct amdgpu_gfx { 1176 struct mutex gpu_clock_mutex; 1177 struct amdgpu_gca_config config; 1178 struct amdgpu_rlc rlc; 1179 struct amdgpu_mec mec; 1180 struct amdgpu_scratch scratch; 1181 const struct firmware *me_fw; /* ME firmware */ 1182 uint32_t me_fw_version; 1183 const struct firmware *pfp_fw; /* PFP firmware */ 1184 uint32_t pfp_fw_version; 1185 const struct firmware *ce_fw; /* CE firmware */ 1186 uint32_t ce_fw_version; 1187 const struct firmware *rlc_fw; /* RLC firmware */ 1188 uint32_t rlc_fw_version; 1189 const struct firmware *mec_fw; /* MEC firmware */ 1190 uint32_t mec_fw_version; 1191 const struct firmware *mec2_fw; /* MEC2 firmware */ 1192 uint32_t mec2_fw_version; 1193 uint32_t me_feature_version; 1194 uint32_t ce_feature_version; 1195 uint32_t pfp_feature_version; 1196 uint32_t rlc_feature_version; 1197 uint32_t mec_feature_version; 1198 uint32_t mec2_feature_version; 1199 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 1200 unsigned num_gfx_rings; 1201 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 1202 unsigned num_compute_rings; 1203 struct amdgpu_irq_src eop_irq; 1204 struct amdgpu_irq_src priv_reg_irq; 1205 struct amdgpu_irq_src priv_inst_irq; 1206 /* gfx status */ 1207 uint32_t gfx_current_status; 1208 /* ce ram size*/ 1209 unsigned ce_ram_size; 1210 }; 1211 1212 int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm, 1213 unsigned size, struct amdgpu_ib *ib); 1214 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib); 1215 int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, 1216 struct amdgpu_ib *ib, void *owner); 1217 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 1218 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 1219 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 1220 /* Ring access between begin & end cannot sleep */ 1221 void amdgpu_ring_free_size(struct amdgpu_ring *ring); 1222 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 1223 int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw); 1224 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 1225 void amdgpu_ring_commit(struct amdgpu_ring *ring); 1226 void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring); 1227 void amdgpu_ring_undo(struct amdgpu_ring *ring); 1228 void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring); 1229 unsigned amdgpu_ring_backup(struct amdgpu_ring *ring, 1230 uint32_t **data); 1231 int amdgpu_ring_restore(struct amdgpu_ring *ring, 1232 unsigned size, uint32_t *data); 1233 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 1234 unsigned ring_size, u32 nop, u32 align_mask, 1235 struct amdgpu_irq_src *irq_src, unsigned irq_type, 1236 enum amdgpu_ring_type ring_type); 1237 void amdgpu_ring_fini(struct amdgpu_ring *ring); 1238 1239 /* 1240 * CS. 1241 */ 1242 struct amdgpu_cs_chunk { 1243 uint32_t chunk_id; 1244 uint32_t length_dw; 1245 uint32_t *kdata; 1246 void __user *user_ptr; 1247 }; 1248 1249 struct amdgpu_cs_parser { 1250 struct amdgpu_device *adev; 1251 struct drm_file *filp; 1252 struct amdgpu_ctx *ctx; 1253 struct amdgpu_bo_list *bo_list; 1254 /* chunks */ 1255 unsigned nchunks; 1256 struct amdgpu_cs_chunk *chunks; 1257 /* relocations */ 1258 struct amdgpu_bo_list_entry *vm_bos; 1259 struct list_head validated; 1260 1261 struct amdgpu_ib *ibs; 1262 uint32_t num_ibs; 1263 1264 struct ww_acquire_ctx ticket; 1265 1266 /* user fence */ 1267 struct amdgpu_user_fence uf; 1268 }; 1269 1270 struct amdgpu_job { 1271 struct amd_sched_job base; 1272 struct amdgpu_device *adev; 1273 struct amdgpu_ib *ibs; 1274 uint32_t num_ibs; 1275 struct mutex job_lock; 1276 struct amdgpu_user_fence uf; 1277 int (*free_job)(struct amdgpu_job *job); 1278 }; 1279 #define to_amdgpu_job(sched_job) \ 1280 container_of((sched_job), struct amdgpu_job, base) 1281 1282 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx) 1283 { 1284 return p->ibs[ib_idx].ptr[idx]; 1285 } 1286 1287 /* 1288 * Writeback 1289 */ 1290 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 1291 1292 struct amdgpu_wb { 1293 struct amdgpu_bo *wb_obj; 1294 volatile uint32_t *wb; 1295 uint64_t gpu_addr; 1296 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 1297 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 1298 }; 1299 1300 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); 1301 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); 1302 1303 /** 1304 * struct amdgpu_pm - power management datas 1305 * It keeps track of various data needed to take powermanagement decision. 1306 */ 1307 1308 enum amdgpu_pm_state_type { 1309 /* not used for dpm */ 1310 POWER_STATE_TYPE_DEFAULT, 1311 POWER_STATE_TYPE_POWERSAVE, 1312 /* user selectable states */ 1313 POWER_STATE_TYPE_BATTERY, 1314 POWER_STATE_TYPE_BALANCED, 1315 POWER_STATE_TYPE_PERFORMANCE, 1316 /* internal states */ 1317 POWER_STATE_TYPE_INTERNAL_UVD, 1318 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1319 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1320 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1321 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1322 POWER_STATE_TYPE_INTERNAL_BOOT, 1323 POWER_STATE_TYPE_INTERNAL_THERMAL, 1324 POWER_STATE_TYPE_INTERNAL_ACPI, 1325 POWER_STATE_TYPE_INTERNAL_ULV, 1326 POWER_STATE_TYPE_INTERNAL_3DPERF, 1327 }; 1328 1329 enum amdgpu_int_thermal_type { 1330 THERMAL_TYPE_NONE, 1331 THERMAL_TYPE_EXTERNAL, 1332 THERMAL_TYPE_EXTERNAL_GPIO, 1333 THERMAL_TYPE_RV6XX, 1334 THERMAL_TYPE_RV770, 1335 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1336 THERMAL_TYPE_EVERGREEN, 1337 THERMAL_TYPE_SUMO, 1338 THERMAL_TYPE_NI, 1339 THERMAL_TYPE_SI, 1340 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1341 THERMAL_TYPE_CI, 1342 THERMAL_TYPE_KV, 1343 }; 1344 1345 enum amdgpu_dpm_auto_throttle_src { 1346 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, 1347 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1348 }; 1349 1350 enum amdgpu_dpm_event_src { 1351 AMDGPU_DPM_EVENT_SRC_ANALOG = 0, 1352 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1, 1353 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2, 1354 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1355 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1356 }; 1357 1358 #define AMDGPU_MAX_VCE_LEVELS 6 1359 1360 enum amdgpu_vce_level { 1361 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1362 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1363 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1364 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1365 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1366 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1367 }; 1368 1369 struct amdgpu_ps { 1370 u32 caps; /* vbios flags */ 1371 u32 class; /* vbios flags */ 1372 u32 class2; /* vbios flags */ 1373 /* UVD clocks */ 1374 u32 vclk; 1375 u32 dclk; 1376 /* VCE clocks */ 1377 u32 evclk; 1378 u32 ecclk; 1379 bool vce_active; 1380 enum amdgpu_vce_level vce_level; 1381 /* asic priv */ 1382 void *ps_priv; 1383 }; 1384 1385 struct amdgpu_dpm_thermal { 1386 /* thermal interrupt work */ 1387 struct work_struct work; 1388 /* low temperature threshold */ 1389 int min_temp; 1390 /* high temperature threshold */ 1391 int max_temp; 1392 /* was last interrupt low to high or high to low */ 1393 bool high_to_low; 1394 /* interrupt source */ 1395 struct amdgpu_irq_src irq; 1396 }; 1397 1398 enum amdgpu_clk_action 1399 { 1400 AMDGPU_SCLK_UP = 1, 1401 AMDGPU_SCLK_DOWN 1402 }; 1403 1404 struct amdgpu_blacklist_clocks 1405 { 1406 u32 sclk; 1407 u32 mclk; 1408 enum amdgpu_clk_action action; 1409 }; 1410 1411 struct amdgpu_clock_and_voltage_limits { 1412 u32 sclk; 1413 u32 mclk; 1414 u16 vddc; 1415 u16 vddci; 1416 }; 1417 1418 struct amdgpu_clock_array { 1419 u32 count; 1420 u32 *values; 1421 }; 1422 1423 struct amdgpu_clock_voltage_dependency_entry { 1424 u32 clk; 1425 u16 v; 1426 }; 1427 1428 struct amdgpu_clock_voltage_dependency_table { 1429 u32 count; 1430 struct amdgpu_clock_voltage_dependency_entry *entries; 1431 }; 1432 1433 union amdgpu_cac_leakage_entry { 1434 struct { 1435 u16 vddc; 1436 u32 leakage; 1437 }; 1438 struct { 1439 u16 vddc1; 1440 u16 vddc2; 1441 u16 vddc3; 1442 }; 1443 }; 1444 1445 struct amdgpu_cac_leakage_table { 1446 u32 count; 1447 union amdgpu_cac_leakage_entry *entries; 1448 }; 1449 1450 struct amdgpu_phase_shedding_limits_entry { 1451 u16 voltage; 1452 u32 sclk; 1453 u32 mclk; 1454 }; 1455 1456 struct amdgpu_phase_shedding_limits_table { 1457 u32 count; 1458 struct amdgpu_phase_shedding_limits_entry *entries; 1459 }; 1460 1461 struct amdgpu_uvd_clock_voltage_dependency_entry { 1462 u32 vclk; 1463 u32 dclk; 1464 u16 v; 1465 }; 1466 1467 struct amdgpu_uvd_clock_voltage_dependency_table { 1468 u8 count; 1469 struct amdgpu_uvd_clock_voltage_dependency_entry *entries; 1470 }; 1471 1472 struct amdgpu_vce_clock_voltage_dependency_entry { 1473 u32 ecclk; 1474 u32 evclk; 1475 u16 v; 1476 }; 1477 1478 struct amdgpu_vce_clock_voltage_dependency_table { 1479 u8 count; 1480 struct amdgpu_vce_clock_voltage_dependency_entry *entries; 1481 }; 1482 1483 struct amdgpu_ppm_table { 1484 u8 ppm_design; 1485 u16 cpu_core_number; 1486 u32 platform_tdp; 1487 u32 small_ac_platform_tdp; 1488 u32 platform_tdc; 1489 u32 small_ac_platform_tdc; 1490 u32 apu_tdp; 1491 u32 dgpu_tdp; 1492 u32 dgpu_ulv_power; 1493 u32 tj_max; 1494 }; 1495 1496 struct amdgpu_cac_tdp_table { 1497 u16 tdp; 1498 u16 configurable_tdp; 1499 u16 tdc; 1500 u16 battery_power_limit; 1501 u16 small_power_limit; 1502 u16 low_cac_leakage; 1503 u16 high_cac_leakage; 1504 u16 maximum_power_delivery_limit; 1505 }; 1506 1507 struct amdgpu_dpm_dynamic_state { 1508 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; 1509 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; 1510 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; 1511 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1512 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1513 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1514 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1515 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1516 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1517 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; 1518 struct amdgpu_clock_array valid_sclk_values; 1519 struct amdgpu_clock_array valid_mclk_values; 1520 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; 1521 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; 1522 u32 mclk_sclk_ratio; 1523 u32 sclk_mclk_delta; 1524 u16 vddc_vddci_delta; 1525 u16 min_vddc_for_pcie_gen2; 1526 struct amdgpu_cac_leakage_table cac_leakage_table; 1527 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; 1528 struct amdgpu_ppm_table *ppm_table; 1529 struct amdgpu_cac_tdp_table *cac_tdp_table; 1530 }; 1531 1532 struct amdgpu_dpm_fan { 1533 u16 t_min; 1534 u16 t_med; 1535 u16 t_high; 1536 u16 pwm_min; 1537 u16 pwm_med; 1538 u16 pwm_high; 1539 u8 t_hyst; 1540 u32 cycle_delay; 1541 u16 t_max; 1542 u8 control_mode; 1543 u16 default_max_fan_pwm; 1544 u16 default_fan_output_sensitivity; 1545 u16 fan_output_sensitivity; 1546 bool ucode_fan_control; 1547 }; 1548 1549 enum amdgpu_pcie_gen { 1550 AMDGPU_PCIE_GEN1 = 0, 1551 AMDGPU_PCIE_GEN2 = 1, 1552 AMDGPU_PCIE_GEN3 = 2, 1553 AMDGPU_PCIE_GEN_INVALID = 0xffff 1554 }; 1555 1556 enum amdgpu_dpm_forced_level { 1557 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0, 1558 AMDGPU_DPM_FORCED_LEVEL_LOW = 1, 1559 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2, 1560 }; 1561 1562 struct amdgpu_vce_state { 1563 /* vce clocks */ 1564 u32 evclk; 1565 u32 ecclk; 1566 /* gpu clocks */ 1567 u32 sclk; 1568 u32 mclk; 1569 u8 clk_idx; 1570 u8 pstate; 1571 }; 1572 1573 struct amdgpu_dpm_funcs { 1574 int (*get_temperature)(struct amdgpu_device *adev); 1575 int (*pre_set_power_state)(struct amdgpu_device *adev); 1576 int (*set_power_state)(struct amdgpu_device *adev); 1577 void (*post_set_power_state)(struct amdgpu_device *adev); 1578 void (*display_configuration_changed)(struct amdgpu_device *adev); 1579 u32 (*get_sclk)(struct amdgpu_device *adev, bool low); 1580 u32 (*get_mclk)(struct amdgpu_device *adev, bool low); 1581 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps); 1582 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m); 1583 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level); 1584 bool (*vblank_too_short)(struct amdgpu_device *adev); 1585 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate); 1586 void (*powergate_vce)(struct amdgpu_device *adev, bool gate); 1587 void (*enable_bapm)(struct amdgpu_device *adev, bool enable); 1588 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode); 1589 u32 (*get_fan_control_mode)(struct amdgpu_device *adev); 1590 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed); 1591 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed); 1592 }; 1593 1594 struct amdgpu_dpm { 1595 struct amdgpu_ps *ps; 1596 /* number of valid power states */ 1597 int num_ps; 1598 /* current power state that is active */ 1599 struct amdgpu_ps *current_ps; 1600 /* requested power state */ 1601 struct amdgpu_ps *requested_ps; 1602 /* boot up power state */ 1603 struct amdgpu_ps *boot_ps; 1604 /* default uvd power state */ 1605 struct amdgpu_ps *uvd_ps; 1606 /* vce requirements */ 1607 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS]; 1608 enum amdgpu_vce_level vce_level; 1609 enum amdgpu_pm_state_type state; 1610 enum amdgpu_pm_state_type user_state; 1611 u32 platform_caps; 1612 u32 voltage_response_time; 1613 u32 backbias_response_time; 1614 void *priv; 1615 u32 new_active_crtcs; 1616 int new_active_crtc_count; 1617 u32 current_active_crtcs; 1618 int current_active_crtc_count; 1619 struct amdgpu_dpm_dynamic_state dyn_state; 1620 struct amdgpu_dpm_fan fan; 1621 u32 tdp_limit; 1622 u32 near_tdp_limit; 1623 u32 near_tdp_limit_adjusted; 1624 u32 sq_ramping_threshold; 1625 u32 cac_leakage; 1626 u16 tdp_od_limit; 1627 u32 tdp_adjustment; 1628 u16 load_line_slope; 1629 bool power_control; 1630 bool ac_power; 1631 /* special states active */ 1632 bool thermal_active; 1633 bool uvd_active; 1634 bool vce_active; 1635 /* thermal handling */ 1636 struct amdgpu_dpm_thermal thermal; 1637 /* forced levels */ 1638 enum amdgpu_dpm_forced_level forced_level; 1639 }; 1640 1641 struct amdgpu_pm { 1642 struct mutex mutex; 1643 u32 current_sclk; 1644 u32 current_mclk; 1645 u32 default_sclk; 1646 u32 default_mclk; 1647 struct amdgpu_i2c_chan *i2c_bus; 1648 /* internal thermal controller on rv6xx+ */ 1649 enum amdgpu_int_thermal_type int_thermal_type; 1650 struct device *int_hwmon_dev; 1651 /* fan control parameters */ 1652 bool no_fan; 1653 u8 fan_pulses_per_revolution; 1654 u8 fan_min_rpm; 1655 u8 fan_max_rpm; 1656 /* dpm */ 1657 bool dpm_enabled; 1658 struct amdgpu_dpm dpm; 1659 const struct firmware *fw; /* SMC firmware */ 1660 uint32_t fw_version; 1661 const struct amdgpu_dpm_funcs *funcs; 1662 }; 1663 1664 /* 1665 * UVD 1666 */ 1667 #define AMDGPU_MAX_UVD_HANDLES 10 1668 #define AMDGPU_UVD_STACK_SIZE (1024*1024) 1669 #define AMDGPU_UVD_HEAP_SIZE (1024*1024) 1670 #define AMDGPU_UVD_FIRMWARE_OFFSET 256 1671 1672 struct amdgpu_uvd { 1673 struct amdgpu_bo *vcpu_bo; 1674 void *cpu_addr; 1675 uint64_t gpu_addr; 1676 atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; 1677 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; 1678 struct delayed_work idle_work; 1679 const struct firmware *fw; /* UVD firmware */ 1680 struct amdgpu_ring ring; 1681 struct amdgpu_irq_src irq; 1682 bool address_64_bit; 1683 }; 1684 1685 /* 1686 * VCE 1687 */ 1688 #define AMDGPU_MAX_VCE_HANDLES 16 1689 #define AMDGPU_VCE_FIRMWARE_OFFSET 256 1690 1691 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0) 1692 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1) 1693 1694 struct amdgpu_vce { 1695 struct amdgpu_bo *vcpu_bo; 1696 uint64_t gpu_addr; 1697 unsigned fw_version; 1698 unsigned fb_version; 1699 atomic_t handles[AMDGPU_MAX_VCE_HANDLES]; 1700 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES]; 1701 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES]; 1702 struct delayed_work idle_work; 1703 const struct firmware *fw; /* VCE firmware */ 1704 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS]; 1705 struct amdgpu_irq_src irq; 1706 unsigned harvest_config; 1707 }; 1708 1709 /* 1710 * SDMA 1711 */ 1712 struct amdgpu_sdma_instance { 1713 /* SDMA firmware */ 1714 const struct firmware *fw; 1715 uint32_t fw_version; 1716 uint32_t feature_version; 1717 1718 struct amdgpu_ring ring; 1719 bool burst_nop; 1720 }; 1721 1722 struct amdgpu_sdma { 1723 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 1724 struct amdgpu_irq_src trap_irq; 1725 struct amdgpu_irq_src illegal_inst_irq; 1726 int num_instances; 1727 }; 1728 1729 /* 1730 * Firmware 1731 */ 1732 struct amdgpu_firmware { 1733 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 1734 bool smu_load; 1735 struct amdgpu_bo *fw_buf; 1736 unsigned int fw_size; 1737 }; 1738 1739 /* 1740 * Benchmarking 1741 */ 1742 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 1743 1744 1745 /* 1746 * Testing 1747 */ 1748 void amdgpu_test_moves(struct amdgpu_device *adev); 1749 void amdgpu_test_ring_sync(struct amdgpu_device *adev, 1750 struct amdgpu_ring *cpA, 1751 struct amdgpu_ring *cpB); 1752 void amdgpu_test_syncing(struct amdgpu_device *adev); 1753 1754 /* 1755 * MMU Notifier 1756 */ 1757 #if defined(CONFIG_MMU_NOTIFIER) 1758 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); 1759 void amdgpu_mn_unregister(struct amdgpu_bo *bo); 1760 #else 1761 static int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) 1762 { 1763 return -ENODEV; 1764 } 1765 static void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} 1766 #endif 1767 1768 /* 1769 * Debugfs 1770 */ 1771 struct amdgpu_debugfs { 1772 struct drm_info_list *files; 1773 unsigned num_files; 1774 }; 1775 1776 int amdgpu_debugfs_add_files(struct amdgpu_device *adev, 1777 struct drm_info_list *files, 1778 unsigned nfiles); 1779 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); 1780 1781 #if defined(CONFIG_DEBUG_FS) 1782 int amdgpu_debugfs_init(struct drm_minor *minor); 1783 void amdgpu_debugfs_cleanup(struct drm_minor *minor); 1784 #endif 1785 1786 /* 1787 * amdgpu smumgr functions 1788 */ 1789 struct amdgpu_smumgr_funcs { 1790 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 1791 int (*request_smu_load_fw)(struct amdgpu_device *adev); 1792 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 1793 }; 1794 1795 /* 1796 * amdgpu smumgr 1797 */ 1798 struct amdgpu_smumgr { 1799 struct amdgpu_bo *toc_buf; 1800 struct amdgpu_bo *smu_buf; 1801 /* asic priv smu data */ 1802 void *priv; 1803 spinlock_t smu_lock; 1804 /* smumgr functions */ 1805 const struct amdgpu_smumgr_funcs *smumgr_funcs; 1806 /* ucode loading complete flag */ 1807 uint32_t fw_flags; 1808 }; 1809 1810 /* 1811 * ASIC specific register table accessible by UMD 1812 */ 1813 struct amdgpu_allowed_register_entry { 1814 uint32_t reg_offset; 1815 bool untouched; 1816 bool grbm_indexed; 1817 }; 1818 1819 struct amdgpu_cu_info { 1820 uint32_t number; /* total active CU number */ 1821 uint32_t ao_cu_mask; 1822 uint32_t bitmap[4][4]; 1823 }; 1824 1825 1826 /* 1827 * ASIC specific functions. 1828 */ 1829 struct amdgpu_asic_funcs { 1830 bool (*read_disabled_bios)(struct amdgpu_device *adev); 1831 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 1832 u32 sh_num, u32 reg_offset, u32 *value); 1833 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 1834 int (*reset)(struct amdgpu_device *adev); 1835 /* wait for mc_idle */ 1836 int (*wait_for_mc_idle)(struct amdgpu_device *adev); 1837 /* get the reference clock */ 1838 u32 (*get_xclk)(struct amdgpu_device *adev); 1839 /* get the gpu clock counter */ 1840 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 1841 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info); 1842 /* MM block clocks */ 1843 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 1844 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 1845 }; 1846 1847 /* 1848 * IOCTL. 1849 */ 1850 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 1851 struct drm_file *filp); 1852 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 1853 struct drm_file *filp); 1854 1855 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 1856 struct drm_file *filp); 1857 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 1858 struct drm_file *filp); 1859 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 1860 struct drm_file *filp); 1861 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1862 struct drm_file *filp); 1863 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 1864 struct drm_file *filp); 1865 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 1866 struct drm_file *filp); 1867 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1868 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1869 1870 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 1871 struct drm_file *filp); 1872 1873 /* VRAM scratch page for HDP bug, default vram page */ 1874 struct amdgpu_vram_scratch { 1875 struct amdgpu_bo *robj; 1876 volatile uint32_t *ptr; 1877 u64 gpu_addr; 1878 }; 1879 1880 /* 1881 * ACPI 1882 */ 1883 struct amdgpu_atif_notification_cfg { 1884 bool enabled; 1885 int command_code; 1886 }; 1887 1888 struct amdgpu_atif_notifications { 1889 bool display_switch; 1890 bool expansion_mode_change; 1891 bool thermal_state; 1892 bool forced_power_state; 1893 bool system_power_state; 1894 bool display_conf_change; 1895 bool px_gfx_switch; 1896 bool brightness_change; 1897 bool dgpu_display_event; 1898 }; 1899 1900 struct amdgpu_atif_functions { 1901 bool system_params; 1902 bool sbios_requests; 1903 bool select_active_disp; 1904 bool lid_state; 1905 bool get_tv_standard; 1906 bool set_tv_standard; 1907 bool get_panel_expansion_mode; 1908 bool set_panel_expansion_mode; 1909 bool temperature_change; 1910 bool graphics_device_types; 1911 }; 1912 1913 struct amdgpu_atif { 1914 struct amdgpu_atif_notifications notifications; 1915 struct amdgpu_atif_functions functions; 1916 struct amdgpu_atif_notification_cfg notification_cfg; 1917 struct amdgpu_encoder *encoder_for_bl; 1918 }; 1919 1920 struct amdgpu_atcs_functions { 1921 bool get_ext_state; 1922 bool pcie_perf_req; 1923 bool pcie_dev_rdy; 1924 bool pcie_bus_width; 1925 }; 1926 1927 struct amdgpu_atcs { 1928 struct amdgpu_atcs_functions functions; 1929 }; 1930 1931 /* 1932 * CGS 1933 */ 1934 void *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1935 void amdgpu_cgs_destroy_device(void *cgs_device); 1936 1937 1938 /* 1939 * Core structure, functions and helpers. 1940 */ 1941 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 1942 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1943 1944 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1945 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 1946 1947 struct amdgpu_ip_block_status { 1948 bool valid; 1949 bool sw; 1950 bool hw; 1951 }; 1952 1953 struct amdgpu_device { 1954 struct device *dev; 1955 struct drm_device *ddev; 1956 struct pci_dev *pdev; 1957 1958 /* ASIC */ 1959 enum amd_asic_type asic_type; 1960 uint32_t family; 1961 uint32_t rev_id; 1962 uint32_t external_rev_id; 1963 unsigned long flags; 1964 int usec_timeout; 1965 const struct amdgpu_asic_funcs *asic_funcs; 1966 bool shutdown; 1967 bool suspend; 1968 bool need_dma32; 1969 bool accel_working; 1970 struct work_struct reset_work; 1971 struct notifier_block acpi_nb; 1972 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 1973 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1974 unsigned debugfs_count; 1975 #if defined(CONFIG_DEBUG_FS) 1976 struct dentry *debugfs_regs; 1977 #endif 1978 struct amdgpu_atif atif; 1979 struct amdgpu_atcs atcs; 1980 struct mutex srbm_mutex; 1981 /* GRBM index mutex. Protects concurrent access to GRBM index */ 1982 struct mutex grbm_idx_mutex; 1983 struct dev_pm_domain vga_pm_domain; 1984 bool have_disp_power_ref; 1985 1986 /* BIOS */ 1987 uint8_t *bios; 1988 bool is_atom_bios; 1989 uint16_t bios_header_start; 1990 struct amdgpu_bo *stollen_vga_memory; 1991 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 1992 1993 /* Register/doorbell mmio */ 1994 resource_size_t rmmio_base; 1995 resource_size_t rmmio_size; 1996 void __iomem *rmmio; 1997 /* protects concurrent MM_INDEX/DATA based register access */ 1998 spinlock_t mmio_idx_lock; 1999 /* protects concurrent SMC based register access */ 2000 spinlock_t smc_idx_lock; 2001 amdgpu_rreg_t smc_rreg; 2002 amdgpu_wreg_t smc_wreg; 2003 /* protects concurrent PCIE register access */ 2004 spinlock_t pcie_idx_lock; 2005 amdgpu_rreg_t pcie_rreg; 2006 amdgpu_wreg_t pcie_wreg; 2007 /* protects concurrent UVD register access */ 2008 spinlock_t uvd_ctx_idx_lock; 2009 amdgpu_rreg_t uvd_ctx_rreg; 2010 amdgpu_wreg_t uvd_ctx_wreg; 2011 /* protects concurrent DIDT register access */ 2012 spinlock_t didt_idx_lock; 2013 amdgpu_rreg_t didt_rreg; 2014 amdgpu_wreg_t didt_wreg; 2015 /* protects concurrent ENDPOINT (audio) register access */ 2016 spinlock_t audio_endpt_idx_lock; 2017 amdgpu_block_rreg_t audio_endpt_rreg; 2018 amdgpu_block_wreg_t audio_endpt_wreg; 2019 void __iomem *rio_mem; 2020 resource_size_t rio_mem_size; 2021 struct amdgpu_doorbell doorbell; 2022 2023 /* clock/pll info */ 2024 struct amdgpu_clock clock; 2025 2026 /* MC */ 2027 struct amdgpu_mc mc; 2028 struct amdgpu_gart gart; 2029 struct amdgpu_dummy_page dummy_page; 2030 struct amdgpu_vm_manager vm_manager; 2031 2032 /* memory management */ 2033 struct amdgpu_mman mman; 2034 struct amdgpu_gem gem; 2035 struct amdgpu_vram_scratch vram_scratch; 2036 struct amdgpu_wb wb; 2037 atomic64_t vram_usage; 2038 atomic64_t vram_vis_usage; 2039 atomic64_t gtt_usage; 2040 atomic64_t num_bytes_moved; 2041 atomic_t gpu_reset_counter; 2042 2043 /* display */ 2044 struct amdgpu_mode_info mode_info; 2045 struct work_struct hotplug_work; 2046 struct amdgpu_irq_src crtc_irq; 2047 struct amdgpu_irq_src pageflip_irq; 2048 struct amdgpu_irq_src hpd_irq; 2049 2050 /* rings */ 2051 unsigned fence_context; 2052 struct mutex ring_lock; 2053 unsigned num_rings; 2054 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 2055 bool ib_pool_ready; 2056 struct amdgpu_sa_manager ring_tmp_bo; 2057 2058 /* interrupts */ 2059 struct amdgpu_irq irq; 2060 2061 /* dpm */ 2062 struct amdgpu_pm pm; 2063 u32 cg_flags; 2064 u32 pg_flags; 2065 2066 /* amdgpu smumgr */ 2067 struct amdgpu_smumgr smu; 2068 2069 /* gfx */ 2070 struct amdgpu_gfx gfx; 2071 2072 /* sdma */ 2073 struct amdgpu_sdma sdma; 2074 2075 /* uvd */ 2076 bool has_uvd; 2077 struct amdgpu_uvd uvd; 2078 2079 /* vce */ 2080 struct amdgpu_vce vce; 2081 2082 /* firmwares */ 2083 struct amdgpu_firmware firmware; 2084 2085 /* GDS */ 2086 struct amdgpu_gds gds; 2087 2088 const struct amdgpu_ip_block_version *ip_blocks; 2089 int num_ip_blocks; 2090 struct amdgpu_ip_block_status *ip_block_status; 2091 struct mutex mn_lock; 2092 DECLARE_HASHTABLE(mn_hash, 7); 2093 2094 /* tracking pinned memory */ 2095 u64 vram_pin_size; 2096 u64 gart_pin_size; 2097 2098 /* amdkfd interface */ 2099 struct kfd_dev *kfd; 2100 2101 /* kernel conext for IB submission */ 2102 struct amdgpu_ctx kernel_ctx; 2103 }; 2104 2105 bool amdgpu_device_is_px(struct drm_device *dev); 2106 int amdgpu_device_init(struct amdgpu_device *adev, 2107 struct drm_device *ddev, 2108 struct pci_dev *pdev, 2109 uint32_t flags); 2110 void amdgpu_device_fini(struct amdgpu_device *adev); 2111 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 2112 2113 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 2114 bool always_indirect); 2115 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 2116 bool always_indirect); 2117 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 2118 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 2119 2120 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 2121 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 2122 2123 /* 2124 * Cast helper 2125 */ 2126 extern const struct fence_ops amdgpu_fence_ops; 2127 static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f) 2128 { 2129 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base); 2130 2131 if (__f->base.ops == &amdgpu_fence_ops) 2132 return __f; 2133 2134 return NULL; 2135 } 2136 2137 /* 2138 * Registers read & write functions. 2139 */ 2140 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false) 2141 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true) 2142 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false)) 2143 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false) 2144 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true) 2145 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2146 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2147 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 2148 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 2149 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 2150 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 2151 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 2152 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 2153 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 2154 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 2155 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 2156 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 2157 #define WREG32_P(reg, val, mask) \ 2158 do { \ 2159 uint32_t tmp_ = RREG32(reg); \ 2160 tmp_ &= (mask); \ 2161 tmp_ |= ((val) & ~(mask)); \ 2162 WREG32(reg, tmp_); \ 2163 } while (0) 2164 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2165 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2166 #define WREG32_PLL_P(reg, val, mask) \ 2167 do { \ 2168 uint32_t tmp_ = RREG32_PLL(reg); \ 2169 tmp_ &= (mask); \ 2170 tmp_ |= ((val) & ~(mask)); \ 2171 WREG32_PLL(reg, tmp_); \ 2172 } while (0) 2173 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 2174 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 2175 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 2176 2177 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 2178 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 2179 2180 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 2181 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 2182 2183 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 2184 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 2185 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 2186 2187 #define REG_GET_FIELD(value, reg, field) \ 2188 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 2189 2190 /* 2191 * BIOS helpers. 2192 */ 2193 #define RBIOS8(i) (adev->bios[i]) 2194 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2195 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2196 2197 /* 2198 * RING helpers. 2199 */ 2200 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 2201 { 2202 if (ring->count_dw <= 0) 2203 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 2204 ring->ring[ring->wptr++] = v; 2205 ring->wptr &= ring->ptr_mask; 2206 ring->count_dw--; 2207 ring->ring_free_dw--; 2208 } 2209 2210 static inline struct amdgpu_sdma_instance * 2211 amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 2212 { 2213 struct amdgpu_device *adev = ring->adev; 2214 int i; 2215 2216 for (i = 0; i < adev->sdma.num_instances; i++) 2217 if (&adev->sdma.instance[i].ring == ring) 2218 break; 2219 2220 if (i < AMDGPU_MAX_SDMA_INSTANCES) 2221 return &adev->sdma.instance[i]; 2222 else 2223 return NULL; 2224 } 2225 2226 /* 2227 * ASICs macro. 2228 */ 2229 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 2230 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 2231 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev)) 2232 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 2233 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 2234 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 2235 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 2236 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 2237 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 2238 #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info)) 2239 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) 2240 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) 2241 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 2242 #define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags))) 2243 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 2244 #define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib))) 2245 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 2246 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 2247 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r)) 2248 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 2249 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 2250 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 2251 #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib)) 2252 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 2253 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 2254 #define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait)) 2255 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 2256 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 2257 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) 2258 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) 2259 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) 2260 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) 2261 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 2262 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) 2263 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev)) 2264 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 2265 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 2266 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 2267 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) 2268 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) 2269 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) 2270 #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base)) 2271 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) 2272 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) 2273 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) 2274 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s)) 2275 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) 2276 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 2277 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 2278 #define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev)) 2279 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev)) 2280 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev)) 2281 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev)) 2282 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev)) 2283 #define amdgpu_dpm_get_sclk(adev, l) (adev)->pm.funcs->get_sclk((adev), (l)) 2284 #define amdgpu_dpm_get_mclk(adev, l) (adev)->pm.funcs->get_mclk((adev), (l)) 2285 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps)) 2286 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)) 2287 #define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l)) 2288 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev)) 2289 #define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g)) 2290 #define amdgpu_dpm_powergate_vce(adev, g) (adev)->pm.funcs->powergate_vce((adev), (g)) 2291 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e)) 2292 #define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m)) 2293 #define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev)) 2294 #define amdgpu_dpm_set_fan_speed_percent(adev, s) (adev)->pm.funcs->set_fan_speed_percent((adev), (s)) 2295 #define amdgpu_dpm_get_fan_speed_percent(adev, s) (adev)->pm.funcs->get_fan_speed_percent((adev), (s)) 2296 2297 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) 2298 2299 /* Common functions */ 2300 int amdgpu_gpu_reset(struct amdgpu_device *adev); 2301 void amdgpu_pci_config_reset(struct amdgpu_device *adev); 2302 bool amdgpu_card_posted(struct amdgpu_device *adev); 2303 void amdgpu_update_display_priority(struct amdgpu_device *adev); 2304 bool amdgpu_boot_test_post_card(struct amdgpu_device *adev); 2305 struct amdgpu_cs_parser *amdgpu_cs_parser_create(struct amdgpu_device *adev, 2306 struct drm_file *filp, 2307 struct amdgpu_ctx *ctx, 2308 struct amdgpu_ib *ibs, 2309 uint32_t num_ibs); 2310 2311 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); 2312 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 2313 u32 ip_instance, u32 ring, 2314 struct amdgpu_ring **out_ring); 2315 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain); 2316 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 2317 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2318 uint32_t flags); 2319 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 2320 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 2321 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 2322 struct ttm_mem_reg *mem); 2323 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); 2324 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); 2325 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); 2326 void amdgpu_program_register_sequence(struct amdgpu_device *adev, 2327 const u32 *registers, 2328 const u32 array_size); 2329 2330 bool amdgpu_device_is_px(struct drm_device *dev); 2331 /* atpx handler */ 2332 #if defined(CONFIG_VGA_SWITCHEROO) 2333 void amdgpu_register_atpx_handler(void); 2334 void amdgpu_unregister_atpx_handler(void); 2335 #else 2336 static inline void amdgpu_register_atpx_handler(void) {} 2337 static inline void amdgpu_unregister_atpx_handler(void) {} 2338 #endif 2339 2340 /* 2341 * KMS 2342 */ 2343 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 2344 extern int amdgpu_max_kms_ioctl; 2345 2346 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 2347 int amdgpu_driver_unload_kms(struct drm_device *dev); 2348 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 2349 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 2350 void amdgpu_driver_postclose_kms(struct drm_device *dev, 2351 struct drm_file *file_priv); 2352 void amdgpu_driver_preclose_kms(struct drm_device *dev, 2353 struct drm_file *file_priv); 2354 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2355 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2356 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 2357 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 2358 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 2359 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, 2360 int *max_error, 2361 struct timeval *vblank_time, 2362 unsigned flags); 2363 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 2364 unsigned long arg); 2365 2366 /* 2367 * vm 2368 */ 2369 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); 2370 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 2371 struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev, 2372 struct amdgpu_vm *vm, 2373 struct list_head *head); 2374 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, 2375 struct amdgpu_sync *sync); 2376 void amdgpu_vm_flush(struct amdgpu_ring *ring, 2377 struct amdgpu_vm *vm, 2378 struct fence *updates); 2379 void amdgpu_vm_fence(struct amdgpu_device *adev, 2380 struct amdgpu_vm *vm, 2381 struct amdgpu_fence *fence); 2382 uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr); 2383 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, 2384 struct amdgpu_vm *vm); 2385 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 2386 struct amdgpu_vm *vm); 2387 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, 2388 struct amdgpu_vm *vm, struct amdgpu_sync *sync); 2389 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 2390 struct amdgpu_bo_va *bo_va, 2391 struct ttm_mem_reg *mem); 2392 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 2393 struct amdgpu_bo *bo); 2394 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 2395 struct amdgpu_bo *bo); 2396 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 2397 struct amdgpu_vm *vm, 2398 struct amdgpu_bo *bo); 2399 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 2400 struct amdgpu_bo_va *bo_va, 2401 uint64_t addr, uint64_t offset, 2402 uint64_t size, uint32_t flags); 2403 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 2404 struct amdgpu_bo_va *bo_va, 2405 uint64_t addr); 2406 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, 2407 struct amdgpu_bo_va *bo_va); 2408 int amdgpu_vm_free_job(struct amdgpu_job *job); 2409 /* 2410 * functions used by amdgpu_encoder.c 2411 */ 2412 struct amdgpu_afmt_acr { 2413 u32 clock; 2414 2415 int n_32khz; 2416 int cts_32khz; 2417 2418 int n_44_1khz; 2419 int cts_44_1khz; 2420 2421 int n_48khz; 2422 int cts_48khz; 2423 2424 }; 2425 2426 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 2427 2428 /* amdgpu_acpi.c */ 2429 #if defined(CONFIG_ACPI) 2430 int amdgpu_acpi_init(struct amdgpu_device *adev); 2431 void amdgpu_acpi_fini(struct amdgpu_device *adev); 2432 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 2433 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 2434 u8 perf_req, bool advertise); 2435 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 2436 #else 2437 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 2438 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 2439 #endif 2440 2441 struct amdgpu_bo_va_mapping * 2442 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 2443 uint64_t addr, struct amdgpu_bo **bo); 2444 2445 #include "amdgpu_object.h" 2446 2447 #endif 2448