1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include <linux/atomic.h> 32 #include <linux/wait.h> 33 #include <linux/list.h> 34 #include <linux/kref.h> 35 #include <linux/interval_tree.h> 36 #include <linux/hashtable.h> 37 #include <linux/dma-fence.h> 38 39 #include <ttm/ttm_bo_api.h> 40 #include <ttm/ttm_bo_driver.h> 41 #include <ttm/ttm_placement.h> 42 #include <ttm/ttm_module.h> 43 #include <ttm/ttm_execbuf_util.h> 44 45 #include <drm/drmP.h> 46 #include <drm/drm_gem.h> 47 #include <drm/amdgpu_drm.h> 48 49 #include "amd_shared.h" 50 #include "amdgpu_mode.h" 51 #include "amdgpu_ih.h" 52 #include "amdgpu_irq.h" 53 #include "amdgpu_ucode.h" 54 #include "amdgpu_ttm.h" 55 #include "amdgpu_gds.h" 56 #include "amdgpu_sync.h" 57 #include "amdgpu_ring.h" 58 #include "amdgpu_vm.h" 59 #include "amd_powerplay.h" 60 #include "amdgpu_dpm.h" 61 #include "amdgpu_acp.h" 62 63 #include "gpu_scheduler.h" 64 #include "amdgpu_virt.h" 65 66 /* 67 * Modules parameters. 68 */ 69 extern int amdgpu_modeset; 70 extern int amdgpu_vram_limit; 71 extern int amdgpu_gart_size; 72 extern int amdgpu_moverate; 73 extern int amdgpu_benchmarking; 74 extern int amdgpu_testing; 75 extern int amdgpu_audio; 76 extern int amdgpu_disp_priority; 77 extern int amdgpu_hw_i2c; 78 extern int amdgpu_pcie_gen2; 79 extern int amdgpu_msi; 80 extern int amdgpu_lockup_timeout; 81 extern int amdgpu_dpm; 82 extern int amdgpu_smc_load_fw; 83 extern int amdgpu_aspm; 84 extern int amdgpu_runtime_pm; 85 extern unsigned amdgpu_ip_block_mask; 86 extern int amdgpu_bapm; 87 extern int amdgpu_deep_color; 88 extern int amdgpu_vm_size; 89 extern int amdgpu_vm_block_size; 90 extern int amdgpu_vm_fault_stop; 91 extern int amdgpu_vm_debug; 92 extern int amdgpu_sched_jobs; 93 extern int amdgpu_sched_hw_submission; 94 extern int amdgpu_powerplay; 95 extern int amdgpu_powercontainment; 96 extern unsigned amdgpu_pcie_gen_cap; 97 extern unsigned amdgpu_pcie_lane_cap; 98 extern unsigned amdgpu_cg_mask; 99 extern unsigned amdgpu_pg_mask; 100 extern char *amdgpu_disable_cu; 101 extern int amdgpu_sclk_deep_sleep_en; 102 extern char *amdgpu_virtual_display; 103 extern unsigned amdgpu_pp_feature_mask; 104 extern int amdgpu_vram_page_split; 105 106 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 107 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 108 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 109 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 110 #define AMDGPU_IB_POOL_SIZE 16 111 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 112 #define AMDGPUFB_CONN_LIMIT 4 113 #define AMDGPU_BIOS_NUM_SCRATCH 8 114 115 /* max number of IP instances */ 116 #define AMDGPU_MAX_SDMA_INSTANCES 2 117 118 /* hardcode that limit for now */ 119 #define AMDGPU_VA_RESERVED_SIZE (8 << 20) 120 121 /* hard reset data */ 122 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 123 124 /* reset flags */ 125 #define AMDGPU_RESET_GFX (1 << 0) 126 #define AMDGPU_RESET_COMPUTE (1 << 1) 127 #define AMDGPU_RESET_DMA (1 << 2) 128 #define AMDGPU_RESET_CP (1 << 3) 129 #define AMDGPU_RESET_GRBM (1 << 4) 130 #define AMDGPU_RESET_DMA1 (1 << 5) 131 #define AMDGPU_RESET_RLC (1 << 6) 132 #define AMDGPU_RESET_SEM (1 << 7) 133 #define AMDGPU_RESET_IH (1 << 8) 134 #define AMDGPU_RESET_VMC (1 << 9) 135 #define AMDGPU_RESET_MC (1 << 10) 136 #define AMDGPU_RESET_DISPLAY (1 << 11) 137 #define AMDGPU_RESET_UVD (1 << 12) 138 #define AMDGPU_RESET_VCE (1 << 13) 139 #define AMDGPU_RESET_VCE1 (1 << 14) 140 141 /* GFX current status */ 142 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 143 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 144 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 145 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 146 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 147 148 /* max cursor sizes (in pixels) */ 149 #define CIK_CURSOR_WIDTH 128 150 #define CIK_CURSOR_HEIGHT 128 151 152 struct amdgpu_device; 153 struct amdgpu_ib; 154 struct amdgpu_cs_parser; 155 struct amdgpu_job; 156 struct amdgpu_irq_src; 157 struct amdgpu_fpriv; 158 159 enum amdgpu_cp_irq { 160 AMDGPU_CP_IRQ_GFX_EOP = 0, 161 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 162 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 163 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 164 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 165 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 166 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 167 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 168 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 169 170 AMDGPU_CP_IRQ_LAST 171 }; 172 173 enum amdgpu_sdma_irq { 174 AMDGPU_SDMA_IRQ_TRAP0 = 0, 175 AMDGPU_SDMA_IRQ_TRAP1, 176 177 AMDGPU_SDMA_IRQ_LAST 178 }; 179 180 enum amdgpu_thermal_irq { 181 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 182 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 183 184 AMDGPU_THERMAL_IRQ_LAST 185 }; 186 187 int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 188 enum amd_ip_block_type block_type, 189 enum amd_clockgating_state state); 190 int amdgpu_set_powergating_state(struct amdgpu_device *adev, 191 enum amd_ip_block_type block_type, 192 enum amd_powergating_state state); 193 int amdgpu_wait_for_idle(struct amdgpu_device *adev, 194 enum amd_ip_block_type block_type); 195 bool amdgpu_is_idle(struct amdgpu_device *adev, 196 enum amd_ip_block_type block_type); 197 198 #define AMDGPU_MAX_IP_NUM 16 199 200 struct amdgpu_ip_block_status { 201 bool valid; 202 bool sw; 203 bool hw; 204 bool late_initialized; 205 bool hang; 206 }; 207 208 struct amdgpu_ip_block_version { 209 const enum amd_ip_block_type type; 210 const u32 major; 211 const u32 minor; 212 const u32 rev; 213 const struct amd_ip_funcs *funcs; 214 }; 215 216 struct amdgpu_ip_block { 217 struct amdgpu_ip_block_status status; 218 const struct amdgpu_ip_block_version *version; 219 }; 220 221 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 222 enum amd_ip_block_type type, 223 u32 major, u32 minor); 224 225 struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, 226 enum amd_ip_block_type type); 227 228 int amdgpu_ip_block_add(struct amdgpu_device *adev, 229 const struct amdgpu_ip_block_version *ip_block_version); 230 231 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 232 struct amdgpu_buffer_funcs { 233 /* maximum bytes in a single operation */ 234 uint32_t copy_max_bytes; 235 236 /* number of dw to reserve per operation */ 237 unsigned copy_num_dw; 238 239 /* used for buffer migration */ 240 void (*emit_copy_buffer)(struct amdgpu_ib *ib, 241 /* src addr in bytes */ 242 uint64_t src_offset, 243 /* dst addr in bytes */ 244 uint64_t dst_offset, 245 /* number of byte to transfer */ 246 uint32_t byte_count); 247 248 /* maximum bytes in a single operation */ 249 uint32_t fill_max_bytes; 250 251 /* number of dw to reserve per operation */ 252 unsigned fill_num_dw; 253 254 /* used for buffer clearing */ 255 void (*emit_fill_buffer)(struct amdgpu_ib *ib, 256 /* value to write to memory */ 257 uint32_t src_data, 258 /* dst addr in bytes */ 259 uint64_t dst_offset, 260 /* number of byte to fill */ 261 uint32_t byte_count); 262 }; 263 264 /* provided by hw blocks that can write ptes, e.g., sdma */ 265 struct amdgpu_vm_pte_funcs { 266 /* copy pte entries from GART */ 267 void (*copy_pte)(struct amdgpu_ib *ib, 268 uint64_t pe, uint64_t src, 269 unsigned count); 270 /* write pte one entry at a time with addr mapping */ 271 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, 272 uint64_t value, unsigned count, 273 uint32_t incr); 274 /* for linear pte/pde updates without addr mapping */ 275 void (*set_pte_pde)(struct amdgpu_ib *ib, 276 uint64_t pe, 277 uint64_t addr, unsigned count, 278 uint32_t incr, uint32_t flags); 279 }; 280 281 /* provided by the gmc block */ 282 struct amdgpu_gart_funcs { 283 /* flush the vm tlb via mmio */ 284 void (*flush_gpu_tlb)(struct amdgpu_device *adev, 285 uint32_t vmid); 286 /* write pte/pde updates using the cpu */ 287 int (*set_pte_pde)(struct amdgpu_device *adev, 288 void *cpu_pt_addr, /* cpu addr of page table */ 289 uint32_t gpu_page_idx, /* pte/pde to update */ 290 uint64_t addr, /* addr to write into pte/pde */ 291 uint32_t flags); /* access flags */ 292 }; 293 294 /* provided by the ih block */ 295 struct amdgpu_ih_funcs { 296 /* ring read/write ptr handling, called from interrupt context */ 297 u32 (*get_wptr)(struct amdgpu_device *adev); 298 void (*decode_iv)(struct amdgpu_device *adev, 299 struct amdgpu_iv_entry *entry); 300 void (*set_rptr)(struct amdgpu_device *adev); 301 }; 302 303 /* 304 * BIOS. 305 */ 306 bool amdgpu_get_bios(struct amdgpu_device *adev); 307 bool amdgpu_read_bios(struct amdgpu_device *adev); 308 309 /* 310 * Dummy page 311 */ 312 struct amdgpu_dummy_page { 313 struct page *page; 314 dma_addr_t addr; 315 }; 316 int amdgpu_dummy_page_init(struct amdgpu_device *adev); 317 void amdgpu_dummy_page_fini(struct amdgpu_device *adev); 318 319 320 /* 321 * Clocks 322 */ 323 324 #define AMDGPU_MAX_PPLL 3 325 326 struct amdgpu_clock { 327 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 328 struct amdgpu_pll spll; 329 struct amdgpu_pll mpll; 330 /* 10 Khz units */ 331 uint32_t default_mclk; 332 uint32_t default_sclk; 333 uint32_t default_dispclk; 334 uint32_t current_dispclk; 335 uint32_t dp_extclk; 336 uint32_t max_pixel_clock; 337 }; 338 339 /* 340 * BO. 341 */ 342 struct amdgpu_bo_list_entry { 343 struct amdgpu_bo *robj; 344 struct ttm_validate_buffer tv; 345 struct amdgpu_bo_va *bo_va; 346 uint32_t priority; 347 struct page **user_pages; 348 int user_invalidated; 349 }; 350 351 struct amdgpu_bo_va_mapping { 352 struct list_head list; 353 struct interval_tree_node it; 354 uint64_t offset; 355 uint32_t flags; 356 }; 357 358 /* bo virtual addresses in a specific vm */ 359 struct amdgpu_bo_va { 360 /* protected by bo being reserved */ 361 struct list_head bo_list; 362 struct dma_fence *last_pt_update; 363 unsigned ref_count; 364 365 /* protected by vm mutex and spinlock */ 366 struct list_head vm_status; 367 368 /* mappings for this bo_va */ 369 struct list_head invalids; 370 struct list_head valids; 371 372 /* constant after initialization */ 373 struct amdgpu_vm *vm; 374 struct amdgpu_bo *bo; 375 }; 376 377 #define AMDGPU_GEM_DOMAIN_MAX 0x3 378 379 struct amdgpu_bo { 380 /* Protected by tbo.reserved */ 381 u32 prefered_domains; 382 u32 allowed_domains; 383 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 384 struct ttm_placement placement; 385 struct ttm_buffer_object tbo; 386 struct ttm_bo_kmap_obj kmap; 387 u64 flags; 388 unsigned pin_count; 389 void *kptr; 390 u64 tiling_flags; 391 u64 metadata_flags; 392 void *metadata; 393 u32 metadata_size; 394 /* list of all virtual address to which this bo 395 * is associated to 396 */ 397 struct list_head va; 398 /* Constant after initialization */ 399 struct drm_gem_object gem_base; 400 struct amdgpu_bo *parent; 401 struct amdgpu_bo *shadow; 402 403 struct ttm_bo_kmap_obj dma_buf_vmap; 404 struct amdgpu_mn *mn; 405 struct list_head mn_list; 406 struct list_head shadow_list; 407 }; 408 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) 409 410 void amdgpu_gem_object_free(struct drm_gem_object *obj); 411 int amdgpu_gem_object_open(struct drm_gem_object *obj, 412 struct drm_file *file_priv); 413 void amdgpu_gem_object_close(struct drm_gem_object *obj, 414 struct drm_file *file_priv); 415 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 416 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); 417 struct drm_gem_object * 418 amdgpu_gem_prime_import_sg_table(struct drm_device *dev, 419 struct dma_buf_attachment *attach, 420 struct sg_table *sg); 421 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, 422 struct drm_gem_object *gobj, 423 int flags); 424 int amdgpu_gem_prime_pin(struct drm_gem_object *obj); 425 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); 426 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); 427 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); 428 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 429 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); 430 431 /* sub-allocation manager, it has to be protected by another lock. 432 * By conception this is an helper for other part of the driver 433 * like the indirect buffer or semaphore, which both have their 434 * locking. 435 * 436 * Principe is simple, we keep a list of sub allocation in offset 437 * order (first entry has offset == 0, last entry has the highest 438 * offset). 439 * 440 * When allocating new object we first check if there is room at 441 * the end total_size - (last_object_offset + last_object_size) >= 442 * alloc_size. If so we allocate new object there. 443 * 444 * When there is not enough room at the end, we start waiting for 445 * each sub object until we reach object_offset+object_size >= 446 * alloc_size, this object then become the sub object we return. 447 * 448 * Alignment can't be bigger than page size. 449 * 450 * Hole are not considered for allocation to keep things simple. 451 * Assumption is that there won't be hole (all object on same 452 * alignment). 453 */ 454 455 #define AMDGPU_SA_NUM_FENCE_LISTS 32 456 457 struct amdgpu_sa_manager { 458 wait_queue_head_t wq; 459 struct amdgpu_bo *bo; 460 struct list_head *hole; 461 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 462 struct list_head olist; 463 unsigned size; 464 uint64_t gpu_addr; 465 void *cpu_ptr; 466 uint32_t domain; 467 uint32_t align; 468 }; 469 470 /* sub-allocation buffer */ 471 struct amdgpu_sa_bo { 472 struct list_head olist; 473 struct list_head flist; 474 struct amdgpu_sa_manager *manager; 475 unsigned soffset; 476 unsigned eoffset; 477 struct dma_fence *fence; 478 }; 479 480 /* 481 * GEM objects. 482 */ 483 void amdgpu_gem_force_release(struct amdgpu_device *adev); 484 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 485 int alignment, u32 initial_domain, 486 u64 flags, bool kernel, 487 struct drm_gem_object **obj); 488 489 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 490 struct drm_device *dev, 491 struct drm_mode_create_dumb *args); 492 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 493 struct drm_device *dev, 494 uint32_t handle, uint64_t *offset_p); 495 int amdgpu_fence_slab_init(void); 496 void amdgpu_fence_slab_fini(void); 497 498 /* 499 * GART structures, functions & helpers 500 */ 501 struct amdgpu_mc; 502 503 #define AMDGPU_GPU_PAGE_SIZE 4096 504 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) 505 #define AMDGPU_GPU_PAGE_SHIFT 12 506 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) 507 508 struct amdgpu_gart { 509 dma_addr_t table_addr; 510 struct amdgpu_bo *robj; 511 void *ptr; 512 unsigned num_gpu_pages; 513 unsigned num_cpu_pages; 514 unsigned table_size; 515 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 516 struct page **pages; 517 #endif 518 bool ready; 519 const struct amdgpu_gart_funcs *gart_funcs; 520 }; 521 522 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); 523 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); 524 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); 525 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); 526 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); 527 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); 528 int amdgpu_gart_init(struct amdgpu_device *adev); 529 void amdgpu_gart_fini(struct amdgpu_device *adev); 530 void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, 531 int pages); 532 int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, 533 int pages, struct page **pagelist, 534 dma_addr_t *dma_addr, uint32_t flags); 535 int amdgpu_ttm_recover_gart(struct amdgpu_device *adev); 536 537 /* 538 * GPU MC structures, functions & helpers 539 */ 540 struct amdgpu_mc { 541 resource_size_t aper_size; 542 resource_size_t aper_base; 543 resource_size_t agp_base; 544 /* for some chips with <= 32MB we need to lie 545 * about vram size near mc fb location */ 546 u64 mc_vram_size; 547 u64 visible_vram_size; 548 u64 gtt_size; 549 u64 gtt_start; 550 u64 gtt_end; 551 u64 vram_start; 552 u64 vram_end; 553 unsigned vram_width; 554 u64 real_vram_size; 555 int vram_mtrr; 556 u64 gtt_base_align; 557 u64 mc_mask; 558 const struct firmware *fw; /* MC firmware */ 559 uint32_t fw_version; 560 struct amdgpu_irq_src vm_fault; 561 uint32_t vram_type; 562 uint32_t srbm_soft_reset; 563 struct amdgpu_mode_mc_save save; 564 }; 565 566 /* 567 * GPU doorbell structures, functions & helpers 568 */ 569 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 570 { 571 AMDGPU_DOORBELL_KIQ = 0x000, 572 AMDGPU_DOORBELL_HIQ = 0x001, 573 AMDGPU_DOORBELL_DIQ = 0x002, 574 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 575 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 576 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 577 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 578 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 579 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 580 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 581 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 582 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 583 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 584 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 585 AMDGPU_DOORBELL_IH = 0x1E8, 586 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 587 AMDGPU_DOORBELL_INVALID = 0xFFFF 588 } AMDGPU_DOORBELL_ASSIGNMENT; 589 590 struct amdgpu_doorbell { 591 /* doorbell mmio */ 592 resource_size_t base; 593 resource_size_t size; 594 u32 __iomem *ptr; 595 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 596 }; 597 598 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 599 phys_addr_t *aperture_base, 600 size_t *aperture_size, 601 size_t *start_offset); 602 603 /* 604 * IRQS. 605 */ 606 607 struct amdgpu_flip_work { 608 struct delayed_work flip_work; 609 struct work_struct unpin_work; 610 struct amdgpu_device *adev; 611 int crtc_id; 612 u32 target_vblank; 613 uint64_t base; 614 struct drm_pending_vblank_event *event; 615 struct amdgpu_bo *old_abo; 616 struct dma_fence *excl; 617 unsigned shared_count; 618 struct dma_fence **shared; 619 struct dma_fence_cb cb; 620 bool async; 621 }; 622 623 624 /* 625 * CP & rings. 626 */ 627 628 struct amdgpu_ib { 629 struct amdgpu_sa_bo *sa_bo; 630 uint32_t length_dw; 631 uint64_t gpu_addr; 632 uint32_t *ptr; 633 uint32_t flags; 634 }; 635 636 extern const struct amd_sched_backend_ops amdgpu_sched_ops; 637 638 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, 639 struct amdgpu_job **job, struct amdgpu_vm *vm); 640 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, 641 struct amdgpu_job **job); 642 643 void amdgpu_job_free_resources(struct amdgpu_job *job); 644 void amdgpu_job_free(struct amdgpu_job *job); 645 int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, 646 struct amd_sched_entity *entity, void *owner, 647 struct dma_fence **f); 648 649 /* 650 * context related structures 651 */ 652 653 struct amdgpu_ctx_ring { 654 uint64_t sequence; 655 struct dma_fence **fences; 656 struct amd_sched_entity entity; 657 }; 658 659 struct amdgpu_ctx { 660 struct kref refcount; 661 struct amdgpu_device *adev; 662 unsigned reset_counter; 663 spinlock_t ring_lock; 664 struct dma_fence **fences; 665 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; 666 bool preamble_presented; 667 }; 668 669 struct amdgpu_ctx_mgr { 670 struct amdgpu_device *adev; 671 struct mutex lock; 672 /* protected by lock */ 673 struct idr ctx_handles; 674 }; 675 676 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 677 int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 678 679 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 680 struct dma_fence *fence); 681 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 682 struct amdgpu_ring *ring, uint64_t seq); 683 684 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 685 struct drm_file *filp); 686 687 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 688 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 689 690 /* 691 * file private structure 692 */ 693 694 struct amdgpu_fpriv { 695 struct amdgpu_vm vm; 696 struct mutex bo_list_lock; 697 struct idr bo_list_handles; 698 struct amdgpu_ctx_mgr ctx_mgr; 699 }; 700 701 /* 702 * residency list 703 */ 704 705 struct amdgpu_bo_list { 706 struct mutex lock; 707 struct amdgpu_bo *gds_obj; 708 struct amdgpu_bo *gws_obj; 709 struct amdgpu_bo *oa_obj; 710 unsigned first_userptr; 711 unsigned num_entries; 712 struct amdgpu_bo_list_entry *array; 713 }; 714 715 struct amdgpu_bo_list * 716 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); 717 void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list, 718 struct list_head *validated); 719 void amdgpu_bo_list_put(struct amdgpu_bo_list *list); 720 void amdgpu_bo_list_free(struct amdgpu_bo_list *list); 721 722 /* 723 * GFX stuff 724 */ 725 #include "clearstate_defs.h" 726 727 struct amdgpu_rlc_funcs { 728 void (*enter_safe_mode)(struct amdgpu_device *adev); 729 void (*exit_safe_mode)(struct amdgpu_device *adev); 730 }; 731 732 struct amdgpu_rlc { 733 /* for power gating */ 734 struct amdgpu_bo *save_restore_obj; 735 uint64_t save_restore_gpu_addr; 736 volatile uint32_t *sr_ptr; 737 const u32 *reg_list; 738 u32 reg_list_size; 739 /* for clear state */ 740 struct amdgpu_bo *clear_state_obj; 741 uint64_t clear_state_gpu_addr; 742 volatile uint32_t *cs_ptr; 743 const struct cs_section_def *cs_data; 744 u32 clear_state_size; 745 /* for cp tables */ 746 struct amdgpu_bo *cp_table_obj; 747 uint64_t cp_table_gpu_addr; 748 volatile uint32_t *cp_table_ptr; 749 u32 cp_table_size; 750 751 /* safe mode for updating CG/PG state */ 752 bool in_safe_mode; 753 const struct amdgpu_rlc_funcs *funcs; 754 755 /* for firmware data */ 756 u32 save_and_restore_offset; 757 u32 clear_state_descriptor_offset; 758 u32 avail_scratch_ram_locations; 759 u32 reg_restore_list_size; 760 u32 reg_list_format_start; 761 u32 reg_list_format_separate_start; 762 u32 starting_offsets_start; 763 u32 reg_list_format_size_bytes; 764 u32 reg_list_size_bytes; 765 766 u32 *register_list_format; 767 u32 *register_restore; 768 }; 769 770 struct amdgpu_mec { 771 struct amdgpu_bo *hpd_eop_obj; 772 u64 hpd_eop_gpu_addr; 773 u32 num_pipe; 774 u32 num_mec; 775 u32 num_queue; 776 }; 777 778 /* 779 * GPU scratch registers structures, functions & helpers 780 */ 781 struct amdgpu_scratch { 782 unsigned num_reg; 783 uint32_t reg_base; 784 bool free[32]; 785 uint32_t reg[32]; 786 }; 787 788 /* 789 * GFX configurations 790 */ 791 #define AMDGPU_GFX_MAX_SE 4 792 #define AMDGPU_GFX_MAX_SH_PER_SE 2 793 794 struct amdgpu_rb_config { 795 uint32_t rb_backend_disable; 796 uint32_t user_rb_backend_disable; 797 uint32_t raster_config; 798 uint32_t raster_config_1; 799 }; 800 801 struct amdgpu_gca_config { 802 unsigned max_shader_engines; 803 unsigned max_tile_pipes; 804 unsigned max_cu_per_sh; 805 unsigned max_sh_per_se; 806 unsigned max_backends_per_se; 807 unsigned max_texture_channel_caches; 808 unsigned max_gprs; 809 unsigned max_gs_threads; 810 unsigned max_hw_contexts; 811 unsigned sc_prim_fifo_size_frontend; 812 unsigned sc_prim_fifo_size_backend; 813 unsigned sc_hiz_tile_fifo_size; 814 unsigned sc_earlyz_tile_fifo_size; 815 816 unsigned num_tile_pipes; 817 unsigned backend_enable_mask; 818 unsigned mem_max_burst_length_bytes; 819 unsigned mem_row_size_in_kb; 820 unsigned shader_engine_tile_size; 821 unsigned num_gpus; 822 unsigned multi_gpu_tile_size; 823 unsigned mc_arb_ramcfg; 824 unsigned gb_addr_config; 825 unsigned num_rbs; 826 827 uint32_t tile_mode_array[32]; 828 uint32_t macrotile_mode_array[16]; 829 830 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; 831 }; 832 833 struct amdgpu_cu_info { 834 uint32_t number; /* total active CU number */ 835 uint32_t ao_cu_mask; 836 uint32_t bitmap[4][4]; 837 }; 838 839 struct amdgpu_gfx_funcs { 840 /* get the gpu clock counter */ 841 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 842 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); 843 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields); 844 }; 845 846 struct amdgpu_gfx { 847 struct mutex gpu_clock_mutex; 848 struct amdgpu_gca_config config; 849 struct amdgpu_rlc rlc; 850 struct amdgpu_mec mec; 851 struct amdgpu_scratch scratch; 852 const struct firmware *me_fw; /* ME firmware */ 853 uint32_t me_fw_version; 854 const struct firmware *pfp_fw; /* PFP firmware */ 855 uint32_t pfp_fw_version; 856 const struct firmware *ce_fw; /* CE firmware */ 857 uint32_t ce_fw_version; 858 const struct firmware *rlc_fw; /* RLC firmware */ 859 uint32_t rlc_fw_version; 860 const struct firmware *mec_fw; /* MEC firmware */ 861 uint32_t mec_fw_version; 862 const struct firmware *mec2_fw; /* MEC2 firmware */ 863 uint32_t mec2_fw_version; 864 uint32_t me_feature_version; 865 uint32_t ce_feature_version; 866 uint32_t pfp_feature_version; 867 uint32_t rlc_feature_version; 868 uint32_t mec_feature_version; 869 uint32_t mec2_feature_version; 870 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 871 unsigned num_gfx_rings; 872 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 873 unsigned num_compute_rings; 874 struct amdgpu_irq_src eop_irq; 875 struct amdgpu_irq_src priv_reg_irq; 876 struct amdgpu_irq_src priv_inst_irq; 877 /* gfx status */ 878 uint32_t gfx_current_status; 879 /* ce ram size*/ 880 unsigned ce_ram_size; 881 struct amdgpu_cu_info cu_info; 882 const struct amdgpu_gfx_funcs *funcs; 883 884 /* reset mask */ 885 uint32_t grbm_soft_reset; 886 uint32_t srbm_soft_reset; 887 }; 888 889 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 890 unsigned size, struct amdgpu_ib *ib); 891 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 892 struct dma_fence *f); 893 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 894 struct amdgpu_ib *ib, struct dma_fence *last_vm_update, 895 struct amdgpu_job *job, struct dma_fence **f); 896 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 897 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 898 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 899 900 /* 901 * CS. 902 */ 903 struct amdgpu_cs_chunk { 904 uint32_t chunk_id; 905 uint32_t length_dw; 906 void *kdata; 907 }; 908 909 struct amdgpu_cs_parser { 910 struct amdgpu_device *adev; 911 struct drm_file *filp; 912 struct amdgpu_ctx *ctx; 913 914 /* chunks */ 915 unsigned nchunks; 916 struct amdgpu_cs_chunk *chunks; 917 918 /* scheduler job object */ 919 struct amdgpu_job *job; 920 921 /* buffer objects */ 922 struct ww_acquire_ctx ticket; 923 struct amdgpu_bo_list *bo_list; 924 struct amdgpu_bo_list_entry vm_pd; 925 struct list_head validated; 926 struct dma_fence *fence; 927 uint64_t bytes_moved_threshold; 928 uint64_t bytes_moved; 929 struct amdgpu_bo_list_entry *evictable; 930 931 /* user fence */ 932 struct amdgpu_bo_list_entry uf_entry; 933 }; 934 935 #define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */ 936 #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */ 937 #define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */ 938 939 struct amdgpu_job { 940 struct amd_sched_job base; 941 struct amdgpu_device *adev; 942 struct amdgpu_vm *vm; 943 struct amdgpu_ring *ring; 944 struct amdgpu_sync sync; 945 struct amdgpu_ib *ibs; 946 struct dma_fence *fence; /* the hw fence */ 947 uint32_t preamble_status; 948 uint32_t num_ibs; 949 void *owner; 950 uint64_t fence_ctx; /* the fence_context this job uses */ 951 bool vm_needs_flush; 952 unsigned vm_id; 953 uint64_t vm_pd_addr; 954 uint32_t gds_base, gds_size; 955 uint32_t gws_base, gws_size; 956 uint32_t oa_base, oa_size; 957 958 /* user fence handling */ 959 uint64_t uf_addr; 960 uint64_t uf_sequence; 961 962 }; 963 #define to_amdgpu_job(sched_job) \ 964 container_of((sched_job), struct amdgpu_job, base) 965 966 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 967 uint32_t ib_idx, int idx) 968 { 969 return p->job->ibs[ib_idx].ptr[idx]; 970 } 971 972 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 973 uint32_t ib_idx, int idx, 974 uint32_t value) 975 { 976 p->job->ibs[ib_idx].ptr[idx] = value; 977 } 978 979 /* 980 * Writeback 981 */ 982 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 983 984 struct amdgpu_wb { 985 struct amdgpu_bo *wb_obj; 986 volatile uint32_t *wb; 987 uint64_t gpu_addr; 988 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 989 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 990 }; 991 992 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); 993 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); 994 995 void amdgpu_get_pcie_info(struct amdgpu_device *adev); 996 997 /* 998 * UVD 999 */ 1000 #define AMDGPU_DEFAULT_UVD_HANDLES 10 1001 #define AMDGPU_MAX_UVD_HANDLES 40 1002 #define AMDGPU_UVD_STACK_SIZE (200*1024) 1003 #define AMDGPU_UVD_HEAP_SIZE (256*1024) 1004 #define AMDGPU_UVD_SESSION_SIZE (50*1024) 1005 #define AMDGPU_UVD_FIRMWARE_OFFSET 256 1006 1007 struct amdgpu_uvd { 1008 struct amdgpu_bo *vcpu_bo; 1009 void *cpu_addr; 1010 uint64_t gpu_addr; 1011 unsigned fw_version; 1012 void *saved_bo; 1013 unsigned max_handles; 1014 atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; 1015 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; 1016 struct delayed_work idle_work; 1017 const struct firmware *fw; /* UVD firmware */ 1018 struct amdgpu_ring ring; 1019 struct amdgpu_irq_src irq; 1020 bool address_64_bit; 1021 bool use_ctx_buf; 1022 struct amd_sched_entity entity; 1023 uint32_t srbm_soft_reset; 1024 }; 1025 1026 /* 1027 * VCE 1028 */ 1029 #define AMDGPU_MAX_VCE_HANDLES 16 1030 #define AMDGPU_VCE_FIRMWARE_OFFSET 256 1031 1032 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0) 1033 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1) 1034 1035 struct amdgpu_vce { 1036 struct amdgpu_bo *vcpu_bo; 1037 uint64_t gpu_addr; 1038 unsigned fw_version; 1039 unsigned fb_version; 1040 atomic_t handles[AMDGPU_MAX_VCE_HANDLES]; 1041 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES]; 1042 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES]; 1043 struct delayed_work idle_work; 1044 struct mutex idle_mutex; 1045 const struct firmware *fw; /* VCE firmware */ 1046 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS]; 1047 struct amdgpu_irq_src irq; 1048 unsigned harvest_config; 1049 struct amd_sched_entity entity; 1050 uint32_t srbm_soft_reset; 1051 unsigned num_rings; 1052 }; 1053 1054 /* 1055 * SDMA 1056 */ 1057 struct amdgpu_sdma_instance { 1058 /* SDMA firmware */ 1059 const struct firmware *fw; 1060 uint32_t fw_version; 1061 uint32_t feature_version; 1062 1063 struct amdgpu_ring ring; 1064 bool burst_nop; 1065 }; 1066 1067 struct amdgpu_sdma { 1068 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 1069 #ifdef CONFIG_DRM_AMDGPU_SI 1070 //SI DMA has a difference trap irq number for the second engine 1071 struct amdgpu_irq_src trap_irq_1; 1072 #endif 1073 struct amdgpu_irq_src trap_irq; 1074 struct amdgpu_irq_src illegal_inst_irq; 1075 int num_instances; 1076 uint32_t srbm_soft_reset; 1077 }; 1078 1079 /* 1080 * Firmware 1081 */ 1082 struct amdgpu_firmware { 1083 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 1084 bool smu_load; 1085 struct amdgpu_bo *fw_buf; 1086 unsigned int fw_size; 1087 }; 1088 1089 /* 1090 * Benchmarking 1091 */ 1092 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 1093 1094 1095 /* 1096 * Testing 1097 */ 1098 void amdgpu_test_moves(struct amdgpu_device *adev); 1099 void amdgpu_test_ring_sync(struct amdgpu_device *adev, 1100 struct amdgpu_ring *cpA, 1101 struct amdgpu_ring *cpB); 1102 void amdgpu_test_syncing(struct amdgpu_device *adev); 1103 1104 /* 1105 * MMU Notifier 1106 */ 1107 #if defined(CONFIG_MMU_NOTIFIER) 1108 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); 1109 void amdgpu_mn_unregister(struct amdgpu_bo *bo); 1110 #else 1111 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) 1112 { 1113 return -ENODEV; 1114 } 1115 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} 1116 #endif 1117 1118 /* 1119 * Debugfs 1120 */ 1121 struct amdgpu_debugfs { 1122 const struct drm_info_list *files; 1123 unsigned num_files; 1124 }; 1125 1126 int amdgpu_debugfs_add_files(struct amdgpu_device *adev, 1127 const struct drm_info_list *files, 1128 unsigned nfiles); 1129 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); 1130 1131 #if defined(CONFIG_DEBUG_FS) 1132 int amdgpu_debugfs_init(struct drm_minor *minor); 1133 void amdgpu_debugfs_cleanup(struct drm_minor *minor); 1134 #endif 1135 1136 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev); 1137 1138 /* 1139 * amdgpu smumgr functions 1140 */ 1141 struct amdgpu_smumgr_funcs { 1142 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 1143 int (*request_smu_load_fw)(struct amdgpu_device *adev); 1144 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 1145 }; 1146 1147 /* 1148 * amdgpu smumgr 1149 */ 1150 struct amdgpu_smumgr { 1151 struct amdgpu_bo *toc_buf; 1152 struct amdgpu_bo *smu_buf; 1153 /* asic priv smu data */ 1154 void *priv; 1155 spinlock_t smu_lock; 1156 /* smumgr functions */ 1157 const struct amdgpu_smumgr_funcs *smumgr_funcs; 1158 /* ucode loading complete flag */ 1159 uint32_t fw_flags; 1160 }; 1161 1162 /* 1163 * ASIC specific register table accessible by UMD 1164 */ 1165 struct amdgpu_allowed_register_entry { 1166 uint32_t reg_offset; 1167 bool untouched; 1168 bool grbm_indexed; 1169 }; 1170 1171 /* 1172 * ASIC specific functions. 1173 */ 1174 struct amdgpu_asic_funcs { 1175 bool (*read_disabled_bios)(struct amdgpu_device *adev); 1176 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 1177 u8 *bios, u32 length_bytes); 1178 void (*detect_hw_virtualization) (struct amdgpu_device *adev); 1179 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 1180 u32 sh_num, u32 reg_offset, u32 *value); 1181 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 1182 int (*reset)(struct amdgpu_device *adev); 1183 /* get the reference clock */ 1184 u32 (*get_xclk)(struct amdgpu_device *adev); 1185 /* MM block clocks */ 1186 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 1187 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 1188 /* static power management */ 1189 int (*get_pcie_lanes)(struct amdgpu_device *adev); 1190 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 1191 }; 1192 1193 /* 1194 * IOCTL. 1195 */ 1196 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 1197 struct drm_file *filp); 1198 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 1199 struct drm_file *filp); 1200 1201 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 1202 struct drm_file *filp); 1203 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 1204 struct drm_file *filp); 1205 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 1206 struct drm_file *filp); 1207 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1208 struct drm_file *filp); 1209 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 1210 struct drm_file *filp); 1211 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 1212 struct drm_file *filp); 1213 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1214 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1215 1216 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 1217 struct drm_file *filp); 1218 1219 /* VRAM scratch page for HDP bug, default vram page */ 1220 struct amdgpu_vram_scratch { 1221 struct amdgpu_bo *robj; 1222 volatile uint32_t *ptr; 1223 u64 gpu_addr; 1224 }; 1225 1226 /* 1227 * ACPI 1228 */ 1229 struct amdgpu_atif_notification_cfg { 1230 bool enabled; 1231 int command_code; 1232 }; 1233 1234 struct amdgpu_atif_notifications { 1235 bool display_switch; 1236 bool expansion_mode_change; 1237 bool thermal_state; 1238 bool forced_power_state; 1239 bool system_power_state; 1240 bool display_conf_change; 1241 bool px_gfx_switch; 1242 bool brightness_change; 1243 bool dgpu_display_event; 1244 }; 1245 1246 struct amdgpu_atif_functions { 1247 bool system_params; 1248 bool sbios_requests; 1249 bool select_active_disp; 1250 bool lid_state; 1251 bool get_tv_standard; 1252 bool set_tv_standard; 1253 bool get_panel_expansion_mode; 1254 bool set_panel_expansion_mode; 1255 bool temperature_change; 1256 bool graphics_device_types; 1257 }; 1258 1259 struct amdgpu_atif { 1260 struct amdgpu_atif_notifications notifications; 1261 struct amdgpu_atif_functions functions; 1262 struct amdgpu_atif_notification_cfg notification_cfg; 1263 struct amdgpu_encoder *encoder_for_bl; 1264 }; 1265 1266 struct amdgpu_atcs_functions { 1267 bool get_ext_state; 1268 bool pcie_perf_req; 1269 bool pcie_dev_rdy; 1270 bool pcie_bus_width; 1271 }; 1272 1273 struct amdgpu_atcs { 1274 struct amdgpu_atcs_functions functions; 1275 }; 1276 1277 /* 1278 * CGS 1279 */ 1280 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1281 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 1282 1283 /* 1284 * Core structure, functions and helpers. 1285 */ 1286 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 1287 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1288 1289 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1290 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 1291 1292 struct amdgpu_device { 1293 struct device *dev; 1294 struct drm_device *ddev; 1295 struct pci_dev *pdev; 1296 1297 #ifdef CONFIG_DRM_AMD_ACP 1298 struct amdgpu_acp acp; 1299 #endif 1300 1301 /* ASIC */ 1302 enum amd_asic_type asic_type; 1303 uint32_t family; 1304 uint32_t rev_id; 1305 uint32_t external_rev_id; 1306 unsigned long flags; 1307 int usec_timeout; 1308 const struct amdgpu_asic_funcs *asic_funcs; 1309 bool shutdown; 1310 bool need_dma32; 1311 bool accel_working; 1312 struct work_struct reset_work; 1313 struct notifier_block acpi_nb; 1314 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 1315 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1316 unsigned debugfs_count; 1317 #if defined(CONFIG_DEBUG_FS) 1318 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1319 #endif 1320 struct amdgpu_atif atif; 1321 struct amdgpu_atcs atcs; 1322 struct mutex srbm_mutex; 1323 /* GRBM index mutex. Protects concurrent access to GRBM index */ 1324 struct mutex grbm_idx_mutex; 1325 struct dev_pm_domain vga_pm_domain; 1326 bool have_disp_power_ref; 1327 1328 /* BIOS */ 1329 uint8_t *bios; 1330 bool is_atom_bios; 1331 struct amdgpu_bo *stollen_vga_memory; 1332 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 1333 1334 /* Register/doorbell mmio */ 1335 resource_size_t rmmio_base; 1336 resource_size_t rmmio_size; 1337 void __iomem *rmmio; 1338 /* protects concurrent MM_INDEX/DATA based register access */ 1339 spinlock_t mmio_idx_lock; 1340 /* protects concurrent SMC based register access */ 1341 spinlock_t smc_idx_lock; 1342 amdgpu_rreg_t smc_rreg; 1343 amdgpu_wreg_t smc_wreg; 1344 /* protects concurrent PCIE register access */ 1345 spinlock_t pcie_idx_lock; 1346 amdgpu_rreg_t pcie_rreg; 1347 amdgpu_wreg_t pcie_wreg; 1348 amdgpu_rreg_t pciep_rreg; 1349 amdgpu_wreg_t pciep_wreg; 1350 /* protects concurrent UVD register access */ 1351 spinlock_t uvd_ctx_idx_lock; 1352 amdgpu_rreg_t uvd_ctx_rreg; 1353 amdgpu_wreg_t uvd_ctx_wreg; 1354 /* protects concurrent DIDT register access */ 1355 spinlock_t didt_idx_lock; 1356 amdgpu_rreg_t didt_rreg; 1357 amdgpu_wreg_t didt_wreg; 1358 /* protects concurrent gc_cac register access */ 1359 spinlock_t gc_cac_idx_lock; 1360 amdgpu_rreg_t gc_cac_rreg; 1361 amdgpu_wreg_t gc_cac_wreg; 1362 /* protects concurrent ENDPOINT (audio) register access */ 1363 spinlock_t audio_endpt_idx_lock; 1364 amdgpu_block_rreg_t audio_endpt_rreg; 1365 amdgpu_block_wreg_t audio_endpt_wreg; 1366 void __iomem *rio_mem; 1367 resource_size_t rio_mem_size; 1368 struct amdgpu_doorbell doorbell; 1369 1370 /* clock/pll info */ 1371 struct amdgpu_clock clock; 1372 1373 /* MC */ 1374 struct amdgpu_mc mc; 1375 struct amdgpu_gart gart; 1376 struct amdgpu_dummy_page dummy_page; 1377 struct amdgpu_vm_manager vm_manager; 1378 1379 /* memory management */ 1380 struct amdgpu_mman mman; 1381 struct amdgpu_vram_scratch vram_scratch; 1382 struct amdgpu_wb wb; 1383 atomic64_t vram_usage; 1384 atomic64_t vram_vis_usage; 1385 atomic64_t gtt_usage; 1386 atomic64_t num_bytes_moved; 1387 atomic64_t num_evictions; 1388 atomic_t gpu_reset_counter; 1389 1390 /* data for buffer migration throttling */ 1391 struct { 1392 spinlock_t lock; 1393 s64 last_update_us; 1394 s64 accum_us; /* accumulated microseconds */ 1395 u32 log2_max_MBps; 1396 } mm_stats; 1397 1398 /* display */ 1399 bool enable_virtual_display; 1400 struct amdgpu_mode_info mode_info; 1401 struct work_struct hotplug_work; 1402 struct amdgpu_irq_src crtc_irq; 1403 struct amdgpu_irq_src pageflip_irq; 1404 struct amdgpu_irq_src hpd_irq; 1405 1406 /* rings */ 1407 u64 fence_context; 1408 unsigned num_rings; 1409 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 1410 bool ib_pool_ready; 1411 struct amdgpu_sa_manager ring_tmp_bo; 1412 1413 /* interrupts */ 1414 struct amdgpu_irq irq; 1415 1416 /* powerplay */ 1417 struct amd_powerplay powerplay; 1418 bool pp_enabled; 1419 bool pp_force_state_enabled; 1420 1421 /* dpm */ 1422 struct amdgpu_pm pm; 1423 u32 cg_flags; 1424 u32 pg_flags; 1425 1426 /* amdgpu smumgr */ 1427 struct amdgpu_smumgr smu; 1428 1429 /* gfx */ 1430 struct amdgpu_gfx gfx; 1431 1432 /* sdma */ 1433 struct amdgpu_sdma sdma; 1434 1435 /* uvd */ 1436 struct amdgpu_uvd uvd; 1437 1438 /* vce */ 1439 struct amdgpu_vce vce; 1440 1441 /* firmwares */ 1442 struct amdgpu_firmware firmware; 1443 1444 /* GDS */ 1445 struct amdgpu_gds gds; 1446 1447 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1448 int num_ip_blocks; 1449 struct mutex mn_lock; 1450 DECLARE_HASHTABLE(mn_hash, 7); 1451 1452 /* tracking pinned memory */ 1453 u64 vram_pin_size; 1454 u64 invisible_pin_size; 1455 u64 gart_pin_size; 1456 1457 /* amdkfd interface */ 1458 struct kfd_dev *kfd; 1459 1460 struct amdgpu_virtualization virtualization; 1461 1462 /* link all shadow bo */ 1463 struct list_head shadow_list; 1464 struct mutex shadow_list_lock; 1465 /* link all gtt */ 1466 spinlock_t gtt_list_lock; 1467 struct list_head gtt_list; 1468 1469 }; 1470 1471 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1472 { 1473 return container_of(bdev, struct amdgpu_device, mman.bdev); 1474 } 1475 1476 bool amdgpu_device_is_px(struct drm_device *dev); 1477 int amdgpu_device_init(struct amdgpu_device *adev, 1478 struct drm_device *ddev, 1479 struct pci_dev *pdev, 1480 uint32_t flags); 1481 void amdgpu_device_fini(struct amdgpu_device *adev); 1482 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1483 1484 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 1485 bool always_indirect); 1486 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 1487 bool always_indirect); 1488 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1489 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1490 1491 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 1492 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 1493 1494 /* 1495 * Registers read & write functions. 1496 */ 1497 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false) 1498 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true) 1499 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false)) 1500 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false) 1501 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true) 1502 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1503 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1504 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1505 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1506 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1507 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1508 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1509 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1510 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1511 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1512 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1513 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1514 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1515 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1516 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1517 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1518 #define WREG32_P(reg, val, mask) \ 1519 do { \ 1520 uint32_t tmp_ = RREG32(reg); \ 1521 tmp_ &= (mask); \ 1522 tmp_ |= ((val) & ~(mask)); \ 1523 WREG32(reg, tmp_); \ 1524 } while (0) 1525 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1526 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1527 #define WREG32_PLL_P(reg, val, mask) \ 1528 do { \ 1529 uint32_t tmp_ = RREG32_PLL(reg); \ 1530 tmp_ &= (mask); \ 1531 tmp_ |= ((val) & ~(mask)); \ 1532 WREG32_PLL(reg, tmp_); \ 1533 } while (0) 1534 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 1535 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1536 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1537 1538 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 1539 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 1540 1541 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1542 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1543 1544 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1545 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1546 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1547 1548 #define REG_GET_FIELD(value, reg, field) \ 1549 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1550 1551 #define WREG32_FIELD(reg, field, val) \ 1552 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1553 1554 /* 1555 * BIOS helpers. 1556 */ 1557 #define RBIOS8(i) (adev->bios[i]) 1558 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1559 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1560 1561 /* 1562 * RING helpers. 1563 */ 1564 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 1565 { 1566 if (ring->count_dw <= 0) 1567 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 1568 ring->ring[ring->wptr++] = v; 1569 ring->wptr &= ring->ptr_mask; 1570 ring->count_dw--; 1571 } 1572 1573 static inline struct amdgpu_sdma_instance * 1574 amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 1575 { 1576 struct amdgpu_device *adev = ring->adev; 1577 int i; 1578 1579 for (i = 0; i < adev->sdma.num_instances; i++) 1580 if (&adev->sdma.instance[i].ring == ring) 1581 break; 1582 1583 if (i < AMDGPU_MAX_SDMA_INSTANCES) 1584 return &adev->sdma.instance[i]; 1585 else 1586 return NULL; 1587 } 1588 1589 /* 1590 * ASICs macro. 1591 */ 1592 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1593 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1594 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1595 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1596 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1597 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1598 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1599 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1600 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1601 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1602 #define amdgpu_asic_detect_hw_virtualization(adev) (adev)->asic_funcs->detect_hw_virtualization((adev)) 1603 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1604 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) 1605 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) 1606 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 1607 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) 1608 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 1609 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 1610 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 1611 #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t)) 1612 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 1613 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 1614 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 1615 #define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c)) 1616 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) 1617 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 1618 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 1619 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 1620 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 1621 #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r)) 1622 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r)) 1623 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d)) 1624 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) 1625 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) 1626 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) 1627 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) 1628 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) 1629 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) 1630 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) 1631 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 1632 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) 1633 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev)) 1634 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 1635 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 1636 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 1637 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) 1638 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) 1639 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) 1640 #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async)) 1641 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) 1642 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) 1643 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) 1644 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s)) 1645 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) 1646 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 1647 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 1648 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 1649 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) 1650 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) 1651 1652 /* Common functions */ 1653 int amdgpu_gpu_reset(struct amdgpu_device *adev); 1654 bool amdgpu_need_backup(struct amdgpu_device *adev); 1655 void amdgpu_pci_config_reset(struct amdgpu_device *adev); 1656 bool amdgpu_card_posted(struct amdgpu_device *adev); 1657 void amdgpu_update_display_priority(struct amdgpu_device *adev); 1658 1659 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); 1660 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 1661 u32 ip_instance, u32 ring, 1662 struct amdgpu_ring **out_ring); 1663 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain); 1664 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 1665 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages); 1666 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 1667 uint32_t flags); 1668 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 1669 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm); 1670 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 1671 unsigned long end); 1672 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, 1673 int *last_invalidated); 1674 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 1675 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 1676 struct ttm_mem_reg *mem); 1677 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); 1678 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); 1679 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); 1680 u64 amdgpu_ttm_get_gtt_mem_size(struct amdgpu_device *adev); 1681 int amdgpu_ttm_global_init(struct amdgpu_device *adev); 1682 int amdgpu_ttm_init(struct amdgpu_device *adev); 1683 void amdgpu_ttm_fini(struct amdgpu_device *adev); 1684 void amdgpu_program_register_sequence(struct amdgpu_device *adev, 1685 const u32 *registers, 1686 const u32 array_size); 1687 1688 bool amdgpu_device_is_px(struct drm_device *dev); 1689 /* atpx handler */ 1690 #if defined(CONFIG_VGA_SWITCHEROO) 1691 void amdgpu_register_atpx_handler(void); 1692 void amdgpu_unregister_atpx_handler(void); 1693 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1694 bool amdgpu_is_atpx_hybrid(void); 1695 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1696 #else 1697 static inline void amdgpu_register_atpx_handler(void) {} 1698 static inline void amdgpu_unregister_atpx_handler(void) {} 1699 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1700 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1701 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1702 #endif 1703 1704 /* 1705 * KMS 1706 */ 1707 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1708 extern const int amdgpu_max_kms_ioctl; 1709 1710 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1711 int amdgpu_driver_unload_kms(struct drm_device *dev); 1712 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1713 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1714 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1715 struct drm_file *file_priv); 1716 void amdgpu_driver_preclose_kms(struct drm_device *dev, 1717 struct drm_file *file_priv); 1718 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); 1719 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); 1720 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 1721 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1722 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1723 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, 1724 int *max_error, 1725 struct timeval *vblank_time, 1726 unsigned flags); 1727 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1728 unsigned long arg); 1729 1730 /* 1731 * functions used by amdgpu_encoder.c 1732 */ 1733 struct amdgpu_afmt_acr { 1734 u32 clock; 1735 1736 int n_32khz; 1737 int cts_32khz; 1738 1739 int n_44_1khz; 1740 int cts_44_1khz; 1741 1742 int n_48khz; 1743 int cts_48khz; 1744 1745 }; 1746 1747 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1748 1749 /* amdgpu_acpi.c */ 1750 #if defined(CONFIG_ACPI) 1751 int amdgpu_acpi_init(struct amdgpu_device *adev); 1752 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1753 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1754 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1755 u8 perf_req, bool advertise); 1756 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1757 #else 1758 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1759 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1760 #endif 1761 1762 struct amdgpu_bo_va_mapping * 1763 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1764 uint64_t addr, struct amdgpu_bo **bo); 1765 int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser); 1766 1767 #include "amdgpu_object.h" 1768 #endif 1769