1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 54 #include <drm/ttm/ttm_bo.h> 55 #include <drm/ttm/ttm_placement.h> 56 57 #include <drm/amdgpu_drm.h> 58 #include <drm/drm_gem.h> 59 #include <drm/drm_ioctl.h> 60 61 #include <kgd_kfd_interface.h> 62 #include "dm_pp_interface.h" 63 #include "kgd_pp_interface.h" 64 65 #include "amd_shared.h" 66 #include "amdgpu_mode.h" 67 #include "amdgpu_ih.h" 68 #include "amdgpu_irq.h" 69 #include "amdgpu_ucode.h" 70 #include "amdgpu_ttm.h" 71 #include "amdgpu_psp.h" 72 #include "amdgpu_gds.h" 73 #include "amdgpu_sync.h" 74 #include "amdgpu_ring.h" 75 #include "amdgpu_vm.h" 76 #include "amdgpu_dpm.h" 77 #include "amdgpu_acp.h" 78 #include "amdgpu_uvd.h" 79 #include "amdgpu_vce.h" 80 #include "amdgpu_vcn.h" 81 #include "amdgpu_jpeg.h" 82 #include "amdgpu_vpe.h" 83 #include "amdgpu_umsch_mm.h" 84 #include "amdgpu_gmc.h" 85 #include "amdgpu_gfx.h" 86 #include "amdgpu_sdma.h" 87 #include "amdgpu_lsdma.h" 88 #include "amdgpu_nbio.h" 89 #include "amdgpu_hdp.h" 90 #include "amdgpu_dm.h" 91 #include "amdgpu_virt.h" 92 #include "amdgpu_csa.h" 93 #include "amdgpu_mes_ctx.h" 94 #include "amdgpu_gart.h" 95 #include "amdgpu_debugfs.h" 96 #include "amdgpu_job.h" 97 #include "amdgpu_bo_list.h" 98 #include "amdgpu_gem.h" 99 #include "amdgpu_doorbell.h" 100 #include "amdgpu_amdkfd.h" 101 #include "amdgpu_discovery.h" 102 #include "amdgpu_mes.h" 103 #include "amdgpu_umc.h" 104 #include "amdgpu_mmhub.h" 105 #include "amdgpu_gfxhub.h" 106 #include "amdgpu_df.h" 107 #include "amdgpu_smuio.h" 108 #include "amdgpu_fdinfo.h" 109 #include "amdgpu_mca.h" 110 #include "amdgpu_aca.h" 111 #include "amdgpu_ras.h" 112 #include "amdgpu_xcp.h" 113 #include "amdgpu_seq64.h" 114 #include "amdgpu_reg_state.h" 115 116 #define MAX_GPU_INSTANCE 64 117 118 struct amdgpu_gpu_instance { 119 struct amdgpu_device *adev; 120 int mgpu_fan_enabled; 121 }; 122 123 struct amdgpu_mgpu_info { 124 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 125 struct mutex mutex; 126 uint32_t num_gpu; 127 uint32_t num_dgpu; 128 uint32_t num_apu; 129 130 /* delayed reset_func for XGMI configuration if necessary */ 131 struct delayed_work delayed_reset_work; 132 bool pending_reset; 133 }; 134 135 enum amdgpu_ss { 136 AMDGPU_SS_DRV_LOAD, 137 AMDGPU_SS_DEV_D0, 138 AMDGPU_SS_DEV_D3, 139 AMDGPU_SS_DRV_UNLOAD 140 }; 141 142 struct amdgpu_hwip_reg_entry { 143 u32 hwip; 144 u32 inst; 145 u32 seg; 146 u32 reg_offset; 147 const char *reg_name; 148 }; 149 150 struct amdgpu_watchdog_timer { 151 bool timeout_fatal_disable; 152 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 153 }; 154 155 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 156 157 /* 158 * Modules parameters. 159 */ 160 extern int amdgpu_modeset; 161 extern unsigned int amdgpu_vram_limit; 162 extern int amdgpu_vis_vram_limit; 163 extern int amdgpu_gart_size; 164 extern int amdgpu_gtt_size; 165 extern int amdgpu_moverate; 166 extern int amdgpu_audio; 167 extern int amdgpu_disp_priority; 168 extern int amdgpu_hw_i2c; 169 extern int amdgpu_pcie_gen2; 170 extern int amdgpu_msi; 171 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 172 extern int amdgpu_dpm; 173 extern int amdgpu_fw_load_type; 174 extern int amdgpu_aspm; 175 extern int amdgpu_runtime_pm; 176 extern uint amdgpu_ip_block_mask; 177 extern int amdgpu_bapm; 178 extern int amdgpu_deep_color; 179 extern int amdgpu_vm_size; 180 extern int amdgpu_vm_block_size; 181 extern int amdgpu_vm_fragment_size; 182 extern int amdgpu_vm_fault_stop; 183 extern int amdgpu_vm_debug; 184 extern int amdgpu_vm_update_mode; 185 extern int amdgpu_exp_hw_support; 186 extern int amdgpu_dc; 187 extern int amdgpu_sched_jobs; 188 extern int amdgpu_sched_hw_submission; 189 extern uint amdgpu_pcie_gen_cap; 190 extern uint amdgpu_pcie_lane_cap; 191 extern u64 amdgpu_cg_mask; 192 extern uint amdgpu_pg_mask; 193 extern uint amdgpu_sdma_phase_quantum; 194 extern char *amdgpu_disable_cu; 195 extern char *amdgpu_virtual_display; 196 extern uint amdgpu_pp_feature_mask; 197 extern uint amdgpu_force_long_training; 198 extern int amdgpu_lbpw; 199 extern int amdgpu_compute_multipipe; 200 extern int amdgpu_gpu_recovery; 201 extern int amdgpu_emu_mode; 202 extern uint amdgpu_smu_memory_pool_size; 203 extern int amdgpu_smu_pptable_id; 204 extern uint amdgpu_dc_feature_mask; 205 extern uint amdgpu_freesync_vid_mode; 206 extern uint amdgpu_dc_debug_mask; 207 extern uint amdgpu_dc_visual_confirm; 208 extern int amdgpu_dm_abm_level; 209 extern int amdgpu_backlight; 210 extern int amdgpu_damage_clips; 211 extern struct amdgpu_mgpu_info mgpu_info; 212 extern int amdgpu_ras_enable; 213 extern uint amdgpu_ras_mask; 214 extern int amdgpu_bad_page_threshold; 215 extern bool amdgpu_ignore_bad_page_threshold; 216 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 217 extern int amdgpu_async_gfx_ring; 218 extern int amdgpu_mcbp; 219 extern int amdgpu_discovery; 220 extern int amdgpu_mes; 221 extern int amdgpu_mes_log_enable; 222 extern int amdgpu_mes_kiq; 223 extern int amdgpu_noretry; 224 extern int amdgpu_force_asic_type; 225 extern int amdgpu_smartshift_bias; 226 extern int amdgpu_use_xgmi_p2p; 227 extern int amdgpu_mtype_local; 228 extern bool enforce_isolation; 229 #ifdef CONFIG_HSA_AMD 230 extern int sched_policy; 231 extern bool debug_evictions; 232 extern bool no_system_mem_limit; 233 extern int halt_if_hws_hang; 234 #else 235 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 236 static const bool __maybe_unused debug_evictions; /* = false */ 237 static const bool __maybe_unused no_system_mem_limit; 238 static const int __maybe_unused halt_if_hws_hang; 239 #endif 240 #ifdef CONFIG_HSA_AMD_P2P 241 extern bool pcie_p2p; 242 #endif 243 244 extern int amdgpu_tmz; 245 extern int amdgpu_reset_method; 246 247 #ifdef CONFIG_DRM_AMDGPU_SI 248 extern int amdgpu_si_support; 249 #endif 250 #ifdef CONFIG_DRM_AMDGPU_CIK 251 extern int amdgpu_cik_support; 252 #endif 253 extern int amdgpu_num_kcq; 254 255 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 256 extern int amdgpu_vcnfw_log; 257 extern int amdgpu_sg_display; 258 extern int amdgpu_umsch_mm; 259 extern int amdgpu_seamless; 260 261 extern int amdgpu_user_partt_mode; 262 extern int amdgpu_agp; 263 264 extern int amdgpu_wbrf; 265 266 #define AMDGPU_VM_MAX_NUM_CTX 4096 267 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 268 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 269 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 270 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 271 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 272 #define AMDGPUFB_CONN_LIMIT 4 273 #define AMDGPU_BIOS_NUM_SCRATCH 16 274 275 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 276 277 /* hard reset data */ 278 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 279 280 /* reset flags */ 281 #define AMDGPU_RESET_GFX (1 << 0) 282 #define AMDGPU_RESET_COMPUTE (1 << 1) 283 #define AMDGPU_RESET_DMA (1 << 2) 284 #define AMDGPU_RESET_CP (1 << 3) 285 #define AMDGPU_RESET_GRBM (1 << 4) 286 #define AMDGPU_RESET_DMA1 (1 << 5) 287 #define AMDGPU_RESET_RLC (1 << 6) 288 #define AMDGPU_RESET_SEM (1 << 7) 289 #define AMDGPU_RESET_IH (1 << 8) 290 #define AMDGPU_RESET_VMC (1 << 9) 291 #define AMDGPU_RESET_MC (1 << 10) 292 #define AMDGPU_RESET_DISPLAY (1 << 11) 293 #define AMDGPU_RESET_UVD (1 << 12) 294 #define AMDGPU_RESET_VCE (1 << 13) 295 #define AMDGPU_RESET_VCE1 (1 << 14) 296 297 /* max cursor sizes (in pixels) */ 298 #define CIK_CURSOR_WIDTH 128 299 #define CIK_CURSOR_HEIGHT 128 300 301 /* smart shift bias level limits */ 302 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 303 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 304 305 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */ 306 #define AMDGPU_SWCTF_EXTRA_DELAY 50 307 308 struct amdgpu_xcp_mgr; 309 struct amdgpu_device; 310 struct amdgpu_irq_src; 311 struct amdgpu_fpriv; 312 struct amdgpu_bo_va_mapping; 313 struct kfd_vm_fault_info; 314 struct amdgpu_hive_info; 315 struct amdgpu_reset_context; 316 struct amdgpu_reset_control; 317 318 enum amdgpu_cp_irq { 319 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 320 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 321 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 322 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 323 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 324 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 325 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 326 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 327 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 328 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 329 330 AMDGPU_CP_IRQ_LAST 331 }; 332 333 enum amdgpu_thermal_irq { 334 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 335 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 336 337 AMDGPU_THERMAL_IRQ_LAST 338 }; 339 340 enum amdgpu_kiq_irq { 341 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 342 AMDGPU_CP_KIQ_IRQ_LAST 343 }; 344 #define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */ 345 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 346 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 347 #define MAX_KIQ_REG_TRY 1000 348 349 int amdgpu_device_ip_set_clockgating_state(void *dev, 350 enum amd_ip_block_type block_type, 351 enum amd_clockgating_state state); 352 int amdgpu_device_ip_set_powergating_state(void *dev, 353 enum amd_ip_block_type block_type, 354 enum amd_powergating_state state); 355 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 356 u64 *flags); 357 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 358 enum amd_ip_block_type block_type); 359 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 360 enum amd_ip_block_type block_type); 361 362 #define AMDGPU_MAX_IP_NUM 16 363 364 struct amdgpu_ip_block_status { 365 bool valid; 366 bool sw; 367 bool hw; 368 bool late_initialized; 369 bool hang; 370 }; 371 372 struct amdgpu_ip_block_version { 373 const enum amd_ip_block_type type; 374 const u32 major; 375 const u32 minor; 376 const u32 rev; 377 const struct amd_ip_funcs *funcs; 378 }; 379 380 struct amdgpu_ip_block { 381 struct amdgpu_ip_block_status status; 382 const struct amdgpu_ip_block_version *version; 383 }; 384 385 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 386 enum amd_ip_block_type type, 387 u32 major, u32 minor); 388 389 struct amdgpu_ip_block * 390 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 391 enum amd_ip_block_type type); 392 393 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 394 const struct amdgpu_ip_block_version *ip_block_version); 395 396 /* 397 * BIOS. 398 */ 399 bool amdgpu_get_bios(struct amdgpu_device *adev); 400 bool amdgpu_read_bios(struct amdgpu_device *adev); 401 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 402 u8 *bios, u32 length_bytes); 403 /* 404 * Clocks 405 */ 406 407 #define AMDGPU_MAX_PPLL 3 408 409 struct amdgpu_clock { 410 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 411 struct amdgpu_pll spll; 412 struct amdgpu_pll mpll; 413 /* 10 Khz units */ 414 uint32_t default_mclk; 415 uint32_t default_sclk; 416 uint32_t default_dispclk; 417 uint32_t current_dispclk; 418 uint32_t dp_extclk; 419 uint32_t max_pixel_clock; 420 }; 421 422 /* sub-allocation manager, it has to be protected by another lock. 423 * By conception this is an helper for other part of the driver 424 * like the indirect buffer or semaphore, which both have their 425 * locking. 426 * 427 * Principe is simple, we keep a list of sub allocation in offset 428 * order (first entry has offset == 0, last entry has the highest 429 * offset). 430 * 431 * When allocating new object we first check if there is room at 432 * the end total_size - (last_object_offset + last_object_size) >= 433 * alloc_size. If so we allocate new object there. 434 * 435 * When there is not enough room at the end, we start waiting for 436 * each sub object until we reach object_offset+object_size >= 437 * alloc_size, this object then become the sub object we return. 438 * 439 * Alignment can't be bigger than page size. 440 * 441 * Hole are not considered for allocation to keep things simple. 442 * Assumption is that there won't be hole (all object on same 443 * alignment). 444 */ 445 446 struct amdgpu_sa_manager { 447 struct drm_suballoc_manager base; 448 struct amdgpu_bo *bo; 449 uint64_t gpu_addr; 450 void *cpu_ptr; 451 }; 452 453 int amdgpu_fence_slab_init(void); 454 void amdgpu_fence_slab_fini(void); 455 456 /* 457 * IRQS. 458 */ 459 460 struct amdgpu_flip_work { 461 struct delayed_work flip_work; 462 struct work_struct unpin_work; 463 struct amdgpu_device *adev; 464 int crtc_id; 465 u32 target_vblank; 466 uint64_t base; 467 struct drm_pending_vblank_event *event; 468 struct amdgpu_bo *old_abo; 469 unsigned shared_count; 470 struct dma_fence **shared; 471 struct dma_fence_cb cb; 472 bool async; 473 }; 474 475 476 /* 477 * file private structure 478 */ 479 480 struct amdgpu_fpriv { 481 struct amdgpu_vm vm; 482 struct amdgpu_bo_va *prt_va; 483 struct amdgpu_bo_va *csa_va; 484 struct amdgpu_bo_va *seq64_va; 485 struct mutex bo_list_lock; 486 struct idr bo_list_handles; 487 struct amdgpu_ctx_mgr ctx_mgr; 488 /** GPU partition selection */ 489 uint32_t xcp_id; 490 }; 491 492 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 493 494 /* 495 * Writeback 496 */ 497 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 498 499 struct amdgpu_wb { 500 struct amdgpu_bo *wb_obj; 501 volatile uint32_t *wb; 502 uint64_t gpu_addr; 503 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 504 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 505 spinlock_t lock; 506 }; 507 508 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 509 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 510 511 /* 512 * Benchmarking 513 */ 514 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 515 516 /* 517 * ASIC specific register table accessible by UMD 518 */ 519 struct amdgpu_allowed_register_entry { 520 uint32_t reg_offset; 521 bool grbm_indexed; 522 }; 523 524 /** 525 * enum amd_reset_method - Methods for resetting AMD GPU devices 526 * 527 * @AMD_RESET_METHOD_NONE: The device will not be reset. 528 * @AMD_RESET_LEGACY: Method reserved for SI, CIK and VI ASICs. 529 * @AMD_RESET_MODE0: Reset the entire ASIC. Not currently available for the 530 * any device. 531 * @AMD_RESET_MODE1: Resets all IP blocks on the ASIC (SDMA, GFX, VCN, etc.) 532 * individually. Suitable only for some discrete GPU, not 533 * available for all ASICs. 534 * @AMD_RESET_MODE2: Resets a lesser level of IPs compared to MODE1. Which IPs 535 * are reset depends on the ASIC. Notably doesn't reset IPs 536 * shared with the CPU on APUs or the memory controllers (so 537 * VRAM is not lost). Not available on all ASICs. 538 * @AMD_RESET_BACO: BACO (Bus Alive, Chip Off) method powers off and on the card 539 * but without powering off the PCI bus. Suitable only for 540 * discrete GPUs. 541 * @AMD_RESET_PCI: Does a full bus reset using core Linux subsystem PCI reset 542 * and does a secondary bus reset or FLR, depending on what the 543 * underlying hardware supports. 544 * 545 * Methods available for AMD GPU driver for resetting the device. Not all 546 * methods are suitable for every device. User can override the method using 547 * module parameter `reset_method`. 548 */ 549 enum amd_reset_method { 550 AMD_RESET_METHOD_NONE = -1, 551 AMD_RESET_METHOD_LEGACY = 0, 552 AMD_RESET_METHOD_MODE0, 553 AMD_RESET_METHOD_MODE1, 554 AMD_RESET_METHOD_MODE2, 555 AMD_RESET_METHOD_BACO, 556 AMD_RESET_METHOD_PCI, 557 }; 558 559 struct amdgpu_video_codec_info { 560 u32 codec_type; 561 u32 max_width; 562 u32 max_height; 563 u32 max_pixels_per_frame; 564 u32 max_level; 565 }; 566 567 #define codec_info_build(type, width, height, level) \ 568 .codec_type = type,\ 569 .max_width = width,\ 570 .max_height = height,\ 571 .max_pixels_per_frame = height * width,\ 572 .max_level = level, 573 574 struct amdgpu_video_codecs { 575 const u32 codec_count; 576 const struct amdgpu_video_codec_info *codec_array; 577 }; 578 579 /* 580 * ASIC specific functions. 581 */ 582 struct amdgpu_asic_funcs { 583 bool (*read_disabled_bios)(struct amdgpu_device *adev); 584 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 585 u8 *bios, u32 length_bytes); 586 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 587 u32 sh_num, u32 reg_offset, u32 *value); 588 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 589 int (*reset)(struct amdgpu_device *adev); 590 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 591 /* get the reference clock */ 592 u32 (*get_xclk)(struct amdgpu_device *adev); 593 /* MM block clocks */ 594 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 595 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 596 /* static power management */ 597 int (*get_pcie_lanes)(struct amdgpu_device *adev); 598 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 599 /* get config memsize register */ 600 u32 (*get_config_memsize)(struct amdgpu_device *adev); 601 /* flush hdp write queue */ 602 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 603 /* invalidate hdp read cache */ 604 void (*invalidate_hdp)(struct amdgpu_device *adev, 605 struct amdgpu_ring *ring); 606 /* check if the asic needs a full reset of if soft reset will work */ 607 bool (*need_full_reset)(struct amdgpu_device *adev); 608 /* initialize doorbell layout for specific asic*/ 609 void (*init_doorbell_index)(struct amdgpu_device *adev); 610 /* PCIe bandwidth usage */ 611 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 612 uint64_t *count1); 613 /* do we need to reset the asic at init time (e.g., kexec) */ 614 bool (*need_reset_on_init)(struct amdgpu_device *adev); 615 /* PCIe replay counter */ 616 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 617 /* device supports BACO */ 618 int (*supports_baco)(struct amdgpu_device *adev); 619 /* pre asic_init quirks */ 620 void (*pre_asic_init)(struct amdgpu_device *adev); 621 /* enter/exit umd stable pstate */ 622 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 623 /* query video codecs */ 624 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 625 const struct amdgpu_video_codecs **codecs); 626 /* encode "> 32bits" smn addressing */ 627 u64 (*encode_ext_smn_addressing)(int ext_id); 628 629 ssize_t (*get_reg_state)(struct amdgpu_device *adev, 630 enum amdgpu_reg_state reg_state, void *buf, 631 size_t max_size); 632 }; 633 634 /* 635 * IOCTL. 636 */ 637 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 638 struct drm_file *filp); 639 640 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 641 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 642 struct drm_file *filp); 643 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 644 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 645 struct drm_file *filp); 646 647 /* VRAM scratch page for HDP bug, default vram page */ 648 struct amdgpu_mem_scratch { 649 struct amdgpu_bo *robj; 650 volatile uint32_t *ptr; 651 u64 gpu_addr; 652 }; 653 654 /* 655 * CGS 656 */ 657 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 658 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 659 660 /* 661 * Core structure, functions and helpers. 662 */ 663 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 664 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 665 666 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t); 667 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t); 668 669 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 670 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 671 672 typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device*, uint64_t); 673 typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device*, uint64_t, uint64_t); 674 675 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 676 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 677 678 struct amdgpu_mmio_remap { 679 u32 reg_offset; 680 resource_size_t bus_addr; 681 }; 682 683 /* Define the HW IP blocks will be used in driver , add more if necessary */ 684 enum amd_hw_ip_block_type { 685 GC_HWIP = 1, 686 HDP_HWIP, 687 SDMA0_HWIP, 688 SDMA1_HWIP, 689 SDMA2_HWIP, 690 SDMA3_HWIP, 691 SDMA4_HWIP, 692 SDMA5_HWIP, 693 SDMA6_HWIP, 694 SDMA7_HWIP, 695 LSDMA_HWIP, 696 MMHUB_HWIP, 697 ATHUB_HWIP, 698 NBIO_HWIP, 699 MP0_HWIP, 700 MP1_HWIP, 701 UVD_HWIP, 702 VCN_HWIP = UVD_HWIP, 703 JPEG_HWIP = VCN_HWIP, 704 VCN1_HWIP, 705 VCE_HWIP, 706 VPE_HWIP, 707 DF_HWIP, 708 DCE_HWIP, 709 OSSSYS_HWIP, 710 SMUIO_HWIP, 711 PWR_HWIP, 712 NBIF_HWIP, 713 THM_HWIP, 714 CLK_HWIP, 715 UMC_HWIP, 716 RSMU_HWIP, 717 XGMI_HWIP, 718 DCI_HWIP, 719 PCIE_HWIP, 720 MAX_HWIP 721 }; 722 723 #define HWIP_MAX_INSTANCE 44 724 725 #define HW_ID_MAX 300 726 #define IP_VERSION_FULL(mj, mn, rv, var, srev) \ 727 (((mj) << 24) | ((mn) << 16) | ((rv) << 8) | ((var) << 4) | (srev)) 728 #define IP_VERSION(mj, mn, rv) IP_VERSION_FULL(mj, mn, rv, 0, 0) 729 #define IP_VERSION_MAJ(ver) ((ver) >> 24) 730 #define IP_VERSION_MIN(ver) (((ver) >> 16) & 0xFF) 731 #define IP_VERSION_REV(ver) (((ver) >> 8) & 0xFF) 732 #define IP_VERSION_VARIANT(ver) (((ver) >> 4) & 0xF) 733 #define IP_VERSION_SUBREV(ver) ((ver) & 0xF) 734 #define IP_VERSION_MAJ_MIN_REV(ver) ((ver) >> 8) 735 736 struct amdgpu_ip_map_info { 737 /* Map of logical to actual dev instances/mask */ 738 uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE]; 739 int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev, 740 enum amd_hw_ip_block_type block, 741 int8_t inst); 742 uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev, 743 enum amd_hw_ip_block_type block, 744 uint32_t mask); 745 }; 746 747 struct amd_powerplay { 748 void *pp_handle; 749 const struct amd_pm_funcs *pp_funcs; 750 }; 751 752 struct ip_discovery_top; 753 754 /* polaris10 kickers */ 755 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 756 ((rid == 0xE3) || \ 757 (rid == 0xE4) || \ 758 (rid == 0xE5) || \ 759 (rid == 0xE7) || \ 760 (rid == 0xEF))) || \ 761 ((did == 0x6FDF) && \ 762 ((rid == 0xE7) || \ 763 (rid == 0xEF) || \ 764 (rid == 0xFF)))) 765 766 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 767 ((rid == 0xE1) || \ 768 (rid == 0xF7))) 769 770 /* polaris11 kickers */ 771 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 772 ((rid == 0xE0) || \ 773 (rid == 0xE5))) || \ 774 ((did == 0x67FF) && \ 775 ((rid == 0xCF) || \ 776 (rid == 0xEF) || \ 777 (rid == 0xFF)))) 778 779 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 780 ((rid == 0xE2))) 781 782 /* polaris12 kickers */ 783 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 784 ((rid == 0xC0) || \ 785 (rid == 0xC1) || \ 786 (rid == 0xC3) || \ 787 (rid == 0xC7))) || \ 788 ((did == 0x6981) && \ 789 ((rid == 0x00) || \ 790 (rid == 0x01) || \ 791 (rid == 0x10)))) 792 793 struct amdgpu_mqd_prop { 794 uint64_t mqd_gpu_addr; 795 uint64_t hqd_base_gpu_addr; 796 uint64_t rptr_gpu_addr; 797 uint64_t wptr_gpu_addr; 798 uint32_t queue_size; 799 bool use_doorbell; 800 uint32_t doorbell_index; 801 uint64_t eop_gpu_addr; 802 uint32_t hqd_pipe_priority; 803 uint32_t hqd_queue_priority; 804 bool allow_tunneling; 805 bool hqd_active; 806 }; 807 808 struct amdgpu_mqd { 809 unsigned mqd_size; 810 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 811 struct amdgpu_mqd_prop *p); 812 }; 813 814 #define AMDGPU_RESET_MAGIC_NUM 64 815 #define AMDGPU_MAX_DF_PERFMONS 4 816 struct amdgpu_reset_domain; 817 struct amdgpu_fru_info; 818 819 struct amdgpu_reset_info { 820 /* reset dump register */ 821 u32 *reset_dump_reg_list; 822 u32 *reset_dump_reg_value; 823 int num_regs; 824 825 #ifdef CONFIG_DEV_COREDUMP 826 struct amdgpu_coredump_info *coredump_info; 827 #endif 828 }; 829 830 /* 831 * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise. 832 */ 833 #define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size) 834 835 struct amdgpu_device { 836 struct device *dev; 837 struct pci_dev *pdev; 838 struct drm_device ddev; 839 840 #ifdef CONFIG_DRM_AMD_ACP 841 struct amdgpu_acp acp; 842 #endif 843 struct amdgpu_hive_info *hive; 844 struct amdgpu_xcp_mgr *xcp_mgr; 845 /* ASIC */ 846 enum amd_asic_type asic_type; 847 uint32_t family; 848 uint32_t rev_id; 849 uint32_t external_rev_id; 850 unsigned long flags; 851 unsigned long apu_flags; 852 int usec_timeout; 853 const struct amdgpu_asic_funcs *asic_funcs; 854 bool shutdown; 855 bool need_swiotlb; 856 bool accel_working; 857 struct notifier_block acpi_nb; 858 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 859 struct debugfs_blob_wrapper debugfs_vbios_blob; 860 struct debugfs_blob_wrapper debugfs_discovery_blob; 861 struct mutex srbm_mutex; 862 /* GRBM index mutex. Protects concurrent access to GRBM index */ 863 struct mutex grbm_idx_mutex; 864 struct dev_pm_domain vga_pm_domain; 865 bool have_disp_power_ref; 866 bool have_atomics_support; 867 868 /* BIOS */ 869 bool is_atom_fw; 870 uint8_t *bios; 871 uint32_t bios_size; 872 uint32_t bios_scratch_reg_offset; 873 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 874 875 /* Register/doorbell mmio */ 876 resource_size_t rmmio_base; 877 resource_size_t rmmio_size; 878 void __iomem *rmmio; 879 /* protects concurrent MM_INDEX/DATA based register access */ 880 spinlock_t mmio_idx_lock; 881 struct amdgpu_mmio_remap rmmio_remap; 882 /* protects concurrent SMC based register access */ 883 spinlock_t smc_idx_lock; 884 amdgpu_rreg_t smc_rreg; 885 amdgpu_wreg_t smc_wreg; 886 /* protects concurrent PCIE register access */ 887 spinlock_t pcie_idx_lock; 888 amdgpu_rreg_t pcie_rreg; 889 amdgpu_wreg_t pcie_wreg; 890 amdgpu_rreg_t pciep_rreg; 891 amdgpu_wreg_t pciep_wreg; 892 amdgpu_rreg_ext_t pcie_rreg_ext; 893 amdgpu_wreg_ext_t pcie_wreg_ext; 894 amdgpu_rreg64_t pcie_rreg64; 895 amdgpu_wreg64_t pcie_wreg64; 896 amdgpu_rreg64_ext_t pcie_rreg64_ext; 897 amdgpu_wreg64_ext_t pcie_wreg64_ext; 898 /* protects concurrent UVD register access */ 899 spinlock_t uvd_ctx_idx_lock; 900 amdgpu_rreg_t uvd_ctx_rreg; 901 amdgpu_wreg_t uvd_ctx_wreg; 902 /* protects concurrent DIDT register access */ 903 spinlock_t didt_idx_lock; 904 amdgpu_rreg_t didt_rreg; 905 amdgpu_wreg_t didt_wreg; 906 /* protects concurrent gc_cac register access */ 907 spinlock_t gc_cac_idx_lock; 908 amdgpu_rreg_t gc_cac_rreg; 909 amdgpu_wreg_t gc_cac_wreg; 910 /* protects concurrent se_cac register access */ 911 spinlock_t se_cac_idx_lock; 912 amdgpu_rreg_t se_cac_rreg; 913 amdgpu_wreg_t se_cac_wreg; 914 /* protects concurrent ENDPOINT (audio) register access */ 915 spinlock_t audio_endpt_idx_lock; 916 amdgpu_block_rreg_t audio_endpt_rreg; 917 amdgpu_block_wreg_t audio_endpt_wreg; 918 struct amdgpu_doorbell doorbell; 919 920 /* clock/pll info */ 921 struct amdgpu_clock clock; 922 923 /* MC */ 924 struct amdgpu_gmc gmc; 925 struct amdgpu_gart gart; 926 dma_addr_t dummy_page_addr; 927 struct amdgpu_vm_manager vm_manager; 928 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 929 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS); 930 931 /* memory management */ 932 struct amdgpu_mman mman; 933 struct amdgpu_mem_scratch mem_scratch; 934 struct amdgpu_wb wb; 935 atomic64_t num_bytes_moved; 936 atomic64_t num_evictions; 937 atomic64_t num_vram_cpu_page_faults; 938 atomic_t gpu_reset_counter; 939 atomic_t vram_lost_counter; 940 941 /* data for buffer migration throttling */ 942 struct { 943 spinlock_t lock; 944 s64 last_update_us; 945 s64 accum_us; /* accumulated microseconds */ 946 s64 accum_us_vis; /* for visible VRAM */ 947 u32 log2_max_MBps; 948 } mm_stats; 949 950 /* display */ 951 bool enable_virtual_display; 952 struct amdgpu_vkms_output *amdgpu_vkms_output; 953 struct amdgpu_mode_info mode_info; 954 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 955 struct delayed_work hotplug_work; 956 struct amdgpu_irq_src crtc_irq; 957 struct amdgpu_irq_src vline0_irq; 958 struct amdgpu_irq_src vupdate_irq; 959 struct amdgpu_irq_src pageflip_irq; 960 struct amdgpu_irq_src hpd_irq; 961 struct amdgpu_irq_src dmub_trace_irq; 962 struct amdgpu_irq_src dmub_outbox_irq; 963 964 /* rings */ 965 u64 fence_context; 966 unsigned num_rings; 967 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 968 struct dma_fence __rcu *gang_submit; 969 bool ib_pool_ready; 970 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 971 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 972 973 /* interrupts */ 974 struct amdgpu_irq irq; 975 976 /* powerplay */ 977 struct amd_powerplay powerplay; 978 struct amdgpu_pm pm; 979 u64 cg_flags; 980 u32 pg_flags; 981 982 /* nbio */ 983 struct amdgpu_nbio nbio; 984 985 /* hdp */ 986 struct amdgpu_hdp hdp; 987 988 /* smuio */ 989 struct amdgpu_smuio smuio; 990 991 /* mmhub */ 992 struct amdgpu_mmhub mmhub; 993 994 /* gfxhub */ 995 struct amdgpu_gfxhub gfxhub; 996 997 /* gfx */ 998 struct amdgpu_gfx gfx; 999 1000 /* sdma */ 1001 struct amdgpu_sdma sdma; 1002 1003 /* lsdma */ 1004 struct amdgpu_lsdma lsdma; 1005 1006 /* uvd */ 1007 struct amdgpu_uvd uvd; 1008 1009 /* vce */ 1010 struct amdgpu_vce vce; 1011 1012 /* vcn */ 1013 struct amdgpu_vcn vcn; 1014 1015 /* jpeg */ 1016 struct amdgpu_jpeg jpeg; 1017 1018 /* vpe */ 1019 struct amdgpu_vpe vpe; 1020 1021 /* umsch */ 1022 struct amdgpu_umsch_mm umsch_mm; 1023 bool enable_umsch_mm; 1024 1025 /* firmwares */ 1026 struct amdgpu_firmware firmware; 1027 1028 /* PSP */ 1029 struct psp_context psp; 1030 1031 /* GDS */ 1032 struct amdgpu_gds gds; 1033 1034 /* for userq and VM fences */ 1035 struct amdgpu_seq64 seq64; 1036 1037 /* KFD */ 1038 struct amdgpu_kfd_dev kfd; 1039 1040 /* UMC */ 1041 struct amdgpu_umc umc; 1042 1043 /* display related functionality */ 1044 struct amdgpu_display_manager dm; 1045 1046 /* mes */ 1047 bool enable_mes; 1048 bool enable_mes_kiq; 1049 struct amdgpu_mes mes; 1050 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 1051 1052 /* df */ 1053 struct amdgpu_df df; 1054 1055 /* MCA */ 1056 struct amdgpu_mca mca; 1057 1058 /* ACA */ 1059 struct amdgpu_aca aca; 1060 1061 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1062 uint32_t harvest_ip_mask; 1063 int num_ip_blocks; 1064 struct mutex mn_lock; 1065 DECLARE_HASHTABLE(mn_hash, 7); 1066 1067 /* tracking pinned memory */ 1068 atomic64_t vram_pin_size; 1069 atomic64_t visible_pin_size; 1070 atomic64_t gart_pin_size; 1071 1072 /* soc15 register offset based on ip, instance and segment */ 1073 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1074 struct amdgpu_ip_map_info ip_map; 1075 1076 /* delayed work_func for deferring clockgating during resume */ 1077 struct delayed_work delayed_init_work; 1078 1079 struct amdgpu_virt virt; 1080 1081 /* link all shadow bo */ 1082 struct list_head shadow_list; 1083 struct mutex shadow_list_lock; 1084 1085 /* record hw reset is performed */ 1086 bool has_hw_reset; 1087 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1088 1089 /* s3/s4 mask */ 1090 bool in_suspend; 1091 bool in_s3; 1092 bool in_s4; 1093 bool in_s0ix; 1094 /* indicate amdgpu suspension status */ 1095 bool suspend_complete; 1096 1097 enum pp_mp1_state mp1_state; 1098 struct amdgpu_doorbell_index doorbell_index; 1099 1100 struct mutex notifier_lock; 1101 1102 int asic_reset_res; 1103 struct work_struct xgmi_reset_work; 1104 struct list_head reset_list; 1105 1106 long gfx_timeout; 1107 long sdma_timeout; 1108 long video_timeout; 1109 long compute_timeout; 1110 long psp_timeout; 1111 1112 uint64_t unique_id; 1113 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1114 1115 /* enable runtime pm on the device */ 1116 bool in_runpm; 1117 bool has_pr3; 1118 1119 bool ucode_sysfs_en; 1120 1121 struct amdgpu_fru_info *fru_info; 1122 atomic_t throttling_logging_enabled; 1123 struct ratelimit_state throttling_logging_rs; 1124 uint32_t ras_hw_enabled; 1125 uint32_t ras_enabled; 1126 1127 bool no_hw_access; 1128 struct pci_saved_state *pci_state; 1129 pci_channel_state_t pci_channel_state; 1130 1131 /* Track auto wait count on s_barrier settings */ 1132 bool barrier_has_auto_waitcnt; 1133 1134 struct amdgpu_reset_control *reset_cntl; 1135 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1136 1137 bool ram_is_direct_mapped; 1138 1139 struct list_head ras_list; 1140 1141 struct ip_discovery_top *ip_top; 1142 1143 struct amdgpu_reset_domain *reset_domain; 1144 1145 struct mutex benchmark_mutex; 1146 1147 struct amdgpu_reset_info reset_info; 1148 1149 bool scpm_enabled; 1150 uint32_t scpm_status; 1151 1152 struct work_struct reset_work; 1153 1154 bool job_hang; 1155 bool dc_enabled; 1156 /* Mask of active clusters */ 1157 uint32_t aid_mask; 1158 1159 /* Debug */ 1160 bool debug_vm; 1161 bool debug_largebar; 1162 bool debug_disable_soft_recovery; 1163 bool debug_use_vram_fw_buf; 1164 }; 1165 1166 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, 1167 uint8_t ip, uint8_t inst) 1168 { 1169 /* This considers only major/minor/rev and ignores 1170 * subrevision/variant fields. 1171 */ 1172 return adev->ip_versions[ip][inst] & ~0xFFU; 1173 } 1174 1175 static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev, 1176 uint8_t ip, uint8_t inst) 1177 { 1178 /* This returns full version - major/minor/rev/variant/subrevision */ 1179 return adev->ip_versions[ip][inst]; 1180 } 1181 1182 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1183 { 1184 return container_of(ddev, struct amdgpu_device, ddev); 1185 } 1186 1187 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1188 { 1189 return &adev->ddev; 1190 } 1191 1192 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1193 { 1194 return container_of(bdev, struct amdgpu_device, mman.bdev); 1195 } 1196 1197 int amdgpu_device_init(struct amdgpu_device *adev, 1198 uint32_t flags); 1199 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1200 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1201 1202 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1203 1204 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1205 void *buf, size_t size, bool write); 1206 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1207 void *buf, size_t size, bool write); 1208 1209 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1210 void *buf, size_t size, bool write); 1211 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, 1212 uint32_t inst, uint32_t reg_addr, char reg_name[], 1213 uint32_t expected_value, uint32_t mask); 1214 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1215 uint32_t reg, uint32_t acc_flags); 1216 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, 1217 u64 reg_addr); 1218 uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, 1219 uint32_t reg, uint32_t acc_flags, 1220 uint32_t xcc_id); 1221 void amdgpu_device_wreg(struct amdgpu_device *adev, 1222 uint32_t reg, uint32_t v, 1223 uint32_t acc_flags); 1224 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, 1225 u64 reg_addr, u32 reg_data); 1226 void amdgpu_device_xcc_wreg(struct amdgpu_device *adev, 1227 uint32_t reg, uint32_t v, 1228 uint32_t acc_flags, 1229 uint32_t xcc_id); 1230 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1231 uint32_t reg, uint32_t v, uint32_t xcc_id); 1232 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1233 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1234 1235 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1236 u32 reg_addr); 1237 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1238 u32 reg_addr); 1239 u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, 1240 u64 reg_addr); 1241 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1242 u32 reg_addr, u32 reg_data); 1243 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1244 u32 reg_addr, u64 reg_data); 1245 void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, 1246 u64 reg_addr, u64 reg_data); 1247 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev); 1248 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1249 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1250 1251 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev); 1252 1253 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1254 struct amdgpu_reset_context *reset_context); 1255 1256 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1257 struct amdgpu_reset_context *reset_context); 1258 1259 int emu_soc_asic_init(struct amdgpu_device *adev); 1260 1261 /* 1262 * Registers read & write functions. 1263 */ 1264 #define AMDGPU_REGS_NO_KIQ (1<<1) 1265 #define AMDGPU_REGS_RLC (1<<2) 1266 1267 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1268 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1269 1270 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0) 1271 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0) 1272 1273 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1274 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1275 1276 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1277 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1278 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1279 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1280 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1281 #define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst) 1282 #define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst) 1283 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1284 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1285 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1286 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1287 #define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg)) 1288 #define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v)) 1289 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1290 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1291 #define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg)) 1292 #define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v)) 1293 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1294 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1295 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1296 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1297 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1298 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1299 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1300 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1301 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1302 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1303 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1304 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1305 #define WREG32_P(reg, val, mask) \ 1306 do { \ 1307 uint32_t tmp_ = RREG32(reg); \ 1308 tmp_ &= (mask); \ 1309 tmp_ |= ((val) & ~(mask)); \ 1310 WREG32(reg, tmp_); \ 1311 } while (0) 1312 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1313 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1314 #define WREG32_PLL_P(reg, val, mask) \ 1315 do { \ 1316 uint32_t tmp_ = RREG32_PLL(reg); \ 1317 tmp_ &= (mask); \ 1318 tmp_ |= ((val) & ~(mask)); \ 1319 WREG32_PLL(reg, tmp_); \ 1320 } while (0) 1321 1322 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1323 do { \ 1324 u32 tmp = RREG32_SMC(_Reg); \ 1325 tmp &= (_Mask); \ 1326 tmp |= ((_Val) & ~(_Mask)); \ 1327 WREG32_SMC(_Reg, tmp); \ 1328 } while (0) 1329 1330 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1331 1332 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1333 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1334 1335 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1336 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1337 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1338 1339 #define REG_GET_FIELD(value, reg, field) \ 1340 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1341 1342 #define WREG32_FIELD(reg, field, val) \ 1343 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1344 1345 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1346 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1347 1348 #define AMDGPU_GET_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> (l)) 1349 /* 1350 * BIOS helpers. 1351 */ 1352 #define RBIOS8(i) (adev->bios[i]) 1353 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1354 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1355 1356 /* 1357 * ASICs macro. 1358 */ 1359 #define amdgpu_asic_set_vga_state(adev, state) \ 1360 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0) 1361 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1362 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1363 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1364 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1365 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1366 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1367 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1368 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1369 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1370 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1371 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1372 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1373 #define amdgpu_asic_flush_hdp(adev, r) \ 1374 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1375 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1376 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \ 1377 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0)) 1378 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1379 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1380 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1381 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1382 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1383 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1384 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1385 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1386 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1387 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1388 1389 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)) 1390 1391 #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i)) 1392 #define for_each_inst(i, inst_mask) \ 1393 for (i = ffs(inst_mask); i-- != 0; \ 1394 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1))) 1395 1396 /* Common functions */ 1397 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1398 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1399 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1400 struct amdgpu_job *job, 1401 struct amdgpu_reset_context *reset_context); 1402 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1403 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1404 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1405 bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev); 1406 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1407 1408 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1409 u64 num_vis_bytes); 1410 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1411 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1412 const u32 *registers, 1413 const u32 array_size); 1414 1415 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1416 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1417 bool amdgpu_device_supports_px(struct drm_device *dev); 1418 bool amdgpu_device_supports_boco(struct drm_device *dev); 1419 bool amdgpu_device_supports_smart_shift(struct drm_device *dev); 1420 int amdgpu_device_supports_baco(struct drm_device *dev); 1421 void amdgpu_device_detect_runtime_pm_mode(struct amdgpu_device *adev); 1422 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1423 struct amdgpu_device *peer_adev); 1424 int amdgpu_device_baco_enter(struct drm_device *dev); 1425 int amdgpu_device_baco_exit(struct drm_device *dev); 1426 1427 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1428 struct amdgpu_ring *ring); 1429 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1430 struct amdgpu_ring *ring); 1431 1432 void amdgpu_device_halt(struct amdgpu_device *adev); 1433 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, 1434 u32 reg); 1435 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, 1436 u32 reg, u32 v); 1437 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1438 struct dma_fence *gang); 1439 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1440 1441 /* atpx handler */ 1442 #if defined(CONFIG_VGA_SWITCHEROO) 1443 void amdgpu_register_atpx_handler(void); 1444 void amdgpu_unregister_atpx_handler(void); 1445 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1446 bool amdgpu_is_atpx_hybrid(void); 1447 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1448 bool amdgpu_has_atpx(void); 1449 #else 1450 static inline void amdgpu_register_atpx_handler(void) {} 1451 static inline void amdgpu_unregister_atpx_handler(void) {} 1452 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1453 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1454 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1455 static inline bool amdgpu_has_atpx(void) { return false; } 1456 #endif 1457 1458 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1459 void *amdgpu_atpx_get_dhandle(void); 1460 #else 1461 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1462 #endif 1463 1464 /* 1465 * KMS 1466 */ 1467 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1468 extern const int amdgpu_max_kms_ioctl; 1469 1470 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1471 void amdgpu_driver_unload_kms(struct drm_device *dev); 1472 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1473 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1474 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1475 struct drm_file *file_priv); 1476 void amdgpu_driver_release_kms(struct drm_device *dev); 1477 1478 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1479 int amdgpu_device_prepare(struct drm_device *dev); 1480 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1481 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1482 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1483 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1484 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1485 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1486 struct drm_file *filp); 1487 1488 /* 1489 * functions used by amdgpu_encoder.c 1490 */ 1491 struct amdgpu_afmt_acr { 1492 u32 clock; 1493 1494 int n_32khz; 1495 int cts_32khz; 1496 1497 int n_44_1khz; 1498 int cts_44_1khz; 1499 1500 int n_48khz; 1501 int cts_48khz; 1502 1503 }; 1504 1505 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1506 1507 /* amdgpu_acpi.c */ 1508 1509 struct amdgpu_numa_info { 1510 uint64_t size; 1511 int pxm; 1512 int nid; 1513 }; 1514 1515 /* ATCS Device/Driver State */ 1516 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1517 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1518 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1519 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1520 1521 #if defined(CONFIG_ACPI) 1522 int amdgpu_acpi_init(struct amdgpu_device *adev); 1523 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1524 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1525 bool amdgpu_acpi_is_power_shift_control_supported(void); 1526 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1527 u8 perf_req, bool advertise); 1528 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1529 u8 dev_state, bool drv_state); 1530 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state); 1531 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1532 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, 1533 u64 *tmr_size); 1534 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, 1535 struct amdgpu_numa_info *numa_info); 1536 1537 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1538 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1539 void amdgpu_acpi_detect(void); 1540 void amdgpu_acpi_release(void); 1541 #else 1542 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1543 static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, 1544 u64 *tmr_offset, u64 *tmr_size) 1545 { 1546 return -EINVAL; 1547 } 1548 static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, 1549 int xcc_id, 1550 struct amdgpu_numa_info *numa_info) 1551 { 1552 return -EINVAL; 1553 } 1554 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1555 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1556 static inline void amdgpu_acpi_detect(void) { } 1557 static inline void amdgpu_acpi_release(void) { } 1558 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1559 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1560 u8 dev_state, bool drv_state) { return 0; } 1561 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, 1562 enum amdgpu_ss ss_state) { return 0; } 1563 #endif 1564 1565 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1566 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1567 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1568 void amdgpu_choose_low_power_state(struct amdgpu_device *adev); 1569 #else 1570 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1571 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1572 static inline void amdgpu_choose_low_power_state(struct amdgpu_device *adev) { } 1573 #endif 1574 1575 #if defined(CONFIG_DRM_AMD_DC) 1576 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1577 #else 1578 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1579 #endif 1580 1581 1582 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1583 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1584 1585 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1586 pci_channel_state_t state); 1587 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1588 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1589 void amdgpu_pci_resume(struct pci_dev *pdev); 1590 1591 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1592 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1593 1594 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1595 1596 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1597 enum amd_clockgating_state state); 1598 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1599 enum amd_powergating_state state); 1600 1601 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1602 { 1603 return amdgpu_gpu_recovery != 0 && 1604 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1605 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1606 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1607 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1608 } 1609 1610 #include "amdgpu_object.h" 1611 1612 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1613 { 1614 return adev->gmc.tmz_enabled; 1615 } 1616 1617 int amdgpu_in_reset(struct amdgpu_device *adev); 1618 1619 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 1620 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 1621 extern const struct attribute_group amdgpu_flash_attr_group; 1622 1623 #endif 1624