1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #include "amdgpu_ctx.h" 38 39 #include <linux/atomic.h> 40 #include <linux/wait.h> 41 #include <linux/list.h> 42 #include <linux/kref.h> 43 #include <linux/rbtree.h> 44 #include <linux/hashtable.h> 45 #include <linux/dma-fence.h> 46 #include <linux/pci.h> 47 48 #include <drm/ttm/ttm_bo.h> 49 #include <drm/ttm/ttm_placement.h> 50 51 #include <drm/amdgpu_drm.h> 52 #include <drm/drm_gem.h> 53 #include <drm/drm_ioctl.h> 54 55 #include <kgd_kfd_interface.h> 56 #include "dm_pp_interface.h" 57 #include "kgd_pp_interface.h" 58 59 #include "amd_shared.h" 60 #include "amdgpu_utils.h" 61 #include "amdgpu_mode.h" 62 #include "amdgpu_ih.h" 63 #include "amdgpu_irq.h" 64 #include "amdgpu_ucode.h" 65 #include "amdgpu_ttm.h" 66 #include "amdgpu_psp.h" 67 #include "amdgpu_gds.h" 68 #include "amdgpu_sync.h" 69 #include "amdgpu_ring.h" 70 #include "amdgpu_vm.h" 71 #include "amdgpu_dpm.h" 72 #include "amdgpu_acp.h" 73 #include "amdgpu_uvd.h" 74 #include "amdgpu_vce.h" 75 #include "amdgpu_vcn.h" 76 #include "amdgpu_jpeg.h" 77 #include "amdgpu_vpe.h" 78 #include "amdgpu_umsch_mm.h" 79 #include "amdgpu_gmc.h" 80 #include "amdgpu_gfx.h" 81 #include "amdgpu_sdma.h" 82 #include "amdgpu_lsdma.h" 83 #include "amdgpu_nbio.h" 84 #include "amdgpu_reg_access.h" 85 #include "amdgpu_hdp.h" 86 #include "amdgpu_dm.h" 87 #include "amdgpu_virt.h" 88 #include "amdgpu_csa.h" 89 #include "amdgpu_mes_ctx.h" 90 #include "amdgpu_gart.h" 91 #include "amdgpu_debugfs.h" 92 #include "amdgpu_job.h" 93 #include "amdgpu_bo_list.h" 94 #include "amdgpu_gem.h" 95 #include "amdgpu_doorbell.h" 96 #include "amdgpu_amdkfd.h" 97 #include "amdgpu_discovery.h" 98 #include "amdgpu_mes.h" 99 #include "amdgpu_umc.h" 100 #include "amdgpu_mmhub.h" 101 #include "amdgpu_gfxhub.h" 102 #include "amdgpu_df.h" 103 #include "amdgpu_smuio.h" 104 #include "amdgpu_fdinfo.h" 105 #include "amdgpu_mca.h" 106 #include "amdgpu_aca.h" 107 #include "amdgpu_ras.h" 108 #include "amdgpu_lockdep.h" 109 #include "amdgpu_cper.h" 110 #include "amdgpu_xcp.h" 111 #include "amdgpu_seq64.h" 112 #include "amdgpu_reg_state.h" 113 #include "amdgpu_userq.h" 114 #include "amdgpu_eviction_fence.h" 115 #include "amdgpu_ip.h" 116 #if defined(CONFIG_DRM_AMD_ISP) 117 #include "amdgpu_isp.h" 118 #endif 119 120 #define MAX_GPU_INSTANCE 64 121 122 #define GFX_SLICE_PERIOD_MS 250 123 124 struct amdgpu_gpu_instance { 125 struct amdgpu_device *adev; 126 int mgpu_fan_enabled; 127 }; 128 129 struct amdgpu_mgpu_info { 130 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 131 struct mutex mutex; 132 uint32_t num_gpu; 133 uint32_t num_dgpu; 134 uint32_t num_apu; 135 }; 136 137 enum amdgpu_ss { 138 AMDGPU_SS_DRV_LOAD, 139 AMDGPU_SS_DEV_D0, 140 AMDGPU_SS_DEV_D3, 141 AMDGPU_SS_DRV_UNLOAD 142 }; 143 144 struct amdgpu_hwip_reg_entry { 145 u32 hwip; 146 u32 inst; 147 u32 seg; 148 u32 reg_offset; 149 const char *reg_name; 150 }; 151 152 struct amdgpu_watchdog_timer { 153 bool timeout_fatal_disable; 154 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 155 }; 156 157 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 158 159 /* 160 * Modules parameters. 161 */ 162 extern int amdgpu_modeset; 163 extern unsigned int amdgpu_vram_limit; 164 extern int amdgpu_vis_vram_limit; 165 extern int amdgpu_gart_size; 166 extern int amdgpu_gtt_size; 167 extern int amdgpu_moverate; 168 extern int amdgpu_audio; 169 extern int amdgpu_disp_priority; 170 extern int amdgpu_hw_i2c; 171 extern int amdgpu_pcie_gen2; 172 extern int amdgpu_msi; 173 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 174 extern int amdgpu_dpm; 175 extern int amdgpu_fw_load_type; 176 extern int amdgpu_aspm; 177 extern int amdgpu_runtime_pm; 178 extern uint amdgpu_ip_block_mask; 179 extern int amdgpu_bapm; 180 extern int amdgpu_deep_color; 181 extern int amdgpu_vm_size; 182 extern int amdgpu_vm_block_size; 183 extern int amdgpu_vm_fragment_size; 184 extern int amdgpu_vm_fault_stop; 185 extern int amdgpu_vm_debug; 186 extern int amdgpu_vm_update_mode; 187 extern int amdgpu_exp_hw_support; 188 extern int amdgpu_dc; 189 extern int amdgpu_sched_jobs; 190 extern int amdgpu_sched_hw_submission; 191 extern uint amdgpu_pcie_gen_cap; 192 extern uint amdgpu_pcie_lane_cap; 193 extern u64 amdgpu_cg_mask; 194 extern uint amdgpu_pg_mask; 195 extern uint amdgpu_sdma_phase_quantum; 196 extern char *amdgpu_disable_cu; 197 extern char *amdgpu_virtual_display; 198 extern uint amdgpu_pp_feature_mask; 199 extern uint amdgpu_force_long_training; 200 extern int amdgpu_lbpw; 201 extern int amdgpu_compute_multipipe; 202 extern int amdgpu_gpu_recovery; 203 extern int amdgpu_emu_mode; 204 extern uint amdgpu_smu_memory_pool_size; 205 extern int amdgpu_smu_pptable_id; 206 extern uint amdgpu_dc_feature_mask; 207 extern uint amdgpu_freesync_vid_mode; 208 extern uint amdgpu_dc_debug_mask; 209 extern uint amdgpu_dc_visual_confirm; 210 extern int amdgpu_dm_abm_level; 211 extern int amdgpu_backlight; 212 extern int amdgpu_damage_clips; 213 extern struct amdgpu_mgpu_info mgpu_info; 214 extern int amdgpu_ras_enable; 215 extern uint amdgpu_ras_mask; 216 extern int amdgpu_bad_page_threshold; 217 extern bool amdgpu_ignore_bad_page_threshold; 218 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 219 extern int amdgpu_async_gfx_ring; 220 extern int amdgpu_mcbp; 221 extern int amdgpu_discovery; 222 extern int amdgpu_mes_log_enable; 223 extern int amdgpu_uni_mes; 224 extern int amdgpu_noretry; 225 extern int amdgpu_force_asic_type; 226 extern int amdgpu_smartshift_bias; 227 extern int amdgpu_use_xgmi_p2p; 228 extern int amdgpu_mtype_local; 229 extern int amdgpu_enforce_isolation; 230 #ifdef CONFIG_HSA_AMD 231 extern int sched_policy; 232 extern bool debug_evictions; 233 extern bool no_system_mem_limit; 234 extern int halt_if_hws_hang; 235 extern uint amdgpu_svm_default_granularity; 236 #else 237 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 238 static const bool __maybe_unused debug_evictions; /* = false */ 239 static const bool __maybe_unused no_system_mem_limit; 240 static const int __maybe_unused halt_if_hws_hang; 241 #endif 242 #ifdef CONFIG_HSA_AMD_P2P 243 extern bool pcie_p2p; 244 #endif 245 246 extern int amdgpu_tmz; 247 extern int amdgpu_reset_method; 248 249 #ifdef CONFIG_DRM_AMDGPU_SI 250 extern int amdgpu_si_support; 251 #endif 252 #ifdef CONFIG_DRM_AMDGPU_CIK 253 extern int amdgpu_cik_support; 254 #endif 255 extern int amdgpu_num_kcq; 256 257 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 258 #define AMDGPU_UMSCHFW_LOG_SIZE (32 * 1024) 259 extern int amdgpu_vcnfw_log; 260 extern int amdgpu_sg_display; 261 extern int amdgpu_umsch_mm; 262 extern int amdgpu_seamless; 263 extern int amdgpu_umsch_mm_fwlog; 264 265 extern int amdgpu_user_partt_mode; 266 extern int amdgpu_agp; 267 extern int amdgpu_rebar; 268 269 extern int amdgpu_wbrf; 270 extern int amdgpu_user_queue; 271 extern int amdgpu_ptl; 272 273 extern uint amdgpu_hdmi_hpd_debounce_delay_ms; 274 275 #define AMDGPU_VM_MAX_NUM_CTX 4096 276 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 277 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 278 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 279 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 280 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 281 #define AMDGPUFB_CONN_LIMIT 4 282 #define AMDGPU_BIOS_NUM_SCRATCH 16 283 284 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 285 286 /* hard reset data */ 287 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 288 289 /* reset flags */ 290 #define AMDGPU_RESET_GFX (1 << 0) 291 #define AMDGPU_RESET_COMPUTE (1 << 1) 292 #define AMDGPU_RESET_DMA (1 << 2) 293 #define AMDGPU_RESET_CP (1 << 3) 294 #define AMDGPU_RESET_GRBM (1 << 4) 295 #define AMDGPU_RESET_DMA1 (1 << 5) 296 #define AMDGPU_RESET_RLC (1 << 6) 297 #define AMDGPU_RESET_SEM (1 << 7) 298 #define AMDGPU_RESET_IH (1 << 8) 299 #define AMDGPU_RESET_VMC (1 << 9) 300 #define AMDGPU_RESET_MC (1 << 10) 301 #define AMDGPU_RESET_DISPLAY (1 << 11) 302 #define AMDGPU_RESET_UVD (1 << 12) 303 #define AMDGPU_RESET_VCE (1 << 13) 304 #define AMDGPU_RESET_VCE1 (1 << 14) 305 306 /* reset mask */ 307 #define AMDGPU_RESET_TYPE_FULL (1 << 0) /* full adapter reset, mode1/mode2/BACO/etc. */ 308 #define AMDGPU_RESET_TYPE_SOFT_RESET (1 << 1) /* IP level soft reset */ 309 #define AMDGPU_RESET_TYPE_PER_QUEUE (1 << 2) /* per queue */ 310 #define AMDGPU_RESET_TYPE_PER_PIPE (1 << 3) /* per pipe */ 311 312 /* max cursor sizes (in pixels) */ 313 #define CIK_CURSOR_WIDTH 128 314 #define CIK_CURSOR_HEIGHT 128 315 316 /* smart shift bias level limits */ 317 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 318 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 319 320 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */ 321 #define AMDGPU_SWCTF_EXTRA_DELAY 50 322 323 struct amdgpu_xcp_mgr; 324 struct amdgpu_device; 325 struct amdgpu_irq_src; 326 struct amdgpu_fpriv; 327 struct amdgpu_bo_va_mapping; 328 struct kfd_vm_fault_info; 329 struct amdgpu_hive_info; 330 struct amdgpu_reset_context; 331 struct amdgpu_reset_control; 332 struct amdgpu_coredump_info; 333 334 enum amdgpu_cp_irq { 335 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 336 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 337 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 338 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 339 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 340 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 341 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 342 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 343 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 344 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 345 346 AMDGPU_CP_IRQ_LAST 347 }; 348 349 enum amdgpu_thermal_irq { 350 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 351 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 352 353 AMDGPU_THERMAL_IRQ_LAST 354 }; 355 356 enum amdgpu_kiq_irq { 357 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 358 AMDGPU_CP_KIQ_IRQ_LAST 359 }; 360 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 361 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 362 #define MAX_KIQ_REG_TRY 1000 363 364 /* 365 * BIOS. 366 */ 367 bool amdgpu_get_bios(struct amdgpu_device *adev); 368 bool amdgpu_read_bios(struct amdgpu_device *adev); 369 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 370 u8 *bios, u32 length_bytes); 371 void amdgpu_bios_release(struct amdgpu_device *adev); 372 /* 373 * Clocks 374 */ 375 376 #define AMDGPU_MAX_PPLL 3 377 378 struct amdgpu_clock { 379 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 380 struct amdgpu_pll spll; 381 struct amdgpu_pll mpll; 382 /* 10 Khz units */ 383 uint32_t default_mclk; 384 uint32_t default_sclk; 385 uint32_t default_dispclk; 386 uint32_t dp_extclk; 387 uint32_t max_pixel_clock; 388 }; 389 390 /* sub-allocation manager, it has to be protected by another lock. 391 * By conception this is an helper for other part of the driver 392 * like the indirect buffer or semaphore, which both have their 393 * locking. 394 * 395 * Principe is simple, we keep a list of sub allocation in offset 396 * order (first entry has offset == 0, last entry has the highest 397 * offset). 398 * 399 * When allocating new object we first check if there is room at 400 * the end total_size - (last_object_offset + last_object_size) >= 401 * alloc_size. If so we allocate new object there. 402 * 403 * When there is not enough room at the end, we start waiting for 404 * each sub object until we reach object_offset+object_size >= 405 * alloc_size, this object then become the sub object we return. 406 * 407 * Alignment can't be bigger than page size. 408 * 409 * Hole are not considered for allocation to keep things simple. 410 * Assumption is that there won't be hole (all object on same 411 * alignment). 412 */ 413 414 struct amdgpu_sa_manager { 415 struct drm_suballoc_manager base; 416 struct amdgpu_bo *bo; 417 uint64_t gpu_addr; 418 void *cpu_ptr; 419 }; 420 421 /* 422 * IRQS. 423 */ 424 425 struct amdgpu_flip_work { 426 struct delayed_work flip_work; 427 struct work_struct unpin_work; 428 struct amdgpu_device *adev; 429 int crtc_id; 430 u32 target_vblank; 431 uint64_t base; 432 struct drm_pending_vblank_event *event; 433 struct amdgpu_bo *old_abo; 434 unsigned shared_count; 435 struct dma_fence **shared; 436 struct dma_fence_cb cb; 437 bool async; 438 }; 439 440 /* 441 * file private structure 442 */ 443 444 struct amdgpu_fpriv { 445 struct amdgpu_vm vm; 446 struct amdgpu_bo_va *prt_va; 447 struct amdgpu_bo_va *csa_va; 448 struct amdgpu_bo_va *seq64_va; 449 struct mutex bo_list_lock; 450 struct idr bo_list_handles; 451 struct amdgpu_ctx_mgr ctx_mgr; 452 struct amdgpu_userq_mgr userq_mgr; 453 454 /* Eviction fence infra */ 455 struct amdgpu_eviction_fence_mgr evf_mgr; 456 457 /** GPU partition selection */ 458 uint32_t xcp_id; 459 }; 460 461 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 462 463 /* 464 * Writeback 465 */ 466 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 467 468 /** 469 * struct amdgpu_wb - This struct is used for small GPU memory allocation. 470 * 471 * This struct is used to allocate a small amount of GPU memory that can be 472 * used to shadow certain states into the memory. This is especially useful for 473 * providing easy CPU access to some states without requiring register access 474 * (e.g., if some block is power gated, reading register may be problematic). 475 * 476 * Note: the term writeback was initially used because many of the amdgpu 477 * components had some level of writeback memory, and this struct initially 478 * described those components. 479 */ 480 struct amdgpu_wb { 481 482 /** 483 * @wb_obj: 484 * 485 * Buffer Object used for the writeback memory. 486 */ 487 struct amdgpu_bo *wb_obj; 488 489 /** 490 * @wb: 491 * 492 * Pointer to the first writeback slot. In terms of CPU address 493 * this value can be accessed directly by using the offset as an index. 494 * For the GPU address, it is necessary to use gpu_addr and the offset. 495 */ 496 uint32_t *wb; 497 498 /** 499 * @gpu_addr: 500 * 501 * Writeback base address in the GPU. 502 */ 503 uint64_t gpu_addr; 504 505 /** 506 * @num_wb: 507 * 508 * Number of writeback slots reserved for amdgpu. 509 */ 510 u32 num_wb; 511 512 /** 513 * @used: 514 * 515 * Track the writeback slot already used. 516 */ 517 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 518 519 /** 520 * @lock: 521 * 522 * Protects read and write of the used field array. 523 */ 524 spinlock_t lock; 525 }; 526 527 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 528 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 529 530 /* 531 * Benchmarking 532 */ 533 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 534 535 /* 536 * ASIC specific register table accessible by UMD 537 */ 538 struct amdgpu_allowed_register_entry { 539 uint32_t reg_offset; 540 bool grbm_indexed; 541 }; 542 543 struct amdgpu_video_codec_info { 544 u32 codec_type; 545 u32 max_width; 546 u32 max_height; 547 u32 max_pixels_per_frame; 548 u32 max_level; 549 }; 550 551 #define codec_info_build(type, width, height, level) \ 552 .codec_type = type,\ 553 .max_width = width,\ 554 .max_height = height,\ 555 .max_pixels_per_frame = height * width,\ 556 .max_level = level, 557 558 struct amdgpu_video_codecs { 559 const u32 codec_count; 560 const struct amdgpu_video_codec_info *codec_array; 561 }; 562 563 /* 564 * ASIC specific functions. 565 */ 566 struct amdgpu_asic_funcs { 567 bool (*read_disabled_bios)(struct amdgpu_device *adev); 568 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 569 u8 *bios, u32 length_bytes); 570 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 571 u32 sh_num, u32 reg_offset, u32 *value); 572 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 573 int (*reset)(struct amdgpu_device *adev); 574 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 575 /* get the reference clock */ 576 u32 (*get_xclk)(struct amdgpu_device *adev); 577 /* MM block clocks */ 578 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 579 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 580 /* static power management */ 581 int (*get_pcie_lanes)(struct amdgpu_device *adev); 582 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 583 /* get config memsize register */ 584 u32 (*get_config_memsize)(struct amdgpu_device *adev); 585 /* flush hdp write queue */ 586 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 587 /* invalidate hdp read cache */ 588 void (*invalidate_hdp)(struct amdgpu_device *adev, 589 struct amdgpu_ring *ring); 590 /* check if the asic needs a full reset of if soft reset will work */ 591 bool (*need_full_reset)(struct amdgpu_device *adev); 592 /* initialize doorbell layout for specific asic*/ 593 void (*init_doorbell_index)(struct amdgpu_device *adev); 594 /* PCIe bandwidth usage */ 595 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 596 uint64_t *count1); 597 /* do we need to reset the asic at init time (e.g., kexec) */ 598 bool (*need_reset_on_init)(struct amdgpu_device *adev); 599 /* PCIe replay counter */ 600 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 601 /* device supports BACO */ 602 int (*supports_baco)(struct amdgpu_device *adev); 603 /* pre asic_init quirks */ 604 void (*pre_asic_init)(struct amdgpu_device *adev); 605 /* enter/exit umd stable pstate */ 606 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 607 /* query video codecs */ 608 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 609 const struct amdgpu_video_codecs **codecs); 610 /* encode "> 32bits" smn addressing */ 611 u64 (*encode_ext_smn_addressing)(int ext_id); 612 613 ssize_t (*get_reg_state)(struct amdgpu_device *adev, 614 enum amdgpu_reg_state reg_state, void *buf, 615 size_t max_size); 616 }; 617 618 /* 619 * IOCTL. 620 */ 621 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 622 struct drm_file *filp); 623 624 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 625 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 626 struct drm_file *filp); 627 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 628 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 629 struct drm_file *filp); 630 631 /* VRAM scratch page for HDP bug, default vram page */ 632 struct amdgpu_mem_scratch { 633 struct amdgpu_bo *robj; 634 uint32_t *ptr; 635 u64 gpu_addr; 636 }; 637 638 /* 639 * CGS 640 */ 641 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 642 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 643 644 /* 645 * Core structure, functions and helpers. 646 */ 647 struct amdgpu_mmio_remap { 648 u32 reg_offset; 649 resource_size_t bus_addr; 650 struct amdgpu_bo *bo; 651 }; 652 653 enum amdgpu_uid_type { 654 AMDGPU_UID_TYPE_XCD, 655 AMDGPU_UID_TYPE_AID, 656 AMDGPU_UID_TYPE_SOC, 657 AMDGPU_UID_TYPE_MID, 658 AMDGPU_UID_TYPE_MAX 659 }; 660 661 #define AMDGPU_UID_INST_MAX 8 /* max number of instances for each UID type */ 662 663 struct amdgpu_uid { 664 uint64_t uid[AMDGPU_UID_TYPE_MAX][AMDGPU_UID_INST_MAX]; 665 struct amdgpu_device *adev; 666 }; 667 668 #define MAX_UMA_OPTION_NAME 28 669 #define MAX_UMA_OPTION_ENTRIES 19 670 671 #define AMDGPU_UMA_FLAG_AUTO BIT(1) 672 #define AMDGPU_UMA_FLAG_CUSTOM BIT(0) 673 674 /** 675 * struct amdgpu_uma_carveout_option - single UMA carveout option 676 * @name: Name of the carveout option 677 * @memory_carved_mb: Amount of memory carved in MB 678 * @flags: ATCS flags supported by this option 679 */ 680 struct amdgpu_uma_carveout_option { 681 char name[MAX_UMA_OPTION_NAME]; 682 uint32_t memory_carved_mb; 683 uint8_t flags; 684 }; 685 686 /** 687 * struct amdgpu_uma_carveout_info - table of available UMA carveout options 688 * @num_entries: Number of available options 689 * @uma_option_index: The index of the option currently applied 690 * @update_lock: Lock to serialize changes to the option 691 * @entries: The array of carveout options 692 */ 693 struct amdgpu_uma_carveout_info { 694 uint8_t num_entries; 695 uint8_t uma_option_index; 696 struct mutex update_lock; 697 struct amdgpu_uma_carveout_option entries[MAX_UMA_OPTION_ENTRIES]; 698 }; 699 700 struct amd_powerplay { 701 void *pp_handle; 702 const struct amd_pm_funcs *pp_funcs; 703 }; 704 705 /* polaris10 kickers */ 706 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 707 ((rid == 0xE3) || \ 708 (rid == 0xE4) || \ 709 (rid == 0xE5) || \ 710 (rid == 0xE7) || \ 711 (rid == 0xEF))) || \ 712 ((did == 0x6FDF) && \ 713 ((rid == 0xE7) || \ 714 (rid == 0xEF) || \ 715 (rid == 0xFF)))) 716 717 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 718 ((rid == 0xE1) || \ 719 (rid == 0xF7))) 720 721 /* polaris11 kickers */ 722 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 723 ((rid == 0xE0) || \ 724 (rid == 0xE5))) || \ 725 ((did == 0x67FF) && \ 726 ((rid == 0xCF) || \ 727 (rid == 0xEF) || \ 728 (rid == 0xFF)))) 729 730 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 731 ((rid == 0xE2))) 732 733 /* polaris12 kickers */ 734 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 735 ((rid == 0xC0) || \ 736 (rid == 0xC1) || \ 737 (rid == 0xC3) || \ 738 (rid == 0xC7))) || \ 739 ((did == 0x6981) && \ 740 ((rid == 0x00) || \ 741 (rid == 0x01) || \ 742 (rid == 0x10)))) 743 744 enum amdgpu_mqd_update_flag { 745 AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE = 1, 746 AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE = 2, 747 AMDGPU_UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ 748 }; 749 750 struct amdgpu_mqd_prop { 751 uint64_t mqd_gpu_addr; 752 uint64_t hqd_base_gpu_addr; 753 uint64_t rptr_gpu_addr; 754 uint64_t wptr_gpu_addr; 755 uint32_t queue_size; 756 bool use_doorbell; 757 uint32_t doorbell_index; 758 uint64_t eop_gpu_addr; 759 uint32_t hqd_pipe_priority; 760 uint32_t hqd_queue_priority; 761 uint32_t mqd_stride_size; 762 bool allow_tunneling; 763 bool hqd_active; 764 uint64_t shadow_addr; 765 uint64_t gds_bkup_addr; 766 uint64_t csa_addr; 767 uint64_t fence_address; 768 bool tmz_queue; 769 bool kernel_queue; 770 uint32_t *cu_mask; 771 uint32_t cu_mask_count; 772 uint32_t cu_flags; 773 bool is_user_cu_masked; 774 }; 775 776 struct amdgpu_mqd { 777 unsigned mqd_size; 778 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 779 struct amdgpu_mqd_prop *p); 780 }; 781 782 struct amdgpu_pcie_reset_ctx { 783 bool in_link_reset; 784 bool occurs_dpc; 785 bool audio_suspended; 786 struct pci_dev *swus; 787 struct pci_saved_state *swus_pcistate; 788 struct pci_saved_state *swds_pcistate; 789 }; 790 791 /* 792 * Custom Init levels could be defined for different situations where a full 793 * initialization of all hardware blocks are not expected. Sample cases are 794 * custom init sequences after resume after S0i3/S3, reset on initialization, 795 * partial reset of blocks etc. Presently, this defines only two levels. Levels 796 * are described in corresponding struct definitions - amdgpu_init_default, 797 * amdgpu_init_minimal_xgmi. 798 */ 799 enum amdgpu_init_lvl_id { 800 AMDGPU_INIT_LEVEL_DEFAULT, 801 AMDGPU_INIT_LEVEL_MINIMAL_XGMI, 802 AMDGPU_INIT_LEVEL_RESET_RECOVERY, 803 }; 804 805 struct amdgpu_init_level { 806 enum amdgpu_init_lvl_id level; 807 uint32_t hwini_ip_block_mask; 808 }; 809 810 #define AMDGPU_RESET_MAGIC_NUM 64 811 #define AMDGPU_MAX_DF_PERFMONS 4 812 struct amdgpu_reset_domain; 813 struct amdgpu_fru_info; 814 815 enum amdgpu_enforce_isolation_mode { 816 AMDGPU_ENFORCE_ISOLATION_DISABLE = 0, 817 AMDGPU_ENFORCE_ISOLATION_ENABLE = 1, 818 AMDGPU_ENFORCE_ISOLATION_ENABLE_LEGACY = 2, 819 AMDGPU_ENFORCE_ISOLATION_NO_CLEANER_SHADER = 3, 820 }; 821 822 struct amdgpu_device { 823 struct device *dev; 824 struct pci_dev *pdev; 825 struct drm_device ddev; 826 827 #ifdef CONFIG_DRM_AMD_ACP 828 struct amdgpu_acp acp; 829 #endif 830 struct amdgpu_hive_info *hive; 831 struct amdgpu_xcp_mgr *xcp_mgr; 832 /* ASIC */ 833 enum amd_asic_type asic_type; 834 uint32_t family; 835 uint32_t rev_id; 836 uint32_t external_rev_id; 837 unsigned long flags; 838 unsigned long apu_flags; 839 int usec_timeout; 840 const struct amdgpu_asic_funcs *asic_funcs; 841 bool shutdown; 842 bool need_swiotlb; 843 bool accel_working; 844 struct notifier_block acpi_nb; 845 struct notifier_block pm_nb; 846 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 847 struct debugfs_blob_wrapper debugfs_vbios_blob; 848 struct mutex srbm_mutex; 849 /* GRBM index mutex. Protects concurrent access to GRBM index */ 850 struct mutex grbm_idx_mutex; 851 struct dev_pm_domain vga_pm_domain; 852 bool have_disp_power_ref; 853 bool have_atomics_support; 854 855 /* BIOS */ 856 bool is_atom_fw; 857 uint8_t *bios; 858 uint32_t bios_size; 859 uint32_t bios_scratch_reg_offset; 860 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 861 862 /* Register/doorbell mmio */ 863 resource_size_t rmmio_base; 864 resource_size_t rmmio_size; 865 void __iomem *rmmio; 866 /* protects concurrent MM_INDEX/DATA based register access */ 867 spinlock_t mmio_idx_lock; 868 struct amdgpu_mmio_remap rmmio_remap; 869 /* Indirect register access blocks */ 870 struct amdgpu_reg_access reg; 871 struct amdgpu_doorbell doorbell; 872 873 /* clock/pll info */ 874 struct amdgpu_clock clock; 875 876 /* MC */ 877 struct amdgpu_gmc gmc; 878 struct amdgpu_gart gart; 879 dma_addr_t dummy_page_addr; 880 struct amdgpu_vm_manager vm_manager; 881 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 882 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS); 883 884 /* memory management */ 885 struct amdgpu_mman mman; 886 struct amdgpu_mem_scratch mem_scratch; 887 struct amdgpu_wb wb; 888 atomic64_t num_bytes_moved; 889 atomic64_t num_evictions; 890 atomic64_t num_vram_cpu_page_faults; 891 atomic_t gpu_reset_counter; 892 atomic_t vram_lost_counter; 893 894 /* data for buffer migration throttling */ 895 struct { 896 spinlock_t lock; 897 s64 last_update_us; 898 s64 accum_us; /* accumulated microseconds */ 899 s64 accum_us_vis; /* for visible VRAM */ 900 u32 log2_max_MBps; 901 } mm_stats; 902 903 /* discovery*/ 904 struct amdgpu_discovery_info discovery; 905 906 /* display */ 907 bool enable_virtual_display; 908 struct amdgpu_vkms_output *amdgpu_vkms_output; 909 struct amdgpu_mode_info mode_info; 910 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 911 struct delayed_work hotplug_work; 912 struct amdgpu_irq_src crtc_irq; 913 struct amdgpu_irq_src vline0_irq; 914 struct amdgpu_irq_src vupdate_irq; 915 struct amdgpu_irq_src pageflip_irq; 916 struct amdgpu_irq_src hpd_irq; 917 struct amdgpu_irq_src dmub_trace_irq; 918 struct amdgpu_irq_src dmub_outbox_irq; 919 920 /* rings */ 921 u64 fence_context; 922 unsigned num_rings; 923 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 924 struct dma_fence __rcu *gang_submit; 925 bool ib_pool_ready; 926 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 927 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 928 929 /* interrupts */ 930 struct amdgpu_irq irq; 931 932 /* powerplay */ 933 struct amd_powerplay powerplay; 934 struct amdgpu_pm pm; 935 u64 cg_flags; 936 u32 pg_flags; 937 938 /* nbio */ 939 struct amdgpu_nbio nbio; 940 941 /* hdp */ 942 struct amdgpu_hdp hdp; 943 944 /* smuio */ 945 struct amdgpu_smuio smuio; 946 947 /* mmhub */ 948 struct amdgpu_mmhub mmhub; 949 950 /* gfxhub */ 951 struct amdgpu_gfxhub gfxhub; 952 953 /* gfx */ 954 struct amdgpu_gfx gfx; 955 956 /* sdma */ 957 struct amdgpu_sdma sdma; 958 959 /* lsdma */ 960 struct amdgpu_lsdma lsdma; 961 962 /* uvd */ 963 struct amdgpu_uvd uvd; 964 965 /* vce */ 966 struct amdgpu_vce vce; 967 968 /* vcn */ 969 struct amdgpu_vcn vcn; 970 971 /* jpeg */ 972 struct amdgpu_jpeg jpeg; 973 974 /* vpe */ 975 struct amdgpu_vpe vpe; 976 977 /* umsch */ 978 struct amdgpu_umsch_mm umsch_mm; 979 bool enable_umsch_mm; 980 981 /* firmwares */ 982 struct amdgpu_firmware firmware; 983 984 /* PSP */ 985 struct psp_context psp; 986 987 /* GDS */ 988 struct amdgpu_gds gds; 989 990 /* for userq and VM fences */ 991 struct amdgpu_seq64 seq64; 992 993 /* UMC */ 994 struct amdgpu_umc umc; 995 996 /* display related functionality */ 997 struct amdgpu_display_manager dm; 998 999 #if defined(CONFIG_DRM_AMD_ISP) 1000 /* isp */ 1001 struct amdgpu_isp isp; 1002 #endif 1003 1004 /* mes */ 1005 bool enable_mes; 1006 bool enable_mes_kiq; 1007 bool enable_uni_mes; 1008 struct amdgpu_mes mes; 1009 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 1010 const struct amdgpu_userq_funcs *userq_funcs[AMDGPU_HW_IP_NUM]; 1011 1012 /** 1013 * @userq_doorbell_xa: Global user queue map (doorbell index → queue) 1014 * Key: doorbell_index (unique global identifier for the queue) 1015 * Value: struct amdgpu_usermode_queue 1016 */ 1017 struct xarray userq_doorbell_xa; 1018 1019 /* df */ 1020 struct amdgpu_df df; 1021 1022 /* MCA */ 1023 struct amdgpu_mca mca; 1024 1025 /* ACA */ 1026 struct amdgpu_aca aca; 1027 1028 /* CPER */ 1029 struct amdgpu_cper cper; 1030 1031 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1032 uint32_t harvest_ip_mask; 1033 int num_ip_blocks; 1034 struct mutex mn_lock; 1035 DECLARE_HASHTABLE(mn_hash, 7); 1036 1037 /* tracking pinned memory */ 1038 atomic64_t vram_pin_size; 1039 atomic64_t visible_pin_size; 1040 atomic64_t gart_pin_size; 1041 1042 /* soc15 register offset based on ip, instance and segment */ 1043 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1044 struct amdgpu_ip_map_info ip_map; 1045 1046 /* delayed work_func for deferring clockgating during resume */ 1047 struct delayed_work delayed_init_work; 1048 1049 struct amdgpu_virt virt; 1050 1051 /* record hw reset is performed */ 1052 bool has_hw_reset; 1053 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1054 1055 /* s3/s4 mask */ 1056 bool in_suspend; 1057 bool in_s3; 1058 bool in_s4; 1059 bool in_s0ix; 1060 suspend_state_t last_suspend_state; 1061 1062 enum pp_mp1_state mp1_state; 1063 struct amdgpu_doorbell_index doorbell_index; 1064 1065 struct mutex notifier_lock; 1066 1067 int asic_reset_res; 1068 struct work_struct xgmi_reset_work; 1069 struct list_head reset_list; 1070 1071 long gfx_timeout; 1072 long sdma_timeout; 1073 long video_timeout; 1074 long compute_timeout; 1075 long psp_timeout; 1076 1077 uint64_t unique_id; 1078 uint8_t unitid; 1079 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1080 1081 /* enable runtime pm on the device */ 1082 bool in_runpm; 1083 bool has_pr3; 1084 1085 bool ucode_sysfs_en; 1086 1087 struct amdgpu_fru_info *fru_info; 1088 atomic_t throttling_logging_enabled; 1089 struct ratelimit_state throttling_logging_rs; 1090 uint32_t ras_hw_enabled; 1091 uint32_t ras_enabled; 1092 bool ras_default_ecc_enabled; 1093 1094 bool no_hw_access; 1095 struct pci_saved_state *pci_state; 1096 pci_channel_state_t pci_channel_state; 1097 1098 struct amdgpu_pcie_reset_ctx pcie_reset_ctx; 1099 1100 /* Track auto wait count on s_barrier settings */ 1101 bool barrier_has_auto_waitcnt; 1102 1103 struct amdgpu_reset_control *reset_cntl; 1104 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1105 1106 bool ram_is_direct_mapped; 1107 1108 struct list_head ras_list; 1109 1110 struct amdgpu_reset_domain *reset_domain; 1111 1112 #ifdef CONFIG_DEV_COREDUMP 1113 struct amdgpu_coredump_info *coredump; 1114 struct work_struct coredump_work; 1115 #endif 1116 1117 struct mutex benchmark_mutex; 1118 1119 bool scpm_enabled; 1120 uint32_t scpm_status; 1121 1122 struct work_struct reset_work; 1123 1124 bool dc_enabled; 1125 /* Mask of active clusters */ 1126 uint32_t aid_mask; 1127 1128 /* Debug */ 1129 bool debug_vm; 1130 bool debug_largebar; 1131 bool debug_disable_soft_recovery; 1132 bool debug_use_vram_fw_buf; 1133 bool debug_enable_ras_aca; 1134 bool debug_exp_resets; 1135 bool debug_disable_gpu_ring_reset; 1136 bool debug_vm_userptr; 1137 bool debug_disable_ce_logs; 1138 bool debug_enable_ce_cs; 1139 1140 /* Protection for the following isolation structure */ 1141 struct mutex enforce_isolation_mutex; 1142 enum amdgpu_enforce_isolation_mode enforce_isolation[MAX_XCP]; 1143 struct amdgpu_isolation { 1144 void *owner; 1145 struct dma_fence *spearhead; 1146 struct amdgpu_sync active; 1147 struct amdgpu_sync prev; 1148 } isolation[MAX_XCP]; 1149 1150 struct amdgpu_init_level *init_lvl; 1151 1152 /* This flag is used to determine how VRAM allocations are handled for APUs 1153 * in KFD: VRAM or GTT. 1154 */ 1155 bool apu_prefer_gtt; 1156 1157 bool userq_halt_for_enforce_isolation; 1158 struct amdgpu_uid *uid_info; 1159 1160 struct amdgpu_uma_carveout_info uma_info; 1161 1162 /* KFD 1163 * Must be last --ends in a flexible-array member. 1164 */ 1165 struct amdgpu_kfd_dev kfd; 1166 }; 1167 1168 /* 1169 * MES FW uses address(mqd_addr + sizeof(struct mqd) + 3*sizeof(uint32_t)) 1170 * as fence address and writes a 32 bit fence value to this address. 1171 * Driver needs to allocate at least 4 DWs extra memory in addition to 1172 * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE for safety. 1173 */ 1174 #define AMDGPU_MQD_SIZE_ALIGN(mqd_size) AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32)) 1175 1176 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, 1177 uint8_t ip, uint8_t inst) 1178 { 1179 /* This considers only major/minor/rev and ignores 1180 * subrevision/variant fields. 1181 */ 1182 return adev->ip_versions[ip][inst] & ~0xFFU; 1183 } 1184 1185 static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev, 1186 uint8_t ip, uint8_t inst) 1187 { 1188 /* This returns full version - major/minor/rev/variant/subrevision */ 1189 return adev->ip_versions[ip][inst]; 1190 } 1191 1192 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1193 { 1194 return container_of(ddev, struct amdgpu_device, ddev); 1195 } 1196 1197 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1198 { 1199 return &adev->ddev; 1200 } 1201 1202 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1203 { 1204 return container_of(bdev, struct amdgpu_device, mman.bdev); 1205 } 1206 1207 static inline bool amdgpu_is_multi_aid(struct amdgpu_device *adev) 1208 { 1209 return !!adev->aid_mask; 1210 } 1211 1212 int amdgpu_device_init(struct amdgpu_device *adev, 1213 uint32_t flags); 1214 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1215 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1216 1217 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1218 1219 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1220 void *buf, size_t size, bool write); 1221 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1222 void *buf, size_t size, bool write); 1223 1224 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1225 void *buf, size_t size, bool write); 1226 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev); 1227 bool amdgpu_device_asic_has_dc_support(struct pci_dev *pdev, 1228 enum amd_asic_type asic_type); 1229 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1230 1231 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev); 1232 1233 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1234 struct amdgpu_reset_context *reset_context); 1235 1236 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1237 struct amdgpu_reset_context *reset_context); 1238 1239 int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context); 1240 1241 int emu_soc_asic_init(struct amdgpu_device *adev); 1242 1243 /* 1244 * Registers read & write functions. 1245 */ 1246 #define AMDGPU_REGS_NO_KIQ (1<<1) 1247 #define AMDGPU_REGS_RLC (1<<2) 1248 1249 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1250 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1251 1252 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0) 1253 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0) 1254 1255 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1256 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1257 1258 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1259 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1260 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1261 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1262 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1263 #define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst) 1264 #define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst) 1265 #define RREG32_PCIE(reg) amdgpu_reg_pcie_rd32(adev, (reg)) 1266 #define WREG32_PCIE(reg, v) amdgpu_reg_pcie_wr32(adev, (reg), (v)) 1267 #define RREG32_PCIE_PORT(reg) amdgpu_reg_pciep_rd32(adev, (reg)) 1268 #define WREG32_PCIE_PORT(reg, v) amdgpu_reg_pciep_wr32(adev, (reg), (v)) 1269 #define RREG32_PCIE_EXT(reg) amdgpu_reg_pcie_ext_rd32(adev, (reg)) 1270 #define WREG32_PCIE_EXT(reg, v) amdgpu_reg_pcie_ext_wr32(adev, (reg), (v)) 1271 #define RREG64_PCIE(reg) amdgpu_reg_pcie_rd64(adev, (reg)) 1272 #define WREG64_PCIE(reg, v) amdgpu_reg_pcie_wr64(adev, (reg), (v)) 1273 #define RREG64_PCIE_EXT(reg) amdgpu_reg_pcie_ext_rd64(adev, (reg)) 1274 #define WREG64_PCIE_EXT(reg, v) amdgpu_reg_pcie_ext_wr64(adev, (reg), (v)) 1275 #define RREG32_SMC(reg) amdgpu_reg_smc_rd32(adev, (reg)) 1276 #define WREG32_SMC(reg, v) amdgpu_reg_smc_wr32(adev, (reg), (v)) 1277 #define RREG32_UVD_CTX(reg) amdgpu_reg_uvd_ctx_rd32(adev, (reg)) 1278 #define WREG32_UVD_CTX(reg, v) amdgpu_reg_uvd_ctx_wr32(adev, (reg), (v)) 1279 #define RREG32_DIDT(reg) amdgpu_reg_didt_rd32(adev, (reg)) 1280 #define WREG32_DIDT(reg, v) amdgpu_reg_didt_wr32(adev, (reg), (v)) 1281 #define RREG32_GC_CAC(reg) amdgpu_reg_gc_cac_rd32(adev, (reg)) 1282 #define WREG32_GC_CAC(reg, v) amdgpu_reg_gc_cac_wr32(adev, (reg), (v)) 1283 #define RREG32_SE_CAC(reg) amdgpu_reg_se_cac_rd32(adev, (reg)) 1284 #define WREG32_SE_CAC(reg, v) amdgpu_reg_se_cac_wr32(adev, (reg), (v)) 1285 #define RREG32_AUDIO_ENDPT(block, reg) \ 1286 amdgpu_reg_audio_endpt_rd32(adev, (block), (reg)) 1287 #define WREG32_AUDIO_ENDPT(block, reg, v) \ 1288 amdgpu_reg_audio_endpt_wr32(adev, (block), (reg), (v)) 1289 #define WREG32_P(reg, val, mask) \ 1290 do { \ 1291 uint32_t tmp_ = RREG32(reg); \ 1292 tmp_ &= (mask); \ 1293 tmp_ |= ((val) & ~(mask)); \ 1294 WREG32(reg, tmp_); \ 1295 } while (0) 1296 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1297 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1298 #define WREG32_PLL_P(reg, val, mask) \ 1299 do { \ 1300 uint32_t tmp_ = RREG32_PLL(reg); \ 1301 tmp_ &= (mask); \ 1302 tmp_ |= ((val) & ~(mask)); \ 1303 WREG32_PLL(reg, tmp_); \ 1304 } while (0) 1305 1306 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1307 do { \ 1308 u32 tmp = RREG32_SMC(_Reg); \ 1309 tmp &= (_Mask); \ 1310 tmp |= ((_Val) & ~(_Mask)); \ 1311 WREG32_SMC(_Reg, tmp); \ 1312 } while (0) 1313 1314 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1315 1316 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1317 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1318 1319 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1320 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1321 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1322 1323 #define REG_GET_FIELD(value, reg, field) \ 1324 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1325 1326 #define WREG32_FIELD(reg, field, val) \ 1327 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1328 1329 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1330 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1331 1332 #define AMDGPU_GET_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> (l)) 1333 /* 1334 * BIOS helpers. 1335 */ 1336 #define RBIOS8(i) (adev->bios[i]) 1337 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1338 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1339 1340 #include "amdgpu_reset.h" 1341 1342 /* 1343 * ASICs macro. 1344 */ 1345 #define amdgpu_asic_set_vga_state(adev, state) \ 1346 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0) 1347 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1348 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1349 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1350 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1351 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1352 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1353 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1354 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1355 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1356 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1357 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1358 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1359 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1360 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1361 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1362 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1363 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1364 #define amdgpu_asic_supports_baco(adev) \ 1365 ((adev)->asic_funcs->supports_baco ? (adev)->asic_funcs->supports_baco((adev)) : 0) 1366 #define amdgpu_asic_pre_asic_init(adev) \ 1367 { \ 1368 if ((adev)->asic_funcs && (adev)->asic_funcs->pre_asic_init) \ 1369 (adev)->asic_funcs->pre_asic_init((adev)); \ 1370 } 1371 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1372 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1373 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1374 1375 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)) 1376 1377 #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i)) 1378 #define for_each_inst(i, inst_mask) \ 1379 for (i = ffs(inst_mask); i-- != 0; \ 1380 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1))) 1381 1382 /* Common functions */ 1383 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1384 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1385 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1386 struct amdgpu_job *job, 1387 struct amdgpu_reset_context *reset_context); 1388 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1389 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1390 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1391 bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev); 1392 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1393 1394 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1395 u64 num_vis_bytes); 1396 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1397 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1398 const u32 *registers, 1399 const u32 array_size); 1400 1401 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1402 int amdgpu_device_link_reset(struct amdgpu_device *adev); 1403 bool amdgpu_device_supports_atpx(struct amdgpu_device *adev); 1404 bool amdgpu_device_supports_px(struct amdgpu_device *adev); 1405 bool amdgpu_device_supports_boco(struct amdgpu_device *adev); 1406 bool amdgpu_device_supports_smart_shift(struct amdgpu_device *adev); 1407 int amdgpu_device_supports_baco(struct amdgpu_device *adev); 1408 void amdgpu_device_detect_runtime_pm_mode(struct amdgpu_device *adev); 1409 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1410 struct amdgpu_device *peer_adev); 1411 int amdgpu_device_baco_enter(struct amdgpu_device *adev); 1412 int amdgpu_device_baco_exit(struct amdgpu_device *adev); 1413 1414 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1415 struct amdgpu_ring *ring); 1416 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1417 struct amdgpu_ring *ring); 1418 1419 void amdgpu_device_halt(struct amdgpu_device *adev); 1420 struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev); 1421 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1422 struct dma_fence *gang); 1423 struct dma_fence *amdgpu_device_enforce_isolation(struct amdgpu_device *adev, 1424 struct amdgpu_ring *ring, 1425 struct amdgpu_job *job); 1426 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1427 ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring); 1428 ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset); 1429 void amdgpu_sdma_set_vm_pte_scheds(struct amdgpu_device *adev, 1430 const struct amdgpu_vm_pte_funcs *vm_pte_funcs); 1431 void amdgpu_sdma_set_buffer_funcs_scheds(struct amdgpu_device *adev, 1432 const struct amdgpu_buffer_funcs *buffer_funcs); 1433 1434 /* atpx handler */ 1435 #if defined(CONFIG_VGA_SWITCHEROO) 1436 void amdgpu_register_atpx_handler(void); 1437 void amdgpu_unregister_atpx_handler(void); 1438 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1439 bool amdgpu_is_atpx_hybrid(void); 1440 bool amdgpu_has_atpx(void); 1441 #else 1442 static inline void amdgpu_register_atpx_handler(void) {} 1443 static inline void amdgpu_unregister_atpx_handler(void) {} 1444 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1445 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1446 static inline bool amdgpu_has_atpx(void) { return false; } 1447 #endif 1448 1449 /* 1450 * KMS 1451 */ 1452 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1453 extern const int amdgpu_max_kms_ioctl; 1454 1455 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1456 void amdgpu_driver_unload_kms(struct drm_device *dev); 1457 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1458 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1459 struct drm_file *file_priv); 1460 void amdgpu_driver_release_kms(struct drm_device *dev); 1461 1462 int amdgpu_device_prepare(struct drm_device *dev); 1463 void amdgpu_device_complete(struct drm_device *dev); 1464 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1465 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1466 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1467 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1468 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1469 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1470 struct drm_file *filp); 1471 1472 /* 1473 * functions used by amdgpu_encoder.c 1474 */ 1475 struct amdgpu_afmt_acr { 1476 u32 clock; 1477 1478 int n_32khz; 1479 int cts_32khz; 1480 1481 int n_44_1khz; 1482 int cts_44_1khz; 1483 1484 int n_48khz; 1485 int cts_48khz; 1486 1487 }; 1488 1489 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1490 1491 /* amdgpu_acpi.c */ 1492 1493 struct amdgpu_numa_info { 1494 uint64_t size; 1495 int pxm; 1496 int nid; 1497 }; 1498 1499 /* ATCS Device/Driver State */ 1500 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1501 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1502 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1503 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1504 1505 #if defined(CONFIG_ACPI) 1506 int amdgpu_acpi_init(struct amdgpu_device *adev); 1507 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1508 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1509 bool amdgpu_acpi_is_power_shift_control_supported(void); 1510 bool amdgpu_acpi_is_set_uma_allocation_size_supported(void); 1511 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1512 u8 perf_req, bool advertise); 1513 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1514 u8 dev_state, bool drv_state); 1515 int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev, 1516 enum amdgpu_ss ss_state); 1517 int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type); 1518 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1519 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, 1520 u64 *tmr_size); 1521 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, 1522 struct amdgpu_numa_info *numa_info); 1523 1524 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1525 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1526 void amdgpu_acpi_detect(void); 1527 void amdgpu_acpi_release(void); 1528 #else 1529 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1530 static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, 1531 u64 *tmr_offset, u64 *tmr_size) 1532 { 1533 return -EINVAL; 1534 } 1535 static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, 1536 int xcc_id, 1537 struct amdgpu_numa_info *numa_info) 1538 { 1539 return -EINVAL; 1540 } 1541 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1542 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1543 static inline void amdgpu_acpi_detect(void) { } 1544 static inline void amdgpu_acpi_release(void) { } 1545 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1546 static inline bool amdgpu_acpi_is_set_uma_allocation_size_supported(void) { return false; } 1547 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1548 u8 dev_state, bool drv_state) { return 0; } 1549 static inline int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev, 1550 enum amdgpu_ss ss_state) 1551 { 1552 return 0; 1553 } 1554 static inline int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type) 1555 { 1556 return -EINVAL; 1557 } 1558 static inline void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps) { } 1559 #endif 1560 1561 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1562 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1563 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1564 #else 1565 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1566 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1567 #endif 1568 1569 #if defined(CONFIG_DRM_AMD_ISP) 1570 int amdgpu_acpi_get_isp4_dev(struct acpi_device **dev); 1571 #endif 1572 1573 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1574 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1575 1576 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1577 pci_channel_state_t state); 1578 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1579 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1580 void amdgpu_pci_resume(struct pci_dev *pdev); 1581 1582 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1583 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1584 1585 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1586 1587 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1588 enum amd_clockgating_state state); 1589 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1590 enum amd_powergating_state state); 1591 1592 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1593 { 1594 return amdgpu_gpu_recovery != 0 && 1595 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1596 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1597 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1598 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1599 } 1600 1601 #include "amdgpu_object.h" 1602 1603 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1604 { 1605 return adev->gmc.tmz_enabled; 1606 } 1607 1608 int amdgpu_in_reset(struct amdgpu_device *adev); 1609 1610 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 1611 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 1612 extern const struct attribute_group amdgpu_flash_attr_group; 1613 1614 void amdgpu_set_init_level(struct amdgpu_device *adev, 1615 enum amdgpu_init_lvl_id lvl); 1616 1617 static inline int amdgpu_device_bus_status_check(struct amdgpu_device *adev) 1618 { 1619 u32 status; 1620 int r; 1621 1622 r = pci_read_config_dword(adev->pdev, PCI_COMMAND, &status); 1623 if (r || PCI_POSSIBLE_ERROR(status)) { 1624 dev_err(adev->dev, "device lost from bus!"); 1625 return -ENODEV; 1626 } 1627 1628 return 0; 1629 } 1630 1631 void amdgpu_device_set_uid(struct amdgpu_uid *uid_info, 1632 enum amdgpu_uid_type type, uint8_t inst, 1633 uint64_t uid); 1634 uint64_t amdgpu_device_get_uid(struct amdgpu_uid *uid_info, 1635 enum amdgpu_uid_type type, uint8_t inst); 1636 #endif 1637