1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 54 #include <drm/ttm/ttm_bo.h> 55 #include <drm/ttm/ttm_placement.h> 56 57 #include <drm/amdgpu_drm.h> 58 #include <drm/drm_gem.h> 59 #include <drm/drm_ioctl.h> 60 61 #include <kgd_kfd_interface.h> 62 #include "dm_pp_interface.h" 63 #include "kgd_pp_interface.h" 64 65 #include "amd_shared.h" 66 #include "amdgpu_mode.h" 67 #include "amdgpu_ih.h" 68 #include "amdgpu_irq.h" 69 #include "amdgpu_ucode.h" 70 #include "amdgpu_ttm.h" 71 #include "amdgpu_psp.h" 72 #include "amdgpu_gds.h" 73 #include "amdgpu_sync.h" 74 #include "amdgpu_ring.h" 75 #include "amdgpu_vm.h" 76 #include "amdgpu_dpm.h" 77 #include "amdgpu_acp.h" 78 #include "amdgpu_uvd.h" 79 #include "amdgpu_vce.h" 80 #include "amdgpu_vcn.h" 81 #include "amdgpu_jpeg.h" 82 #include "amdgpu_vpe.h" 83 #include "amdgpu_umsch_mm.h" 84 #include "amdgpu_gmc.h" 85 #include "amdgpu_gfx.h" 86 #include "amdgpu_sdma.h" 87 #include "amdgpu_lsdma.h" 88 #include "amdgpu_nbio.h" 89 #include "amdgpu_hdp.h" 90 #include "amdgpu_dm.h" 91 #include "amdgpu_virt.h" 92 #include "amdgpu_csa.h" 93 #include "amdgpu_mes_ctx.h" 94 #include "amdgpu_gart.h" 95 #include "amdgpu_debugfs.h" 96 #include "amdgpu_job.h" 97 #include "amdgpu_bo_list.h" 98 #include "amdgpu_gem.h" 99 #include "amdgpu_doorbell.h" 100 #include "amdgpu_amdkfd.h" 101 #include "amdgpu_discovery.h" 102 #include "amdgpu_mes.h" 103 #include "amdgpu_umc.h" 104 #include "amdgpu_mmhub.h" 105 #include "amdgpu_gfxhub.h" 106 #include "amdgpu_df.h" 107 #include "amdgpu_smuio.h" 108 #include "amdgpu_fdinfo.h" 109 #include "amdgpu_mca.h" 110 #include "amdgpu_aca.h" 111 #include "amdgpu_ras.h" 112 #include "amdgpu_cper.h" 113 #include "amdgpu_xcp.h" 114 #include "amdgpu_seq64.h" 115 #include "amdgpu_reg_state.h" 116 #if defined(CONFIG_DRM_AMD_ISP) 117 #include "amdgpu_isp.h" 118 #endif 119 120 #define MAX_GPU_INSTANCE 64 121 122 #define GFX_SLICE_PERIOD_MS 250 123 124 struct amdgpu_gpu_instance { 125 struct amdgpu_device *adev; 126 int mgpu_fan_enabled; 127 }; 128 129 struct amdgpu_mgpu_info { 130 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 131 struct mutex mutex; 132 uint32_t num_gpu; 133 uint32_t num_dgpu; 134 uint32_t num_apu; 135 }; 136 137 enum amdgpu_ss { 138 AMDGPU_SS_DRV_LOAD, 139 AMDGPU_SS_DEV_D0, 140 AMDGPU_SS_DEV_D3, 141 AMDGPU_SS_DRV_UNLOAD 142 }; 143 144 struct amdgpu_hwip_reg_entry { 145 u32 hwip; 146 u32 inst; 147 u32 seg; 148 u32 reg_offset; 149 const char *reg_name; 150 }; 151 152 struct amdgpu_watchdog_timer { 153 bool timeout_fatal_disable; 154 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 155 }; 156 157 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 158 159 /* 160 * Modules parameters. 161 */ 162 extern int amdgpu_modeset; 163 extern unsigned int amdgpu_vram_limit; 164 extern int amdgpu_vis_vram_limit; 165 extern int amdgpu_gart_size; 166 extern int amdgpu_gtt_size; 167 extern int amdgpu_moverate; 168 extern int amdgpu_audio; 169 extern int amdgpu_disp_priority; 170 extern int amdgpu_hw_i2c; 171 extern int amdgpu_pcie_gen2; 172 extern int amdgpu_msi; 173 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 174 extern int amdgpu_dpm; 175 extern int amdgpu_fw_load_type; 176 extern int amdgpu_aspm; 177 extern int amdgpu_runtime_pm; 178 extern uint amdgpu_ip_block_mask; 179 extern int amdgpu_bapm; 180 extern int amdgpu_deep_color; 181 extern int amdgpu_vm_size; 182 extern int amdgpu_vm_block_size; 183 extern int amdgpu_vm_fragment_size; 184 extern int amdgpu_vm_fault_stop; 185 extern int amdgpu_vm_debug; 186 extern int amdgpu_vm_update_mode; 187 extern int amdgpu_exp_hw_support; 188 extern int amdgpu_dc; 189 extern int amdgpu_sched_jobs; 190 extern int amdgpu_sched_hw_submission; 191 extern uint amdgpu_pcie_gen_cap; 192 extern uint amdgpu_pcie_lane_cap; 193 extern u64 amdgpu_cg_mask; 194 extern uint amdgpu_pg_mask; 195 extern uint amdgpu_sdma_phase_quantum; 196 extern char *amdgpu_disable_cu; 197 extern char *amdgpu_virtual_display; 198 extern uint amdgpu_pp_feature_mask; 199 extern uint amdgpu_force_long_training; 200 extern int amdgpu_lbpw; 201 extern int amdgpu_compute_multipipe; 202 extern int amdgpu_gpu_recovery; 203 extern int amdgpu_emu_mode; 204 extern uint amdgpu_smu_memory_pool_size; 205 extern int amdgpu_smu_pptable_id; 206 extern uint amdgpu_dc_feature_mask; 207 extern uint amdgpu_freesync_vid_mode; 208 extern uint amdgpu_dc_debug_mask; 209 extern uint amdgpu_dc_visual_confirm; 210 extern int amdgpu_dm_abm_level; 211 extern int amdgpu_backlight; 212 extern int amdgpu_damage_clips; 213 extern struct amdgpu_mgpu_info mgpu_info; 214 extern int amdgpu_ras_enable; 215 extern uint amdgpu_ras_mask; 216 extern int amdgpu_bad_page_threshold; 217 extern bool amdgpu_ignore_bad_page_threshold; 218 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 219 extern int amdgpu_async_gfx_ring; 220 extern int amdgpu_mcbp; 221 extern int amdgpu_discovery; 222 extern int amdgpu_mes; 223 extern int amdgpu_mes_log_enable; 224 extern int amdgpu_mes_kiq; 225 extern int amdgpu_uni_mes; 226 extern int amdgpu_noretry; 227 extern int amdgpu_force_asic_type; 228 extern int amdgpu_smartshift_bias; 229 extern int amdgpu_use_xgmi_p2p; 230 extern int amdgpu_mtype_local; 231 extern bool enforce_isolation; 232 #ifdef CONFIG_HSA_AMD 233 extern int sched_policy; 234 extern bool debug_evictions; 235 extern bool no_system_mem_limit; 236 extern int halt_if_hws_hang; 237 extern uint amdgpu_svm_default_granularity; 238 #else 239 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 240 static const bool __maybe_unused debug_evictions; /* = false */ 241 static const bool __maybe_unused no_system_mem_limit; 242 static const int __maybe_unused halt_if_hws_hang; 243 #endif 244 #ifdef CONFIG_HSA_AMD_P2P 245 extern bool pcie_p2p; 246 #endif 247 248 extern int amdgpu_tmz; 249 extern int amdgpu_reset_method; 250 251 #ifdef CONFIG_DRM_AMDGPU_SI 252 extern int amdgpu_si_support; 253 #endif 254 #ifdef CONFIG_DRM_AMDGPU_CIK 255 extern int amdgpu_cik_support; 256 #endif 257 extern int amdgpu_num_kcq; 258 259 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 260 #define AMDGPU_UMSCHFW_LOG_SIZE (32 * 1024) 261 extern int amdgpu_vcnfw_log; 262 extern int amdgpu_sg_display; 263 extern int amdgpu_umsch_mm; 264 extern int amdgpu_seamless; 265 extern int amdgpu_umsch_mm_fwlog; 266 267 extern int amdgpu_user_partt_mode; 268 extern int amdgpu_agp; 269 extern int amdgpu_rebar; 270 271 extern int amdgpu_wbrf; 272 273 #define AMDGPU_VM_MAX_NUM_CTX 4096 274 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 275 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 276 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 277 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 278 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 279 #define AMDGPUFB_CONN_LIMIT 4 280 #define AMDGPU_BIOS_NUM_SCRATCH 16 281 282 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 283 284 /* hard reset data */ 285 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 286 287 /* reset flags */ 288 #define AMDGPU_RESET_GFX (1 << 0) 289 #define AMDGPU_RESET_COMPUTE (1 << 1) 290 #define AMDGPU_RESET_DMA (1 << 2) 291 #define AMDGPU_RESET_CP (1 << 3) 292 #define AMDGPU_RESET_GRBM (1 << 4) 293 #define AMDGPU_RESET_DMA1 (1 << 5) 294 #define AMDGPU_RESET_RLC (1 << 6) 295 #define AMDGPU_RESET_SEM (1 << 7) 296 #define AMDGPU_RESET_IH (1 << 8) 297 #define AMDGPU_RESET_VMC (1 << 9) 298 #define AMDGPU_RESET_MC (1 << 10) 299 #define AMDGPU_RESET_DISPLAY (1 << 11) 300 #define AMDGPU_RESET_UVD (1 << 12) 301 #define AMDGPU_RESET_VCE (1 << 13) 302 #define AMDGPU_RESET_VCE1 (1 << 14) 303 304 /* reset mask */ 305 #define AMDGPU_RESET_TYPE_FULL (1 << 0) /* full adapter reset, mode1/mode2/BACO/etc. */ 306 #define AMDGPU_RESET_TYPE_SOFT_RESET (1 << 1) /* IP level soft reset */ 307 #define AMDGPU_RESET_TYPE_PER_QUEUE (1 << 2) /* per queue */ 308 #define AMDGPU_RESET_TYPE_PER_PIPE (1 << 3) /* per pipe */ 309 310 /* max cursor sizes (in pixels) */ 311 #define CIK_CURSOR_WIDTH 128 312 #define CIK_CURSOR_HEIGHT 128 313 314 /* smart shift bias level limits */ 315 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 316 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 317 318 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */ 319 #define AMDGPU_SWCTF_EXTRA_DELAY 50 320 321 struct amdgpu_xcp_mgr; 322 struct amdgpu_device; 323 struct amdgpu_irq_src; 324 struct amdgpu_fpriv; 325 struct amdgpu_bo_va_mapping; 326 struct kfd_vm_fault_info; 327 struct amdgpu_hive_info; 328 struct amdgpu_reset_context; 329 struct amdgpu_reset_control; 330 331 enum amdgpu_cp_irq { 332 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 333 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 334 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 335 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 336 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 337 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 338 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 339 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 340 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 341 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 342 343 AMDGPU_CP_IRQ_LAST 344 }; 345 346 enum amdgpu_thermal_irq { 347 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 348 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 349 350 AMDGPU_THERMAL_IRQ_LAST 351 }; 352 353 enum amdgpu_kiq_irq { 354 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 355 AMDGPU_CP_KIQ_IRQ_LAST 356 }; 357 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 358 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 359 #define MAX_KIQ_REG_TRY 1000 360 361 int amdgpu_device_ip_set_clockgating_state(void *dev, 362 enum amd_ip_block_type block_type, 363 enum amd_clockgating_state state); 364 int amdgpu_device_ip_set_powergating_state(void *dev, 365 enum amd_ip_block_type block_type, 366 enum amd_powergating_state state); 367 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 368 u64 *flags); 369 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 370 enum amd_ip_block_type block_type); 371 bool amdgpu_device_ip_is_valid(struct amdgpu_device *adev, 372 enum amd_ip_block_type block_type); 373 int amdgpu_ip_block_suspend(struct amdgpu_ip_block *ip_block); 374 375 int amdgpu_ip_block_resume(struct amdgpu_ip_block *ip_block); 376 377 #define AMDGPU_MAX_IP_NUM 16 378 379 struct amdgpu_ip_block_status { 380 bool valid; 381 bool sw; 382 bool hw; 383 bool late_initialized; 384 bool hang; 385 }; 386 387 struct amdgpu_ip_block_version { 388 const enum amd_ip_block_type type; 389 const u32 major; 390 const u32 minor; 391 const u32 rev; 392 const struct amd_ip_funcs *funcs; 393 }; 394 395 struct amdgpu_ip_block { 396 struct amdgpu_ip_block_status status; 397 const struct amdgpu_ip_block_version *version; 398 struct amdgpu_device *adev; 399 }; 400 401 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 402 enum amd_ip_block_type type, 403 u32 major, u32 minor); 404 405 struct amdgpu_ip_block * 406 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 407 enum amd_ip_block_type type); 408 409 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 410 const struct amdgpu_ip_block_version *ip_block_version); 411 412 /* 413 * BIOS. 414 */ 415 bool amdgpu_get_bios(struct amdgpu_device *adev); 416 bool amdgpu_read_bios(struct amdgpu_device *adev); 417 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 418 u8 *bios, u32 length_bytes); 419 void amdgpu_bios_release(struct amdgpu_device *adev); 420 /* 421 * Clocks 422 */ 423 424 #define AMDGPU_MAX_PPLL 3 425 426 struct amdgpu_clock { 427 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 428 struct amdgpu_pll spll; 429 struct amdgpu_pll mpll; 430 /* 10 Khz units */ 431 uint32_t default_mclk; 432 uint32_t default_sclk; 433 uint32_t default_dispclk; 434 uint32_t current_dispclk; 435 uint32_t dp_extclk; 436 uint32_t max_pixel_clock; 437 }; 438 439 /* sub-allocation manager, it has to be protected by another lock. 440 * By conception this is an helper for other part of the driver 441 * like the indirect buffer or semaphore, which both have their 442 * locking. 443 * 444 * Principe is simple, we keep a list of sub allocation in offset 445 * order (first entry has offset == 0, last entry has the highest 446 * offset). 447 * 448 * When allocating new object we first check if there is room at 449 * the end total_size - (last_object_offset + last_object_size) >= 450 * alloc_size. If so we allocate new object there. 451 * 452 * When there is not enough room at the end, we start waiting for 453 * each sub object until we reach object_offset+object_size >= 454 * alloc_size, this object then become the sub object we return. 455 * 456 * Alignment can't be bigger than page size. 457 * 458 * Hole are not considered for allocation to keep things simple. 459 * Assumption is that there won't be hole (all object on same 460 * alignment). 461 */ 462 463 struct amdgpu_sa_manager { 464 struct drm_suballoc_manager base; 465 struct amdgpu_bo *bo; 466 uint64_t gpu_addr; 467 void *cpu_ptr; 468 }; 469 470 int amdgpu_fence_slab_init(void); 471 void amdgpu_fence_slab_fini(void); 472 473 /* 474 * IRQS. 475 */ 476 477 struct amdgpu_flip_work { 478 struct delayed_work flip_work; 479 struct work_struct unpin_work; 480 struct amdgpu_device *adev; 481 int crtc_id; 482 u32 target_vblank; 483 uint64_t base; 484 struct drm_pending_vblank_event *event; 485 struct amdgpu_bo *old_abo; 486 unsigned shared_count; 487 struct dma_fence **shared; 488 struct dma_fence_cb cb; 489 bool async; 490 }; 491 492 493 /* 494 * file private structure 495 */ 496 497 struct amdgpu_fpriv { 498 struct amdgpu_vm vm; 499 struct amdgpu_bo_va *prt_va; 500 struct amdgpu_bo_va *csa_va; 501 struct amdgpu_bo_va *seq64_va; 502 struct mutex bo_list_lock; 503 struct idr bo_list_handles; 504 struct amdgpu_ctx_mgr ctx_mgr; 505 /** GPU partition selection */ 506 uint32_t xcp_id; 507 }; 508 509 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 510 511 /* 512 * Writeback 513 */ 514 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 515 516 struct amdgpu_wb { 517 struct amdgpu_bo *wb_obj; 518 volatile uint32_t *wb; 519 uint64_t gpu_addr; 520 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 521 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 522 spinlock_t lock; 523 }; 524 525 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 526 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 527 528 /* 529 * Benchmarking 530 */ 531 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 532 533 /* 534 * ASIC specific register table accessible by UMD 535 */ 536 struct amdgpu_allowed_register_entry { 537 uint32_t reg_offset; 538 bool grbm_indexed; 539 }; 540 541 /** 542 * enum amd_reset_method - Methods for resetting AMD GPU devices 543 * 544 * @AMD_RESET_METHOD_NONE: The device will not be reset. 545 * @AMD_RESET_LEGACY: Method reserved for SI, CIK and VI ASICs. 546 * @AMD_RESET_MODE0: Reset the entire ASIC. Not currently available for the 547 * any device. 548 * @AMD_RESET_MODE1: Resets all IP blocks on the ASIC (SDMA, GFX, VCN, etc.) 549 * individually. Suitable only for some discrete GPU, not 550 * available for all ASICs. 551 * @AMD_RESET_MODE2: Resets a lesser level of IPs compared to MODE1. Which IPs 552 * are reset depends on the ASIC. Notably doesn't reset IPs 553 * shared with the CPU on APUs or the memory controllers (so 554 * VRAM is not lost). Not available on all ASICs. 555 * @AMD_RESET_LINK: Triggers SW-UP link reset on other GPUs 556 * @AMD_RESET_BACO: BACO (Bus Alive, Chip Off) method powers off and on the card 557 * but without powering off the PCI bus. Suitable only for 558 * discrete GPUs. 559 * @AMD_RESET_PCI: Does a full bus reset using core Linux subsystem PCI reset 560 * and does a secondary bus reset or FLR, depending on what the 561 * underlying hardware supports. 562 * 563 * Methods available for AMD GPU driver for resetting the device. Not all 564 * methods are suitable for every device. User can override the method using 565 * module parameter `reset_method`. 566 */ 567 enum amd_reset_method { 568 AMD_RESET_METHOD_NONE = -1, 569 AMD_RESET_METHOD_LEGACY = 0, 570 AMD_RESET_METHOD_MODE0, 571 AMD_RESET_METHOD_MODE1, 572 AMD_RESET_METHOD_MODE2, 573 AMD_RESET_METHOD_LINK, 574 AMD_RESET_METHOD_BACO, 575 AMD_RESET_METHOD_PCI, 576 AMD_RESET_METHOD_ON_INIT, 577 }; 578 579 struct amdgpu_video_codec_info { 580 u32 codec_type; 581 u32 max_width; 582 u32 max_height; 583 u32 max_pixels_per_frame; 584 u32 max_level; 585 }; 586 587 #define codec_info_build(type, width, height, level) \ 588 .codec_type = type,\ 589 .max_width = width,\ 590 .max_height = height,\ 591 .max_pixels_per_frame = height * width,\ 592 .max_level = level, 593 594 struct amdgpu_video_codecs { 595 const u32 codec_count; 596 const struct amdgpu_video_codec_info *codec_array; 597 }; 598 599 /* 600 * ASIC specific functions. 601 */ 602 struct amdgpu_asic_funcs { 603 bool (*read_disabled_bios)(struct amdgpu_device *adev); 604 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 605 u8 *bios, u32 length_bytes); 606 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 607 u32 sh_num, u32 reg_offset, u32 *value); 608 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 609 int (*reset)(struct amdgpu_device *adev); 610 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 611 /* get the reference clock */ 612 u32 (*get_xclk)(struct amdgpu_device *adev); 613 /* MM block clocks */ 614 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 615 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 616 /* static power management */ 617 int (*get_pcie_lanes)(struct amdgpu_device *adev); 618 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 619 /* get config memsize register */ 620 u32 (*get_config_memsize)(struct amdgpu_device *adev); 621 /* flush hdp write queue */ 622 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 623 /* invalidate hdp read cache */ 624 void (*invalidate_hdp)(struct amdgpu_device *adev, 625 struct amdgpu_ring *ring); 626 /* check if the asic needs a full reset of if soft reset will work */ 627 bool (*need_full_reset)(struct amdgpu_device *adev); 628 /* initialize doorbell layout for specific asic*/ 629 void (*init_doorbell_index)(struct amdgpu_device *adev); 630 /* PCIe bandwidth usage */ 631 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 632 uint64_t *count1); 633 /* do we need to reset the asic at init time (e.g., kexec) */ 634 bool (*need_reset_on_init)(struct amdgpu_device *adev); 635 /* PCIe replay counter */ 636 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 637 /* device supports BACO */ 638 int (*supports_baco)(struct amdgpu_device *adev); 639 /* pre asic_init quirks */ 640 void (*pre_asic_init)(struct amdgpu_device *adev); 641 /* enter/exit umd stable pstate */ 642 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 643 /* query video codecs */ 644 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 645 const struct amdgpu_video_codecs **codecs); 646 /* encode "> 32bits" smn addressing */ 647 u64 (*encode_ext_smn_addressing)(int ext_id); 648 649 ssize_t (*get_reg_state)(struct amdgpu_device *adev, 650 enum amdgpu_reg_state reg_state, void *buf, 651 size_t max_size); 652 }; 653 654 /* 655 * IOCTL. 656 */ 657 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 658 struct drm_file *filp); 659 660 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 661 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 662 struct drm_file *filp); 663 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 664 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 665 struct drm_file *filp); 666 667 /* VRAM scratch page for HDP bug, default vram page */ 668 struct amdgpu_mem_scratch { 669 struct amdgpu_bo *robj; 670 volatile uint32_t *ptr; 671 u64 gpu_addr; 672 }; 673 674 /* 675 * CGS 676 */ 677 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 678 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 679 680 /* 681 * Core structure, functions and helpers. 682 */ 683 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 684 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 685 686 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t); 687 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t); 688 689 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 690 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 691 692 typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device*, uint64_t); 693 typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device*, uint64_t, uint64_t); 694 695 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 696 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 697 698 struct amdgpu_mmio_remap { 699 u32 reg_offset; 700 resource_size_t bus_addr; 701 }; 702 703 /* Define the HW IP blocks will be used in driver , add more if necessary */ 704 enum amd_hw_ip_block_type { 705 GC_HWIP = 1, 706 HDP_HWIP, 707 SDMA0_HWIP, 708 SDMA1_HWIP, 709 SDMA2_HWIP, 710 SDMA3_HWIP, 711 SDMA4_HWIP, 712 SDMA5_HWIP, 713 SDMA6_HWIP, 714 SDMA7_HWIP, 715 LSDMA_HWIP, 716 MMHUB_HWIP, 717 ATHUB_HWIP, 718 NBIO_HWIP, 719 MP0_HWIP, 720 MP1_HWIP, 721 UVD_HWIP, 722 VCN_HWIP = UVD_HWIP, 723 JPEG_HWIP = VCN_HWIP, 724 VCN1_HWIP, 725 VCE_HWIP, 726 VPE_HWIP, 727 DF_HWIP, 728 DCE_HWIP, 729 OSSSYS_HWIP, 730 SMUIO_HWIP, 731 PWR_HWIP, 732 NBIF_HWIP, 733 THM_HWIP, 734 CLK_HWIP, 735 UMC_HWIP, 736 RSMU_HWIP, 737 XGMI_HWIP, 738 DCI_HWIP, 739 PCIE_HWIP, 740 ISP_HWIP, 741 MAX_HWIP 742 }; 743 744 #define HWIP_MAX_INSTANCE 44 745 746 #define HW_ID_MAX 300 747 #define IP_VERSION_FULL(mj, mn, rv, var, srev) \ 748 (((mj) << 24) | ((mn) << 16) | ((rv) << 8) | ((var) << 4) | (srev)) 749 #define IP_VERSION(mj, mn, rv) IP_VERSION_FULL(mj, mn, rv, 0, 0) 750 #define IP_VERSION_MAJ(ver) ((ver) >> 24) 751 #define IP_VERSION_MIN(ver) (((ver) >> 16) & 0xFF) 752 #define IP_VERSION_REV(ver) (((ver) >> 8) & 0xFF) 753 #define IP_VERSION_VARIANT(ver) (((ver) >> 4) & 0xF) 754 #define IP_VERSION_SUBREV(ver) ((ver) & 0xF) 755 #define IP_VERSION_MAJ_MIN_REV(ver) ((ver) >> 8) 756 757 struct amdgpu_ip_map_info { 758 /* Map of logical to actual dev instances/mask */ 759 uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE]; 760 int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev, 761 enum amd_hw_ip_block_type block, 762 int8_t inst); 763 uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev, 764 enum amd_hw_ip_block_type block, 765 uint32_t mask); 766 }; 767 768 struct amd_powerplay { 769 void *pp_handle; 770 const struct amd_pm_funcs *pp_funcs; 771 }; 772 773 struct ip_discovery_top; 774 775 /* polaris10 kickers */ 776 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 777 ((rid == 0xE3) || \ 778 (rid == 0xE4) || \ 779 (rid == 0xE5) || \ 780 (rid == 0xE7) || \ 781 (rid == 0xEF))) || \ 782 ((did == 0x6FDF) && \ 783 ((rid == 0xE7) || \ 784 (rid == 0xEF) || \ 785 (rid == 0xFF)))) 786 787 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 788 ((rid == 0xE1) || \ 789 (rid == 0xF7))) 790 791 /* polaris11 kickers */ 792 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 793 ((rid == 0xE0) || \ 794 (rid == 0xE5))) || \ 795 ((did == 0x67FF) && \ 796 ((rid == 0xCF) || \ 797 (rid == 0xEF) || \ 798 (rid == 0xFF)))) 799 800 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 801 ((rid == 0xE2))) 802 803 /* polaris12 kickers */ 804 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 805 ((rid == 0xC0) || \ 806 (rid == 0xC1) || \ 807 (rid == 0xC3) || \ 808 (rid == 0xC7))) || \ 809 ((did == 0x6981) && \ 810 ((rid == 0x00) || \ 811 (rid == 0x01) || \ 812 (rid == 0x10)))) 813 814 struct amdgpu_mqd_prop { 815 uint64_t mqd_gpu_addr; 816 uint64_t hqd_base_gpu_addr; 817 uint64_t rptr_gpu_addr; 818 uint64_t wptr_gpu_addr; 819 uint32_t queue_size; 820 bool use_doorbell; 821 uint32_t doorbell_index; 822 uint64_t eop_gpu_addr; 823 uint32_t hqd_pipe_priority; 824 uint32_t hqd_queue_priority; 825 bool allow_tunneling; 826 bool hqd_active; 827 }; 828 829 struct amdgpu_mqd { 830 unsigned mqd_size; 831 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 832 struct amdgpu_mqd_prop *p); 833 }; 834 835 struct amdgpu_pcie_reset_ctx { 836 bool in_link_reset; 837 bool occurs_dpc; 838 bool audio_suspended; 839 }; 840 841 /* 842 * Custom Init levels could be defined for different situations where a full 843 * initialization of all hardware blocks are not expected. Sample cases are 844 * custom init sequences after resume after S0i3/S3, reset on initialization, 845 * partial reset of blocks etc. Presently, this defines only two levels. Levels 846 * are described in corresponding struct definitions - amdgpu_init_default, 847 * amdgpu_init_minimal_xgmi. 848 */ 849 enum amdgpu_init_lvl_id { 850 AMDGPU_INIT_LEVEL_DEFAULT, 851 AMDGPU_INIT_LEVEL_MINIMAL_XGMI, 852 AMDGPU_INIT_LEVEL_RESET_RECOVERY, 853 }; 854 855 struct amdgpu_init_level { 856 enum amdgpu_init_lvl_id level; 857 uint32_t hwini_ip_block_mask; 858 }; 859 860 #define AMDGPU_RESET_MAGIC_NUM 64 861 #define AMDGPU_MAX_DF_PERFMONS 4 862 struct amdgpu_reset_domain; 863 struct amdgpu_fru_info; 864 865 /* 866 * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise. 867 */ 868 #define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size) 869 870 struct amdgpu_device { 871 struct device *dev; 872 struct pci_dev *pdev; 873 struct drm_device ddev; 874 875 #ifdef CONFIG_DRM_AMD_ACP 876 struct amdgpu_acp acp; 877 #endif 878 struct amdgpu_hive_info *hive; 879 struct amdgpu_xcp_mgr *xcp_mgr; 880 /* ASIC */ 881 enum amd_asic_type asic_type; 882 uint32_t family; 883 uint32_t rev_id; 884 uint32_t external_rev_id; 885 unsigned long flags; 886 unsigned long apu_flags; 887 int usec_timeout; 888 const struct amdgpu_asic_funcs *asic_funcs; 889 bool shutdown; 890 bool need_swiotlb; 891 bool accel_working; 892 struct notifier_block acpi_nb; 893 struct notifier_block pm_nb; 894 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 895 struct debugfs_blob_wrapper debugfs_vbios_blob; 896 struct debugfs_blob_wrapper debugfs_discovery_blob; 897 struct mutex srbm_mutex; 898 /* GRBM index mutex. Protects concurrent access to GRBM index */ 899 struct mutex grbm_idx_mutex; 900 struct dev_pm_domain vga_pm_domain; 901 bool have_disp_power_ref; 902 bool have_atomics_support; 903 904 /* BIOS */ 905 bool is_atom_fw; 906 uint8_t *bios; 907 uint32_t bios_size; 908 uint32_t bios_scratch_reg_offset; 909 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 910 911 /* Register/doorbell mmio */ 912 resource_size_t rmmio_base; 913 resource_size_t rmmio_size; 914 void __iomem *rmmio; 915 /* protects concurrent MM_INDEX/DATA based register access */ 916 spinlock_t mmio_idx_lock; 917 struct amdgpu_mmio_remap rmmio_remap; 918 /* protects concurrent SMC based register access */ 919 spinlock_t smc_idx_lock; 920 amdgpu_rreg_t smc_rreg; 921 amdgpu_wreg_t smc_wreg; 922 /* protects concurrent PCIE register access */ 923 spinlock_t pcie_idx_lock; 924 amdgpu_rreg_t pcie_rreg; 925 amdgpu_wreg_t pcie_wreg; 926 amdgpu_rreg_t pciep_rreg; 927 amdgpu_wreg_t pciep_wreg; 928 amdgpu_rreg_ext_t pcie_rreg_ext; 929 amdgpu_wreg_ext_t pcie_wreg_ext; 930 amdgpu_rreg64_t pcie_rreg64; 931 amdgpu_wreg64_t pcie_wreg64; 932 amdgpu_rreg64_ext_t pcie_rreg64_ext; 933 amdgpu_wreg64_ext_t pcie_wreg64_ext; 934 /* protects concurrent UVD register access */ 935 spinlock_t uvd_ctx_idx_lock; 936 amdgpu_rreg_t uvd_ctx_rreg; 937 amdgpu_wreg_t uvd_ctx_wreg; 938 /* protects concurrent DIDT register access */ 939 spinlock_t didt_idx_lock; 940 amdgpu_rreg_t didt_rreg; 941 amdgpu_wreg_t didt_wreg; 942 /* protects concurrent gc_cac register access */ 943 spinlock_t gc_cac_idx_lock; 944 amdgpu_rreg_t gc_cac_rreg; 945 amdgpu_wreg_t gc_cac_wreg; 946 /* protects concurrent se_cac register access */ 947 spinlock_t se_cac_idx_lock; 948 amdgpu_rreg_t se_cac_rreg; 949 amdgpu_wreg_t se_cac_wreg; 950 /* protects concurrent ENDPOINT (audio) register access */ 951 spinlock_t audio_endpt_idx_lock; 952 amdgpu_block_rreg_t audio_endpt_rreg; 953 amdgpu_block_wreg_t audio_endpt_wreg; 954 struct amdgpu_doorbell doorbell; 955 956 /* clock/pll info */ 957 struct amdgpu_clock clock; 958 959 /* MC */ 960 struct amdgpu_gmc gmc; 961 struct amdgpu_gart gart; 962 dma_addr_t dummy_page_addr; 963 struct amdgpu_vm_manager vm_manager; 964 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 965 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS); 966 967 /* memory management */ 968 struct amdgpu_mman mman; 969 struct amdgpu_mem_scratch mem_scratch; 970 struct amdgpu_wb wb; 971 atomic64_t num_bytes_moved; 972 atomic64_t num_evictions; 973 atomic64_t num_vram_cpu_page_faults; 974 atomic_t gpu_reset_counter; 975 atomic_t vram_lost_counter; 976 977 /* data for buffer migration throttling */ 978 struct { 979 spinlock_t lock; 980 s64 last_update_us; 981 s64 accum_us; /* accumulated microseconds */ 982 s64 accum_us_vis; /* for visible VRAM */ 983 u32 log2_max_MBps; 984 } mm_stats; 985 986 /* display */ 987 bool enable_virtual_display; 988 struct amdgpu_vkms_output *amdgpu_vkms_output; 989 struct amdgpu_mode_info mode_info; 990 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 991 struct delayed_work hotplug_work; 992 struct amdgpu_irq_src crtc_irq; 993 struct amdgpu_irq_src vline0_irq; 994 struct amdgpu_irq_src vupdate_irq; 995 struct amdgpu_irq_src pageflip_irq; 996 struct amdgpu_irq_src hpd_irq; 997 struct amdgpu_irq_src dmub_trace_irq; 998 struct amdgpu_irq_src dmub_outbox_irq; 999 1000 /* rings */ 1001 u64 fence_context; 1002 unsigned num_rings; 1003 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 1004 struct dma_fence __rcu *gang_submit; 1005 bool ib_pool_ready; 1006 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 1007 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 1008 1009 /* interrupts */ 1010 struct amdgpu_irq irq; 1011 1012 /* powerplay */ 1013 struct amd_powerplay powerplay; 1014 struct amdgpu_pm pm; 1015 u64 cg_flags; 1016 u32 pg_flags; 1017 1018 /* nbio */ 1019 struct amdgpu_nbio nbio; 1020 1021 /* hdp */ 1022 struct amdgpu_hdp hdp; 1023 1024 /* smuio */ 1025 struct amdgpu_smuio smuio; 1026 1027 /* mmhub */ 1028 struct amdgpu_mmhub mmhub; 1029 1030 /* gfxhub */ 1031 struct amdgpu_gfxhub gfxhub; 1032 1033 /* gfx */ 1034 struct amdgpu_gfx gfx; 1035 1036 /* sdma */ 1037 struct amdgpu_sdma sdma; 1038 1039 /* lsdma */ 1040 struct amdgpu_lsdma lsdma; 1041 1042 /* uvd */ 1043 struct amdgpu_uvd uvd; 1044 1045 /* vce */ 1046 struct amdgpu_vce vce; 1047 1048 /* vcn */ 1049 struct amdgpu_vcn vcn; 1050 1051 /* jpeg */ 1052 struct amdgpu_jpeg jpeg; 1053 1054 /* vpe */ 1055 struct amdgpu_vpe vpe; 1056 1057 /* umsch */ 1058 struct amdgpu_umsch_mm umsch_mm; 1059 bool enable_umsch_mm; 1060 1061 /* firmwares */ 1062 struct amdgpu_firmware firmware; 1063 1064 /* PSP */ 1065 struct psp_context psp; 1066 1067 /* GDS */ 1068 struct amdgpu_gds gds; 1069 1070 /* for userq and VM fences */ 1071 struct amdgpu_seq64 seq64; 1072 1073 /* KFD */ 1074 struct amdgpu_kfd_dev kfd; 1075 1076 /* UMC */ 1077 struct amdgpu_umc umc; 1078 1079 /* display related functionality */ 1080 struct amdgpu_display_manager dm; 1081 1082 #if defined(CONFIG_DRM_AMD_ISP) 1083 /* isp */ 1084 struct amdgpu_isp isp; 1085 #endif 1086 1087 /* mes */ 1088 bool enable_mes; 1089 bool enable_mes_kiq; 1090 bool enable_uni_mes; 1091 struct amdgpu_mes mes; 1092 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 1093 1094 /* df */ 1095 struct amdgpu_df df; 1096 1097 /* MCA */ 1098 struct amdgpu_mca mca; 1099 1100 /* ACA */ 1101 struct amdgpu_aca aca; 1102 1103 /* CPER */ 1104 struct amdgpu_cper cper; 1105 1106 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1107 uint32_t harvest_ip_mask; 1108 int num_ip_blocks; 1109 struct mutex mn_lock; 1110 DECLARE_HASHTABLE(mn_hash, 7); 1111 1112 /* tracking pinned memory */ 1113 atomic64_t vram_pin_size; 1114 atomic64_t visible_pin_size; 1115 atomic64_t gart_pin_size; 1116 1117 /* soc15 register offset based on ip, instance and segment */ 1118 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1119 struct amdgpu_ip_map_info ip_map; 1120 1121 /* delayed work_func for deferring clockgating during resume */ 1122 struct delayed_work delayed_init_work; 1123 1124 struct amdgpu_virt virt; 1125 1126 /* record hw reset is performed */ 1127 bool has_hw_reset; 1128 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1129 1130 /* s3/s4 mask */ 1131 bool in_suspend; 1132 bool in_s3; 1133 bool in_s4; 1134 bool in_s0ix; 1135 1136 enum pp_mp1_state mp1_state; 1137 struct amdgpu_doorbell_index doorbell_index; 1138 1139 struct mutex notifier_lock; 1140 1141 int asic_reset_res; 1142 struct work_struct xgmi_reset_work; 1143 struct list_head reset_list; 1144 1145 long gfx_timeout; 1146 long sdma_timeout; 1147 long video_timeout; 1148 long compute_timeout; 1149 long psp_timeout; 1150 1151 uint64_t unique_id; 1152 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1153 1154 /* enable runtime pm on the device */ 1155 bool in_runpm; 1156 bool has_pr3; 1157 1158 bool ucode_sysfs_en; 1159 1160 struct amdgpu_fru_info *fru_info; 1161 atomic_t throttling_logging_enabled; 1162 struct ratelimit_state throttling_logging_rs; 1163 uint32_t ras_hw_enabled; 1164 uint32_t ras_enabled; 1165 bool ras_default_ecc_enabled; 1166 1167 bool no_hw_access; 1168 struct pci_saved_state *pci_state; 1169 pci_channel_state_t pci_channel_state; 1170 1171 struct amdgpu_pcie_reset_ctx pcie_reset_ctx; 1172 1173 /* Track auto wait count on s_barrier settings */ 1174 bool barrier_has_auto_waitcnt; 1175 1176 struct amdgpu_reset_control *reset_cntl; 1177 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1178 1179 bool ram_is_direct_mapped; 1180 1181 struct list_head ras_list; 1182 1183 struct ip_discovery_top *ip_top; 1184 1185 struct amdgpu_reset_domain *reset_domain; 1186 1187 struct mutex benchmark_mutex; 1188 1189 bool scpm_enabled; 1190 uint32_t scpm_status; 1191 1192 struct work_struct reset_work; 1193 1194 bool dc_enabled; 1195 /* Mask of active clusters */ 1196 uint32_t aid_mask; 1197 1198 /* Debug */ 1199 bool debug_vm; 1200 bool debug_largebar; 1201 bool debug_disable_soft_recovery; 1202 bool debug_use_vram_fw_buf; 1203 bool debug_enable_ras_aca; 1204 bool debug_exp_resets; 1205 bool debug_disable_gpu_ring_reset; 1206 1207 /* Protection for the following isolation structure */ 1208 struct mutex enforce_isolation_mutex; 1209 bool enforce_isolation[MAX_XCP]; 1210 struct amdgpu_isolation { 1211 void *owner; 1212 struct dma_fence *spearhead; 1213 struct amdgpu_sync active; 1214 struct amdgpu_sync prev; 1215 } isolation[MAX_XCP]; 1216 1217 struct amdgpu_init_level *init_lvl; 1218 1219 /* This flag is used to determine how VRAM allocations are handled for APUs 1220 * in KFD: VRAM or GTT. 1221 */ 1222 bool apu_prefer_gtt; 1223 }; 1224 1225 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, 1226 uint8_t ip, uint8_t inst) 1227 { 1228 /* This considers only major/minor/rev and ignores 1229 * subrevision/variant fields. 1230 */ 1231 return adev->ip_versions[ip][inst] & ~0xFFU; 1232 } 1233 1234 static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev, 1235 uint8_t ip, uint8_t inst) 1236 { 1237 /* This returns full version - major/minor/rev/variant/subrevision */ 1238 return adev->ip_versions[ip][inst]; 1239 } 1240 1241 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1242 { 1243 return container_of(ddev, struct amdgpu_device, ddev); 1244 } 1245 1246 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1247 { 1248 return &adev->ddev; 1249 } 1250 1251 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1252 { 1253 return container_of(bdev, struct amdgpu_device, mman.bdev); 1254 } 1255 1256 int amdgpu_device_init(struct amdgpu_device *adev, 1257 uint32_t flags); 1258 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1259 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1260 1261 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1262 1263 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1264 void *buf, size_t size, bool write); 1265 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1266 void *buf, size_t size, bool write); 1267 1268 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1269 void *buf, size_t size, bool write); 1270 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, 1271 uint32_t inst, uint32_t reg_addr, char reg_name[], 1272 uint32_t expected_value, uint32_t mask); 1273 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1274 uint32_t reg, uint32_t acc_flags); 1275 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, 1276 u64 reg_addr); 1277 uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, 1278 uint32_t reg, uint32_t acc_flags, 1279 uint32_t xcc_id); 1280 void amdgpu_device_wreg(struct amdgpu_device *adev, 1281 uint32_t reg, uint32_t v, 1282 uint32_t acc_flags); 1283 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, 1284 u64 reg_addr, u32 reg_data); 1285 void amdgpu_device_xcc_wreg(struct amdgpu_device *adev, 1286 uint32_t reg, uint32_t v, 1287 uint32_t acc_flags, 1288 uint32_t xcc_id); 1289 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1290 uint32_t reg, uint32_t v, uint32_t xcc_id); 1291 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1292 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1293 1294 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1295 u32 reg_addr); 1296 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1297 u32 reg_addr); 1298 u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, 1299 u64 reg_addr); 1300 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1301 u32 reg_addr, u32 reg_data); 1302 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1303 u32 reg_addr, u64 reg_data); 1304 void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, 1305 u64 reg_addr, u64 reg_data); 1306 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev); 1307 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1308 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1309 1310 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev); 1311 1312 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1313 struct amdgpu_reset_context *reset_context); 1314 1315 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1316 struct amdgpu_reset_context *reset_context); 1317 1318 int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context); 1319 1320 int emu_soc_asic_init(struct amdgpu_device *adev); 1321 1322 /* 1323 * Registers read & write functions. 1324 */ 1325 #define AMDGPU_REGS_NO_KIQ (1<<1) 1326 #define AMDGPU_REGS_RLC (1<<2) 1327 1328 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1329 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1330 1331 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0) 1332 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0) 1333 1334 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1335 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1336 1337 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1338 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1339 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1340 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1341 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1342 #define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst) 1343 #define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst) 1344 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1345 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1346 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1347 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1348 #define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg)) 1349 #define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v)) 1350 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1351 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1352 #define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg)) 1353 #define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v)) 1354 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1355 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1356 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1357 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1358 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1359 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1360 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1361 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1362 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1363 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1364 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1365 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1366 #define WREG32_P(reg, val, mask) \ 1367 do { \ 1368 uint32_t tmp_ = RREG32(reg); \ 1369 tmp_ &= (mask); \ 1370 tmp_ |= ((val) & ~(mask)); \ 1371 WREG32(reg, tmp_); \ 1372 } while (0) 1373 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1374 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1375 #define WREG32_PLL_P(reg, val, mask) \ 1376 do { \ 1377 uint32_t tmp_ = RREG32_PLL(reg); \ 1378 tmp_ &= (mask); \ 1379 tmp_ |= ((val) & ~(mask)); \ 1380 WREG32_PLL(reg, tmp_); \ 1381 } while (0) 1382 1383 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1384 do { \ 1385 u32 tmp = RREG32_SMC(_Reg); \ 1386 tmp &= (_Mask); \ 1387 tmp |= ((_Val) & ~(_Mask)); \ 1388 WREG32_SMC(_Reg, tmp); \ 1389 } while (0) 1390 1391 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1392 1393 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1394 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1395 1396 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1397 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1398 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1399 1400 #define REG_GET_FIELD(value, reg, field) \ 1401 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1402 1403 #define WREG32_FIELD(reg, field, val) \ 1404 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1405 1406 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1407 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1408 1409 #define AMDGPU_GET_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> (l)) 1410 /* 1411 * BIOS helpers. 1412 */ 1413 #define RBIOS8(i) (adev->bios[i]) 1414 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1415 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1416 1417 /* 1418 * ASICs macro. 1419 */ 1420 #define amdgpu_asic_set_vga_state(adev, state) \ 1421 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0) 1422 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1423 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1424 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1425 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1426 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1427 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1428 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1429 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1430 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1431 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1432 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1433 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1434 #define amdgpu_asic_flush_hdp(adev, r) \ 1435 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1436 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1437 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \ 1438 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0)) 1439 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1440 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1441 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1442 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1443 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1444 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1445 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1446 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1447 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1448 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1449 1450 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)) 1451 1452 #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i)) 1453 #define for_each_inst(i, inst_mask) \ 1454 for (i = ffs(inst_mask); i-- != 0; \ 1455 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1))) 1456 1457 /* Common functions */ 1458 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1459 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1460 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1461 struct amdgpu_job *job, 1462 struct amdgpu_reset_context *reset_context); 1463 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1464 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1465 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1466 bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev); 1467 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1468 1469 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1470 u64 num_vis_bytes); 1471 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1472 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1473 const u32 *registers, 1474 const u32 array_size); 1475 1476 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1477 int amdgpu_device_link_reset(struct amdgpu_device *adev); 1478 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1479 bool amdgpu_device_supports_px(struct drm_device *dev); 1480 bool amdgpu_device_supports_boco(struct drm_device *dev); 1481 bool amdgpu_device_supports_smart_shift(struct drm_device *dev); 1482 int amdgpu_device_supports_baco(struct drm_device *dev); 1483 void amdgpu_device_detect_runtime_pm_mode(struct amdgpu_device *adev); 1484 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1485 struct amdgpu_device *peer_adev); 1486 int amdgpu_device_baco_enter(struct drm_device *dev); 1487 int amdgpu_device_baco_exit(struct drm_device *dev); 1488 1489 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1490 struct amdgpu_ring *ring); 1491 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1492 struct amdgpu_ring *ring); 1493 1494 void amdgpu_device_halt(struct amdgpu_device *adev); 1495 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, 1496 u32 reg); 1497 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, 1498 u32 reg, u32 v); 1499 struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev); 1500 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1501 struct dma_fence *gang); 1502 struct dma_fence *amdgpu_device_enforce_isolation(struct amdgpu_device *adev, 1503 struct amdgpu_ring *ring, 1504 struct amdgpu_job *job); 1505 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1506 ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring); 1507 ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset); 1508 1509 /* atpx handler */ 1510 #if defined(CONFIG_VGA_SWITCHEROO) 1511 void amdgpu_register_atpx_handler(void); 1512 void amdgpu_unregister_atpx_handler(void); 1513 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1514 bool amdgpu_is_atpx_hybrid(void); 1515 bool amdgpu_has_atpx(void); 1516 #else 1517 static inline void amdgpu_register_atpx_handler(void) {} 1518 static inline void amdgpu_unregister_atpx_handler(void) {} 1519 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1520 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1521 static inline bool amdgpu_has_atpx(void) { return false; } 1522 #endif 1523 1524 /* 1525 * KMS 1526 */ 1527 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1528 extern const int amdgpu_max_kms_ioctl; 1529 1530 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1531 void amdgpu_driver_unload_kms(struct drm_device *dev); 1532 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1533 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1534 struct drm_file *file_priv); 1535 void amdgpu_driver_release_kms(struct drm_device *dev); 1536 1537 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1538 int amdgpu_device_prepare(struct drm_device *dev); 1539 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1540 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1541 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1542 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1543 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1544 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1545 struct drm_file *filp); 1546 1547 /* 1548 * functions used by amdgpu_encoder.c 1549 */ 1550 struct amdgpu_afmt_acr { 1551 u32 clock; 1552 1553 int n_32khz; 1554 int cts_32khz; 1555 1556 int n_44_1khz; 1557 int cts_44_1khz; 1558 1559 int n_48khz; 1560 int cts_48khz; 1561 1562 }; 1563 1564 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1565 1566 /* amdgpu_acpi.c */ 1567 1568 struct amdgpu_numa_info { 1569 uint64_t size; 1570 int pxm; 1571 int nid; 1572 }; 1573 1574 /* ATCS Device/Driver State */ 1575 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1576 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1577 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1578 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1579 1580 #if defined(CONFIG_ACPI) 1581 int amdgpu_acpi_init(struct amdgpu_device *adev); 1582 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1583 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1584 bool amdgpu_acpi_is_power_shift_control_supported(void); 1585 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1586 u8 perf_req, bool advertise); 1587 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1588 u8 dev_state, bool drv_state); 1589 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state); 1590 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1591 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, 1592 u64 *tmr_size); 1593 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, 1594 struct amdgpu_numa_info *numa_info); 1595 1596 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1597 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1598 void amdgpu_acpi_detect(void); 1599 void amdgpu_acpi_release(void); 1600 #else 1601 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1602 static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, 1603 u64 *tmr_offset, u64 *tmr_size) 1604 { 1605 return -EINVAL; 1606 } 1607 static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, 1608 int xcc_id, 1609 struct amdgpu_numa_info *numa_info) 1610 { 1611 return -EINVAL; 1612 } 1613 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1614 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1615 static inline void amdgpu_acpi_detect(void) { } 1616 static inline void amdgpu_acpi_release(void) { } 1617 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1618 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1619 u8 dev_state, bool drv_state) { return 0; } 1620 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, 1621 enum amdgpu_ss ss_state) { return 0; } 1622 static inline void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps) { } 1623 #endif 1624 1625 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1626 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1627 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1628 void amdgpu_choose_low_power_state(struct amdgpu_device *adev); 1629 #else 1630 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1631 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1632 static inline void amdgpu_choose_low_power_state(struct amdgpu_device *adev) { } 1633 #endif 1634 1635 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1636 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1637 1638 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1639 pci_channel_state_t state); 1640 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1641 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1642 void amdgpu_pci_resume(struct pci_dev *pdev); 1643 1644 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1645 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1646 1647 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1648 1649 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1650 enum amd_clockgating_state state); 1651 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1652 enum amd_powergating_state state); 1653 1654 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1655 { 1656 return amdgpu_gpu_recovery != 0 && 1657 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1658 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1659 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1660 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1661 } 1662 1663 #include "amdgpu_object.h" 1664 1665 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1666 { 1667 return adev->gmc.tmz_enabled; 1668 } 1669 1670 int amdgpu_in_reset(struct amdgpu_device *adev); 1671 1672 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 1673 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 1674 extern const struct attribute_group amdgpu_flash_attr_group; 1675 1676 void amdgpu_set_init_level(struct amdgpu_device *adev, 1677 enum amdgpu_init_lvl_id lvl); 1678 #endif 1679