1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #include "amdgpu_ctx.h" 38 39 #include <linux/atomic.h> 40 #include <linux/wait.h> 41 #include <linux/list.h> 42 #include <linux/kref.h> 43 #include <linux/rbtree.h> 44 #include <linux/hashtable.h> 45 #include <linux/dma-fence.h> 46 #include <linux/pci.h> 47 48 #include <drm/ttm/ttm_bo.h> 49 #include <drm/ttm/ttm_placement.h> 50 51 #include <drm/amdgpu_drm.h> 52 #include <drm/drm_gem.h> 53 #include <drm/drm_ioctl.h> 54 55 #include <kgd_kfd_interface.h> 56 #include "dm_pp_interface.h" 57 #include "kgd_pp_interface.h" 58 59 #include "amd_shared.h" 60 #include "amdgpu_utils.h" 61 #include "amdgpu_mode.h" 62 #include "amdgpu_ih.h" 63 #include "amdgpu_irq.h" 64 #include "amdgpu_ucode.h" 65 #include "amdgpu_ttm.h" 66 #include "amdgpu_psp.h" 67 #include "amdgpu_gds.h" 68 #include "amdgpu_sync.h" 69 #include "amdgpu_ring.h" 70 #include "amdgpu_vm.h" 71 #include "amdgpu_dpm.h" 72 #include "amdgpu_acp.h" 73 #include "amdgpu_uvd.h" 74 #include "amdgpu_vce.h" 75 #include "amdgpu_vcn.h" 76 #include "amdgpu_jpeg.h" 77 #include "amdgpu_vpe.h" 78 #include "amdgpu_umsch_mm.h" 79 #include "amdgpu_gmc.h" 80 #include "amdgpu_gfx.h" 81 #include "amdgpu_sdma.h" 82 #include "amdgpu_lsdma.h" 83 #include "amdgpu_nbio.h" 84 #include "amdgpu_reg_access.h" 85 #include "amdgpu_hdp.h" 86 #include "amdgpu_dm.h" 87 #include "amdgpu_virt.h" 88 #include "amdgpu_csa.h" 89 #include "amdgpu_mes_ctx.h" 90 #include "amdgpu_gart.h" 91 #include "amdgpu_debugfs.h" 92 #include "amdgpu_job.h" 93 #include "amdgpu_bo_list.h" 94 #include "amdgpu_gem.h" 95 #include "amdgpu_doorbell.h" 96 #include "amdgpu_amdkfd.h" 97 #include "amdgpu_discovery.h" 98 #include "amdgpu_mes.h" 99 #include "amdgpu_umc.h" 100 #include "amdgpu_mmhub.h" 101 #include "amdgpu_gfxhub.h" 102 #include "amdgpu_df.h" 103 #include "amdgpu_smuio.h" 104 #include "amdgpu_fdinfo.h" 105 #include "amdgpu_mca.h" 106 #include "amdgpu_aca.h" 107 #include "amdgpu_ras.h" 108 #include "amdgpu_cper.h" 109 #include "amdgpu_xcp.h" 110 #include "amdgpu_seq64.h" 111 #include "amdgpu_reg_state.h" 112 #include "amdgpu_userq.h" 113 #include "amdgpu_eviction_fence.h" 114 #include "amdgpu_ip.h" 115 #if defined(CONFIG_DRM_AMD_ISP) 116 #include "amdgpu_isp.h" 117 #endif 118 119 #define MAX_GPU_INSTANCE 64 120 121 #define GFX_SLICE_PERIOD_MS 250 122 123 struct amdgpu_gpu_instance { 124 struct amdgpu_device *adev; 125 int mgpu_fan_enabled; 126 }; 127 128 struct amdgpu_mgpu_info { 129 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 130 struct mutex mutex; 131 uint32_t num_gpu; 132 uint32_t num_dgpu; 133 uint32_t num_apu; 134 }; 135 136 enum amdgpu_ss { 137 AMDGPU_SS_DRV_LOAD, 138 AMDGPU_SS_DEV_D0, 139 AMDGPU_SS_DEV_D3, 140 AMDGPU_SS_DRV_UNLOAD 141 }; 142 143 struct amdgpu_hwip_reg_entry { 144 u32 hwip; 145 u32 inst; 146 u32 seg; 147 u32 reg_offset; 148 const char *reg_name; 149 }; 150 151 struct amdgpu_watchdog_timer { 152 bool timeout_fatal_disable; 153 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 154 }; 155 156 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 157 158 /* 159 * Modules parameters. 160 */ 161 extern int amdgpu_modeset; 162 extern unsigned int amdgpu_vram_limit; 163 extern int amdgpu_vis_vram_limit; 164 extern int amdgpu_gart_size; 165 extern int amdgpu_gtt_size; 166 extern int amdgpu_moverate; 167 extern int amdgpu_audio; 168 extern int amdgpu_disp_priority; 169 extern int amdgpu_hw_i2c; 170 extern int amdgpu_pcie_gen2; 171 extern int amdgpu_msi; 172 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 173 extern int amdgpu_dpm; 174 extern int amdgpu_fw_load_type; 175 extern int amdgpu_aspm; 176 extern int amdgpu_runtime_pm; 177 extern uint amdgpu_ip_block_mask; 178 extern int amdgpu_bapm; 179 extern int amdgpu_deep_color; 180 extern int amdgpu_vm_size; 181 extern int amdgpu_vm_block_size; 182 extern int amdgpu_vm_fragment_size; 183 extern int amdgpu_vm_fault_stop; 184 extern int amdgpu_vm_debug; 185 extern int amdgpu_vm_update_mode; 186 extern int amdgpu_exp_hw_support; 187 extern int amdgpu_dc; 188 extern int amdgpu_sched_jobs; 189 extern int amdgpu_sched_hw_submission; 190 extern uint amdgpu_pcie_gen_cap; 191 extern uint amdgpu_pcie_lane_cap; 192 extern u64 amdgpu_cg_mask; 193 extern uint amdgpu_pg_mask; 194 extern uint amdgpu_sdma_phase_quantum; 195 extern char *amdgpu_disable_cu; 196 extern char *amdgpu_virtual_display; 197 extern uint amdgpu_pp_feature_mask; 198 extern uint amdgpu_force_long_training; 199 extern int amdgpu_lbpw; 200 extern int amdgpu_compute_multipipe; 201 extern int amdgpu_gpu_recovery; 202 extern int amdgpu_emu_mode; 203 extern uint amdgpu_smu_memory_pool_size; 204 extern int amdgpu_smu_pptable_id; 205 extern uint amdgpu_dc_feature_mask; 206 extern uint amdgpu_freesync_vid_mode; 207 extern uint amdgpu_dc_debug_mask; 208 extern uint amdgpu_dc_visual_confirm; 209 extern int amdgpu_dm_abm_level; 210 extern int amdgpu_backlight; 211 extern int amdgpu_damage_clips; 212 extern struct amdgpu_mgpu_info mgpu_info; 213 extern int amdgpu_ras_enable; 214 extern uint amdgpu_ras_mask; 215 extern int amdgpu_bad_page_threshold; 216 extern bool amdgpu_ignore_bad_page_threshold; 217 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 218 extern int amdgpu_async_gfx_ring; 219 extern int amdgpu_mcbp; 220 extern int amdgpu_discovery; 221 extern int amdgpu_mes_log_enable; 222 extern int amdgpu_uni_mes; 223 extern int amdgpu_noretry; 224 extern int amdgpu_force_asic_type; 225 extern int amdgpu_smartshift_bias; 226 extern int amdgpu_use_xgmi_p2p; 227 extern int amdgpu_mtype_local; 228 extern int amdgpu_enforce_isolation; 229 #ifdef CONFIG_HSA_AMD 230 extern int sched_policy; 231 extern bool debug_evictions; 232 extern bool no_system_mem_limit; 233 extern int halt_if_hws_hang; 234 extern uint amdgpu_svm_default_granularity; 235 #else 236 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 237 static const bool __maybe_unused debug_evictions; /* = false */ 238 static const bool __maybe_unused no_system_mem_limit; 239 static const int __maybe_unused halt_if_hws_hang; 240 #endif 241 #ifdef CONFIG_HSA_AMD_P2P 242 extern bool pcie_p2p; 243 #endif 244 245 extern int amdgpu_tmz; 246 extern int amdgpu_reset_method; 247 248 #ifdef CONFIG_DRM_AMDGPU_SI 249 extern int amdgpu_si_support; 250 #endif 251 #ifdef CONFIG_DRM_AMDGPU_CIK 252 extern int amdgpu_cik_support; 253 #endif 254 extern int amdgpu_num_kcq; 255 256 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 257 #define AMDGPU_UMSCHFW_LOG_SIZE (32 * 1024) 258 extern int amdgpu_vcnfw_log; 259 extern int amdgpu_sg_display; 260 extern int amdgpu_umsch_mm; 261 extern int amdgpu_seamless; 262 extern int amdgpu_umsch_mm_fwlog; 263 264 extern int amdgpu_user_partt_mode; 265 extern int amdgpu_agp; 266 extern int amdgpu_rebar; 267 268 extern int amdgpu_wbrf; 269 extern int amdgpu_user_queue; 270 extern int amdgpu_ptl; 271 272 extern uint amdgpu_hdmi_hpd_debounce_delay_ms; 273 274 #define AMDGPU_VM_MAX_NUM_CTX 4096 275 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 276 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 277 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 278 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 279 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 280 #define AMDGPUFB_CONN_LIMIT 4 281 #define AMDGPU_BIOS_NUM_SCRATCH 16 282 283 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 284 285 /* hard reset data */ 286 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 287 288 /* reset flags */ 289 #define AMDGPU_RESET_GFX (1 << 0) 290 #define AMDGPU_RESET_COMPUTE (1 << 1) 291 #define AMDGPU_RESET_DMA (1 << 2) 292 #define AMDGPU_RESET_CP (1 << 3) 293 #define AMDGPU_RESET_GRBM (1 << 4) 294 #define AMDGPU_RESET_DMA1 (1 << 5) 295 #define AMDGPU_RESET_RLC (1 << 6) 296 #define AMDGPU_RESET_SEM (1 << 7) 297 #define AMDGPU_RESET_IH (1 << 8) 298 #define AMDGPU_RESET_VMC (1 << 9) 299 #define AMDGPU_RESET_MC (1 << 10) 300 #define AMDGPU_RESET_DISPLAY (1 << 11) 301 #define AMDGPU_RESET_UVD (1 << 12) 302 #define AMDGPU_RESET_VCE (1 << 13) 303 #define AMDGPU_RESET_VCE1 (1 << 14) 304 305 /* reset mask */ 306 #define AMDGPU_RESET_TYPE_FULL (1 << 0) /* full adapter reset, mode1/mode2/BACO/etc. */ 307 #define AMDGPU_RESET_TYPE_SOFT_RESET (1 << 1) /* IP level soft reset */ 308 #define AMDGPU_RESET_TYPE_PER_QUEUE (1 << 2) /* per queue */ 309 #define AMDGPU_RESET_TYPE_PER_PIPE (1 << 3) /* per pipe */ 310 311 /* max cursor sizes (in pixels) */ 312 #define CIK_CURSOR_WIDTH 128 313 #define CIK_CURSOR_HEIGHT 128 314 315 /* smart shift bias level limits */ 316 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 317 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 318 319 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */ 320 #define AMDGPU_SWCTF_EXTRA_DELAY 50 321 322 struct amdgpu_xcp_mgr; 323 struct amdgpu_device; 324 struct amdgpu_irq_src; 325 struct amdgpu_fpriv; 326 struct amdgpu_bo_va_mapping; 327 struct kfd_vm_fault_info; 328 struct amdgpu_hive_info; 329 struct amdgpu_reset_context; 330 struct amdgpu_reset_control; 331 struct amdgpu_coredump_info; 332 333 enum amdgpu_cp_irq { 334 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 335 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 336 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 337 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 338 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 339 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 340 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 341 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 342 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 343 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 344 345 AMDGPU_CP_IRQ_LAST 346 }; 347 348 enum amdgpu_thermal_irq { 349 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 350 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 351 352 AMDGPU_THERMAL_IRQ_LAST 353 }; 354 355 enum amdgpu_kiq_irq { 356 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 357 AMDGPU_CP_KIQ_IRQ_LAST 358 }; 359 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 360 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 361 #define MAX_KIQ_REG_TRY 1000 362 363 /* 364 * BIOS. 365 */ 366 bool amdgpu_get_bios(struct amdgpu_device *adev); 367 bool amdgpu_read_bios(struct amdgpu_device *adev); 368 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 369 u8 *bios, u32 length_bytes); 370 void amdgpu_bios_release(struct amdgpu_device *adev); 371 /* 372 * Clocks 373 */ 374 375 #define AMDGPU_MAX_PPLL 3 376 377 struct amdgpu_clock { 378 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 379 struct amdgpu_pll spll; 380 struct amdgpu_pll mpll; 381 /* 10 Khz units */ 382 uint32_t default_mclk; 383 uint32_t default_sclk; 384 uint32_t default_dispclk; 385 uint32_t dp_extclk; 386 uint32_t max_pixel_clock; 387 }; 388 389 /* sub-allocation manager, it has to be protected by another lock. 390 * By conception this is an helper for other part of the driver 391 * like the indirect buffer or semaphore, which both have their 392 * locking. 393 * 394 * Principe is simple, we keep a list of sub allocation in offset 395 * order (first entry has offset == 0, last entry has the highest 396 * offset). 397 * 398 * When allocating new object we first check if there is room at 399 * the end total_size - (last_object_offset + last_object_size) >= 400 * alloc_size. If so we allocate new object there. 401 * 402 * When there is not enough room at the end, we start waiting for 403 * each sub object until we reach object_offset+object_size >= 404 * alloc_size, this object then become the sub object we return. 405 * 406 * Alignment can't be bigger than page size. 407 * 408 * Hole are not considered for allocation to keep things simple. 409 * Assumption is that there won't be hole (all object on same 410 * alignment). 411 */ 412 413 struct amdgpu_sa_manager { 414 struct drm_suballoc_manager base; 415 struct amdgpu_bo *bo; 416 uint64_t gpu_addr; 417 void *cpu_ptr; 418 }; 419 420 /* 421 * IRQS. 422 */ 423 424 struct amdgpu_flip_work { 425 struct delayed_work flip_work; 426 struct work_struct unpin_work; 427 struct amdgpu_device *adev; 428 int crtc_id; 429 u32 target_vblank; 430 uint64_t base; 431 struct drm_pending_vblank_event *event; 432 struct amdgpu_bo *old_abo; 433 unsigned shared_count; 434 struct dma_fence **shared; 435 struct dma_fence_cb cb; 436 bool async; 437 }; 438 439 /* 440 * file private structure 441 */ 442 443 struct amdgpu_fpriv { 444 struct amdgpu_vm vm; 445 struct amdgpu_bo_va *prt_va; 446 struct amdgpu_bo_va *csa_va; 447 struct amdgpu_bo_va *seq64_va; 448 struct mutex bo_list_lock; 449 struct idr bo_list_handles; 450 struct amdgpu_ctx_mgr ctx_mgr; 451 struct amdgpu_userq_mgr userq_mgr; 452 453 /* Eviction fence infra */ 454 struct amdgpu_eviction_fence_mgr evf_mgr; 455 456 /** GPU partition selection */ 457 uint32_t xcp_id; 458 }; 459 460 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 461 462 /* 463 * Writeback 464 */ 465 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 466 467 /** 468 * struct amdgpu_wb - This struct is used for small GPU memory allocation. 469 * 470 * This struct is used to allocate a small amount of GPU memory that can be 471 * used to shadow certain states into the memory. This is especially useful for 472 * providing easy CPU access to some states without requiring register access 473 * (e.g., if some block is power gated, reading register may be problematic). 474 * 475 * Note: the term writeback was initially used because many of the amdgpu 476 * components had some level of writeback memory, and this struct initially 477 * described those components. 478 */ 479 struct amdgpu_wb { 480 481 /** 482 * @wb_obj: 483 * 484 * Buffer Object used for the writeback memory. 485 */ 486 struct amdgpu_bo *wb_obj; 487 488 /** 489 * @wb: 490 * 491 * Pointer to the first writeback slot. In terms of CPU address 492 * this value can be accessed directly by using the offset as an index. 493 * For the GPU address, it is necessary to use gpu_addr and the offset. 494 */ 495 uint32_t *wb; 496 497 /** 498 * @gpu_addr: 499 * 500 * Writeback base address in the GPU. 501 */ 502 uint64_t gpu_addr; 503 504 /** 505 * @num_wb: 506 * 507 * Number of writeback slots reserved for amdgpu. 508 */ 509 u32 num_wb; 510 511 /** 512 * @used: 513 * 514 * Track the writeback slot already used. 515 */ 516 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 517 518 /** 519 * @lock: 520 * 521 * Protects read and write of the used field array. 522 */ 523 spinlock_t lock; 524 }; 525 526 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 527 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 528 529 /* 530 * Benchmarking 531 */ 532 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 533 534 /* 535 * ASIC specific register table accessible by UMD 536 */ 537 struct amdgpu_allowed_register_entry { 538 uint32_t reg_offset; 539 bool grbm_indexed; 540 }; 541 542 struct amdgpu_video_codec_info { 543 u32 codec_type; 544 u32 max_width; 545 u32 max_height; 546 u32 max_pixels_per_frame; 547 u32 max_level; 548 }; 549 550 #define codec_info_build(type, width, height, level) \ 551 .codec_type = type,\ 552 .max_width = width,\ 553 .max_height = height,\ 554 .max_pixels_per_frame = height * width,\ 555 .max_level = level, 556 557 struct amdgpu_video_codecs { 558 const u32 codec_count; 559 const struct amdgpu_video_codec_info *codec_array; 560 }; 561 562 /* 563 * ASIC specific functions. 564 */ 565 struct amdgpu_asic_funcs { 566 bool (*read_disabled_bios)(struct amdgpu_device *adev); 567 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 568 u8 *bios, u32 length_bytes); 569 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 570 u32 sh_num, u32 reg_offset, u32 *value); 571 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 572 int (*reset)(struct amdgpu_device *adev); 573 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 574 /* get the reference clock */ 575 u32 (*get_xclk)(struct amdgpu_device *adev); 576 /* MM block clocks */ 577 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 578 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 579 /* static power management */ 580 int (*get_pcie_lanes)(struct amdgpu_device *adev); 581 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 582 /* get config memsize register */ 583 u32 (*get_config_memsize)(struct amdgpu_device *adev); 584 /* flush hdp write queue */ 585 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 586 /* invalidate hdp read cache */ 587 void (*invalidate_hdp)(struct amdgpu_device *adev, 588 struct amdgpu_ring *ring); 589 /* check if the asic needs a full reset of if soft reset will work */ 590 bool (*need_full_reset)(struct amdgpu_device *adev); 591 /* initialize doorbell layout for specific asic*/ 592 void (*init_doorbell_index)(struct amdgpu_device *adev); 593 /* PCIe bandwidth usage */ 594 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 595 uint64_t *count1); 596 /* do we need to reset the asic at init time (e.g., kexec) */ 597 bool (*need_reset_on_init)(struct amdgpu_device *adev); 598 /* PCIe replay counter */ 599 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 600 /* device supports BACO */ 601 int (*supports_baco)(struct amdgpu_device *adev); 602 /* pre asic_init quirks */ 603 void (*pre_asic_init)(struct amdgpu_device *adev); 604 /* enter/exit umd stable pstate */ 605 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 606 /* query video codecs */ 607 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 608 const struct amdgpu_video_codecs **codecs); 609 /* encode "> 32bits" smn addressing */ 610 u64 (*encode_ext_smn_addressing)(int ext_id); 611 612 ssize_t (*get_reg_state)(struct amdgpu_device *adev, 613 enum amdgpu_reg_state reg_state, void *buf, 614 size_t max_size); 615 }; 616 617 /* 618 * IOCTL. 619 */ 620 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 621 struct drm_file *filp); 622 623 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 624 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 625 struct drm_file *filp); 626 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 627 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 628 struct drm_file *filp); 629 630 /* VRAM scratch page for HDP bug, default vram page */ 631 struct amdgpu_mem_scratch { 632 struct amdgpu_bo *robj; 633 uint32_t *ptr; 634 u64 gpu_addr; 635 }; 636 637 /* 638 * CGS 639 */ 640 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 641 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 642 643 /* 644 * Core structure, functions and helpers. 645 */ 646 struct amdgpu_mmio_remap { 647 u32 reg_offset; 648 resource_size_t bus_addr; 649 struct amdgpu_bo *bo; 650 }; 651 652 enum amdgpu_uid_type { 653 AMDGPU_UID_TYPE_XCD, 654 AMDGPU_UID_TYPE_AID, 655 AMDGPU_UID_TYPE_SOC, 656 AMDGPU_UID_TYPE_MID, 657 AMDGPU_UID_TYPE_MAX 658 }; 659 660 #define AMDGPU_UID_INST_MAX 8 /* max number of instances for each UID type */ 661 662 struct amdgpu_uid { 663 uint64_t uid[AMDGPU_UID_TYPE_MAX][AMDGPU_UID_INST_MAX]; 664 struct amdgpu_device *adev; 665 }; 666 667 #define MAX_UMA_OPTION_NAME 28 668 #define MAX_UMA_OPTION_ENTRIES 19 669 670 #define AMDGPU_UMA_FLAG_AUTO BIT(1) 671 #define AMDGPU_UMA_FLAG_CUSTOM BIT(0) 672 673 /** 674 * struct amdgpu_uma_carveout_option - single UMA carveout option 675 * @name: Name of the carveout option 676 * @memory_carved_mb: Amount of memory carved in MB 677 * @flags: ATCS flags supported by this option 678 */ 679 struct amdgpu_uma_carveout_option { 680 char name[MAX_UMA_OPTION_NAME]; 681 uint32_t memory_carved_mb; 682 uint8_t flags; 683 }; 684 685 /** 686 * struct amdgpu_uma_carveout_info - table of available UMA carveout options 687 * @num_entries: Number of available options 688 * @uma_option_index: The index of the option currently applied 689 * @update_lock: Lock to serialize changes to the option 690 * @entries: The array of carveout options 691 */ 692 struct amdgpu_uma_carveout_info { 693 uint8_t num_entries; 694 uint8_t uma_option_index; 695 struct mutex update_lock; 696 struct amdgpu_uma_carveout_option entries[MAX_UMA_OPTION_ENTRIES]; 697 }; 698 699 struct amd_powerplay { 700 void *pp_handle; 701 const struct amd_pm_funcs *pp_funcs; 702 }; 703 704 /* polaris10 kickers */ 705 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 706 ((rid == 0xE3) || \ 707 (rid == 0xE4) || \ 708 (rid == 0xE5) || \ 709 (rid == 0xE7) || \ 710 (rid == 0xEF))) || \ 711 ((did == 0x6FDF) && \ 712 ((rid == 0xE7) || \ 713 (rid == 0xEF) || \ 714 (rid == 0xFF)))) 715 716 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 717 ((rid == 0xE1) || \ 718 (rid == 0xF7))) 719 720 /* polaris11 kickers */ 721 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 722 ((rid == 0xE0) || \ 723 (rid == 0xE5))) || \ 724 ((did == 0x67FF) && \ 725 ((rid == 0xCF) || \ 726 (rid == 0xEF) || \ 727 (rid == 0xFF)))) 728 729 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 730 ((rid == 0xE2))) 731 732 /* polaris12 kickers */ 733 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 734 ((rid == 0xC0) || \ 735 (rid == 0xC1) || \ 736 (rid == 0xC3) || \ 737 (rid == 0xC7))) || \ 738 ((did == 0x6981) && \ 739 ((rid == 0x00) || \ 740 (rid == 0x01) || \ 741 (rid == 0x10)))) 742 743 enum amdgpu_mqd_update_flag { 744 AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE = 1, 745 AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE = 2, 746 AMDGPU_UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ 747 }; 748 749 struct amdgpu_mqd_prop { 750 uint64_t mqd_gpu_addr; 751 uint64_t hqd_base_gpu_addr; 752 uint64_t rptr_gpu_addr; 753 uint64_t wptr_gpu_addr; 754 uint32_t queue_size; 755 bool use_doorbell; 756 uint32_t doorbell_index; 757 uint64_t eop_gpu_addr; 758 uint32_t hqd_pipe_priority; 759 uint32_t hqd_queue_priority; 760 uint32_t mqd_stride_size; 761 bool allow_tunneling; 762 bool hqd_active; 763 uint64_t shadow_addr; 764 uint64_t gds_bkup_addr; 765 uint64_t csa_addr; 766 uint64_t fence_address; 767 bool tmz_queue; 768 bool kernel_queue; 769 uint32_t *cu_mask; 770 uint32_t cu_mask_count; 771 uint32_t cu_flags; 772 bool is_user_cu_masked; 773 }; 774 775 struct amdgpu_mqd { 776 unsigned mqd_size; 777 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 778 struct amdgpu_mqd_prop *p); 779 }; 780 781 struct amdgpu_pcie_reset_ctx { 782 bool in_link_reset; 783 bool occurs_dpc; 784 bool audio_suspended; 785 struct pci_dev *swus; 786 struct pci_saved_state *swus_pcistate; 787 struct pci_saved_state *swds_pcistate; 788 }; 789 790 /* 791 * Custom Init levels could be defined for different situations where a full 792 * initialization of all hardware blocks are not expected. Sample cases are 793 * custom init sequences after resume after S0i3/S3, reset on initialization, 794 * partial reset of blocks etc. Presently, this defines only two levels. Levels 795 * are described in corresponding struct definitions - amdgpu_init_default, 796 * amdgpu_init_minimal_xgmi. 797 */ 798 enum amdgpu_init_lvl_id { 799 AMDGPU_INIT_LEVEL_DEFAULT, 800 AMDGPU_INIT_LEVEL_MINIMAL_XGMI, 801 AMDGPU_INIT_LEVEL_RESET_RECOVERY, 802 }; 803 804 struct amdgpu_init_level { 805 enum amdgpu_init_lvl_id level; 806 uint32_t hwini_ip_block_mask; 807 }; 808 809 #define AMDGPU_RESET_MAGIC_NUM 64 810 #define AMDGPU_MAX_DF_PERFMONS 4 811 struct amdgpu_reset_domain; 812 struct amdgpu_fru_info; 813 814 enum amdgpu_enforce_isolation_mode { 815 AMDGPU_ENFORCE_ISOLATION_DISABLE = 0, 816 AMDGPU_ENFORCE_ISOLATION_ENABLE = 1, 817 AMDGPU_ENFORCE_ISOLATION_ENABLE_LEGACY = 2, 818 AMDGPU_ENFORCE_ISOLATION_NO_CLEANER_SHADER = 3, 819 }; 820 821 struct amdgpu_device { 822 struct device *dev; 823 struct pci_dev *pdev; 824 struct drm_device ddev; 825 826 #ifdef CONFIG_DRM_AMD_ACP 827 struct amdgpu_acp acp; 828 #endif 829 struct amdgpu_hive_info *hive; 830 struct amdgpu_xcp_mgr *xcp_mgr; 831 /* ASIC */ 832 enum amd_asic_type asic_type; 833 uint32_t family; 834 uint32_t rev_id; 835 uint32_t external_rev_id; 836 unsigned long flags; 837 unsigned long apu_flags; 838 int usec_timeout; 839 const struct amdgpu_asic_funcs *asic_funcs; 840 bool shutdown; 841 bool need_swiotlb; 842 bool accel_working; 843 struct notifier_block acpi_nb; 844 struct notifier_block pm_nb; 845 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 846 struct debugfs_blob_wrapper debugfs_vbios_blob; 847 struct mutex srbm_mutex; 848 /* GRBM index mutex. Protects concurrent access to GRBM index */ 849 struct mutex grbm_idx_mutex; 850 struct dev_pm_domain vga_pm_domain; 851 bool have_disp_power_ref; 852 bool have_atomics_support; 853 854 /* BIOS */ 855 bool is_atom_fw; 856 uint8_t *bios; 857 uint32_t bios_size; 858 uint32_t bios_scratch_reg_offset; 859 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 860 861 /* Register/doorbell mmio */ 862 resource_size_t rmmio_base; 863 resource_size_t rmmio_size; 864 void __iomem *rmmio; 865 /* protects concurrent MM_INDEX/DATA based register access */ 866 spinlock_t mmio_idx_lock; 867 struct amdgpu_mmio_remap rmmio_remap; 868 /* Indirect register access blocks */ 869 struct amdgpu_reg_access reg; 870 struct amdgpu_doorbell doorbell; 871 872 /* clock/pll info */ 873 struct amdgpu_clock clock; 874 875 /* MC */ 876 struct amdgpu_gmc gmc; 877 struct amdgpu_gart gart; 878 dma_addr_t dummy_page_addr; 879 struct amdgpu_vm_manager vm_manager; 880 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 881 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS); 882 883 /* memory management */ 884 struct amdgpu_mman mman; 885 struct amdgpu_mem_scratch mem_scratch; 886 struct amdgpu_wb wb; 887 atomic64_t num_bytes_moved; 888 atomic64_t num_evictions; 889 atomic64_t num_vram_cpu_page_faults; 890 atomic_t gpu_reset_counter; 891 atomic_t vram_lost_counter; 892 893 /* data for buffer migration throttling */ 894 struct { 895 spinlock_t lock; 896 s64 last_update_us; 897 s64 accum_us; /* accumulated microseconds */ 898 s64 accum_us_vis; /* for visible VRAM */ 899 u32 log2_max_MBps; 900 } mm_stats; 901 902 /* discovery*/ 903 struct amdgpu_discovery_info discovery; 904 905 /* display */ 906 bool enable_virtual_display; 907 struct amdgpu_vkms_output *amdgpu_vkms_output; 908 struct amdgpu_mode_info mode_info; 909 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 910 struct delayed_work hotplug_work; 911 struct amdgpu_irq_src crtc_irq; 912 struct amdgpu_irq_src vline0_irq; 913 struct amdgpu_irq_src vupdate_irq; 914 struct amdgpu_irq_src pageflip_irq; 915 struct amdgpu_irq_src hpd_irq; 916 struct amdgpu_irq_src dmub_trace_irq; 917 struct amdgpu_irq_src dmub_outbox_irq; 918 919 /* rings */ 920 u64 fence_context; 921 unsigned num_rings; 922 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 923 struct dma_fence __rcu *gang_submit; 924 bool ib_pool_ready; 925 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 926 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 927 928 /* interrupts */ 929 struct amdgpu_irq irq; 930 931 /* powerplay */ 932 struct amd_powerplay powerplay; 933 struct amdgpu_pm pm; 934 u64 cg_flags; 935 u32 pg_flags; 936 937 /* nbio */ 938 struct amdgpu_nbio nbio; 939 940 /* hdp */ 941 struct amdgpu_hdp hdp; 942 943 /* smuio */ 944 struct amdgpu_smuio smuio; 945 946 /* mmhub */ 947 struct amdgpu_mmhub mmhub; 948 949 /* gfxhub */ 950 struct amdgpu_gfxhub gfxhub; 951 952 /* gfx */ 953 struct amdgpu_gfx gfx; 954 955 /* sdma */ 956 struct amdgpu_sdma sdma; 957 958 /* lsdma */ 959 struct amdgpu_lsdma lsdma; 960 961 /* uvd */ 962 struct amdgpu_uvd uvd; 963 964 /* vce */ 965 struct amdgpu_vce vce; 966 967 /* vcn */ 968 struct amdgpu_vcn vcn; 969 970 /* jpeg */ 971 struct amdgpu_jpeg jpeg; 972 973 /* vpe */ 974 struct amdgpu_vpe vpe; 975 976 /* umsch */ 977 struct amdgpu_umsch_mm umsch_mm; 978 bool enable_umsch_mm; 979 980 /* firmwares */ 981 struct amdgpu_firmware firmware; 982 983 /* PSP */ 984 struct psp_context psp; 985 986 /* GDS */ 987 struct amdgpu_gds gds; 988 989 /* for userq and VM fences */ 990 struct amdgpu_seq64 seq64; 991 992 /* UMC */ 993 struct amdgpu_umc umc; 994 995 /* display related functionality */ 996 struct amdgpu_display_manager dm; 997 998 #if defined(CONFIG_DRM_AMD_ISP) 999 /* isp */ 1000 struct amdgpu_isp isp; 1001 #endif 1002 1003 /* mes */ 1004 bool enable_mes; 1005 bool enable_mes_kiq; 1006 bool enable_uni_mes; 1007 struct amdgpu_mes mes; 1008 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 1009 const struct amdgpu_userq_funcs *userq_funcs[AMDGPU_HW_IP_NUM]; 1010 1011 /** 1012 * @userq_doorbell_xa: Global user queue map (doorbell index → queue) 1013 * Key: doorbell_index (unique global identifier for the queue) 1014 * Value: struct amdgpu_usermode_queue 1015 */ 1016 struct xarray userq_doorbell_xa; 1017 1018 /* df */ 1019 struct amdgpu_df df; 1020 1021 /* MCA */ 1022 struct amdgpu_mca mca; 1023 1024 /* ACA */ 1025 struct amdgpu_aca aca; 1026 1027 /* CPER */ 1028 struct amdgpu_cper cper; 1029 1030 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1031 uint32_t harvest_ip_mask; 1032 int num_ip_blocks; 1033 struct mutex mn_lock; 1034 DECLARE_HASHTABLE(mn_hash, 7); 1035 1036 /* tracking pinned memory */ 1037 atomic64_t vram_pin_size; 1038 atomic64_t visible_pin_size; 1039 atomic64_t gart_pin_size; 1040 1041 /* soc15 register offset based on ip, instance and segment */ 1042 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1043 struct amdgpu_ip_map_info ip_map; 1044 1045 /* delayed work_func for deferring clockgating during resume */ 1046 struct delayed_work delayed_init_work; 1047 1048 struct amdgpu_virt virt; 1049 1050 /* record hw reset is performed */ 1051 bool has_hw_reset; 1052 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1053 1054 /* s3/s4 mask */ 1055 bool in_suspend; 1056 bool in_s3; 1057 bool in_s4; 1058 bool in_s0ix; 1059 suspend_state_t last_suspend_state; 1060 1061 enum pp_mp1_state mp1_state; 1062 struct amdgpu_doorbell_index doorbell_index; 1063 1064 struct mutex notifier_lock; 1065 1066 int asic_reset_res; 1067 struct work_struct xgmi_reset_work; 1068 struct list_head reset_list; 1069 1070 long gfx_timeout; 1071 long sdma_timeout; 1072 long video_timeout; 1073 long compute_timeout; 1074 long psp_timeout; 1075 1076 uint64_t unique_id; 1077 uint8_t unitid; 1078 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1079 1080 /* enable runtime pm on the device */ 1081 bool in_runpm; 1082 bool has_pr3; 1083 1084 bool ucode_sysfs_en; 1085 1086 struct amdgpu_fru_info *fru_info; 1087 atomic_t throttling_logging_enabled; 1088 struct ratelimit_state throttling_logging_rs; 1089 uint32_t ras_hw_enabled; 1090 uint32_t ras_enabled; 1091 bool ras_default_ecc_enabled; 1092 1093 bool no_hw_access; 1094 struct pci_saved_state *pci_state; 1095 pci_channel_state_t pci_channel_state; 1096 1097 struct amdgpu_pcie_reset_ctx pcie_reset_ctx; 1098 1099 /* Track auto wait count on s_barrier settings */ 1100 bool barrier_has_auto_waitcnt; 1101 1102 struct amdgpu_reset_control *reset_cntl; 1103 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1104 1105 bool ram_is_direct_mapped; 1106 1107 struct list_head ras_list; 1108 1109 struct amdgpu_reset_domain *reset_domain; 1110 1111 #ifdef CONFIG_DEV_COREDUMP 1112 struct amdgpu_coredump_info *coredump; 1113 struct work_struct coredump_work; 1114 #endif 1115 1116 struct mutex benchmark_mutex; 1117 1118 bool scpm_enabled; 1119 uint32_t scpm_status; 1120 1121 struct work_struct reset_work; 1122 1123 bool dc_enabled; 1124 /* Mask of active clusters */ 1125 uint32_t aid_mask; 1126 1127 /* Debug */ 1128 bool debug_vm; 1129 bool debug_largebar; 1130 bool debug_disable_soft_recovery; 1131 bool debug_use_vram_fw_buf; 1132 bool debug_enable_ras_aca; 1133 bool debug_exp_resets; 1134 bool debug_disable_gpu_ring_reset; 1135 bool debug_vm_userptr; 1136 bool debug_disable_ce_logs; 1137 bool debug_enable_ce_cs; 1138 1139 /* Protection for the following isolation structure */ 1140 struct mutex enforce_isolation_mutex; 1141 enum amdgpu_enforce_isolation_mode enforce_isolation[MAX_XCP]; 1142 struct amdgpu_isolation { 1143 void *owner; 1144 struct dma_fence *spearhead; 1145 struct amdgpu_sync active; 1146 struct amdgpu_sync prev; 1147 } isolation[MAX_XCP]; 1148 1149 struct amdgpu_init_level *init_lvl; 1150 1151 /* This flag is used to determine how VRAM allocations are handled for APUs 1152 * in KFD: VRAM or GTT. 1153 */ 1154 bool apu_prefer_gtt; 1155 1156 bool userq_halt_for_enforce_isolation; 1157 struct amdgpu_uid *uid_info; 1158 1159 struct amdgpu_uma_carveout_info uma_info; 1160 1161 /* KFD 1162 * Must be last --ends in a flexible-array member. 1163 */ 1164 struct amdgpu_kfd_dev kfd; 1165 }; 1166 1167 /* 1168 * MES FW uses address(mqd_addr + sizeof(struct mqd) + 3*sizeof(uint32_t)) 1169 * as fence address and writes a 32 bit fence value to this address. 1170 * Driver needs to allocate at least 4 DWs extra memory in addition to 1171 * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE for safety. 1172 */ 1173 #define AMDGPU_MQD_SIZE_ALIGN(mqd_size) AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32)) 1174 1175 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, 1176 uint8_t ip, uint8_t inst) 1177 { 1178 /* This considers only major/minor/rev and ignores 1179 * subrevision/variant fields. 1180 */ 1181 return adev->ip_versions[ip][inst] & ~0xFFU; 1182 } 1183 1184 static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev, 1185 uint8_t ip, uint8_t inst) 1186 { 1187 /* This returns full version - major/minor/rev/variant/subrevision */ 1188 return adev->ip_versions[ip][inst]; 1189 } 1190 1191 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1192 { 1193 return container_of(ddev, struct amdgpu_device, ddev); 1194 } 1195 1196 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1197 { 1198 return &adev->ddev; 1199 } 1200 1201 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1202 { 1203 return container_of(bdev, struct amdgpu_device, mman.bdev); 1204 } 1205 1206 static inline bool amdgpu_is_multi_aid(struct amdgpu_device *adev) 1207 { 1208 return !!adev->aid_mask; 1209 } 1210 1211 int amdgpu_device_init(struct amdgpu_device *adev, 1212 uint32_t flags); 1213 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1214 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1215 1216 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1217 1218 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1219 void *buf, size_t size, bool write); 1220 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1221 void *buf, size_t size, bool write); 1222 1223 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1224 void *buf, size_t size, bool write); 1225 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev); 1226 bool amdgpu_device_asic_has_dc_support(struct pci_dev *pdev, 1227 enum amd_asic_type asic_type); 1228 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1229 1230 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev); 1231 1232 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1233 struct amdgpu_reset_context *reset_context); 1234 1235 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1236 struct amdgpu_reset_context *reset_context); 1237 1238 int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context); 1239 1240 int emu_soc_asic_init(struct amdgpu_device *adev); 1241 1242 /* 1243 * Registers read & write functions. 1244 */ 1245 #define AMDGPU_REGS_NO_KIQ (1<<1) 1246 #define AMDGPU_REGS_RLC (1<<2) 1247 1248 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1249 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1250 1251 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0) 1252 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0) 1253 1254 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1255 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1256 1257 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1258 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1259 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1260 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1261 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1262 #define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst) 1263 #define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst) 1264 #define RREG32_PCIE(reg) amdgpu_reg_pcie_rd32(adev, (reg)) 1265 #define WREG32_PCIE(reg, v) amdgpu_reg_pcie_wr32(adev, (reg), (v)) 1266 #define RREG32_PCIE_PORT(reg) amdgpu_reg_pciep_rd32(adev, (reg)) 1267 #define WREG32_PCIE_PORT(reg, v) amdgpu_reg_pciep_wr32(adev, (reg), (v)) 1268 #define RREG32_PCIE_EXT(reg) amdgpu_reg_pcie_ext_rd32(adev, (reg)) 1269 #define WREG32_PCIE_EXT(reg, v) amdgpu_reg_pcie_ext_wr32(adev, (reg), (v)) 1270 #define RREG64_PCIE(reg) amdgpu_reg_pcie_rd64(adev, (reg)) 1271 #define WREG64_PCIE(reg, v) amdgpu_reg_pcie_wr64(adev, (reg), (v)) 1272 #define RREG64_PCIE_EXT(reg) amdgpu_reg_pcie_ext_rd64(adev, (reg)) 1273 #define WREG64_PCIE_EXT(reg, v) amdgpu_reg_pcie_ext_wr64(adev, (reg), (v)) 1274 #define RREG32_SMC(reg) amdgpu_reg_smc_rd32(adev, (reg)) 1275 #define WREG32_SMC(reg, v) amdgpu_reg_smc_wr32(adev, (reg), (v)) 1276 #define RREG32_UVD_CTX(reg) amdgpu_reg_uvd_ctx_rd32(adev, (reg)) 1277 #define WREG32_UVD_CTX(reg, v) amdgpu_reg_uvd_ctx_wr32(adev, (reg), (v)) 1278 #define RREG32_DIDT(reg) amdgpu_reg_didt_rd32(adev, (reg)) 1279 #define WREG32_DIDT(reg, v) amdgpu_reg_didt_wr32(adev, (reg), (v)) 1280 #define RREG32_GC_CAC(reg) amdgpu_reg_gc_cac_rd32(adev, (reg)) 1281 #define WREG32_GC_CAC(reg, v) amdgpu_reg_gc_cac_wr32(adev, (reg), (v)) 1282 #define RREG32_SE_CAC(reg) amdgpu_reg_se_cac_rd32(adev, (reg)) 1283 #define WREG32_SE_CAC(reg, v) amdgpu_reg_se_cac_wr32(adev, (reg), (v)) 1284 #define RREG32_AUDIO_ENDPT(block, reg) \ 1285 amdgpu_reg_audio_endpt_rd32(adev, (block), (reg)) 1286 #define WREG32_AUDIO_ENDPT(block, reg, v) \ 1287 amdgpu_reg_audio_endpt_wr32(adev, (block), (reg), (v)) 1288 #define WREG32_P(reg, val, mask) \ 1289 do { \ 1290 uint32_t tmp_ = RREG32(reg); \ 1291 tmp_ &= (mask); \ 1292 tmp_ |= ((val) & ~(mask)); \ 1293 WREG32(reg, tmp_); \ 1294 } while (0) 1295 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1296 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1297 #define WREG32_PLL_P(reg, val, mask) \ 1298 do { \ 1299 uint32_t tmp_ = RREG32_PLL(reg); \ 1300 tmp_ &= (mask); \ 1301 tmp_ |= ((val) & ~(mask)); \ 1302 WREG32_PLL(reg, tmp_); \ 1303 } while (0) 1304 1305 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1306 do { \ 1307 u32 tmp = RREG32_SMC(_Reg); \ 1308 tmp &= (_Mask); \ 1309 tmp |= ((_Val) & ~(_Mask)); \ 1310 WREG32_SMC(_Reg, tmp); \ 1311 } while (0) 1312 1313 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1314 1315 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1316 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1317 1318 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1319 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1320 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1321 1322 #define REG_GET_FIELD(value, reg, field) \ 1323 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1324 1325 #define WREG32_FIELD(reg, field, val) \ 1326 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1327 1328 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1329 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1330 1331 #define AMDGPU_GET_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> (l)) 1332 /* 1333 * BIOS helpers. 1334 */ 1335 #define RBIOS8(i) (adev->bios[i]) 1336 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1337 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1338 1339 #include "amdgpu_reset.h" 1340 1341 /* 1342 * ASICs macro. 1343 */ 1344 #define amdgpu_asic_set_vga_state(adev, state) \ 1345 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0) 1346 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1347 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1348 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1349 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1350 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1351 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1352 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1353 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1354 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1355 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1356 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1357 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1358 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1359 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1360 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1361 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1362 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1363 #define amdgpu_asic_supports_baco(adev) \ 1364 ((adev)->asic_funcs->supports_baco ? (adev)->asic_funcs->supports_baco((adev)) : 0) 1365 #define amdgpu_asic_pre_asic_init(adev) \ 1366 { \ 1367 if ((adev)->asic_funcs && (adev)->asic_funcs->pre_asic_init) \ 1368 (adev)->asic_funcs->pre_asic_init((adev)); \ 1369 } 1370 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1371 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1372 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1373 1374 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)) 1375 1376 #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i)) 1377 #define for_each_inst(i, inst_mask) \ 1378 for (i = ffs(inst_mask); i-- != 0; \ 1379 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1))) 1380 1381 /* Common functions */ 1382 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1383 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1384 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1385 struct amdgpu_job *job, 1386 struct amdgpu_reset_context *reset_context); 1387 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1388 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1389 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1390 bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev); 1391 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1392 1393 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1394 u64 num_vis_bytes); 1395 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1396 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1397 const u32 *registers, 1398 const u32 array_size); 1399 1400 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1401 int amdgpu_device_link_reset(struct amdgpu_device *adev); 1402 bool amdgpu_device_supports_atpx(struct amdgpu_device *adev); 1403 bool amdgpu_device_supports_px(struct amdgpu_device *adev); 1404 bool amdgpu_device_supports_boco(struct amdgpu_device *adev); 1405 bool amdgpu_device_supports_smart_shift(struct amdgpu_device *adev); 1406 int amdgpu_device_supports_baco(struct amdgpu_device *adev); 1407 void amdgpu_device_detect_runtime_pm_mode(struct amdgpu_device *adev); 1408 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1409 struct amdgpu_device *peer_adev); 1410 int amdgpu_device_baco_enter(struct amdgpu_device *adev); 1411 int amdgpu_device_baco_exit(struct amdgpu_device *adev); 1412 1413 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1414 struct amdgpu_ring *ring); 1415 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1416 struct amdgpu_ring *ring); 1417 1418 void amdgpu_device_halt(struct amdgpu_device *adev); 1419 struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev); 1420 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1421 struct dma_fence *gang); 1422 struct dma_fence *amdgpu_device_enforce_isolation(struct amdgpu_device *adev, 1423 struct amdgpu_ring *ring, 1424 struct amdgpu_job *job); 1425 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1426 ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring); 1427 ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset); 1428 void amdgpu_sdma_set_vm_pte_scheds(struct amdgpu_device *adev, 1429 const struct amdgpu_vm_pte_funcs *vm_pte_funcs); 1430 void amdgpu_sdma_set_buffer_funcs_scheds(struct amdgpu_device *adev, 1431 const struct amdgpu_buffer_funcs *buffer_funcs); 1432 1433 /* atpx handler */ 1434 #if defined(CONFIG_VGA_SWITCHEROO) 1435 void amdgpu_register_atpx_handler(void); 1436 void amdgpu_unregister_atpx_handler(void); 1437 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1438 bool amdgpu_is_atpx_hybrid(void); 1439 bool amdgpu_has_atpx(void); 1440 #else 1441 static inline void amdgpu_register_atpx_handler(void) {} 1442 static inline void amdgpu_unregister_atpx_handler(void) {} 1443 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1444 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1445 static inline bool amdgpu_has_atpx(void) { return false; } 1446 #endif 1447 1448 /* 1449 * KMS 1450 */ 1451 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1452 extern const int amdgpu_max_kms_ioctl; 1453 1454 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1455 void amdgpu_driver_unload_kms(struct drm_device *dev); 1456 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1457 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1458 struct drm_file *file_priv); 1459 void amdgpu_driver_release_kms(struct drm_device *dev); 1460 1461 int amdgpu_device_prepare(struct drm_device *dev); 1462 void amdgpu_device_complete(struct drm_device *dev); 1463 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1464 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1465 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1466 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1467 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1468 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1469 struct drm_file *filp); 1470 1471 /* 1472 * functions used by amdgpu_encoder.c 1473 */ 1474 struct amdgpu_afmt_acr { 1475 u32 clock; 1476 1477 int n_32khz; 1478 int cts_32khz; 1479 1480 int n_44_1khz; 1481 int cts_44_1khz; 1482 1483 int n_48khz; 1484 int cts_48khz; 1485 1486 }; 1487 1488 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1489 1490 /* amdgpu_acpi.c */ 1491 1492 struct amdgpu_numa_info { 1493 uint64_t size; 1494 int pxm; 1495 int nid; 1496 }; 1497 1498 /* ATCS Device/Driver State */ 1499 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1500 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1501 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1502 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1503 1504 #if defined(CONFIG_ACPI) 1505 int amdgpu_acpi_init(struct amdgpu_device *adev); 1506 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1507 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1508 bool amdgpu_acpi_is_power_shift_control_supported(void); 1509 bool amdgpu_acpi_is_set_uma_allocation_size_supported(void); 1510 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1511 u8 perf_req, bool advertise); 1512 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1513 u8 dev_state, bool drv_state); 1514 int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev, 1515 enum amdgpu_ss ss_state); 1516 int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type); 1517 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1518 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, 1519 u64 *tmr_size); 1520 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, 1521 struct amdgpu_numa_info *numa_info); 1522 1523 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1524 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1525 void amdgpu_acpi_detect(void); 1526 void amdgpu_acpi_release(void); 1527 #else 1528 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1529 static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, 1530 u64 *tmr_offset, u64 *tmr_size) 1531 { 1532 return -EINVAL; 1533 } 1534 static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, 1535 int xcc_id, 1536 struct amdgpu_numa_info *numa_info) 1537 { 1538 return -EINVAL; 1539 } 1540 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1541 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1542 static inline void amdgpu_acpi_detect(void) { } 1543 static inline void amdgpu_acpi_release(void) { } 1544 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1545 static inline bool amdgpu_acpi_is_set_uma_allocation_size_supported(void) { return false; } 1546 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1547 u8 dev_state, bool drv_state) { return 0; } 1548 static inline int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev, 1549 enum amdgpu_ss ss_state) 1550 { 1551 return 0; 1552 } 1553 static inline int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type) 1554 { 1555 return -EINVAL; 1556 } 1557 static inline void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps) { } 1558 #endif 1559 1560 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1561 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1562 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1563 #else 1564 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1565 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1566 #endif 1567 1568 #if defined(CONFIG_DRM_AMD_ISP) 1569 int amdgpu_acpi_get_isp4_dev(struct acpi_device **dev); 1570 #endif 1571 1572 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1573 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1574 1575 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1576 pci_channel_state_t state); 1577 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1578 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1579 void amdgpu_pci_resume(struct pci_dev *pdev); 1580 1581 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1582 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1583 1584 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1585 1586 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1587 enum amd_clockgating_state state); 1588 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1589 enum amd_powergating_state state); 1590 1591 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1592 { 1593 return amdgpu_gpu_recovery != 0 && 1594 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1595 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1596 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1597 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1598 } 1599 1600 #include "amdgpu_object.h" 1601 1602 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1603 { 1604 return adev->gmc.tmz_enabled; 1605 } 1606 1607 int amdgpu_in_reset(struct amdgpu_device *adev); 1608 1609 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 1610 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 1611 extern const struct attribute_group amdgpu_flash_attr_group; 1612 1613 void amdgpu_set_init_level(struct amdgpu_device *adev, 1614 enum amdgpu_init_lvl_id lvl); 1615 1616 static inline int amdgpu_device_bus_status_check(struct amdgpu_device *adev) 1617 { 1618 u32 status; 1619 int r; 1620 1621 r = pci_read_config_dword(adev->pdev, PCI_COMMAND, &status); 1622 if (r || PCI_POSSIBLE_ERROR(status)) { 1623 dev_err(adev->dev, "device lost from bus!"); 1624 return -ENODEV; 1625 } 1626 1627 return 0; 1628 } 1629 1630 void amdgpu_device_set_uid(struct amdgpu_uid *uid_info, 1631 enum amdgpu_uid_type type, uint8_t inst, 1632 uint64_t uid); 1633 uint64_t amdgpu_device_get_uid(struct amdgpu_uid *uid_info, 1634 enum amdgpu_uid_type type, uint8_t inst); 1635 #endif 1636