1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 #include <linux/aer.h> 54 55 #include <drm/ttm/ttm_bo_api.h> 56 #include <drm/ttm/ttm_bo_driver.h> 57 #include <drm/ttm/ttm_placement.h> 58 #include <drm/ttm/ttm_execbuf_util.h> 59 60 #include <drm/amdgpu_drm.h> 61 #include <drm/drm_gem.h> 62 #include <drm/drm_ioctl.h> 63 64 #include <kgd_kfd_interface.h> 65 #include "dm_pp_interface.h" 66 #include "kgd_pp_interface.h" 67 68 #include "amd_shared.h" 69 #include "amdgpu_mode.h" 70 #include "amdgpu_ih.h" 71 #include "amdgpu_irq.h" 72 #include "amdgpu_ucode.h" 73 #include "amdgpu_ttm.h" 74 #include "amdgpu_psp.h" 75 #include "amdgpu_gds.h" 76 #include "amdgpu_sync.h" 77 #include "amdgpu_ring.h" 78 #include "amdgpu_vm.h" 79 #include "amdgpu_dpm.h" 80 #include "amdgpu_acp.h" 81 #include "amdgpu_uvd.h" 82 #include "amdgpu_vce.h" 83 #include "amdgpu_vcn.h" 84 #include "amdgpu_jpeg.h" 85 #include "amdgpu_mn.h" 86 #include "amdgpu_gmc.h" 87 #include "amdgpu_gfx.h" 88 #include "amdgpu_sdma.h" 89 #include "amdgpu_nbio.h" 90 #include "amdgpu_hdp.h" 91 #include "amdgpu_dm.h" 92 #include "amdgpu_virt.h" 93 #include "amdgpu_csa.h" 94 #include "amdgpu_mes_ctx.h" 95 #include "amdgpu_gart.h" 96 #include "amdgpu_debugfs.h" 97 #include "amdgpu_job.h" 98 #include "amdgpu_bo_list.h" 99 #include "amdgpu_gem.h" 100 #include "amdgpu_doorbell.h" 101 #include "amdgpu_amdkfd.h" 102 #include "amdgpu_discovery.h" 103 #include "amdgpu_mes.h" 104 #include "amdgpu_umc.h" 105 #include "amdgpu_mmhub.h" 106 #include "amdgpu_gfxhub.h" 107 #include "amdgpu_df.h" 108 #include "amdgpu_smuio.h" 109 #include "amdgpu_fdinfo.h" 110 #include "amdgpu_mca.h" 111 #include "amdgpu_ras.h" 112 113 #define MAX_GPU_INSTANCE 16 114 115 struct amdgpu_gpu_instance 116 { 117 struct amdgpu_device *adev; 118 int mgpu_fan_enabled; 119 }; 120 121 struct amdgpu_mgpu_info 122 { 123 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 124 struct mutex mutex; 125 uint32_t num_gpu; 126 uint32_t num_dgpu; 127 uint32_t num_apu; 128 129 /* delayed reset_func for XGMI configuration if necessary */ 130 struct delayed_work delayed_reset_work; 131 bool pending_reset; 132 }; 133 134 enum amdgpu_ss { 135 AMDGPU_SS_DRV_LOAD, 136 AMDGPU_SS_DEV_D0, 137 AMDGPU_SS_DEV_D3, 138 AMDGPU_SS_DRV_UNLOAD 139 }; 140 141 struct amdgpu_watchdog_timer 142 { 143 bool timeout_fatal_disable; 144 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 145 }; 146 147 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 148 149 /* 150 * Modules parameters. 151 */ 152 extern int amdgpu_modeset; 153 extern int amdgpu_vram_limit; 154 extern int amdgpu_vis_vram_limit; 155 extern int amdgpu_gart_size; 156 extern int amdgpu_gtt_size; 157 extern int amdgpu_moverate; 158 extern int amdgpu_audio; 159 extern int amdgpu_disp_priority; 160 extern int amdgpu_hw_i2c; 161 extern int amdgpu_pcie_gen2; 162 extern int amdgpu_msi; 163 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 164 extern int amdgpu_dpm; 165 extern int amdgpu_fw_load_type; 166 extern int amdgpu_aspm; 167 extern int amdgpu_runtime_pm; 168 extern uint amdgpu_ip_block_mask; 169 extern int amdgpu_bapm; 170 extern int amdgpu_deep_color; 171 extern int amdgpu_vm_size; 172 extern int amdgpu_vm_block_size; 173 extern int amdgpu_vm_fragment_size; 174 extern int amdgpu_vm_fault_stop; 175 extern int amdgpu_vm_debug; 176 extern int amdgpu_vm_update_mode; 177 extern int amdgpu_exp_hw_support; 178 extern int amdgpu_dc; 179 extern int amdgpu_sched_jobs; 180 extern int amdgpu_sched_hw_submission; 181 extern uint amdgpu_pcie_gen_cap; 182 extern uint amdgpu_pcie_lane_cap; 183 extern u64 amdgpu_cg_mask; 184 extern uint amdgpu_pg_mask; 185 extern uint amdgpu_sdma_phase_quantum; 186 extern char *amdgpu_disable_cu; 187 extern char *amdgpu_virtual_display; 188 extern uint amdgpu_pp_feature_mask; 189 extern uint amdgpu_force_long_training; 190 extern int amdgpu_job_hang_limit; 191 extern int amdgpu_lbpw; 192 extern int amdgpu_compute_multipipe; 193 extern int amdgpu_gpu_recovery; 194 extern int amdgpu_emu_mode; 195 extern uint amdgpu_smu_memory_pool_size; 196 extern int amdgpu_smu_pptable_id; 197 extern uint amdgpu_dc_feature_mask; 198 extern uint amdgpu_dc_debug_mask; 199 extern uint amdgpu_dm_abm_level; 200 extern int amdgpu_backlight; 201 extern struct amdgpu_mgpu_info mgpu_info; 202 extern int amdgpu_ras_enable; 203 extern uint amdgpu_ras_mask; 204 extern int amdgpu_bad_page_threshold; 205 extern bool amdgpu_ignore_bad_page_threshold; 206 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 207 extern int amdgpu_async_gfx_ring; 208 extern int amdgpu_mcbp; 209 extern int amdgpu_discovery; 210 extern int amdgpu_mes; 211 extern int amdgpu_mes_kiq; 212 extern int amdgpu_noretry; 213 extern int amdgpu_force_asic_type; 214 extern int amdgpu_smartshift_bias; 215 extern int amdgpu_use_xgmi_p2p; 216 #ifdef CONFIG_HSA_AMD 217 extern int sched_policy; 218 extern bool debug_evictions; 219 extern bool no_system_mem_limit; 220 #else 221 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 222 static const bool __maybe_unused debug_evictions; /* = false */ 223 static const bool __maybe_unused no_system_mem_limit; 224 #endif 225 226 extern int amdgpu_tmz; 227 extern int amdgpu_reset_method; 228 229 #ifdef CONFIG_DRM_AMDGPU_SI 230 extern int amdgpu_si_support; 231 #endif 232 #ifdef CONFIG_DRM_AMDGPU_CIK 233 extern int amdgpu_cik_support; 234 #endif 235 extern int amdgpu_num_kcq; 236 237 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 238 extern int amdgpu_vcnfw_log; 239 240 #define AMDGPU_VM_MAX_NUM_CTX 4096 241 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 242 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 243 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 244 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 245 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 246 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 247 #define AMDGPUFB_CONN_LIMIT 4 248 #define AMDGPU_BIOS_NUM_SCRATCH 16 249 250 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 251 252 /* hard reset data */ 253 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 254 255 /* reset flags */ 256 #define AMDGPU_RESET_GFX (1 << 0) 257 #define AMDGPU_RESET_COMPUTE (1 << 1) 258 #define AMDGPU_RESET_DMA (1 << 2) 259 #define AMDGPU_RESET_CP (1 << 3) 260 #define AMDGPU_RESET_GRBM (1 << 4) 261 #define AMDGPU_RESET_DMA1 (1 << 5) 262 #define AMDGPU_RESET_RLC (1 << 6) 263 #define AMDGPU_RESET_SEM (1 << 7) 264 #define AMDGPU_RESET_IH (1 << 8) 265 #define AMDGPU_RESET_VMC (1 << 9) 266 #define AMDGPU_RESET_MC (1 << 10) 267 #define AMDGPU_RESET_DISPLAY (1 << 11) 268 #define AMDGPU_RESET_UVD (1 << 12) 269 #define AMDGPU_RESET_VCE (1 << 13) 270 #define AMDGPU_RESET_VCE1 (1 << 14) 271 272 /* max cursor sizes (in pixels) */ 273 #define CIK_CURSOR_WIDTH 128 274 #define CIK_CURSOR_HEIGHT 128 275 276 /* smasrt shift bias level limits */ 277 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 278 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 279 280 struct amdgpu_device; 281 struct amdgpu_irq_src; 282 struct amdgpu_fpriv; 283 struct amdgpu_bo_va_mapping; 284 struct kfd_vm_fault_info; 285 struct amdgpu_hive_info; 286 struct amdgpu_reset_context; 287 struct amdgpu_reset_control; 288 289 enum amdgpu_cp_irq { 290 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 291 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 292 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 293 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 294 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 295 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 296 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 297 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 298 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 299 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 300 301 AMDGPU_CP_IRQ_LAST 302 }; 303 304 enum amdgpu_thermal_irq { 305 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 306 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 307 308 AMDGPU_THERMAL_IRQ_LAST 309 }; 310 311 enum amdgpu_kiq_irq { 312 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 313 AMDGPU_CP_KIQ_IRQ_LAST 314 }; 315 316 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 317 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 318 #define MAX_KIQ_REG_TRY 1000 319 320 int amdgpu_device_ip_set_clockgating_state(void *dev, 321 enum amd_ip_block_type block_type, 322 enum amd_clockgating_state state); 323 int amdgpu_device_ip_set_powergating_state(void *dev, 324 enum amd_ip_block_type block_type, 325 enum amd_powergating_state state); 326 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 327 u64 *flags); 328 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 329 enum amd_ip_block_type block_type); 330 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 331 enum amd_ip_block_type block_type); 332 333 #define AMDGPU_MAX_IP_NUM 16 334 335 struct amdgpu_ip_block_status { 336 bool valid; 337 bool sw; 338 bool hw; 339 bool late_initialized; 340 bool hang; 341 }; 342 343 struct amdgpu_ip_block_version { 344 const enum amd_ip_block_type type; 345 const u32 major; 346 const u32 minor; 347 const u32 rev; 348 const struct amd_ip_funcs *funcs; 349 }; 350 351 #define HW_REV(_Major, _Minor, _Rev) \ 352 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 353 354 struct amdgpu_ip_block { 355 struct amdgpu_ip_block_status status; 356 const struct amdgpu_ip_block_version *version; 357 }; 358 359 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 360 enum amd_ip_block_type type, 361 u32 major, u32 minor); 362 363 struct amdgpu_ip_block * 364 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 365 enum amd_ip_block_type type); 366 367 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 368 const struct amdgpu_ip_block_version *ip_block_version); 369 370 /* 371 * BIOS. 372 */ 373 bool amdgpu_get_bios(struct amdgpu_device *adev); 374 bool amdgpu_read_bios(struct amdgpu_device *adev); 375 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 376 u8 *bios, u32 length_bytes); 377 /* 378 * Clocks 379 */ 380 381 #define AMDGPU_MAX_PPLL 3 382 383 struct amdgpu_clock { 384 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 385 struct amdgpu_pll spll; 386 struct amdgpu_pll mpll; 387 /* 10 Khz units */ 388 uint32_t default_mclk; 389 uint32_t default_sclk; 390 uint32_t default_dispclk; 391 uint32_t current_dispclk; 392 uint32_t dp_extclk; 393 uint32_t max_pixel_clock; 394 }; 395 396 /* sub-allocation manager, it has to be protected by another lock. 397 * By conception this is an helper for other part of the driver 398 * like the indirect buffer or semaphore, which both have their 399 * locking. 400 * 401 * Principe is simple, we keep a list of sub allocation in offset 402 * order (first entry has offset == 0, last entry has the highest 403 * offset). 404 * 405 * When allocating new object we first check if there is room at 406 * the end total_size - (last_object_offset + last_object_size) >= 407 * alloc_size. If so we allocate new object there. 408 * 409 * When there is not enough room at the end, we start waiting for 410 * each sub object until we reach object_offset+object_size >= 411 * alloc_size, this object then become the sub object we return. 412 * 413 * Alignment can't be bigger than page size. 414 * 415 * Hole are not considered for allocation to keep things simple. 416 * Assumption is that there won't be hole (all object on same 417 * alignment). 418 */ 419 420 #define AMDGPU_SA_NUM_FENCE_LISTS 32 421 422 struct amdgpu_sa_manager { 423 wait_queue_head_t wq; 424 struct amdgpu_bo *bo; 425 struct list_head *hole; 426 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 427 struct list_head olist; 428 unsigned size; 429 uint64_t gpu_addr; 430 void *cpu_ptr; 431 uint32_t domain; 432 uint32_t align; 433 }; 434 435 /* sub-allocation buffer */ 436 struct amdgpu_sa_bo { 437 struct list_head olist; 438 struct list_head flist; 439 struct amdgpu_sa_manager *manager; 440 unsigned soffset; 441 unsigned eoffset; 442 struct dma_fence *fence; 443 }; 444 445 int amdgpu_fence_slab_init(void); 446 void amdgpu_fence_slab_fini(void); 447 448 /* 449 * IRQS. 450 */ 451 452 struct amdgpu_flip_work { 453 struct delayed_work flip_work; 454 struct work_struct unpin_work; 455 struct amdgpu_device *adev; 456 int crtc_id; 457 u32 target_vblank; 458 uint64_t base; 459 struct drm_pending_vblank_event *event; 460 struct amdgpu_bo *old_abo; 461 unsigned shared_count; 462 struct dma_fence **shared; 463 struct dma_fence_cb cb; 464 bool async; 465 }; 466 467 468 /* 469 * file private structure 470 */ 471 472 struct amdgpu_fpriv { 473 struct amdgpu_vm vm; 474 struct amdgpu_bo_va *prt_va; 475 struct amdgpu_bo_va *csa_va; 476 struct mutex bo_list_lock; 477 struct idr bo_list_handles; 478 struct amdgpu_ctx_mgr ctx_mgr; 479 }; 480 481 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 482 483 /* 484 * Writeback 485 */ 486 #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */ 487 488 struct amdgpu_wb { 489 struct amdgpu_bo *wb_obj; 490 volatile uint32_t *wb; 491 uint64_t gpu_addr; 492 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 493 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 494 }; 495 496 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 497 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 498 499 /* 500 * Benchmarking 501 */ 502 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 503 504 /* 505 * ASIC specific register table accessible by UMD 506 */ 507 struct amdgpu_allowed_register_entry { 508 uint32_t reg_offset; 509 bool grbm_indexed; 510 }; 511 512 enum amd_reset_method { 513 AMD_RESET_METHOD_NONE = -1, 514 AMD_RESET_METHOD_LEGACY = 0, 515 AMD_RESET_METHOD_MODE0, 516 AMD_RESET_METHOD_MODE1, 517 AMD_RESET_METHOD_MODE2, 518 AMD_RESET_METHOD_BACO, 519 AMD_RESET_METHOD_PCI, 520 }; 521 522 struct amdgpu_video_codec_info { 523 u32 codec_type; 524 u32 max_width; 525 u32 max_height; 526 u32 max_pixels_per_frame; 527 u32 max_level; 528 }; 529 530 #define codec_info_build(type, width, height, level) \ 531 .codec_type = type,\ 532 .max_width = width,\ 533 .max_height = height,\ 534 .max_pixels_per_frame = height * width,\ 535 .max_level = level, 536 537 struct amdgpu_video_codecs { 538 const u32 codec_count; 539 const struct amdgpu_video_codec_info *codec_array; 540 }; 541 542 /* 543 * ASIC specific functions. 544 */ 545 struct amdgpu_asic_funcs { 546 bool (*read_disabled_bios)(struct amdgpu_device *adev); 547 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 548 u8 *bios, u32 length_bytes); 549 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 550 u32 sh_num, u32 reg_offset, u32 *value); 551 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 552 int (*reset)(struct amdgpu_device *adev); 553 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 554 /* get the reference clock */ 555 u32 (*get_xclk)(struct amdgpu_device *adev); 556 /* MM block clocks */ 557 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 558 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 559 /* static power management */ 560 int (*get_pcie_lanes)(struct amdgpu_device *adev); 561 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 562 /* get config memsize register */ 563 u32 (*get_config_memsize)(struct amdgpu_device *adev); 564 /* flush hdp write queue */ 565 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 566 /* invalidate hdp read cache */ 567 void (*invalidate_hdp)(struct amdgpu_device *adev, 568 struct amdgpu_ring *ring); 569 /* check if the asic needs a full reset of if soft reset will work */ 570 bool (*need_full_reset)(struct amdgpu_device *adev); 571 /* initialize doorbell layout for specific asic*/ 572 void (*init_doorbell_index)(struct amdgpu_device *adev); 573 /* PCIe bandwidth usage */ 574 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 575 uint64_t *count1); 576 /* do we need to reset the asic at init time (e.g., kexec) */ 577 bool (*need_reset_on_init)(struct amdgpu_device *adev); 578 /* PCIe replay counter */ 579 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 580 /* device supports BACO */ 581 bool (*supports_baco)(struct amdgpu_device *adev); 582 /* pre asic_init quirks */ 583 void (*pre_asic_init)(struct amdgpu_device *adev); 584 /* enter/exit umd stable pstate */ 585 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 586 /* query video codecs */ 587 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 588 const struct amdgpu_video_codecs **codecs); 589 }; 590 591 /* 592 * IOCTL. 593 */ 594 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 595 struct drm_file *filp); 596 597 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 598 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 599 struct drm_file *filp); 600 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 601 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 602 struct drm_file *filp); 603 604 /* VRAM scratch page for HDP bug, default vram page */ 605 struct amdgpu_vram_scratch { 606 struct amdgpu_bo *robj; 607 volatile uint32_t *ptr; 608 u64 gpu_addr; 609 }; 610 611 /* 612 * CGS 613 */ 614 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 615 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 616 617 /* 618 * Core structure, functions and helpers. 619 */ 620 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 621 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 622 623 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 624 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 625 626 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 627 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 628 629 struct amdgpu_mmio_remap { 630 u32 reg_offset; 631 resource_size_t bus_addr; 632 }; 633 634 /* Define the HW IP blocks will be used in driver , add more if necessary */ 635 enum amd_hw_ip_block_type { 636 GC_HWIP = 1, 637 HDP_HWIP, 638 SDMA0_HWIP, 639 SDMA1_HWIP, 640 SDMA2_HWIP, 641 SDMA3_HWIP, 642 SDMA4_HWIP, 643 SDMA5_HWIP, 644 SDMA6_HWIP, 645 SDMA7_HWIP, 646 MMHUB_HWIP, 647 ATHUB_HWIP, 648 NBIO_HWIP, 649 MP0_HWIP, 650 MP1_HWIP, 651 UVD_HWIP, 652 VCN_HWIP = UVD_HWIP, 653 JPEG_HWIP = VCN_HWIP, 654 VCN1_HWIP, 655 VCE_HWIP, 656 DF_HWIP, 657 DCE_HWIP, 658 OSSSYS_HWIP, 659 SMUIO_HWIP, 660 PWR_HWIP, 661 NBIF_HWIP, 662 THM_HWIP, 663 CLK_HWIP, 664 UMC_HWIP, 665 RSMU_HWIP, 666 XGMI_HWIP, 667 DCI_HWIP, 668 MAX_HWIP 669 }; 670 671 #define HWIP_MAX_INSTANCE 11 672 673 #define HW_ID_MAX 300 674 #define IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv)) 675 #define IP_VERSION_MAJ(ver) ((ver) >> 16) 676 #define IP_VERSION_MIN(ver) (((ver) >> 8) & 0xFF) 677 #define IP_VERSION_REV(ver) ((ver) & 0xFF) 678 679 struct amd_powerplay { 680 void *pp_handle; 681 const struct amd_pm_funcs *pp_funcs; 682 }; 683 684 struct ip_discovery_top; 685 686 /* polaris10 kickers */ 687 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 688 ((rid == 0xE3) || \ 689 (rid == 0xE4) || \ 690 (rid == 0xE5) || \ 691 (rid == 0xE7) || \ 692 (rid == 0xEF))) || \ 693 ((did == 0x6FDF) && \ 694 ((rid == 0xE7) || \ 695 (rid == 0xEF) || \ 696 (rid == 0xFF)))) 697 698 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 699 ((rid == 0xE1) || \ 700 (rid == 0xF7))) 701 702 /* polaris11 kickers */ 703 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 704 ((rid == 0xE0) || \ 705 (rid == 0xE5))) || \ 706 ((did == 0x67FF) && \ 707 ((rid == 0xCF) || \ 708 (rid == 0xEF) || \ 709 (rid == 0xFF)))) 710 711 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 712 ((rid == 0xE2))) 713 714 /* polaris12 kickers */ 715 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 716 ((rid == 0xC0) || \ 717 (rid == 0xC1) || \ 718 (rid == 0xC3) || \ 719 (rid == 0xC7))) || \ 720 ((did == 0x6981) && \ 721 ((rid == 0x00) || \ 722 (rid == 0x01) || \ 723 (rid == 0x10)))) 724 725 struct amdgpu_mqd_prop { 726 uint64_t mqd_gpu_addr; 727 uint64_t hqd_base_gpu_addr; 728 uint64_t rptr_gpu_addr; 729 uint64_t wptr_gpu_addr; 730 uint32_t queue_size; 731 bool use_doorbell; 732 uint32_t doorbell_index; 733 uint64_t eop_gpu_addr; 734 uint32_t hqd_pipe_priority; 735 uint32_t hqd_queue_priority; 736 bool hqd_active; 737 }; 738 739 struct amdgpu_mqd { 740 unsigned mqd_size; 741 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 742 struct amdgpu_mqd_prop *p); 743 }; 744 745 #define AMDGPU_RESET_MAGIC_NUM 64 746 #define AMDGPU_MAX_DF_PERFMONS 4 747 #define AMDGPU_PRODUCT_NAME_LEN 64 748 struct amdgpu_reset_domain; 749 750 struct amdgpu_device { 751 struct device *dev; 752 struct pci_dev *pdev; 753 struct drm_device ddev; 754 755 #ifdef CONFIG_DRM_AMD_ACP 756 struct amdgpu_acp acp; 757 #endif 758 struct amdgpu_hive_info *hive; 759 /* ASIC */ 760 enum amd_asic_type asic_type; 761 uint32_t family; 762 uint32_t rev_id; 763 uint32_t external_rev_id; 764 unsigned long flags; 765 unsigned long apu_flags; 766 int usec_timeout; 767 const struct amdgpu_asic_funcs *asic_funcs; 768 bool shutdown; 769 bool need_swiotlb; 770 bool accel_working; 771 struct notifier_block acpi_nb; 772 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 773 struct debugfs_blob_wrapper debugfs_vbios_blob; 774 struct debugfs_blob_wrapper debugfs_discovery_blob; 775 struct mutex srbm_mutex; 776 /* GRBM index mutex. Protects concurrent access to GRBM index */ 777 struct mutex grbm_idx_mutex; 778 struct dev_pm_domain vga_pm_domain; 779 bool have_disp_power_ref; 780 bool have_atomics_support; 781 782 /* BIOS */ 783 bool is_atom_fw; 784 uint8_t *bios; 785 uint32_t bios_size; 786 uint32_t bios_scratch_reg_offset; 787 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 788 789 /* Register/doorbell mmio */ 790 resource_size_t rmmio_base; 791 resource_size_t rmmio_size; 792 void __iomem *rmmio; 793 /* protects concurrent MM_INDEX/DATA based register access */ 794 spinlock_t mmio_idx_lock; 795 struct amdgpu_mmio_remap rmmio_remap; 796 /* protects concurrent SMC based register access */ 797 spinlock_t smc_idx_lock; 798 amdgpu_rreg_t smc_rreg; 799 amdgpu_wreg_t smc_wreg; 800 /* protects concurrent PCIE register access */ 801 spinlock_t pcie_idx_lock; 802 amdgpu_rreg_t pcie_rreg; 803 amdgpu_wreg_t pcie_wreg; 804 amdgpu_rreg_t pciep_rreg; 805 amdgpu_wreg_t pciep_wreg; 806 amdgpu_rreg64_t pcie_rreg64; 807 amdgpu_wreg64_t pcie_wreg64; 808 /* protects concurrent UVD register access */ 809 spinlock_t uvd_ctx_idx_lock; 810 amdgpu_rreg_t uvd_ctx_rreg; 811 amdgpu_wreg_t uvd_ctx_wreg; 812 /* protects concurrent DIDT register access */ 813 spinlock_t didt_idx_lock; 814 amdgpu_rreg_t didt_rreg; 815 amdgpu_wreg_t didt_wreg; 816 /* protects concurrent gc_cac register access */ 817 spinlock_t gc_cac_idx_lock; 818 amdgpu_rreg_t gc_cac_rreg; 819 amdgpu_wreg_t gc_cac_wreg; 820 /* protects concurrent se_cac register access */ 821 spinlock_t se_cac_idx_lock; 822 amdgpu_rreg_t se_cac_rreg; 823 amdgpu_wreg_t se_cac_wreg; 824 /* protects concurrent ENDPOINT (audio) register access */ 825 spinlock_t audio_endpt_idx_lock; 826 amdgpu_block_rreg_t audio_endpt_rreg; 827 amdgpu_block_wreg_t audio_endpt_wreg; 828 struct amdgpu_doorbell doorbell; 829 830 /* clock/pll info */ 831 struct amdgpu_clock clock; 832 833 /* MC */ 834 struct amdgpu_gmc gmc; 835 struct amdgpu_gart gart; 836 dma_addr_t dummy_page_addr; 837 struct amdgpu_vm_manager vm_manager; 838 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 839 unsigned num_vmhubs; 840 841 /* memory management */ 842 struct amdgpu_mman mman; 843 struct amdgpu_vram_scratch vram_scratch; 844 struct amdgpu_wb wb; 845 atomic64_t num_bytes_moved; 846 atomic64_t num_evictions; 847 atomic64_t num_vram_cpu_page_faults; 848 atomic_t gpu_reset_counter; 849 atomic_t vram_lost_counter; 850 851 /* data for buffer migration throttling */ 852 struct { 853 spinlock_t lock; 854 s64 last_update_us; 855 s64 accum_us; /* accumulated microseconds */ 856 s64 accum_us_vis; /* for visible VRAM */ 857 u32 log2_max_MBps; 858 } mm_stats; 859 860 /* display */ 861 bool enable_virtual_display; 862 struct amdgpu_vkms_output *amdgpu_vkms_output; 863 struct amdgpu_mode_info mode_info; 864 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 865 struct work_struct hotplug_work; 866 struct amdgpu_irq_src crtc_irq; 867 struct amdgpu_irq_src vline0_irq; 868 struct amdgpu_irq_src vupdate_irq; 869 struct amdgpu_irq_src pageflip_irq; 870 struct amdgpu_irq_src hpd_irq; 871 struct amdgpu_irq_src dmub_trace_irq; 872 struct amdgpu_irq_src dmub_outbox_irq; 873 874 /* rings */ 875 u64 fence_context; 876 unsigned num_rings; 877 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 878 bool ib_pool_ready; 879 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 880 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 881 882 /* interrupts */ 883 struct amdgpu_irq irq; 884 885 /* powerplay */ 886 struct amd_powerplay powerplay; 887 struct amdgpu_pm pm; 888 u64 cg_flags; 889 u32 pg_flags; 890 891 /* nbio */ 892 struct amdgpu_nbio nbio; 893 894 /* hdp */ 895 struct amdgpu_hdp hdp; 896 897 /* smuio */ 898 struct amdgpu_smuio smuio; 899 900 /* mmhub */ 901 struct amdgpu_mmhub mmhub; 902 903 /* gfxhub */ 904 struct amdgpu_gfxhub gfxhub; 905 906 /* gfx */ 907 struct amdgpu_gfx gfx; 908 909 /* sdma */ 910 struct amdgpu_sdma sdma; 911 912 /* uvd */ 913 struct amdgpu_uvd uvd; 914 915 /* vce */ 916 struct amdgpu_vce vce; 917 918 /* vcn */ 919 struct amdgpu_vcn vcn; 920 921 /* jpeg */ 922 struct amdgpu_jpeg jpeg; 923 924 /* firmwares */ 925 struct amdgpu_firmware firmware; 926 927 /* PSP */ 928 struct psp_context psp; 929 930 /* GDS */ 931 struct amdgpu_gds gds; 932 933 /* KFD */ 934 struct amdgpu_kfd_dev kfd; 935 936 /* UMC */ 937 struct amdgpu_umc umc; 938 939 /* display related functionality */ 940 struct amdgpu_display_manager dm; 941 942 /* mes */ 943 bool enable_mes; 944 bool enable_mes_kiq; 945 struct amdgpu_mes mes; 946 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 947 948 /* df */ 949 struct amdgpu_df df; 950 951 /* MCA */ 952 struct amdgpu_mca mca; 953 954 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 955 uint32_t harvest_ip_mask; 956 int num_ip_blocks; 957 struct mutex mn_lock; 958 DECLARE_HASHTABLE(mn_hash, 7); 959 960 /* tracking pinned memory */ 961 atomic64_t vram_pin_size; 962 atomic64_t visible_pin_size; 963 atomic64_t gart_pin_size; 964 965 /* soc15 register offset based on ip, instance and segment */ 966 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 967 968 /* delayed work_func for deferring clockgating during resume */ 969 struct delayed_work delayed_init_work; 970 971 struct amdgpu_virt virt; 972 973 /* link all shadow bo */ 974 struct list_head shadow_list; 975 struct mutex shadow_list_lock; 976 977 /* record hw reset is performed */ 978 bool has_hw_reset; 979 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 980 981 /* s3/s4 mask */ 982 bool in_suspend; 983 bool in_s3; 984 bool in_s4; 985 bool in_s0ix; 986 987 enum pp_mp1_state mp1_state; 988 struct amdgpu_doorbell_index doorbell_index; 989 990 struct mutex notifier_lock; 991 992 int asic_reset_res; 993 struct work_struct xgmi_reset_work; 994 struct list_head reset_list; 995 996 long gfx_timeout; 997 long sdma_timeout; 998 long video_timeout; 999 long compute_timeout; 1000 1001 uint64_t unique_id; 1002 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1003 1004 /* enable runtime pm on the device */ 1005 bool runpm; 1006 bool in_runpm; 1007 bool has_pr3; 1008 1009 bool pm_sysfs_en; 1010 bool ucode_sysfs_en; 1011 1012 /* Chip product information */ 1013 char product_number[16]; 1014 char product_name[AMDGPU_PRODUCT_NAME_LEN]; 1015 char serial[20]; 1016 1017 atomic_t throttling_logging_enabled; 1018 struct ratelimit_state throttling_logging_rs; 1019 uint32_t ras_hw_enabled; 1020 uint32_t ras_enabled; 1021 1022 bool no_hw_access; 1023 struct pci_saved_state *pci_state; 1024 pci_channel_state_t pci_channel_state; 1025 1026 struct amdgpu_reset_control *reset_cntl; 1027 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1028 1029 bool ram_is_direct_mapped; 1030 1031 struct list_head ras_list; 1032 1033 struct ip_discovery_top *ip_top; 1034 1035 struct amdgpu_reset_domain *reset_domain; 1036 1037 struct mutex benchmark_mutex; 1038 1039 /* reset dump register */ 1040 uint32_t *reset_dump_reg_list; 1041 int num_regs; 1042 1043 bool scpm_enabled; 1044 uint32_t scpm_status; 1045 }; 1046 1047 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1048 { 1049 return container_of(ddev, struct amdgpu_device, ddev); 1050 } 1051 1052 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1053 { 1054 return &adev->ddev; 1055 } 1056 1057 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1058 { 1059 return container_of(bdev, struct amdgpu_device, mman.bdev); 1060 } 1061 1062 int amdgpu_device_init(struct amdgpu_device *adev, 1063 uint32_t flags); 1064 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1065 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1066 1067 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1068 1069 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1070 void *buf, size_t size, bool write); 1071 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1072 void *buf, size_t size, bool write); 1073 1074 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1075 void *buf, size_t size, bool write); 1076 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1077 uint32_t reg, uint32_t acc_flags); 1078 void amdgpu_device_wreg(struct amdgpu_device *adev, 1079 uint32_t reg, uint32_t v, 1080 uint32_t acc_flags); 1081 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1082 uint32_t reg, uint32_t v); 1083 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1084 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1085 1086 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1087 u32 pcie_index, u32 pcie_data, 1088 u32 reg_addr); 1089 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1090 u32 pcie_index, u32 pcie_data, 1091 u32 reg_addr); 1092 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1093 u32 pcie_index, u32 pcie_data, 1094 u32 reg_addr, u32 reg_data); 1095 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1096 u32 pcie_index, u32 pcie_data, 1097 u32 reg_addr, u64 reg_data); 1098 1099 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1100 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1101 1102 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1103 struct amdgpu_reset_context *reset_context); 1104 1105 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1106 struct amdgpu_reset_context *reset_context); 1107 1108 int emu_soc_asic_init(struct amdgpu_device *adev); 1109 1110 /* 1111 * Registers read & write functions. 1112 */ 1113 #define AMDGPU_REGS_NO_KIQ (1<<1) 1114 #define AMDGPU_REGS_RLC (1<<2) 1115 1116 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1117 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1118 1119 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1120 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1121 1122 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1123 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1124 1125 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1126 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1127 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1128 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1129 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1130 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1131 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1132 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1133 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1134 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1135 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1136 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1137 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1138 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1139 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1140 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1141 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1142 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1143 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1144 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1145 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1146 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1147 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1148 #define WREG32_P(reg, val, mask) \ 1149 do { \ 1150 uint32_t tmp_ = RREG32(reg); \ 1151 tmp_ &= (mask); \ 1152 tmp_ |= ((val) & ~(mask)); \ 1153 WREG32(reg, tmp_); \ 1154 } while (0) 1155 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1156 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1157 #define WREG32_PLL_P(reg, val, mask) \ 1158 do { \ 1159 uint32_t tmp_ = RREG32_PLL(reg); \ 1160 tmp_ &= (mask); \ 1161 tmp_ |= ((val) & ~(mask)); \ 1162 WREG32_PLL(reg, tmp_); \ 1163 } while (0) 1164 1165 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1166 do { \ 1167 u32 tmp = RREG32_SMC(_Reg); \ 1168 tmp &= (_Mask); \ 1169 tmp |= ((_Val) & ~(_Mask)); \ 1170 WREG32_SMC(_Reg, tmp); \ 1171 } while (0) 1172 1173 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1174 1175 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1176 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1177 1178 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1179 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1180 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1181 1182 #define REG_GET_FIELD(value, reg, field) \ 1183 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1184 1185 #define WREG32_FIELD(reg, field, val) \ 1186 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1187 1188 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1189 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1190 1191 /* 1192 * BIOS helpers. 1193 */ 1194 #define RBIOS8(i) (adev->bios[i]) 1195 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1196 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1197 1198 /* 1199 * ASICs macro. 1200 */ 1201 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1202 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1203 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1204 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1205 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1206 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1207 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1208 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1209 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1210 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1211 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1212 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1213 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1214 #define amdgpu_asic_flush_hdp(adev, r) \ 1215 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1216 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1217 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \ 1218 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : 0)) 1219 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1220 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1221 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1222 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1223 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1224 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1225 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1226 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1227 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1228 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1229 1230 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1231 1232 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 1233 1234 /* Common functions */ 1235 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1236 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1237 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1238 struct amdgpu_job* job); 1239 int amdgpu_device_gpu_recover_imp(struct amdgpu_device *adev, 1240 struct amdgpu_job *job); 1241 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1242 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1243 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1244 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1245 1246 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1247 u64 num_vis_bytes); 1248 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1249 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1250 const u32 *registers, 1251 const u32 array_size); 1252 1253 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1254 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1255 bool amdgpu_device_supports_px(struct drm_device *dev); 1256 bool amdgpu_device_supports_boco(struct drm_device *dev); 1257 bool amdgpu_device_supports_smart_shift(struct drm_device *dev); 1258 bool amdgpu_device_supports_baco(struct drm_device *dev); 1259 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1260 struct amdgpu_device *peer_adev); 1261 int amdgpu_device_baco_enter(struct drm_device *dev); 1262 int amdgpu_device_baco_exit(struct drm_device *dev); 1263 1264 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1265 struct amdgpu_ring *ring); 1266 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1267 struct amdgpu_ring *ring); 1268 1269 void amdgpu_device_halt(struct amdgpu_device *adev); 1270 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, 1271 u32 reg); 1272 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, 1273 u32 reg, u32 v); 1274 1275 /* atpx handler */ 1276 #if defined(CONFIG_VGA_SWITCHEROO) 1277 void amdgpu_register_atpx_handler(void); 1278 void amdgpu_unregister_atpx_handler(void); 1279 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1280 bool amdgpu_is_atpx_hybrid(void); 1281 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1282 bool amdgpu_has_atpx(void); 1283 #else 1284 static inline void amdgpu_register_atpx_handler(void) {} 1285 static inline void amdgpu_unregister_atpx_handler(void) {} 1286 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1287 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1288 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1289 static inline bool amdgpu_has_atpx(void) { return false; } 1290 #endif 1291 1292 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1293 void *amdgpu_atpx_get_dhandle(void); 1294 #else 1295 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1296 #endif 1297 1298 /* 1299 * KMS 1300 */ 1301 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1302 extern const int amdgpu_max_kms_ioctl; 1303 1304 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1305 void amdgpu_driver_unload_kms(struct drm_device *dev); 1306 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1307 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1308 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1309 struct drm_file *file_priv); 1310 void amdgpu_driver_release_kms(struct drm_device *dev); 1311 1312 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1313 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1314 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1315 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1316 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1317 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1318 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1319 struct drm_file *filp); 1320 1321 /* 1322 * functions used by amdgpu_encoder.c 1323 */ 1324 struct amdgpu_afmt_acr { 1325 u32 clock; 1326 1327 int n_32khz; 1328 int cts_32khz; 1329 1330 int n_44_1khz; 1331 int cts_44_1khz; 1332 1333 int n_48khz; 1334 int cts_48khz; 1335 1336 }; 1337 1338 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1339 1340 /* amdgpu_acpi.c */ 1341 1342 /* ATCS Device/Driver State */ 1343 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1344 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1345 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1346 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1347 1348 #if defined(CONFIG_ACPI) 1349 int amdgpu_acpi_init(struct amdgpu_device *adev); 1350 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1351 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1352 bool amdgpu_acpi_is_power_shift_control_supported(void); 1353 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1354 u8 perf_req, bool advertise); 1355 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1356 u8 dev_state, bool drv_state); 1357 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state); 1358 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1359 1360 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1361 void amdgpu_acpi_detect(void); 1362 #else 1363 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1364 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1365 static inline void amdgpu_acpi_detect(void) { } 1366 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1367 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1368 u8 dev_state, bool drv_state) { return 0; } 1369 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, 1370 enum amdgpu_ss ss_state) { return 0; } 1371 #endif 1372 1373 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1374 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1375 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1376 #else 1377 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1378 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1379 #endif 1380 1381 #if defined(CONFIG_DRM_AMD_DC) 1382 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1383 #else 1384 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1385 #endif 1386 1387 1388 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1389 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1390 1391 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1392 pci_channel_state_t state); 1393 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1394 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1395 void amdgpu_pci_resume(struct pci_dev *pdev); 1396 1397 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1398 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1399 1400 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1401 1402 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1403 enum amd_clockgating_state state); 1404 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1405 enum amd_powergating_state state); 1406 1407 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1408 { 1409 return amdgpu_gpu_recovery != 0 && 1410 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1411 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1412 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1413 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1414 } 1415 1416 #include "amdgpu_object.h" 1417 1418 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1419 { 1420 return adev->gmc.tmz_enabled; 1421 } 1422 1423 int amdgpu_in_reset(struct amdgpu_device *adev); 1424 1425 #endif 1426