1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 54 #include <drm/ttm/ttm_bo.h> 55 #include <drm/ttm/ttm_placement.h> 56 57 #include <drm/amdgpu_drm.h> 58 #include <drm/drm_gem.h> 59 #include <drm/drm_ioctl.h> 60 61 #include <kgd_kfd_interface.h> 62 #include "dm_pp_interface.h" 63 #include "kgd_pp_interface.h" 64 65 #include "amd_shared.h" 66 #include "amdgpu_mode.h" 67 #include "amdgpu_ih.h" 68 #include "amdgpu_irq.h" 69 #include "amdgpu_ucode.h" 70 #include "amdgpu_ttm.h" 71 #include "amdgpu_psp.h" 72 #include "amdgpu_gds.h" 73 #include "amdgpu_sync.h" 74 #include "amdgpu_ring.h" 75 #include "amdgpu_vm.h" 76 #include "amdgpu_dpm.h" 77 #include "amdgpu_acp.h" 78 #include "amdgpu_uvd.h" 79 #include "amdgpu_vce.h" 80 #include "amdgpu_vcn.h" 81 #include "amdgpu_jpeg.h" 82 #include "amdgpu_vpe.h" 83 #include "amdgpu_umsch_mm.h" 84 #include "amdgpu_gmc.h" 85 #include "amdgpu_gfx.h" 86 #include "amdgpu_sdma.h" 87 #include "amdgpu_lsdma.h" 88 #include "amdgpu_nbio.h" 89 #include "amdgpu_hdp.h" 90 #include "amdgpu_dm.h" 91 #include "amdgpu_virt.h" 92 #include "amdgpu_csa.h" 93 #include "amdgpu_mes_ctx.h" 94 #include "amdgpu_gart.h" 95 #include "amdgpu_debugfs.h" 96 #include "amdgpu_job.h" 97 #include "amdgpu_bo_list.h" 98 #include "amdgpu_gem.h" 99 #include "amdgpu_doorbell.h" 100 #include "amdgpu_amdkfd.h" 101 #include "amdgpu_discovery.h" 102 #include "amdgpu_mes.h" 103 #include "amdgpu_umc.h" 104 #include "amdgpu_mmhub.h" 105 #include "amdgpu_gfxhub.h" 106 #include "amdgpu_df.h" 107 #include "amdgpu_smuio.h" 108 #include "amdgpu_fdinfo.h" 109 #include "amdgpu_mca.h" 110 #include "amdgpu_aca.h" 111 #include "amdgpu_ras.h" 112 #include "amdgpu_xcp.h" 113 #include "amdgpu_seq64.h" 114 #include "amdgpu_reg_state.h" 115 #if defined(CONFIG_DRM_AMD_ISP) 116 #include "amdgpu_isp.h" 117 #endif 118 119 #define MAX_GPU_INSTANCE 64 120 121 #define GFX_SLICE_PERIOD msecs_to_jiffies(250) 122 123 struct amdgpu_gpu_instance { 124 struct amdgpu_device *adev; 125 int mgpu_fan_enabled; 126 }; 127 128 struct amdgpu_mgpu_info { 129 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 130 struct mutex mutex; 131 uint32_t num_gpu; 132 uint32_t num_dgpu; 133 uint32_t num_apu; 134 }; 135 136 enum amdgpu_ss { 137 AMDGPU_SS_DRV_LOAD, 138 AMDGPU_SS_DEV_D0, 139 AMDGPU_SS_DEV_D3, 140 AMDGPU_SS_DRV_UNLOAD 141 }; 142 143 struct amdgpu_hwip_reg_entry { 144 u32 hwip; 145 u32 inst; 146 u32 seg; 147 u32 reg_offset; 148 const char *reg_name; 149 }; 150 151 struct amdgpu_watchdog_timer { 152 bool timeout_fatal_disable; 153 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 154 }; 155 156 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 157 158 /* 159 * Modules parameters. 160 */ 161 extern int amdgpu_modeset; 162 extern unsigned int amdgpu_vram_limit; 163 extern int amdgpu_vis_vram_limit; 164 extern int amdgpu_gart_size; 165 extern int amdgpu_gtt_size; 166 extern int amdgpu_moverate; 167 extern int amdgpu_audio; 168 extern int amdgpu_disp_priority; 169 extern int amdgpu_hw_i2c; 170 extern int amdgpu_pcie_gen2; 171 extern int amdgpu_msi; 172 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 173 extern int amdgpu_dpm; 174 extern int amdgpu_fw_load_type; 175 extern int amdgpu_aspm; 176 extern int amdgpu_runtime_pm; 177 extern uint amdgpu_ip_block_mask; 178 extern int amdgpu_bapm; 179 extern int amdgpu_deep_color; 180 extern int amdgpu_vm_size; 181 extern int amdgpu_vm_block_size; 182 extern int amdgpu_vm_fragment_size; 183 extern int amdgpu_vm_fault_stop; 184 extern int amdgpu_vm_debug; 185 extern int amdgpu_vm_update_mode; 186 extern int amdgpu_exp_hw_support; 187 extern int amdgpu_dc; 188 extern int amdgpu_sched_jobs; 189 extern int amdgpu_sched_hw_submission; 190 extern uint amdgpu_pcie_gen_cap; 191 extern uint amdgpu_pcie_lane_cap; 192 extern u64 amdgpu_cg_mask; 193 extern uint amdgpu_pg_mask; 194 extern uint amdgpu_sdma_phase_quantum; 195 extern char *amdgpu_disable_cu; 196 extern char *amdgpu_virtual_display; 197 extern uint amdgpu_pp_feature_mask; 198 extern uint amdgpu_force_long_training; 199 extern int amdgpu_lbpw; 200 extern int amdgpu_compute_multipipe; 201 extern int amdgpu_gpu_recovery; 202 extern int amdgpu_emu_mode; 203 extern uint amdgpu_smu_memory_pool_size; 204 extern int amdgpu_smu_pptable_id; 205 extern uint amdgpu_dc_feature_mask; 206 extern uint amdgpu_freesync_vid_mode; 207 extern uint amdgpu_dc_debug_mask; 208 extern uint amdgpu_dc_visual_confirm; 209 extern int amdgpu_dm_abm_level; 210 extern int amdgpu_backlight; 211 extern int amdgpu_damage_clips; 212 extern struct amdgpu_mgpu_info mgpu_info; 213 extern int amdgpu_ras_enable; 214 extern uint amdgpu_ras_mask; 215 extern int amdgpu_bad_page_threshold; 216 extern bool amdgpu_ignore_bad_page_threshold; 217 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 218 extern int amdgpu_async_gfx_ring; 219 extern int amdgpu_mcbp; 220 extern int amdgpu_discovery; 221 extern int amdgpu_mes; 222 extern int amdgpu_mes_log_enable; 223 extern int amdgpu_mes_kiq; 224 extern int amdgpu_uni_mes; 225 extern int amdgpu_noretry; 226 extern int amdgpu_force_asic_type; 227 extern int amdgpu_smartshift_bias; 228 extern int amdgpu_use_xgmi_p2p; 229 extern int amdgpu_mtype_local; 230 extern bool enforce_isolation; 231 #ifdef CONFIG_HSA_AMD 232 extern int sched_policy; 233 extern bool debug_evictions; 234 extern bool no_system_mem_limit; 235 extern int halt_if_hws_hang; 236 extern uint amdgpu_svm_default_granularity; 237 #else 238 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 239 static const bool __maybe_unused debug_evictions; /* = false */ 240 static const bool __maybe_unused no_system_mem_limit; 241 static const int __maybe_unused halt_if_hws_hang; 242 #endif 243 #ifdef CONFIG_HSA_AMD_P2P 244 extern bool pcie_p2p; 245 #endif 246 247 extern int amdgpu_tmz; 248 extern int amdgpu_reset_method; 249 250 #ifdef CONFIG_DRM_AMDGPU_SI 251 extern int amdgpu_si_support; 252 #endif 253 #ifdef CONFIG_DRM_AMDGPU_CIK 254 extern int amdgpu_cik_support; 255 #endif 256 extern int amdgpu_num_kcq; 257 258 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 259 #define AMDGPU_UMSCHFW_LOG_SIZE (32 * 1024) 260 extern int amdgpu_vcnfw_log; 261 extern int amdgpu_sg_display; 262 extern int amdgpu_umsch_mm; 263 extern int amdgpu_seamless; 264 extern int amdgpu_umsch_mm_fwlog; 265 266 extern int amdgpu_user_partt_mode; 267 extern int amdgpu_agp; 268 269 extern int amdgpu_wbrf; 270 271 #define AMDGPU_VM_MAX_NUM_CTX 4096 272 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 273 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 274 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 275 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 276 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 277 #define AMDGPUFB_CONN_LIMIT 4 278 #define AMDGPU_BIOS_NUM_SCRATCH 16 279 280 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 281 282 /* hard reset data */ 283 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 284 285 /* reset flags */ 286 #define AMDGPU_RESET_GFX (1 << 0) 287 #define AMDGPU_RESET_COMPUTE (1 << 1) 288 #define AMDGPU_RESET_DMA (1 << 2) 289 #define AMDGPU_RESET_CP (1 << 3) 290 #define AMDGPU_RESET_GRBM (1 << 4) 291 #define AMDGPU_RESET_DMA1 (1 << 5) 292 #define AMDGPU_RESET_RLC (1 << 6) 293 #define AMDGPU_RESET_SEM (1 << 7) 294 #define AMDGPU_RESET_IH (1 << 8) 295 #define AMDGPU_RESET_VMC (1 << 9) 296 #define AMDGPU_RESET_MC (1 << 10) 297 #define AMDGPU_RESET_DISPLAY (1 << 11) 298 #define AMDGPU_RESET_UVD (1 << 12) 299 #define AMDGPU_RESET_VCE (1 << 13) 300 #define AMDGPU_RESET_VCE1 (1 << 14) 301 302 /* max cursor sizes (in pixels) */ 303 #define CIK_CURSOR_WIDTH 128 304 #define CIK_CURSOR_HEIGHT 128 305 306 /* smart shift bias level limits */ 307 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 308 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 309 310 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */ 311 #define AMDGPU_SWCTF_EXTRA_DELAY 50 312 313 struct amdgpu_xcp_mgr; 314 struct amdgpu_device; 315 struct amdgpu_irq_src; 316 struct amdgpu_fpriv; 317 struct amdgpu_bo_va_mapping; 318 struct kfd_vm_fault_info; 319 struct amdgpu_hive_info; 320 struct amdgpu_reset_context; 321 struct amdgpu_reset_control; 322 323 enum amdgpu_cp_irq { 324 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 325 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 326 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 327 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 328 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 329 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 330 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 331 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 332 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 333 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 334 335 AMDGPU_CP_IRQ_LAST 336 }; 337 338 enum amdgpu_thermal_irq { 339 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 340 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 341 342 AMDGPU_THERMAL_IRQ_LAST 343 }; 344 345 enum amdgpu_kiq_irq { 346 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 347 AMDGPU_CP_KIQ_IRQ_LAST 348 }; 349 #define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */ 350 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 351 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 352 #define MAX_KIQ_REG_TRY 1000 353 354 int amdgpu_device_ip_set_clockgating_state(void *dev, 355 enum amd_ip_block_type block_type, 356 enum amd_clockgating_state state); 357 int amdgpu_device_ip_set_powergating_state(void *dev, 358 enum amd_ip_block_type block_type, 359 enum amd_powergating_state state); 360 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 361 u64 *flags); 362 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 363 enum amd_ip_block_type block_type); 364 bool amdgpu_device_ip_is_valid(struct amdgpu_device *adev, 365 enum amd_ip_block_type block_type); 366 367 #define AMDGPU_MAX_IP_NUM 16 368 369 struct amdgpu_ip_block_status { 370 bool valid; 371 bool sw; 372 bool hw; 373 bool late_initialized; 374 bool hang; 375 }; 376 377 struct amdgpu_ip_block_version { 378 const enum amd_ip_block_type type; 379 const u32 major; 380 const u32 minor; 381 const u32 rev; 382 const struct amd_ip_funcs *funcs; 383 }; 384 385 struct amdgpu_ip_block { 386 struct amdgpu_ip_block_status status; 387 const struct amdgpu_ip_block_version *version; 388 struct amdgpu_device *adev; 389 }; 390 391 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 392 enum amd_ip_block_type type, 393 u32 major, u32 minor); 394 395 struct amdgpu_ip_block * 396 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 397 enum amd_ip_block_type type); 398 399 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 400 const struct amdgpu_ip_block_version *ip_block_version); 401 402 /* 403 * BIOS. 404 */ 405 bool amdgpu_get_bios(struct amdgpu_device *adev); 406 bool amdgpu_read_bios(struct amdgpu_device *adev); 407 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 408 u8 *bios, u32 length_bytes); 409 /* 410 * Clocks 411 */ 412 413 #define AMDGPU_MAX_PPLL 3 414 415 struct amdgpu_clock { 416 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 417 struct amdgpu_pll spll; 418 struct amdgpu_pll mpll; 419 /* 10 Khz units */ 420 uint32_t default_mclk; 421 uint32_t default_sclk; 422 uint32_t default_dispclk; 423 uint32_t current_dispclk; 424 uint32_t dp_extclk; 425 uint32_t max_pixel_clock; 426 }; 427 428 /* sub-allocation manager, it has to be protected by another lock. 429 * By conception this is an helper for other part of the driver 430 * like the indirect buffer or semaphore, which both have their 431 * locking. 432 * 433 * Principe is simple, we keep a list of sub allocation in offset 434 * order (first entry has offset == 0, last entry has the highest 435 * offset). 436 * 437 * When allocating new object we first check if there is room at 438 * the end total_size - (last_object_offset + last_object_size) >= 439 * alloc_size. If so we allocate new object there. 440 * 441 * When there is not enough room at the end, we start waiting for 442 * each sub object until we reach object_offset+object_size >= 443 * alloc_size, this object then become the sub object we return. 444 * 445 * Alignment can't be bigger than page size. 446 * 447 * Hole are not considered for allocation to keep things simple. 448 * Assumption is that there won't be hole (all object on same 449 * alignment). 450 */ 451 452 struct amdgpu_sa_manager { 453 struct drm_suballoc_manager base; 454 struct amdgpu_bo *bo; 455 uint64_t gpu_addr; 456 void *cpu_ptr; 457 }; 458 459 int amdgpu_fence_slab_init(void); 460 void amdgpu_fence_slab_fini(void); 461 462 /* 463 * IRQS. 464 */ 465 466 struct amdgpu_flip_work { 467 struct delayed_work flip_work; 468 struct work_struct unpin_work; 469 struct amdgpu_device *adev; 470 int crtc_id; 471 u32 target_vblank; 472 uint64_t base; 473 struct drm_pending_vblank_event *event; 474 struct amdgpu_bo *old_abo; 475 unsigned shared_count; 476 struct dma_fence **shared; 477 struct dma_fence_cb cb; 478 bool async; 479 }; 480 481 482 /* 483 * file private structure 484 */ 485 486 struct amdgpu_fpriv { 487 struct amdgpu_vm vm; 488 struct amdgpu_bo_va *prt_va; 489 struct amdgpu_bo_va *csa_va; 490 struct amdgpu_bo_va *seq64_va; 491 struct mutex bo_list_lock; 492 struct idr bo_list_handles; 493 struct amdgpu_ctx_mgr ctx_mgr; 494 /** GPU partition selection */ 495 uint32_t xcp_id; 496 }; 497 498 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 499 500 /* 501 * Writeback 502 */ 503 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 504 505 struct amdgpu_wb { 506 struct amdgpu_bo *wb_obj; 507 volatile uint32_t *wb; 508 uint64_t gpu_addr; 509 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 510 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 511 spinlock_t lock; 512 }; 513 514 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 515 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 516 517 /* 518 * Benchmarking 519 */ 520 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 521 522 /* 523 * ASIC specific register table accessible by UMD 524 */ 525 struct amdgpu_allowed_register_entry { 526 uint32_t reg_offset; 527 bool grbm_indexed; 528 }; 529 530 /** 531 * enum amd_reset_method - Methods for resetting AMD GPU devices 532 * 533 * @AMD_RESET_METHOD_NONE: The device will not be reset. 534 * @AMD_RESET_LEGACY: Method reserved for SI, CIK and VI ASICs. 535 * @AMD_RESET_MODE0: Reset the entire ASIC. Not currently available for the 536 * any device. 537 * @AMD_RESET_MODE1: Resets all IP blocks on the ASIC (SDMA, GFX, VCN, etc.) 538 * individually. Suitable only for some discrete GPU, not 539 * available for all ASICs. 540 * @AMD_RESET_MODE2: Resets a lesser level of IPs compared to MODE1. Which IPs 541 * are reset depends on the ASIC. Notably doesn't reset IPs 542 * shared with the CPU on APUs or the memory controllers (so 543 * VRAM is not lost). Not available on all ASICs. 544 * @AMD_RESET_BACO: BACO (Bus Alive, Chip Off) method powers off and on the card 545 * but without powering off the PCI bus. Suitable only for 546 * discrete GPUs. 547 * @AMD_RESET_PCI: Does a full bus reset using core Linux subsystem PCI reset 548 * and does a secondary bus reset or FLR, depending on what the 549 * underlying hardware supports. 550 * 551 * Methods available for AMD GPU driver for resetting the device. Not all 552 * methods are suitable for every device. User can override the method using 553 * module parameter `reset_method`. 554 */ 555 enum amd_reset_method { 556 AMD_RESET_METHOD_NONE = -1, 557 AMD_RESET_METHOD_LEGACY = 0, 558 AMD_RESET_METHOD_MODE0, 559 AMD_RESET_METHOD_MODE1, 560 AMD_RESET_METHOD_MODE2, 561 AMD_RESET_METHOD_BACO, 562 AMD_RESET_METHOD_PCI, 563 AMD_RESET_METHOD_ON_INIT, 564 }; 565 566 struct amdgpu_video_codec_info { 567 u32 codec_type; 568 u32 max_width; 569 u32 max_height; 570 u32 max_pixels_per_frame; 571 u32 max_level; 572 }; 573 574 #define codec_info_build(type, width, height, level) \ 575 .codec_type = type,\ 576 .max_width = width,\ 577 .max_height = height,\ 578 .max_pixels_per_frame = height * width,\ 579 .max_level = level, 580 581 struct amdgpu_video_codecs { 582 const u32 codec_count; 583 const struct amdgpu_video_codec_info *codec_array; 584 }; 585 586 /* 587 * ASIC specific functions. 588 */ 589 struct amdgpu_asic_funcs { 590 bool (*read_disabled_bios)(struct amdgpu_device *adev); 591 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 592 u8 *bios, u32 length_bytes); 593 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 594 u32 sh_num, u32 reg_offset, u32 *value); 595 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 596 int (*reset)(struct amdgpu_device *adev); 597 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 598 /* get the reference clock */ 599 u32 (*get_xclk)(struct amdgpu_device *adev); 600 /* MM block clocks */ 601 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 602 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 603 /* static power management */ 604 int (*get_pcie_lanes)(struct amdgpu_device *adev); 605 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 606 /* get config memsize register */ 607 u32 (*get_config_memsize)(struct amdgpu_device *adev); 608 /* flush hdp write queue */ 609 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 610 /* invalidate hdp read cache */ 611 void (*invalidate_hdp)(struct amdgpu_device *adev, 612 struct amdgpu_ring *ring); 613 /* check if the asic needs a full reset of if soft reset will work */ 614 bool (*need_full_reset)(struct amdgpu_device *adev); 615 /* initialize doorbell layout for specific asic*/ 616 void (*init_doorbell_index)(struct amdgpu_device *adev); 617 /* PCIe bandwidth usage */ 618 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 619 uint64_t *count1); 620 /* do we need to reset the asic at init time (e.g., kexec) */ 621 bool (*need_reset_on_init)(struct amdgpu_device *adev); 622 /* PCIe replay counter */ 623 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 624 /* device supports BACO */ 625 int (*supports_baco)(struct amdgpu_device *adev); 626 /* pre asic_init quirks */ 627 void (*pre_asic_init)(struct amdgpu_device *adev); 628 /* enter/exit umd stable pstate */ 629 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 630 /* query video codecs */ 631 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 632 const struct amdgpu_video_codecs **codecs); 633 /* encode "> 32bits" smn addressing */ 634 u64 (*encode_ext_smn_addressing)(int ext_id); 635 636 ssize_t (*get_reg_state)(struct amdgpu_device *adev, 637 enum amdgpu_reg_state reg_state, void *buf, 638 size_t max_size); 639 }; 640 641 /* 642 * IOCTL. 643 */ 644 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 645 struct drm_file *filp); 646 647 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 648 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 649 struct drm_file *filp); 650 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 651 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 652 struct drm_file *filp); 653 654 /* VRAM scratch page for HDP bug, default vram page */ 655 struct amdgpu_mem_scratch { 656 struct amdgpu_bo *robj; 657 volatile uint32_t *ptr; 658 u64 gpu_addr; 659 }; 660 661 /* 662 * CGS 663 */ 664 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 665 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 666 667 /* 668 * Core structure, functions and helpers. 669 */ 670 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 671 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 672 673 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t); 674 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t); 675 676 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 677 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 678 679 typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device*, uint64_t); 680 typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device*, uint64_t, uint64_t); 681 682 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 683 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 684 685 struct amdgpu_mmio_remap { 686 u32 reg_offset; 687 resource_size_t bus_addr; 688 }; 689 690 /* Define the HW IP blocks will be used in driver , add more if necessary */ 691 enum amd_hw_ip_block_type { 692 GC_HWIP = 1, 693 HDP_HWIP, 694 SDMA0_HWIP, 695 SDMA1_HWIP, 696 SDMA2_HWIP, 697 SDMA3_HWIP, 698 SDMA4_HWIP, 699 SDMA5_HWIP, 700 SDMA6_HWIP, 701 SDMA7_HWIP, 702 LSDMA_HWIP, 703 MMHUB_HWIP, 704 ATHUB_HWIP, 705 NBIO_HWIP, 706 MP0_HWIP, 707 MP1_HWIP, 708 UVD_HWIP, 709 VCN_HWIP = UVD_HWIP, 710 JPEG_HWIP = VCN_HWIP, 711 VCN1_HWIP, 712 VCE_HWIP, 713 VPE_HWIP, 714 DF_HWIP, 715 DCE_HWIP, 716 OSSSYS_HWIP, 717 SMUIO_HWIP, 718 PWR_HWIP, 719 NBIF_HWIP, 720 THM_HWIP, 721 CLK_HWIP, 722 UMC_HWIP, 723 RSMU_HWIP, 724 XGMI_HWIP, 725 DCI_HWIP, 726 PCIE_HWIP, 727 ISP_HWIP, 728 MAX_HWIP 729 }; 730 731 #define HWIP_MAX_INSTANCE 44 732 733 #define HW_ID_MAX 300 734 #define IP_VERSION_FULL(mj, mn, rv, var, srev) \ 735 (((mj) << 24) | ((mn) << 16) | ((rv) << 8) | ((var) << 4) | (srev)) 736 #define IP_VERSION(mj, mn, rv) IP_VERSION_FULL(mj, mn, rv, 0, 0) 737 #define IP_VERSION_MAJ(ver) ((ver) >> 24) 738 #define IP_VERSION_MIN(ver) (((ver) >> 16) & 0xFF) 739 #define IP_VERSION_REV(ver) (((ver) >> 8) & 0xFF) 740 #define IP_VERSION_VARIANT(ver) (((ver) >> 4) & 0xF) 741 #define IP_VERSION_SUBREV(ver) ((ver) & 0xF) 742 #define IP_VERSION_MAJ_MIN_REV(ver) ((ver) >> 8) 743 744 struct amdgpu_ip_map_info { 745 /* Map of logical to actual dev instances/mask */ 746 uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE]; 747 int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev, 748 enum amd_hw_ip_block_type block, 749 int8_t inst); 750 uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev, 751 enum amd_hw_ip_block_type block, 752 uint32_t mask); 753 }; 754 755 struct amd_powerplay { 756 void *pp_handle; 757 const struct amd_pm_funcs *pp_funcs; 758 }; 759 760 struct ip_discovery_top; 761 762 /* polaris10 kickers */ 763 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 764 ((rid == 0xE3) || \ 765 (rid == 0xE4) || \ 766 (rid == 0xE5) || \ 767 (rid == 0xE7) || \ 768 (rid == 0xEF))) || \ 769 ((did == 0x6FDF) && \ 770 ((rid == 0xE7) || \ 771 (rid == 0xEF) || \ 772 (rid == 0xFF)))) 773 774 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 775 ((rid == 0xE1) || \ 776 (rid == 0xF7))) 777 778 /* polaris11 kickers */ 779 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 780 ((rid == 0xE0) || \ 781 (rid == 0xE5))) || \ 782 ((did == 0x67FF) && \ 783 ((rid == 0xCF) || \ 784 (rid == 0xEF) || \ 785 (rid == 0xFF)))) 786 787 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 788 ((rid == 0xE2))) 789 790 /* polaris12 kickers */ 791 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 792 ((rid == 0xC0) || \ 793 (rid == 0xC1) || \ 794 (rid == 0xC3) || \ 795 (rid == 0xC7))) || \ 796 ((did == 0x6981) && \ 797 ((rid == 0x00) || \ 798 (rid == 0x01) || \ 799 (rid == 0x10)))) 800 801 struct amdgpu_mqd_prop { 802 uint64_t mqd_gpu_addr; 803 uint64_t hqd_base_gpu_addr; 804 uint64_t rptr_gpu_addr; 805 uint64_t wptr_gpu_addr; 806 uint32_t queue_size; 807 bool use_doorbell; 808 uint32_t doorbell_index; 809 uint64_t eop_gpu_addr; 810 uint32_t hqd_pipe_priority; 811 uint32_t hqd_queue_priority; 812 bool allow_tunneling; 813 bool hqd_active; 814 }; 815 816 struct amdgpu_mqd { 817 unsigned mqd_size; 818 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 819 struct amdgpu_mqd_prop *p); 820 }; 821 822 /* 823 * Custom Init levels could be defined for different situations where a full 824 * initialization of all hardware blocks are not expected. Sample cases are 825 * custom init sequences after resume after S0i3/S3, reset on initialization, 826 * partial reset of blocks etc. Presently, this defines only two levels. Levels 827 * are described in corresponding struct definitions - amdgpu_init_default, 828 * amdgpu_init_minimal_xgmi. 829 */ 830 enum amdgpu_init_lvl_id { 831 AMDGPU_INIT_LEVEL_DEFAULT, 832 AMDGPU_INIT_LEVEL_MINIMAL_XGMI, 833 }; 834 835 struct amdgpu_init_level { 836 enum amdgpu_init_lvl_id level; 837 uint32_t hwini_ip_block_mask; 838 }; 839 840 #define AMDGPU_RESET_MAGIC_NUM 64 841 #define AMDGPU_MAX_DF_PERFMONS 4 842 struct amdgpu_reset_domain; 843 struct amdgpu_fru_info; 844 845 /* 846 * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise. 847 */ 848 #define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size) 849 850 struct amdgpu_device { 851 struct device *dev; 852 struct pci_dev *pdev; 853 struct drm_device ddev; 854 855 #ifdef CONFIG_DRM_AMD_ACP 856 struct amdgpu_acp acp; 857 #endif 858 struct amdgpu_hive_info *hive; 859 struct amdgpu_xcp_mgr *xcp_mgr; 860 /* ASIC */ 861 enum amd_asic_type asic_type; 862 uint32_t family; 863 uint32_t rev_id; 864 uint32_t external_rev_id; 865 unsigned long flags; 866 unsigned long apu_flags; 867 int usec_timeout; 868 const struct amdgpu_asic_funcs *asic_funcs; 869 bool shutdown; 870 bool need_swiotlb; 871 bool accel_working; 872 struct notifier_block acpi_nb; 873 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 874 struct debugfs_blob_wrapper debugfs_vbios_blob; 875 struct debugfs_blob_wrapper debugfs_discovery_blob; 876 struct mutex srbm_mutex; 877 /* GRBM index mutex. Protects concurrent access to GRBM index */ 878 struct mutex grbm_idx_mutex; 879 struct dev_pm_domain vga_pm_domain; 880 bool have_disp_power_ref; 881 bool have_atomics_support; 882 883 /* BIOS */ 884 bool is_atom_fw; 885 uint8_t *bios; 886 uint32_t bios_size; 887 uint32_t bios_scratch_reg_offset; 888 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 889 890 /* Register/doorbell mmio */ 891 resource_size_t rmmio_base; 892 resource_size_t rmmio_size; 893 void __iomem *rmmio; 894 /* protects concurrent MM_INDEX/DATA based register access */ 895 spinlock_t mmio_idx_lock; 896 struct amdgpu_mmio_remap rmmio_remap; 897 /* protects concurrent SMC based register access */ 898 spinlock_t smc_idx_lock; 899 amdgpu_rreg_t smc_rreg; 900 amdgpu_wreg_t smc_wreg; 901 /* protects concurrent PCIE register access */ 902 spinlock_t pcie_idx_lock; 903 amdgpu_rreg_t pcie_rreg; 904 amdgpu_wreg_t pcie_wreg; 905 amdgpu_rreg_t pciep_rreg; 906 amdgpu_wreg_t pciep_wreg; 907 amdgpu_rreg_ext_t pcie_rreg_ext; 908 amdgpu_wreg_ext_t pcie_wreg_ext; 909 amdgpu_rreg64_t pcie_rreg64; 910 amdgpu_wreg64_t pcie_wreg64; 911 amdgpu_rreg64_ext_t pcie_rreg64_ext; 912 amdgpu_wreg64_ext_t pcie_wreg64_ext; 913 /* protects concurrent UVD register access */ 914 spinlock_t uvd_ctx_idx_lock; 915 amdgpu_rreg_t uvd_ctx_rreg; 916 amdgpu_wreg_t uvd_ctx_wreg; 917 /* protects concurrent DIDT register access */ 918 spinlock_t didt_idx_lock; 919 amdgpu_rreg_t didt_rreg; 920 amdgpu_wreg_t didt_wreg; 921 /* protects concurrent gc_cac register access */ 922 spinlock_t gc_cac_idx_lock; 923 amdgpu_rreg_t gc_cac_rreg; 924 amdgpu_wreg_t gc_cac_wreg; 925 /* protects concurrent se_cac register access */ 926 spinlock_t se_cac_idx_lock; 927 amdgpu_rreg_t se_cac_rreg; 928 amdgpu_wreg_t se_cac_wreg; 929 /* protects concurrent ENDPOINT (audio) register access */ 930 spinlock_t audio_endpt_idx_lock; 931 amdgpu_block_rreg_t audio_endpt_rreg; 932 amdgpu_block_wreg_t audio_endpt_wreg; 933 struct amdgpu_doorbell doorbell; 934 935 /* clock/pll info */ 936 struct amdgpu_clock clock; 937 938 /* MC */ 939 struct amdgpu_gmc gmc; 940 struct amdgpu_gart gart; 941 dma_addr_t dummy_page_addr; 942 struct amdgpu_vm_manager vm_manager; 943 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 944 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS); 945 946 /* memory management */ 947 struct amdgpu_mman mman; 948 struct amdgpu_mem_scratch mem_scratch; 949 struct amdgpu_wb wb; 950 atomic64_t num_bytes_moved; 951 atomic64_t num_evictions; 952 atomic64_t num_vram_cpu_page_faults; 953 atomic_t gpu_reset_counter; 954 atomic_t vram_lost_counter; 955 956 /* data for buffer migration throttling */ 957 struct { 958 spinlock_t lock; 959 s64 last_update_us; 960 s64 accum_us; /* accumulated microseconds */ 961 s64 accum_us_vis; /* for visible VRAM */ 962 u32 log2_max_MBps; 963 } mm_stats; 964 965 /* display */ 966 bool enable_virtual_display; 967 struct amdgpu_vkms_output *amdgpu_vkms_output; 968 struct amdgpu_mode_info mode_info; 969 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 970 struct delayed_work hotplug_work; 971 struct amdgpu_irq_src crtc_irq; 972 struct amdgpu_irq_src vline0_irq; 973 struct amdgpu_irq_src vupdate_irq; 974 struct amdgpu_irq_src pageflip_irq; 975 struct amdgpu_irq_src hpd_irq; 976 struct amdgpu_irq_src dmub_trace_irq; 977 struct amdgpu_irq_src dmub_outbox_irq; 978 979 /* rings */ 980 u64 fence_context; 981 unsigned num_rings; 982 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 983 struct dma_fence __rcu *gang_submit; 984 bool ib_pool_ready; 985 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 986 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 987 988 /* interrupts */ 989 struct amdgpu_irq irq; 990 991 /* powerplay */ 992 struct amd_powerplay powerplay; 993 struct amdgpu_pm pm; 994 u64 cg_flags; 995 u32 pg_flags; 996 997 /* nbio */ 998 struct amdgpu_nbio nbio; 999 1000 /* hdp */ 1001 struct amdgpu_hdp hdp; 1002 1003 /* smuio */ 1004 struct amdgpu_smuio smuio; 1005 1006 /* mmhub */ 1007 struct amdgpu_mmhub mmhub; 1008 1009 /* gfxhub */ 1010 struct amdgpu_gfxhub gfxhub; 1011 1012 /* gfx */ 1013 struct amdgpu_gfx gfx; 1014 1015 /* sdma */ 1016 struct amdgpu_sdma sdma; 1017 1018 /* lsdma */ 1019 struct amdgpu_lsdma lsdma; 1020 1021 /* uvd */ 1022 struct amdgpu_uvd uvd; 1023 1024 /* vce */ 1025 struct amdgpu_vce vce; 1026 1027 /* vcn */ 1028 struct amdgpu_vcn vcn; 1029 1030 /* jpeg */ 1031 struct amdgpu_jpeg jpeg; 1032 1033 /* vpe */ 1034 struct amdgpu_vpe vpe; 1035 1036 /* umsch */ 1037 struct amdgpu_umsch_mm umsch_mm; 1038 bool enable_umsch_mm; 1039 1040 /* firmwares */ 1041 struct amdgpu_firmware firmware; 1042 1043 /* PSP */ 1044 struct psp_context psp; 1045 1046 /* GDS */ 1047 struct amdgpu_gds gds; 1048 1049 /* for userq and VM fences */ 1050 struct amdgpu_seq64 seq64; 1051 1052 /* KFD */ 1053 struct amdgpu_kfd_dev kfd; 1054 1055 /* UMC */ 1056 struct amdgpu_umc umc; 1057 1058 /* display related functionality */ 1059 struct amdgpu_display_manager dm; 1060 1061 #if defined(CONFIG_DRM_AMD_ISP) 1062 /* isp */ 1063 struct amdgpu_isp isp; 1064 #endif 1065 1066 /* mes */ 1067 bool enable_mes; 1068 bool enable_mes_kiq; 1069 bool enable_uni_mes; 1070 struct amdgpu_mes mes; 1071 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 1072 1073 /* df */ 1074 struct amdgpu_df df; 1075 1076 /* MCA */ 1077 struct amdgpu_mca mca; 1078 1079 /* ACA */ 1080 struct amdgpu_aca aca; 1081 1082 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1083 uint32_t harvest_ip_mask; 1084 int num_ip_blocks; 1085 struct mutex mn_lock; 1086 DECLARE_HASHTABLE(mn_hash, 7); 1087 1088 /* tracking pinned memory */ 1089 atomic64_t vram_pin_size; 1090 atomic64_t visible_pin_size; 1091 atomic64_t gart_pin_size; 1092 1093 /* soc15 register offset based on ip, instance and segment */ 1094 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1095 struct amdgpu_ip_map_info ip_map; 1096 1097 /* delayed work_func for deferring clockgating during resume */ 1098 struct delayed_work delayed_init_work; 1099 1100 struct amdgpu_virt virt; 1101 1102 /* record hw reset is performed */ 1103 bool has_hw_reset; 1104 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1105 1106 /* s3/s4 mask */ 1107 bool in_suspend; 1108 bool in_s3; 1109 bool in_s4; 1110 bool in_s0ix; 1111 /* indicate amdgpu suspension status */ 1112 bool suspend_complete; 1113 1114 enum pp_mp1_state mp1_state; 1115 struct amdgpu_doorbell_index doorbell_index; 1116 1117 struct mutex notifier_lock; 1118 1119 int asic_reset_res; 1120 struct work_struct xgmi_reset_work; 1121 struct list_head reset_list; 1122 1123 long gfx_timeout; 1124 long sdma_timeout; 1125 long video_timeout; 1126 long compute_timeout; 1127 long psp_timeout; 1128 1129 uint64_t unique_id; 1130 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1131 1132 /* enable runtime pm on the device */ 1133 bool in_runpm; 1134 bool has_pr3; 1135 1136 bool ucode_sysfs_en; 1137 1138 struct amdgpu_fru_info *fru_info; 1139 atomic_t throttling_logging_enabled; 1140 struct ratelimit_state throttling_logging_rs; 1141 uint32_t ras_hw_enabled; 1142 uint32_t ras_enabled; 1143 1144 bool no_hw_access; 1145 struct pci_saved_state *pci_state; 1146 pci_channel_state_t pci_channel_state; 1147 1148 /* Track auto wait count on s_barrier settings */ 1149 bool barrier_has_auto_waitcnt; 1150 1151 struct amdgpu_reset_control *reset_cntl; 1152 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1153 1154 bool ram_is_direct_mapped; 1155 1156 struct list_head ras_list; 1157 1158 struct ip_discovery_top *ip_top; 1159 1160 struct amdgpu_reset_domain *reset_domain; 1161 1162 struct mutex benchmark_mutex; 1163 1164 bool scpm_enabled; 1165 uint32_t scpm_status; 1166 1167 struct work_struct reset_work; 1168 1169 bool job_hang; 1170 bool dc_enabled; 1171 /* Mask of active clusters */ 1172 uint32_t aid_mask; 1173 1174 /* Debug */ 1175 bool debug_vm; 1176 bool debug_largebar; 1177 bool debug_disable_soft_recovery; 1178 bool debug_use_vram_fw_buf; 1179 bool debug_enable_ras_aca; 1180 bool debug_exp_resets; 1181 1182 bool enforce_isolation[MAX_XCP]; 1183 /* Added this mutex for cleaner shader isolation between GFX and compute processes */ 1184 struct mutex enforce_isolation_mutex; 1185 1186 struct amdgpu_init_level *init_lvl; 1187 }; 1188 1189 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, 1190 uint8_t ip, uint8_t inst) 1191 { 1192 /* This considers only major/minor/rev and ignores 1193 * subrevision/variant fields. 1194 */ 1195 return adev->ip_versions[ip][inst] & ~0xFFU; 1196 } 1197 1198 static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev, 1199 uint8_t ip, uint8_t inst) 1200 { 1201 /* This returns full version - major/minor/rev/variant/subrevision */ 1202 return adev->ip_versions[ip][inst]; 1203 } 1204 1205 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1206 { 1207 return container_of(ddev, struct amdgpu_device, ddev); 1208 } 1209 1210 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1211 { 1212 return &adev->ddev; 1213 } 1214 1215 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1216 { 1217 return container_of(bdev, struct amdgpu_device, mman.bdev); 1218 } 1219 1220 int amdgpu_device_init(struct amdgpu_device *adev, 1221 uint32_t flags); 1222 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1223 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1224 1225 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1226 1227 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1228 void *buf, size_t size, bool write); 1229 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1230 void *buf, size_t size, bool write); 1231 1232 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1233 void *buf, size_t size, bool write); 1234 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, 1235 uint32_t inst, uint32_t reg_addr, char reg_name[], 1236 uint32_t expected_value, uint32_t mask); 1237 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1238 uint32_t reg, uint32_t acc_flags); 1239 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, 1240 u64 reg_addr); 1241 uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, 1242 uint32_t reg, uint32_t acc_flags, 1243 uint32_t xcc_id); 1244 void amdgpu_device_wreg(struct amdgpu_device *adev, 1245 uint32_t reg, uint32_t v, 1246 uint32_t acc_flags); 1247 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, 1248 u64 reg_addr, u32 reg_data); 1249 void amdgpu_device_xcc_wreg(struct amdgpu_device *adev, 1250 uint32_t reg, uint32_t v, 1251 uint32_t acc_flags, 1252 uint32_t xcc_id); 1253 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1254 uint32_t reg, uint32_t v, uint32_t xcc_id); 1255 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1256 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1257 1258 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1259 u32 reg_addr); 1260 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1261 u32 reg_addr); 1262 u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, 1263 u64 reg_addr); 1264 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1265 u32 reg_addr, u32 reg_data); 1266 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1267 u32 reg_addr, u64 reg_data); 1268 void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, 1269 u64 reg_addr, u64 reg_data); 1270 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev); 1271 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1272 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1273 1274 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev); 1275 1276 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1277 struct amdgpu_reset_context *reset_context); 1278 1279 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1280 struct amdgpu_reset_context *reset_context); 1281 1282 int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context); 1283 1284 int emu_soc_asic_init(struct amdgpu_device *adev); 1285 1286 /* 1287 * Registers read & write functions. 1288 */ 1289 #define AMDGPU_REGS_NO_KIQ (1<<1) 1290 #define AMDGPU_REGS_RLC (1<<2) 1291 1292 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1293 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1294 1295 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0) 1296 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0) 1297 1298 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1299 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1300 1301 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1302 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1303 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1304 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1305 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1306 #define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst) 1307 #define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst) 1308 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1309 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1310 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1311 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1312 #define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg)) 1313 #define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v)) 1314 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1315 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1316 #define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg)) 1317 #define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v)) 1318 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1319 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1320 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1321 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1322 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1323 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1324 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1325 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1326 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1327 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1328 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1329 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1330 #define WREG32_P(reg, val, mask) \ 1331 do { \ 1332 uint32_t tmp_ = RREG32(reg); \ 1333 tmp_ &= (mask); \ 1334 tmp_ |= ((val) & ~(mask)); \ 1335 WREG32(reg, tmp_); \ 1336 } while (0) 1337 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1338 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1339 #define WREG32_PLL_P(reg, val, mask) \ 1340 do { \ 1341 uint32_t tmp_ = RREG32_PLL(reg); \ 1342 tmp_ &= (mask); \ 1343 tmp_ |= ((val) & ~(mask)); \ 1344 WREG32_PLL(reg, tmp_); \ 1345 } while (0) 1346 1347 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1348 do { \ 1349 u32 tmp = RREG32_SMC(_Reg); \ 1350 tmp &= (_Mask); \ 1351 tmp |= ((_Val) & ~(_Mask)); \ 1352 WREG32_SMC(_Reg, tmp); \ 1353 } while (0) 1354 1355 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1356 1357 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1358 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1359 1360 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1361 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1362 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1363 1364 #define REG_GET_FIELD(value, reg, field) \ 1365 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1366 1367 #define WREG32_FIELD(reg, field, val) \ 1368 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1369 1370 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1371 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1372 1373 #define AMDGPU_GET_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> (l)) 1374 /* 1375 * BIOS helpers. 1376 */ 1377 #define RBIOS8(i) (adev->bios[i]) 1378 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1379 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1380 1381 /* 1382 * ASICs macro. 1383 */ 1384 #define amdgpu_asic_set_vga_state(adev, state) \ 1385 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0) 1386 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1387 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1388 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1389 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1390 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1391 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1392 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1393 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1394 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1395 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1396 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1397 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1398 #define amdgpu_asic_flush_hdp(adev, r) \ 1399 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1400 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1401 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \ 1402 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0)) 1403 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1404 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1405 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1406 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1407 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1408 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1409 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1410 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1411 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1412 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1413 1414 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)) 1415 1416 #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i)) 1417 #define for_each_inst(i, inst_mask) \ 1418 for (i = ffs(inst_mask); i-- != 0; \ 1419 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1))) 1420 1421 /* Common functions */ 1422 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1423 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1424 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1425 struct amdgpu_job *job, 1426 struct amdgpu_reset_context *reset_context); 1427 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1428 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1429 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1430 bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev); 1431 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1432 1433 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1434 u64 num_vis_bytes); 1435 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1436 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1437 const u32 *registers, 1438 const u32 array_size); 1439 1440 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1441 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1442 bool amdgpu_device_supports_px(struct drm_device *dev); 1443 bool amdgpu_device_supports_boco(struct drm_device *dev); 1444 bool amdgpu_device_supports_smart_shift(struct drm_device *dev); 1445 int amdgpu_device_supports_baco(struct drm_device *dev); 1446 void amdgpu_device_detect_runtime_pm_mode(struct amdgpu_device *adev); 1447 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1448 struct amdgpu_device *peer_adev); 1449 int amdgpu_device_baco_enter(struct drm_device *dev); 1450 int amdgpu_device_baco_exit(struct drm_device *dev); 1451 1452 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1453 struct amdgpu_ring *ring); 1454 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1455 struct amdgpu_ring *ring); 1456 1457 void amdgpu_device_halt(struct amdgpu_device *adev); 1458 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, 1459 u32 reg); 1460 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, 1461 u32 reg, u32 v); 1462 struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev); 1463 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1464 struct dma_fence *gang); 1465 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1466 1467 /* atpx handler */ 1468 #if defined(CONFIG_VGA_SWITCHEROO) 1469 void amdgpu_register_atpx_handler(void); 1470 void amdgpu_unregister_atpx_handler(void); 1471 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1472 bool amdgpu_is_atpx_hybrid(void); 1473 bool amdgpu_has_atpx(void); 1474 #else 1475 static inline void amdgpu_register_atpx_handler(void) {} 1476 static inline void amdgpu_unregister_atpx_handler(void) {} 1477 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1478 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1479 static inline bool amdgpu_has_atpx(void) { return false; } 1480 #endif 1481 1482 /* 1483 * KMS 1484 */ 1485 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1486 extern const int amdgpu_max_kms_ioctl; 1487 1488 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1489 void amdgpu_driver_unload_kms(struct drm_device *dev); 1490 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1491 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1492 struct drm_file *file_priv); 1493 void amdgpu_driver_release_kms(struct drm_device *dev); 1494 1495 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1496 int amdgpu_device_prepare(struct drm_device *dev); 1497 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1498 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1499 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1500 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1501 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1502 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1503 struct drm_file *filp); 1504 1505 /* 1506 * functions used by amdgpu_encoder.c 1507 */ 1508 struct amdgpu_afmt_acr { 1509 u32 clock; 1510 1511 int n_32khz; 1512 int cts_32khz; 1513 1514 int n_44_1khz; 1515 int cts_44_1khz; 1516 1517 int n_48khz; 1518 int cts_48khz; 1519 1520 }; 1521 1522 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1523 1524 /* amdgpu_acpi.c */ 1525 1526 struct amdgpu_numa_info { 1527 uint64_t size; 1528 int pxm; 1529 int nid; 1530 }; 1531 1532 /* ATCS Device/Driver State */ 1533 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1534 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1535 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1536 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1537 1538 #if defined(CONFIG_ACPI) 1539 int amdgpu_acpi_init(struct amdgpu_device *adev); 1540 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1541 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1542 bool amdgpu_acpi_is_power_shift_control_supported(void); 1543 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1544 u8 perf_req, bool advertise); 1545 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1546 u8 dev_state, bool drv_state); 1547 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state); 1548 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1549 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, 1550 u64 *tmr_size); 1551 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, 1552 struct amdgpu_numa_info *numa_info); 1553 1554 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1555 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1556 void amdgpu_acpi_detect(void); 1557 void amdgpu_acpi_release(void); 1558 #else 1559 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1560 static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, 1561 u64 *tmr_offset, u64 *tmr_size) 1562 { 1563 return -EINVAL; 1564 } 1565 static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, 1566 int xcc_id, 1567 struct amdgpu_numa_info *numa_info) 1568 { 1569 return -EINVAL; 1570 } 1571 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1572 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1573 static inline void amdgpu_acpi_detect(void) { } 1574 static inline void amdgpu_acpi_release(void) { } 1575 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1576 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1577 u8 dev_state, bool drv_state) { return 0; } 1578 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, 1579 enum amdgpu_ss ss_state) { return 0; } 1580 static inline void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps) { } 1581 #endif 1582 1583 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1584 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1585 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1586 void amdgpu_choose_low_power_state(struct amdgpu_device *adev); 1587 #else 1588 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1589 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1590 static inline void amdgpu_choose_low_power_state(struct amdgpu_device *adev) { } 1591 #endif 1592 1593 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1594 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1595 1596 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1597 pci_channel_state_t state); 1598 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1599 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1600 void amdgpu_pci_resume(struct pci_dev *pdev); 1601 1602 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1603 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1604 1605 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1606 1607 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1608 enum amd_clockgating_state state); 1609 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1610 enum amd_powergating_state state); 1611 1612 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1613 { 1614 return amdgpu_gpu_recovery != 0 && 1615 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1616 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1617 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1618 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1619 } 1620 1621 #include "amdgpu_object.h" 1622 1623 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1624 { 1625 return adev->gmc.tmz_enabled; 1626 } 1627 1628 int amdgpu_in_reset(struct amdgpu_device *adev); 1629 1630 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 1631 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 1632 extern const struct attribute_group amdgpu_flash_attr_group; 1633 1634 void amdgpu_set_init_level(struct amdgpu_device *adev, 1635 enum amdgpu_init_lvl_id lvl); 1636 #endif 1637