1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #include "amdgpu_ctx.h" 38 39 #include <linux/atomic.h> 40 #include <linux/wait.h> 41 #include <linux/list.h> 42 #include <linux/kref.h> 43 #include <linux/rbtree.h> 44 #include <linux/hashtable.h> 45 #include <linux/dma-fence.h> 46 #include <linux/pci.h> 47 #include <linux/xarray.h> 48 49 #include <drm/ttm/ttm_bo.h> 50 #include <drm/ttm/ttm_placement.h> 51 52 #include <drm/amdgpu_drm.h> 53 #include <drm/drm_gem.h> 54 #include <drm/drm_ioctl.h> 55 56 #include <kgd_kfd_interface.h> 57 #include "dm_pp_interface.h" 58 #include "kgd_pp_interface.h" 59 60 #include "amd_shared.h" 61 #include "amdgpu_utils.h" 62 #include "amdgpu_mode.h" 63 #include "amdgpu_ih.h" 64 #include "amdgpu_irq.h" 65 #include "amdgpu_ucode.h" 66 #include "amdgpu_ttm.h" 67 #include "amdgpu_psp.h" 68 #include "amdgpu_gds.h" 69 #include "amdgpu_sync.h" 70 #include "amdgpu_ring.h" 71 #include "amdgpu_vm.h" 72 #include "amdgpu_dpm.h" 73 #include "amdgpu_acp.h" 74 #include "amdgpu_uvd.h" 75 #include "amdgpu_vce.h" 76 #include "amdgpu_vcn.h" 77 #include "amdgpu_jpeg.h" 78 #include "amdgpu_vpe.h" 79 #include "amdgpu_umsch_mm.h" 80 #include "amdgpu_gmc.h" 81 #include "amdgpu_gfx.h" 82 #include "amdgpu_sdma.h" 83 #include "amdgpu_lsdma.h" 84 #include "amdgpu_nbio.h" 85 #include "amdgpu_reg_access.h" 86 #include "amdgpu_hdp.h" 87 #include "amdgpu_dm.h" 88 #include "amdgpu_virt.h" 89 #include "amdgpu_csa.h" 90 #include "amdgpu_mes_ctx.h" 91 #include "amdgpu_gart.h" 92 #include "amdgpu_debugfs.h" 93 #include "amdgpu_job.h" 94 #include "amdgpu_bo_list.h" 95 #include "amdgpu_gem.h" 96 #include "amdgpu_doorbell.h" 97 #include "amdgpu_amdkfd.h" 98 #include "amdgpu_discovery.h" 99 #include "amdgpu_mes.h" 100 #include "amdgpu_umc.h" 101 #include "amdgpu_mmhub.h" 102 #include "amdgpu_gfxhub.h" 103 #include "amdgpu_df.h" 104 #include "amdgpu_smuio.h" 105 #include "amdgpu_fdinfo.h" 106 #include "amdgpu_mca.h" 107 #include "amdgpu_ras.h" 108 #include "amdgpu_lockdep.h" 109 #include "amdgpu_cper.h" 110 #include "amdgpu_xcp.h" 111 #include "amdgpu_seq64.h" 112 #include "amdgpu_reg_state.h" 113 #include "amdgpu_userq.h" 114 #include "amdgpu_eviction_fence.h" 115 #include "amdgpu_ip.h" 116 #include "amdgpu_sa.h" 117 #if defined(CONFIG_DRM_AMD_ISP) 118 #include "amdgpu_isp.h" 119 #endif 120 121 #define MAX_GPU_INSTANCE 64 122 123 #define GFX_SLICE_PERIOD_MS 250 124 125 struct amdgpu_gpu_instance { 126 struct amdgpu_device *adev; 127 int mgpu_fan_enabled; 128 }; 129 130 struct amdgpu_mgpu_info { 131 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 132 struct mutex mutex; 133 uint32_t num_gpu; 134 uint32_t num_dgpu; 135 uint32_t num_apu; 136 }; 137 138 enum amdgpu_ss { 139 AMDGPU_SS_DRV_LOAD, 140 AMDGPU_SS_DEV_D0, 141 AMDGPU_SS_DEV_D3, 142 AMDGPU_SS_DRV_UNLOAD 143 }; 144 145 struct amdgpu_hwip_reg_entry { 146 u32 hwip; 147 u32 inst; 148 u32 seg; 149 u32 reg_offset; 150 const char *reg_name; 151 }; 152 153 struct amdgpu_watchdog_timer { 154 bool timeout_fatal_disable; 155 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 156 }; 157 158 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 159 160 /* 161 * Modules parameters. 162 */ 163 extern int amdgpu_modeset; 164 extern unsigned int amdgpu_vram_limit; 165 extern int amdgpu_vis_vram_limit; 166 extern int amdgpu_gart_size; 167 extern int amdgpu_gtt_size; 168 extern int amdgpu_moverate; 169 extern int amdgpu_audio; 170 extern int amdgpu_disp_priority; 171 extern int amdgpu_hw_i2c; 172 extern int amdgpu_pcie_gen2; 173 extern int amdgpu_msi; 174 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 175 extern int amdgpu_dpm; 176 extern int amdgpu_fw_load_type; 177 extern int amdgpu_aspm; 178 extern int amdgpu_runtime_pm; 179 extern uint amdgpu_ip_block_mask; 180 extern int amdgpu_bapm; 181 extern int amdgpu_deep_color; 182 extern int amdgpu_vm_size; 183 extern int amdgpu_vm_block_size; 184 extern int amdgpu_vm_fragment_size; 185 extern int amdgpu_vm_fault_stop; 186 extern int amdgpu_vm_debug; 187 extern int amdgpu_vm_update_mode; 188 extern int amdgpu_exp_hw_support; 189 extern int amdgpu_dc; 190 extern int amdgpu_sched_jobs; 191 extern int amdgpu_sched_hw_submission; 192 extern uint amdgpu_pcie_gen_cap; 193 extern uint amdgpu_pcie_lane_cap; 194 extern u64 amdgpu_cg_mask; 195 extern uint amdgpu_pg_mask; 196 extern uint amdgpu_sdma_phase_quantum; 197 extern char *amdgpu_disable_cu; 198 extern char *amdgpu_virtual_display; 199 extern uint amdgpu_pp_feature_mask; 200 extern uint amdgpu_force_long_training; 201 extern int amdgpu_lbpw; 202 extern int amdgpu_compute_multipipe; 203 extern int amdgpu_gpu_recovery; 204 extern int amdgpu_emu_mode; 205 extern uint amdgpu_smu_memory_pool_size; 206 extern int amdgpu_smu_pptable_id; 207 extern uint amdgpu_dc_feature_mask; 208 extern uint amdgpu_freesync_vid_mode; 209 extern uint amdgpu_dc_debug_mask; 210 extern uint amdgpu_dc_visual_confirm; 211 extern int amdgpu_dm_abm_level; 212 extern int amdgpu_backlight; 213 extern int amdgpu_damage_clips; 214 extern struct amdgpu_mgpu_info mgpu_info; 215 extern int amdgpu_ras_enable; 216 extern uint amdgpu_ras_mask; 217 extern int amdgpu_bad_page_threshold; 218 extern bool amdgpu_ignore_bad_page_threshold; 219 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 220 extern int amdgpu_async_gfx_ring; 221 extern int amdgpu_mcbp; 222 extern int amdgpu_discovery; 223 extern int amdgpu_mes_log_enable; 224 extern int amdgpu_uni_mes; 225 extern int amdgpu_noretry; 226 extern int amdgpu_force_asic_type; 227 extern int amdgpu_smartshift_bias; 228 extern int amdgpu_use_xgmi_p2p; 229 extern int amdgpu_mtype_local; 230 extern int amdgpu_enforce_isolation; 231 #ifdef CONFIG_HSA_AMD 232 extern int sched_policy; 233 extern bool debug_evictions; 234 extern bool no_system_mem_limit; 235 extern int halt_if_hws_hang; 236 extern uint amdgpu_svm_default_granularity; 237 #else 238 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 239 static const bool __maybe_unused debug_evictions; /* = false */ 240 static const bool __maybe_unused no_system_mem_limit; 241 static const int __maybe_unused halt_if_hws_hang; 242 #endif 243 #ifdef CONFIG_HSA_AMD_P2P 244 extern bool pcie_p2p; 245 #endif 246 247 extern int amdgpu_tmz; 248 extern int amdgpu_reset_method; 249 250 #ifdef CONFIG_DRM_AMDGPU_SI 251 extern int amdgpu_si_support; 252 #endif 253 #ifdef CONFIG_DRM_AMDGPU_CIK 254 extern int amdgpu_cik_support; 255 #endif 256 extern int amdgpu_num_kcq; 257 258 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 259 #define AMDGPU_UMSCHFW_LOG_SIZE (32 * 1024) 260 extern int amdgpu_vcnfw_log; 261 extern int amdgpu_sg_display; 262 extern int amdgpu_umsch_mm; 263 extern int amdgpu_seamless; 264 extern int amdgpu_umsch_mm_fwlog; 265 266 extern int amdgpu_user_partt_mode; 267 extern int amdgpu_agp; 268 extern int amdgpu_rebar; 269 270 extern int amdgpu_wbrf; 271 extern int amdgpu_user_queue; 272 extern int amdgpu_ptl; 273 274 extern uint amdgpu_hdmi_hpd_debounce_delay_ms; 275 276 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 277 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 278 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 279 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 280 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 281 #define AMDGPUFB_CONN_LIMIT 4 282 #define AMDGPU_BIOS_NUM_SCRATCH 16 283 284 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 285 286 /* hard reset data */ 287 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 288 289 /* reset flags */ 290 #define AMDGPU_RESET_GFX (1 << 0) 291 #define AMDGPU_RESET_COMPUTE (1 << 1) 292 #define AMDGPU_RESET_DMA (1 << 2) 293 #define AMDGPU_RESET_CP (1 << 3) 294 #define AMDGPU_RESET_GRBM (1 << 4) 295 #define AMDGPU_RESET_DMA1 (1 << 5) 296 #define AMDGPU_RESET_RLC (1 << 6) 297 #define AMDGPU_RESET_SEM (1 << 7) 298 #define AMDGPU_RESET_IH (1 << 8) 299 #define AMDGPU_RESET_VMC (1 << 9) 300 #define AMDGPU_RESET_MC (1 << 10) 301 #define AMDGPU_RESET_DISPLAY (1 << 11) 302 #define AMDGPU_RESET_UVD (1 << 12) 303 #define AMDGPU_RESET_VCE (1 << 13) 304 #define AMDGPU_RESET_VCE1 (1 << 14) 305 306 /* reset mask */ 307 #define AMDGPU_RESET_TYPE_FULL (1 << 0) /* full adapter reset, mode1/mode2/BACO/etc. */ 308 #define AMDGPU_RESET_TYPE_SOFT_RECOVERY (1 << 1) /* soft recovery, eg. kill shaders */ 309 #define AMDGPU_RESET_TYPE_PER_QUEUE (1 << 2) /* per queue */ 310 #define AMDGPU_RESET_TYPE_PER_PIPE (1 << 3) /* per pipe */ 311 #define AMDGPU_RESET_TYPE_IP_BLOCK_SOFT_RESET (1 << 4) /* soft-resets an IP block */ 312 313 /* max cursor sizes (in pixels) */ 314 #define CIK_CURSOR_WIDTH 128 315 #define CIK_CURSOR_HEIGHT 128 316 317 /* smart shift bias level limits */ 318 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 319 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 320 321 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */ 322 #define AMDGPU_SWCTF_EXTRA_DELAY 50 323 324 struct amdgpu_xcp_mgr; 325 struct amdgpu_device; 326 struct amdgpu_irq_src; 327 struct amdgpu_fpriv; 328 struct amdgpu_bo_va_mapping; 329 struct kfd_vm_fault_info; 330 struct amdgpu_hive_info; 331 struct amdgpu_reset_context; 332 struct amdgpu_reset_control; 333 struct amdgpu_coredump_info; 334 335 enum amdgpu_cp_irq { 336 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 337 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 338 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 339 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 340 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 341 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 342 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 343 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 344 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 345 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 346 347 AMDGPU_CP_IRQ_LAST 348 }; 349 350 enum amdgpu_thermal_irq { 351 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 352 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 353 354 AMDGPU_THERMAL_IRQ_LAST 355 }; 356 357 enum amdgpu_kiq_irq { 358 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 359 AMDGPU_CP_KIQ_IRQ_LAST 360 }; 361 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 362 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 363 #define MAX_KIQ_REG_TRY 1000 364 365 /* 366 * BIOS. 367 */ 368 bool amdgpu_get_bios(struct amdgpu_device *adev); 369 bool amdgpu_read_bios(struct amdgpu_device *adev); 370 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 371 u8 *bios, u32 length_bytes); 372 void amdgpu_bios_release(struct amdgpu_device *adev); 373 /* 374 * Clocks 375 */ 376 377 #define AMDGPU_MAX_PPLL 3 378 379 struct amdgpu_clock { 380 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 381 struct amdgpu_pll spll; 382 struct amdgpu_pll mpll; 383 /* 10 Khz units */ 384 uint32_t default_mclk; 385 uint32_t default_sclk; 386 uint32_t default_dispclk; 387 uint32_t dp_extclk; 388 uint32_t max_pixel_clock; 389 }; 390 391 /* 392 * IRQS. 393 */ 394 395 struct amdgpu_flip_work { 396 struct delayed_work flip_work; 397 struct work_struct unpin_work; 398 struct amdgpu_device *adev; 399 int crtc_id; 400 u32 target_vblank; 401 uint64_t base; 402 struct drm_pending_vblank_event *event; 403 struct amdgpu_bo *old_abo; 404 unsigned shared_count; 405 struct dma_fence **shared; 406 struct dma_fence_cb cb; 407 bool async; 408 }; 409 410 /* 411 * file private structure 412 */ 413 414 struct amdgpu_fpriv { 415 struct amdgpu_vm vm; 416 struct amdgpu_bo_va *prt_va; 417 struct amdgpu_bo_va *csa_va; 418 struct amdgpu_bo_va *seq64_va; 419 struct xarray bo_list_handles; 420 struct amdgpu_ctx_mgr ctx_mgr; 421 struct amdgpu_userq_mgr userq_mgr; 422 423 /* Eviction fence infra */ 424 struct amdgpu_eviction_fence_mgr evf_mgr; 425 426 /** GPU partition selection */ 427 uint32_t xcp_id; 428 }; 429 430 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 431 432 /* 433 * Writeback 434 */ 435 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 436 437 /** 438 * struct amdgpu_wb - This struct is used for small GPU memory allocation. 439 * 440 * This struct is used to allocate a small amount of GPU memory that can be 441 * used to shadow certain states into the memory. This is especially useful for 442 * providing easy CPU access to some states without requiring register access 443 * (e.g., if some block is power gated, reading register may be problematic). 444 * 445 * Note: the term writeback was initially used because many of the amdgpu 446 * components had some level of writeback memory, and this struct initially 447 * described those components. 448 */ 449 struct amdgpu_wb { 450 451 /** 452 * @wb_obj: 453 * 454 * Buffer Object used for the writeback memory. 455 */ 456 struct amdgpu_bo *wb_obj; 457 458 /** 459 * @wb: 460 * 461 * Pointer to the first writeback slot. In terms of CPU address 462 * this value can be accessed directly by using the offset as an index. 463 * For the GPU address, it is necessary to use gpu_addr and the offset. 464 */ 465 uint32_t *wb; 466 467 /** 468 * @gpu_addr: 469 * 470 * Writeback base address in the GPU. 471 */ 472 uint64_t gpu_addr; 473 474 /** 475 * @num_wb: 476 * 477 * Number of writeback slots reserved for amdgpu. 478 */ 479 u32 num_wb; 480 481 /** 482 * @used: 483 * 484 * Track the writeback slot already used. 485 */ 486 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 487 488 /** 489 * @lock: 490 * 491 * Protects read and write of the used field array. 492 */ 493 spinlock_t lock; 494 }; 495 496 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 497 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 498 499 /* 500 * Benchmarking 501 */ 502 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 503 504 /* 505 * ASIC specific register table accessible by UMD 506 */ 507 struct amdgpu_allowed_register_entry { 508 uint32_t reg_offset; 509 bool grbm_indexed; 510 }; 511 512 struct amdgpu_video_codec_info { 513 u32 codec_type; 514 u32 max_width; 515 u32 max_height; 516 u32 max_pixels_per_frame; 517 u32 max_level; 518 }; 519 520 #define codec_info_build(type, width, height, level) \ 521 .codec_type = type,\ 522 .max_width = width,\ 523 .max_height = height,\ 524 .max_pixels_per_frame = height * width,\ 525 .max_level = level, 526 527 struct amdgpu_video_codecs { 528 const u32 codec_count; 529 const struct amdgpu_video_codec_info *codec_array; 530 }; 531 532 /* 533 * ASIC specific functions. 534 */ 535 struct amdgpu_asic_funcs { 536 bool (*read_disabled_bios)(struct amdgpu_device *adev); 537 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 538 u8 *bios, u32 length_bytes); 539 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 540 u32 sh_num, u32 reg_offset, u32 *value); 541 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 542 int (*reset)(struct amdgpu_device *adev); 543 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 544 /* get the reference clock */ 545 u32 (*get_xclk)(struct amdgpu_device *adev); 546 /* MM block clocks */ 547 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 548 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 549 /* static power management */ 550 int (*get_pcie_lanes)(struct amdgpu_device *adev); 551 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 552 /* get config memsize register */ 553 u32 (*get_config_memsize)(struct amdgpu_device *adev); 554 /* flush hdp write queue */ 555 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 556 /* invalidate hdp read cache */ 557 void (*invalidate_hdp)(struct amdgpu_device *adev, 558 struct amdgpu_ring *ring); 559 /* initialize doorbell layout for specific asic*/ 560 void (*init_doorbell_index)(struct amdgpu_device *adev); 561 /* PCIe bandwidth usage */ 562 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 563 uint64_t *count1); 564 /* do we need to reset the asic at init time (e.g., kexec) */ 565 bool (*need_reset_on_init)(struct amdgpu_device *adev); 566 /* PCIe replay counter */ 567 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 568 /* device supports BACO */ 569 int (*supports_baco)(struct amdgpu_device *adev); 570 /* pre asic_init quirks */ 571 void (*pre_asic_init)(struct amdgpu_device *adev); 572 /* enter/exit umd stable pstate */ 573 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 574 /* query video codecs */ 575 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 576 const struct amdgpu_video_codecs **codecs); 577 /* encode "> 32bits" smn addressing */ 578 u64 (*encode_ext_smn_addressing)(int ext_id); 579 580 ssize_t (*get_reg_state)(struct amdgpu_device *adev, 581 enum amdgpu_reg_state reg_state, void *buf, 582 size_t max_size); 583 }; 584 585 /* 586 * IOCTL. 587 */ 588 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 589 struct drm_file *filp); 590 591 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 592 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 593 struct drm_file *filp); 594 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 595 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 596 struct drm_file *filp); 597 598 /* VRAM scratch page for HDP bug, default vram page */ 599 struct amdgpu_mem_scratch { 600 struct amdgpu_bo *robj; 601 uint32_t *ptr; 602 u64 gpu_addr; 603 }; 604 605 /* 606 * CGS 607 */ 608 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 609 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 610 611 /* 612 * Core structure, functions and helpers. 613 */ 614 struct amdgpu_mmio_remap { 615 u32 reg_offset; 616 resource_size_t bus_addr; 617 struct amdgpu_bo *bo; 618 }; 619 620 enum amdgpu_uid_type { 621 AMDGPU_UID_TYPE_XCD, 622 AMDGPU_UID_TYPE_AID, 623 AMDGPU_UID_TYPE_SOC, 624 AMDGPU_UID_TYPE_MID, 625 AMDGPU_UID_TYPE_MAX 626 }; 627 628 #define AMDGPU_UID_INST_MAX 8 /* max number of instances for each UID type */ 629 630 struct amdgpu_uid { 631 uint64_t uid[AMDGPU_UID_TYPE_MAX][AMDGPU_UID_INST_MAX]; 632 struct amdgpu_device *adev; 633 }; 634 635 #define MAX_UMA_OPTION_NAME 28 636 #define MAX_UMA_OPTION_ENTRIES 19 637 638 #define AMDGPU_UMA_FLAG_AUTO BIT(1) 639 #define AMDGPU_UMA_FLAG_CUSTOM BIT(0) 640 641 /** 642 * struct amdgpu_uma_carveout_option - single UMA carveout option 643 * @name: Name of the carveout option 644 * @memory_carved_mb: Amount of memory carved in MB 645 * @flags: ATCS flags supported by this option 646 */ 647 struct amdgpu_uma_carveout_option { 648 char name[MAX_UMA_OPTION_NAME]; 649 uint32_t memory_carved_mb; 650 uint8_t flags; 651 }; 652 653 /** 654 * struct amdgpu_uma_carveout_info - table of available UMA carveout options 655 * @num_entries: Number of available options 656 * @uma_option_index: The index of the option currently applied 657 * @update_lock: Lock to serialize changes to the option 658 * @entries: The array of carveout options 659 */ 660 struct amdgpu_uma_carveout_info { 661 uint8_t num_entries; 662 uint8_t uma_option_index; 663 struct mutex update_lock; 664 struct amdgpu_uma_carveout_option entries[MAX_UMA_OPTION_ENTRIES]; 665 }; 666 667 struct amd_powerplay { 668 void *pp_handle; 669 const struct amd_pm_funcs *pp_funcs; 670 }; 671 672 /* polaris10 kickers */ 673 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 674 ((rid == 0xE3) || \ 675 (rid == 0xE4) || \ 676 (rid == 0xE5) || \ 677 (rid == 0xE7) || \ 678 (rid == 0xEF))) || \ 679 ((did == 0x6FDF) && \ 680 ((rid == 0xE7) || \ 681 (rid == 0xEF) || \ 682 (rid == 0xFF)))) 683 684 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 685 ((rid == 0xE1) || \ 686 (rid == 0xF7))) 687 688 /* polaris11 kickers */ 689 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 690 ((rid == 0xE0) || \ 691 (rid == 0xE5))) || \ 692 ((did == 0x67FF) && \ 693 ((rid == 0xCF) || \ 694 (rid == 0xEF) || \ 695 (rid == 0xFF)))) 696 697 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 698 ((rid == 0xE2))) 699 700 /* polaris12 kickers */ 701 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 702 ((rid == 0xC0) || \ 703 (rid == 0xC1) || \ 704 (rid == 0xC3) || \ 705 (rid == 0xC7))) || \ 706 ((did == 0x6981) && \ 707 ((rid == 0x00) || \ 708 (rid == 0x01) || \ 709 (rid == 0x10)))) 710 711 enum amdgpu_mqd_update_flag { 712 AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE = 1, 713 AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE = 2, 714 AMDGPU_UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ 715 }; 716 717 struct amdgpu_mqd_prop { 718 uint64_t mqd_gpu_addr; 719 uint64_t hqd_base_gpu_addr; 720 uint64_t rptr_gpu_addr; 721 uint64_t wptr_gpu_addr; 722 uint32_t queue_size; 723 bool use_doorbell; 724 uint32_t doorbell_index; 725 uint64_t eop_gpu_addr; 726 uint32_t hqd_pipe_priority; 727 uint32_t hqd_queue_priority; 728 uint32_t mqd_stride_size; 729 bool allow_tunneling; 730 bool hqd_active; 731 uint64_t shadow_addr; 732 uint64_t gds_bkup_addr; 733 uint64_t csa_addr; 734 uint64_t fence_address; 735 bool tmz_queue; 736 bool kernel_queue; 737 uint32_t *cu_mask; 738 uint32_t cu_mask_count; 739 uint32_t cu_flags; 740 bool is_user_cu_masked; 741 }; 742 743 struct amdgpu_mqd { 744 unsigned mqd_size; 745 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 746 struct amdgpu_mqd_prop *p); 747 }; 748 749 struct amdgpu_pcie_reset_ctx { 750 bool in_link_reset; 751 bool occurs_dpc; 752 bool audio_suspended; 753 struct pci_dev *swus; 754 struct pci_saved_state *swus_pcistate; 755 struct pci_saved_state *swds_pcistate; 756 }; 757 758 /* 759 * Custom Init levels could be defined for different situations where a full 760 * initialization of all hardware blocks are not expected. Sample cases are 761 * custom init sequences after resume after S0i3/S3, reset on initialization, 762 * partial reset of blocks etc. Presently, this defines only two levels. Levels 763 * are described in corresponding struct definitions - amdgpu_init_default, 764 * amdgpu_init_minimal_xgmi. 765 */ 766 enum amdgpu_init_lvl_id { 767 AMDGPU_INIT_LEVEL_DEFAULT, 768 AMDGPU_INIT_LEVEL_MINIMAL_XGMI, 769 AMDGPU_INIT_LEVEL_RESET_RECOVERY, 770 }; 771 772 struct amdgpu_init_level { 773 enum amdgpu_init_lvl_id level; 774 uint32_t hwini_ip_block_mask; 775 }; 776 777 #define AMDGPU_RESET_MAGIC_NUM 64 778 #define AMDGPU_MAX_DF_PERFMONS 4 779 struct amdgpu_reset_domain; 780 struct amdgpu_fru_info; 781 782 enum amdgpu_enforce_isolation_mode { 783 AMDGPU_ENFORCE_ISOLATION_DISABLE = 0, 784 AMDGPU_ENFORCE_ISOLATION_ENABLE = 1, 785 AMDGPU_ENFORCE_ISOLATION_ENABLE_LEGACY = 2, 786 AMDGPU_ENFORCE_ISOLATION_NO_CLEANER_SHADER = 3, 787 }; 788 789 struct amdgpu_device { 790 struct device *dev; 791 struct pci_dev *pdev; 792 struct drm_device ddev; 793 794 #ifdef CONFIG_DRM_AMD_ACP 795 struct amdgpu_acp acp; 796 #endif 797 struct amdgpu_hive_info *hive; 798 struct amdgpu_xcp_mgr *xcp_mgr; 799 /* ASIC */ 800 enum amd_asic_type asic_type; 801 uint32_t family; 802 uint32_t rev_id; 803 uint32_t external_rev_id; 804 unsigned long flags; 805 unsigned long apu_flags; 806 int usec_timeout; 807 const struct amdgpu_asic_funcs *asic_funcs; 808 bool shutdown; 809 bool need_swiotlb; 810 bool accel_working; 811 struct notifier_block acpi_nb; 812 struct notifier_block pm_nb; 813 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 814 struct debugfs_blob_wrapper debugfs_vbios_blob; 815 struct mutex srbm_mutex; 816 /* GRBM index mutex. Protects concurrent access to GRBM index */ 817 struct mutex grbm_idx_mutex; 818 struct dev_pm_domain vga_pm_domain; 819 bool have_disp_power_ref; 820 bool have_atomics_support; 821 bool is_sw_smu; 822 823 /* BIOS */ 824 bool is_atom_fw; 825 uint8_t *bios; 826 uint32_t bios_size; 827 uint32_t bios_scratch_reg_offset; 828 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 829 830 /* Register/doorbell mmio */ 831 resource_size_t rmmio_base; 832 resource_size_t rmmio_size; 833 void __iomem *rmmio; 834 /* protects concurrent MM_INDEX/DATA based register access */ 835 spinlock_t mmio_idx_lock; 836 struct amdgpu_mmio_remap rmmio_remap; 837 /* Indirect register access blocks */ 838 struct amdgpu_reg_access reg; 839 struct amdgpu_doorbell doorbell; 840 841 /* clock/pll info */ 842 struct amdgpu_clock clock; 843 844 /* MC */ 845 struct amdgpu_gmc gmc; 846 struct amdgpu_gart gart; 847 dma_addr_t dummy_page_addr; 848 struct amdgpu_vm_manager vm_manager; 849 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 850 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS); 851 852 /* memory management */ 853 struct amdgpu_mman mman; 854 struct amdgpu_mem_scratch mem_scratch; 855 struct amdgpu_wb wb; 856 atomic64_t num_bytes_moved; 857 atomic64_t num_evictions; 858 atomic64_t num_vram_cpu_page_faults; 859 atomic_t gpu_reset_counter; 860 atomic_t vram_lost_counter; 861 862 /* data for buffer migration throttling */ 863 struct { 864 spinlock_t lock; 865 s64 last_update_us; 866 s64 accum_us; /* accumulated microseconds */ 867 s64 accum_us_vis; /* for visible VRAM */ 868 u32 log2_max_MBps; 869 } mm_stats; 870 871 /* discovery*/ 872 struct amdgpu_discovery_info discovery; 873 874 /* display */ 875 bool enable_virtual_display; 876 struct amdgpu_vkms_output *amdgpu_vkms_output; 877 struct amdgpu_mode_info mode_info; 878 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 879 struct delayed_work hotplug_work; 880 struct amdgpu_irq_src crtc_irq; 881 struct amdgpu_irq_src vline0_irq; 882 struct amdgpu_irq_src vupdate_irq; 883 struct amdgpu_irq_src pageflip_irq; 884 struct amdgpu_irq_src hpd_irq; 885 struct amdgpu_irq_src dmub_trace_irq; 886 struct amdgpu_irq_src dmub_outbox_irq; 887 888 /* rings */ 889 u64 fence_context; 890 unsigned num_rings; 891 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 892 struct dma_fence __rcu *gang_submit; 893 bool ib_pool_ready; 894 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 895 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 896 897 /* interrupts */ 898 struct amdgpu_irq irq; 899 900 /* powerplay */ 901 struct amd_powerplay powerplay; 902 struct amdgpu_pm pm; 903 u64 cg_flags; 904 u32 pg_flags; 905 906 /* nbio */ 907 struct amdgpu_nbio nbio; 908 909 /* hdp */ 910 struct amdgpu_hdp hdp; 911 912 /* smuio */ 913 struct amdgpu_smuio smuio; 914 915 /* mmhub */ 916 struct amdgpu_mmhub mmhub; 917 918 /* gfxhub */ 919 struct amdgpu_gfxhub gfxhub; 920 921 /* gfx */ 922 struct amdgpu_gfx gfx; 923 924 /* sdma */ 925 struct amdgpu_sdma sdma; 926 927 /* lsdma */ 928 struct amdgpu_lsdma lsdma; 929 930 /* uvd */ 931 struct amdgpu_uvd uvd; 932 933 /* vce */ 934 struct amdgpu_vce vce; 935 936 /* vcn */ 937 struct amdgpu_vcn vcn; 938 939 /* jpeg */ 940 struct amdgpu_jpeg jpeg; 941 942 /* vpe */ 943 struct amdgpu_vpe vpe; 944 945 /* umsch */ 946 struct amdgpu_umsch_mm umsch_mm; 947 bool enable_umsch_mm; 948 949 /* firmwares */ 950 struct amdgpu_firmware firmware; 951 952 /* PSP */ 953 struct psp_context psp; 954 955 /* GDS */ 956 struct amdgpu_gds gds; 957 958 /* for userq and VM fences */ 959 struct amdgpu_seq64 seq64; 960 961 /* UMC */ 962 struct amdgpu_umc umc; 963 964 /* display related functionality */ 965 struct amdgpu_display_manager dm; 966 967 #if defined(CONFIG_DRM_AMD_ISP) 968 /* isp */ 969 struct amdgpu_isp isp; 970 #endif 971 972 /* mes */ 973 bool enable_mes; 974 bool enable_mes_kiq; 975 bool enable_uni_mes; 976 struct amdgpu_mes mes; 977 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 978 const struct amdgpu_userq_funcs *userq_funcs[AMDGPU_HW_IP_NUM]; 979 980 /** 981 * @userq_doorbell_xa: Global user queue map (doorbell index → queue) 982 * Key: doorbell_index (unique global identifier for the queue) 983 * Value: struct amdgpu_usermode_queue 984 */ 985 struct xarray userq_doorbell_xa; 986 987 /* df */ 988 struct amdgpu_df df; 989 990 /* MCA */ 991 struct amdgpu_mca mca; 992 993 /* CPER */ 994 struct amdgpu_cper cper; 995 996 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 997 uint32_t harvest_ip_mask; 998 int num_ip_blocks; 999 struct mutex mn_lock; 1000 DECLARE_HASHTABLE(mn_hash, 7); 1001 1002 /* tracking pinned memory */ 1003 atomic64_t vram_pin_size; 1004 atomic64_t visible_pin_size; 1005 atomic64_t gart_pin_size; 1006 1007 /* soc15 register offset based on ip, instance and segment */ 1008 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1009 struct amdgpu_ip_map_info ip_map; 1010 1011 /* delayed work_func for deferring clockgating during resume */ 1012 struct delayed_work delayed_init_work; 1013 1014 struct amdgpu_virt virt; 1015 1016 /* record hw reset is performed */ 1017 bool has_hw_reset; 1018 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1019 1020 /* s3/s4 mask */ 1021 bool in_suspend; 1022 bool in_s3; 1023 bool in_s4; 1024 bool in_s0ix; 1025 suspend_state_t last_suspend_state; 1026 1027 enum pp_mp1_state mp1_state; 1028 struct amdgpu_doorbell_index doorbell_index; 1029 1030 struct mutex notifier_lock; 1031 1032 int asic_reset_res; 1033 struct work_struct xgmi_reset_work; 1034 struct list_head reset_list; 1035 1036 long gfx_timeout; 1037 long sdma_timeout; 1038 long video_timeout; 1039 long compute_timeout; 1040 long psp_timeout; 1041 1042 uint64_t unique_id; 1043 uint8_t unitid; 1044 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1045 1046 /* enable runtime pm on the device */ 1047 bool in_runpm; 1048 bool has_pr3; 1049 1050 bool ucode_sysfs_en; 1051 1052 struct amdgpu_fru_info *fru_info; 1053 atomic_t throttling_logging_enabled; 1054 struct ratelimit_state throttling_logging_rs; 1055 uint32_t ras_hw_enabled; 1056 uint32_t ras_enabled; 1057 bool ras_default_ecc_enabled; 1058 1059 bool no_hw_access; 1060 struct pci_saved_state *pci_state; 1061 pci_channel_state_t pci_channel_state; 1062 1063 struct amdgpu_pcie_reset_ctx pcie_reset_ctx; 1064 1065 /* Track auto wait count on s_barrier settings */ 1066 bool barrier_has_auto_waitcnt; 1067 1068 struct amdgpu_reset_control *reset_cntl; 1069 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1070 1071 bool ram_is_direct_mapped; 1072 1073 struct list_head ras_list; 1074 1075 struct amdgpu_reset_domain *reset_domain; 1076 1077 #ifdef CONFIG_DEV_COREDUMP 1078 struct amdgpu_coredump_info *coredump; 1079 struct work_struct coredump_work; 1080 #endif 1081 1082 struct mutex benchmark_mutex; 1083 1084 bool scpm_enabled; 1085 uint32_t scpm_status; 1086 1087 struct work_struct reset_work; 1088 1089 bool dc_enabled; 1090 /* Mask of active clusters */ 1091 uint32_t aid_mask; 1092 1093 /* Debug */ 1094 bool debug_vm; 1095 bool debug_largebar; 1096 bool debug_disable_soft_recovery; 1097 bool debug_use_vram_fw_buf; 1098 bool debug_enable_ras_aca; 1099 bool debug_exp_resets; 1100 bool debug_disable_gpu_ring_reset; 1101 bool debug_vm_userptr; 1102 bool debug_disable_ce_logs; 1103 bool debug_enable_ce_cs; 1104 bool debug_hibernation_thaw_resume_gpu; 1105 bool debug_disable_ip_block_soft_reset; 1106 1107 /* Protection for the following isolation structure */ 1108 struct mutex enforce_isolation_mutex; 1109 enum amdgpu_enforce_isolation_mode enforce_isolation[MAX_XCP]; 1110 struct amdgpu_isolation { 1111 void *owner; 1112 struct dma_fence *spearhead; 1113 struct amdgpu_sync active; 1114 struct amdgpu_sync prev; 1115 } isolation[MAX_XCP]; 1116 1117 struct amdgpu_init_level *init_lvl; 1118 1119 /* This flag is used to determine how VRAM allocations are handled for APUs 1120 * in KFD: VRAM or GTT. 1121 */ 1122 bool apu_prefer_gtt; 1123 1124 bool userq_halt_for_enforce_isolation; 1125 struct amdgpu_uid *uid_info; 1126 1127 struct amdgpu_uma_carveout_info uma_info; 1128 1129 /* KFD 1130 * Must be last --ends in a flexible-array member. 1131 */ 1132 struct amdgpu_kfd_dev kfd; 1133 }; 1134 1135 /* 1136 * MES FW uses address(mqd_addr + sizeof(struct mqd) + 3*sizeof(uint32_t)) 1137 * as fence address and writes a 32 bit fence value to this address. 1138 * Driver needs to allocate at least 4 DWs extra memory in addition to 1139 * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE for safety. 1140 */ 1141 #define AMDGPU_MQD_SIZE_ALIGN(mqd_size) AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32)) 1142 1143 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, 1144 uint8_t ip, uint8_t inst) 1145 { 1146 /* This considers only major/minor/rev and ignores 1147 * subrevision/variant fields. 1148 */ 1149 return adev->ip_versions[ip][inst] & ~0xFFU; 1150 } 1151 1152 static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev, 1153 uint8_t ip, uint8_t inst) 1154 { 1155 /* This returns full version - major/minor/rev/variant/subrevision */ 1156 return adev->ip_versions[ip][inst]; 1157 } 1158 1159 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1160 { 1161 return container_of(ddev, struct amdgpu_device, ddev); 1162 } 1163 1164 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1165 { 1166 return &adev->ddev; 1167 } 1168 1169 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1170 { 1171 return container_of(bdev, struct amdgpu_device, mman.bdev); 1172 } 1173 1174 static inline bool amdgpu_is_multi_aid(struct amdgpu_device *adev) 1175 { 1176 return !!adev->aid_mask; 1177 } 1178 1179 int amdgpu_device_init(struct amdgpu_device *adev, 1180 uint32_t flags); 1181 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1182 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1183 1184 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1185 1186 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1187 void *buf, size_t size, bool write); 1188 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1189 void *buf, size_t size, bool write); 1190 1191 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1192 void *buf, size_t size, bool write); 1193 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev); 1194 bool amdgpu_device_asic_has_dc_support(struct pci_dev *pdev, 1195 enum amd_asic_type asic_type); 1196 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1197 1198 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev); 1199 1200 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1201 struct amdgpu_reset_context *reset_context); 1202 1203 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1204 struct amdgpu_reset_context *reset_context); 1205 1206 int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context); 1207 1208 int emu_soc_asic_init(struct amdgpu_device *adev); 1209 1210 /* 1211 * Registers read & write functions. 1212 */ 1213 #define AMDGPU_REGS_NO_KIQ (1<<1) 1214 #define AMDGPU_REGS_RLC (1<<2) 1215 1216 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1217 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1218 1219 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0) 1220 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0) 1221 1222 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1223 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1224 1225 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1226 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1227 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1228 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1229 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1230 #define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst) 1231 #define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst) 1232 #define RREG32_PCIE(reg) amdgpu_reg_pcie_rd32(adev, (reg)) 1233 #define WREG32_PCIE(reg, v) amdgpu_reg_pcie_wr32(adev, (reg), (v)) 1234 #define RREG32_PCIE_PORT(reg) amdgpu_reg_pciep_rd32(adev, (reg)) 1235 #define WREG32_PCIE_PORT(reg, v) amdgpu_reg_pciep_wr32(adev, (reg), (v)) 1236 #define RREG32_PCIE_EXT(reg) amdgpu_reg_pcie_ext_rd32(adev, (reg)) 1237 #define WREG32_PCIE_EXT(reg, v) amdgpu_reg_pcie_ext_wr32(adev, (reg), (v)) 1238 #define RREG64_PCIE(reg) amdgpu_reg_pcie_rd64(adev, (reg)) 1239 #define WREG64_PCIE(reg, v) amdgpu_reg_pcie_wr64(adev, (reg), (v)) 1240 #define RREG64_PCIE_EXT(reg) amdgpu_reg_pcie_ext_rd64(adev, (reg)) 1241 #define WREG64_PCIE_EXT(reg, v) amdgpu_reg_pcie_ext_wr64(adev, (reg), (v)) 1242 #define RREG32_SMC(reg) amdgpu_reg_smc_rd32(adev, (reg)) 1243 #define WREG32_SMC(reg, v) amdgpu_reg_smc_wr32(adev, (reg), (v)) 1244 #define RREG32_UVD_CTX(reg) amdgpu_reg_uvd_ctx_rd32(adev, (reg)) 1245 #define WREG32_UVD_CTX(reg, v) amdgpu_reg_uvd_ctx_wr32(adev, (reg), (v)) 1246 #define RREG32_DIDT(reg) amdgpu_reg_didt_rd32(adev, (reg)) 1247 #define WREG32_DIDT(reg, v) amdgpu_reg_didt_wr32(adev, (reg), (v)) 1248 #define RREG32_GC_CAC(reg) amdgpu_reg_gc_cac_rd32(adev, (reg)) 1249 #define WREG32_GC_CAC(reg, v) amdgpu_reg_gc_cac_wr32(adev, (reg), (v)) 1250 #define RREG32_SE_CAC(reg) amdgpu_reg_se_cac_rd32(adev, (reg)) 1251 #define WREG32_SE_CAC(reg, v) amdgpu_reg_se_cac_wr32(adev, (reg), (v)) 1252 #define RREG32_AUDIO_ENDPT(block, reg) \ 1253 amdgpu_reg_audio_endpt_rd32(adev, (block), (reg)) 1254 #define WREG32_AUDIO_ENDPT(block, reg, v) \ 1255 amdgpu_reg_audio_endpt_wr32(adev, (block), (reg), (v)) 1256 #define WREG32_P(reg, val, mask) \ 1257 do { \ 1258 uint32_t tmp_ = RREG32(reg); \ 1259 tmp_ &= (mask); \ 1260 tmp_ |= ((val) & ~(mask)); \ 1261 WREG32(reg, tmp_); \ 1262 } while (0) 1263 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1264 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1265 #define WREG32_PLL_P(reg, val, mask) \ 1266 do { \ 1267 uint32_t tmp_ = RREG32_PLL(reg); \ 1268 tmp_ &= (mask); \ 1269 tmp_ |= ((val) & ~(mask)); \ 1270 WREG32_PLL(reg, tmp_); \ 1271 } while (0) 1272 1273 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1274 do { \ 1275 u32 tmp = RREG32_SMC(_Reg); \ 1276 tmp &= (_Mask); \ 1277 tmp |= ((_Val) & ~(_Mask)); \ 1278 WREG32_SMC(_Reg, tmp); \ 1279 } while (0) 1280 1281 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1282 1283 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1284 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1285 1286 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1287 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1288 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1289 1290 #define REG_GET_FIELD(value, reg, field) \ 1291 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1292 1293 #define WREG32_FIELD(reg, field, val) \ 1294 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1295 1296 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1297 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1298 1299 #define AMDGPU_GET_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> (l)) 1300 /* 1301 * BIOS helpers. 1302 */ 1303 #define RBIOS8(i) (adev->bios[i]) 1304 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1305 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1306 1307 #include "amdgpu_reset.h" 1308 1309 /* 1310 * ASICs macro. 1311 */ 1312 #define amdgpu_asic_set_vga_state(adev, state) \ 1313 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0) 1314 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1315 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1316 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1317 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1318 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1319 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1320 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1321 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1322 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1323 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1324 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1325 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1326 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1327 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1328 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1329 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1330 #define amdgpu_asic_supports_baco(adev) \ 1331 ((adev)->asic_funcs->supports_baco ? (adev)->asic_funcs->supports_baco((adev)) : 0) 1332 #define amdgpu_asic_pre_asic_init(adev) \ 1333 { \ 1334 if ((adev)->asic_funcs && (adev)->asic_funcs->pre_asic_init) \ 1335 (adev)->asic_funcs->pre_asic_init((adev)); \ 1336 } 1337 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1338 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1339 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1340 1341 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)) 1342 1343 #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i)) 1344 #define for_each_inst(i, inst_mask) \ 1345 for (i = ffs(inst_mask); i-- != 0; \ 1346 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1))) 1347 1348 /* Common functions */ 1349 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1350 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1351 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1352 struct amdgpu_job *job, 1353 struct amdgpu_reset_context *reset_context); 1354 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1355 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1356 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1357 bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev); 1358 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1359 1360 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1361 u64 num_vis_bytes); 1362 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1363 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1364 const u32 *registers, 1365 const u32 array_size); 1366 1367 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1368 int amdgpu_device_link_reset(struct amdgpu_device *adev); 1369 bool amdgpu_device_supports_atpx(struct amdgpu_device *adev); 1370 bool amdgpu_device_supports_px(struct amdgpu_device *adev); 1371 bool amdgpu_device_supports_boco(struct amdgpu_device *adev); 1372 bool amdgpu_device_supports_smart_shift(struct amdgpu_device *adev); 1373 int amdgpu_device_supports_baco(struct amdgpu_device *adev); 1374 void amdgpu_device_detect_runtime_pm_mode(struct amdgpu_device *adev); 1375 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1376 struct amdgpu_device *peer_adev); 1377 int amdgpu_device_baco_enter(struct amdgpu_device *adev); 1378 int amdgpu_device_baco_exit(struct amdgpu_device *adev); 1379 1380 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1381 struct amdgpu_ring *ring); 1382 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1383 struct amdgpu_ring *ring); 1384 1385 void amdgpu_device_halt(struct amdgpu_device *adev); 1386 struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev); 1387 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1388 struct dma_fence *gang); 1389 struct dma_fence *amdgpu_device_enforce_isolation(struct amdgpu_device *adev, 1390 struct amdgpu_ring *ring, 1391 struct amdgpu_job *job); 1392 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1393 ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring); 1394 ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset); 1395 void amdgpu_sdma_set_vm_pte_scheds(struct amdgpu_device *adev, 1396 const struct amdgpu_vm_pte_funcs *vm_pte_funcs); 1397 void amdgpu_sdma_set_buffer_funcs_scheds(struct amdgpu_device *adev, 1398 const struct amdgpu_buffer_funcs *buffer_funcs); 1399 1400 /* atpx handler */ 1401 #if defined(CONFIG_VGA_SWITCHEROO) 1402 void amdgpu_register_atpx_handler(void); 1403 void amdgpu_unregister_atpx_handler(void); 1404 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1405 bool amdgpu_is_atpx_hybrid(void); 1406 bool amdgpu_has_atpx(void); 1407 #else 1408 static inline void amdgpu_register_atpx_handler(void) {} 1409 static inline void amdgpu_unregister_atpx_handler(void) {} 1410 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1411 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1412 static inline bool amdgpu_has_atpx(void) { return false; } 1413 #endif 1414 1415 /* 1416 * KMS 1417 */ 1418 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1419 extern const int amdgpu_max_kms_ioctl; 1420 1421 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1422 void amdgpu_driver_unload_kms(struct drm_device *dev); 1423 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1424 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1425 struct drm_file *file_priv); 1426 void amdgpu_driver_release_kms(struct drm_device *dev); 1427 1428 int amdgpu_device_prepare(struct drm_device *dev); 1429 void amdgpu_device_complete(struct drm_device *dev); 1430 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1431 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1432 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1433 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1434 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1435 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1436 struct drm_file *filp); 1437 int amdgpu_proc_options_ioctl(struct drm_device *dev, void *data, 1438 struct drm_file *filp); 1439 1440 /* 1441 * functions used by amdgpu_encoder.c 1442 */ 1443 struct amdgpu_afmt_acr { 1444 u32 clock; 1445 1446 int n_32khz; 1447 int cts_32khz; 1448 1449 int n_44_1khz; 1450 int cts_44_1khz; 1451 1452 int n_48khz; 1453 int cts_48khz; 1454 1455 }; 1456 1457 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1458 1459 /* amdgpu_acpi.c */ 1460 1461 struct amdgpu_numa_info { 1462 uint64_t size; 1463 int pxm; 1464 int nid; 1465 }; 1466 1467 /* ATCS Device/Driver State */ 1468 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1469 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1470 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1471 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1472 1473 #if defined(CONFIG_ACPI) 1474 int amdgpu_acpi_init(struct amdgpu_device *adev); 1475 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1476 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1477 bool amdgpu_acpi_is_power_shift_control_supported(void); 1478 bool amdgpu_acpi_is_set_uma_allocation_size_supported(void); 1479 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1480 u8 perf_req, bool advertise); 1481 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1482 u8 dev_state, bool drv_state); 1483 int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev, 1484 enum amdgpu_ss ss_state); 1485 int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type); 1486 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1487 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, 1488 u64 *tmr_size); 1489 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, 1490 struct amdgpu_numa_info *numa_info); 1491 1492 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1493 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1494 void amdgpu_acpi_detect(void); 1495 void amdgpu_acpi_release(void); 1496 #else 1497 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1498 static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, 1499 u64 *tmr_offset, u64 *tmr_size) 1500 { 1501 return -EINVAL; 1502 } 1503 static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, 1504 int xcc_id, 1505 struct amdgpu_numa_info *numa_info) 1506 { 1507 return -EINVAL; 1508 } 1509 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1510 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1511 static inline void amdgpu_acpi_detect(void) { } 1512 static inline void amdgpu_acpi_release(void) { } 1513 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1514 static inline bool amdgpu_acpi_is_set_uma_allocation_size_supported(void) { return false; } 1515 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1516 u8 dev_state, bool drv_state) { return 0; } 1517 static inline int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev, 1518 enum amdgpu_ss ss_state) 1519 { 1520 return 0; 1521 } 1522 static inline int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type) 1523 { 1524 return -EINVAL; 1525 } 1526 static inline void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps) { } 1527 #endif 1528 1529 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1530 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1531 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1532 #else 1533 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1534 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1535 #endif 1536 1537 #if defined(CONFIG_DRM_AMD_ISP) 1538 int amdgpu_acpi_get_isp4_dev(struct acpi_device **dev); 1539 #endif 1540 1541 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1542 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1543 1544 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1545 pci_channel_state_t state); 1546 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1547 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1548 void amdgpu_pci_resume(struct pci_dev *pdev); 1549 1550 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1551 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1552 1553 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1554 1555 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1556 enum amd_clockgating_state state); 1557 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1558 enum amd_powergating_state state); 1559 1560 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1561 { 1562 return amdgpu_gpu_recovery != 0 && 1563 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1564 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1565 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1566 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1567 } 1568 1569 #include "amdgpu_object.h" 1570 1571 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1572 { 1573 return adev->gmc.tmz_enabled; 1574 } 1575 1576 int amdgpu_in_reset(struct amdgpu_device *adev); 1577 1578 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 1579 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 1580 extern const struct attribute_group amdgpu_flash_attr_group; 1581 1582 void amdgpu_set_init_level(struct amdgpu_device *adev, 1583 enum amdgpu_init_lvl_id lvl); 1584 1585 static inline int amdgpu_device_bus_status_check(struct amdgpu_device *adev) 1586 { 1587 u32 status; 1588 int r; 1589 1590 r = pci_read_config_dword(adev->pdev, PCI_COMMAND, &status); 1591 if (r || PCI_POSSIBLE_ERROR(status)) { 1592 dev_err(adev->dev, "device lost from bus!"); 1593 return -ENODEV; 1594 } 1595 1596 return 0; 1597 } 1598 1599 void amdgpu_device_set_uid(struct amdgpu_uid *uid_info, 1600 enum amdgpu_uid_type type, uint8_t inst, 1601 uint64_t uid); 1602 uint64_t amdgpu_device_get_uid(struct amdgpu_uid *uid_info, 1603 enum amdgpu_uid_type type, uint8_t inst); 1604 #endif 1605