1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #include "amdgpu_ctx.h" 38 39 #include <linux/atomic.h> 40 #include <linux/wait.h> 41 #include <linux/list.h> 42 #include <linux/kref.h> 43 #include <linux/rbtree.h> 44 #include <linux/hashtable.h> 45 #include <linux/dma-fence.h> 46 #include <linux/pci.h> 47 #include <linux/xarray.h> 48 49 #include <drm/ttm/ttm_bo.h> 50 #include <drm/ttm/ttm_placement.h> 51 52 #include <drm/amdgpu_drm.h> 53 #include <drm/drm_gem.h> 54 #include <drm/drm_ioctl.h> 55 56 #include <kgd_kfd_interface.h> 57 #include "dm_pp_interface.h" 58 #include "kgd_pp_interface.h" 59 60 #include "amd_shared.h" 61 #include "amdgpu_utils.h" 62 #include "amdgpu_mode.h" 63 #include "amdgpu_ih.h" 64 #include "amdgpu_irq.h" 65 #include "amdgpu_ucode.h" 66 #include "amdgpu_ttm.h" 67 #include "amdgpu_psp.h" 68 #include "amdgpu_gds.h" 69 #include "amdgpu_sync.h" 70 #include "amdgpu_ring.h" 71 #include "amdgpu_vm.h" 72 #include "amdgpu_dpm.h" 73 #include "amdgpu_acp.h" 74 #include "amdgpu_uvd.h" 75 #include "amdgpu_vce.h" 76 #include "amdgpu_vcn.h" 77 #include "amdgpu_jpeg.h" 78 #include "amdgpu_vpe.h" 79 #include "amdgpu_umsch_mm.h" 80 #include "amdgpu_gmc.h" 81 #include "amdgpu_gfx.h" 82 #include "amdgpu_sdma.h" 83 #include "amdgpu_lsdma.h" 84 #include "amdgpu_nbio.h" 85 #include "amdgpu_reg_access.h" 86 #include "amdgpu_hdp.h" 87 #include "amdgpu_dm.h" 88 #include "amdgpu_virt.h" 89 #include "amdgpu_csa.h" 90 #include "amdgpu_mes_ctx.h" 91 #include "amdgpu_gart.h" 92 #include "amdgpu_debugfs.h" 93 #include "amdgpu_job.h" 94 #include "amdgpu_bo_list.h" 95 #include "amdgpu_gem.h" 96 #include "amdgpu_doorbell.h" 97 #include "amdgpu_amdkfd.h" 98 #include "amdgpu_discovery.h" 99 #include "amdgpu_umc.h" 100 #include "amdgpu_mmhub.h" 101 #include "amdgpu_gfxhub.h" 102 #include "amdgpu_df.h" 103 #include "amdgpu_smuio.h" 104 #include "amdgpu_fdinfo.h" 105 #include "amdgpu_mca.h" 106 #include "amdgpu_ras.h" 107 #include "amdgpu_lockdep.h" 108 #include "amdgpu_cper.h" 109 #include "amdgpu_xcp.h" 110 #include "amdgpu_seq64.h" 111 #include "amdgpu_reg_state.h" 112 #include "amdgpu_userq.h" 113 #include "amdgpu_eviction_fence.h" 114 #include "amdgpu_wb.h" 115 #include "amdgpu_ip.h" 116 #include "amdgpu_mes.h" 117 #include "amdgpu_sa.h" 118 #include "amdgpu_acpi.h" 119 #if defined(CONFIG_DRM_AMD_ISP) 120 #include "amdgpu_isp.h" 121 #endif 122 123 #define MAX_GPU_INSTANCE 64 124 125 #define GFX_SLICE_PERIOD_MS 250 126 127 struct amdgpu_gpu_instance { 128 struct amdgpu_device *adev; 129 int mgpu_fan_enabled; 130 }; 131 132 struct amdgpu_mgpu_info { 133 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 134 struct mutex mutex; 135 uint32_t num_gpu; 136 uint32_t num_dgpu; 137 uint32_t num_apu; 138 }; 139 140 struct amdgpu_hwip_reg_entry { 141 u32 hwip; 142 u32 inst; 143 u32 seg; 144 u32 reg_offset; 145 const char *reg_name; 146 }; 147 148 struct amdgpu_watchdog_timer { 149 bool timeout_fatal_disable; 150 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 151 }; 152 153 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 154 155 /* 156 * Modules parameters. 157 */ 158 extern int amdgpu_modeset; 159 extern unsigned int amdgpu_vram_limit; 160 extern int amdgpu_vis_vram_limit; 161 extern int amdgpu_gart_size; 162 extern int amdgpu_gtt_size; 163 extern int amdgpu_moverate; 164 extern int amdgpu_audio; 165 extern int amdgpu_disp_priority; 166 extern int amdgpu_hw_i2c; 167 extern int amdgpu_pcie_gen2; 168 extern int amdgpu_msi; 169 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 170 extern int amdgpu_dpm; 171 extern int amdgpu_fw_load_type; 172 extern int amdgpu_aspm; 173 extern int amdgpu_runtime_pm; 174 extern uint amdgpu_ip_block_mask; 175 extern int amdgpu_bapm; 176 extern int amdgpu_deep_color; 177 extern int amdgpu_vm_size; 178 extern int amdgpu_vm_block_size; 179 extern int amdgpu_vm_fragment_size; 180 extern int amdgpu_vm_fault_stop; 181 extern int amdgpu_vm_debug; 182 extern int amdgpu_vm_update_mode; 183 extern int amdgpu_exp_hw_support; 184 extern int amdgpu_dc; 185 extern int amdgpu_sched_jobs; 186 extern int amdgpu_sched_hw_submission; 187 extern uint amdgpu_pcie_gen_cap; 188 extern uint amdgpu_pcie_lane_cap; 189 extern u64 amdgpu_cg_mask; 190 extern uint amdgpu_pg_mask; 191 extern uint amdgpu_sdma_phase_quantum; 192 extern char *amdgpu_disable_cu; 193 extern char *amdgpu_virtual_display; 194 extern uint amdgpu_pp_feature_mask; 195 extern uint amdgpu_force_long_training; 196 extern int amdgpu_lbpw; 197 extern int amdgpu_compute_multipipe; 198 extern int amdgpu_gpu_recovery; 199 extern int amdgpu_emu_mode; 200 extern uint amdgpu_smu_memory_pool_size; 201 extern int amdgpu_smu_pptable_id; 202 extern uint amdgpu_dc_feature_mask; 203 extern uint amdgpu_freesync_vid_mode; 204 extern uint amdgpu_dc_debug_mask; 205 extern uint amdgpu_dc_visual_confirm; 206 extern int amdgpu_dm_abm_level; 207 extern int amdgpu_backlight; 208 extern int amdgpu_damage_clips; 209 extern struct amdgpu_mgpu_info mgpu_info; 210 extern int amdgpu_ras_enable; 211 extern uint amdgpu_ras_mask; 212 extern int amdgpu_bad_page_threshold; 213 extern bool amdgpu_ignore_bad_page_threshold; 214 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 215 extern int amdgpu_async_gfx_ring; 216 extern int amdgpu_mcbp; 217 extern int amdgpu_discovery; 218 extern int amdgpu_mes_log_enable; 219 extern int amdgpu_uni_mes; 220 extern int amdgpu_noretry; 221 extern int amdgpu_force_asic_type; 222 extern int amdgpu_smartshift_bias; 223 extern int amdgpu_use_xgmi_p2p; 224 extern int amdgpu_mtype_local; 225 extern int amdgpu_enforce_isolation; 226 #ifdef CONFIG_HSA_AMD 227 extern int sched_policy; 228 extern bool debug_evictions; 229 extern bool no_system_mem_limit; 230 extern int halt_if_hws_hang; 231 extern uint amdgpu_svm_default_granularity; 232 #else 233 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 234 static const bool __maybe_unused debug_evictions; /* = false */ 235 static const bool __maybe_unused no_system_mem_limit; 236 static const int __maybe_unused halt_if_hws_hang; 237 #endif 238 #ifdef CONFIG_HSA_AMD_P2P 239 extern bool pcie_p2p; 240 #endif 241 242 extern int amdgpu_tmz; 243 extern int amdgpu_reset_method; 244 245 #ifdef CONFIG_DRM_AMDGPU_SI 246 extern int amdgpu_si_support; 247 #endif 248 #ifdef CONFIG_DRM_AMDGPU_CIK 249 extern int amdgpu_cik_support; 250 #endif 251 extern int amdgpu_num_kcq; 252 253 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 254 #define AMDGPU_UMSCHFW_LOG_SIZE (32 * 1024) 255 extern int amdgpu_vcnfw_log; 256 extern int amdgpu_sg_display; 257 extern int amdgpu_umsch_mm; 258 extern int amdgpu_seamless; 259 extern int amdgpu_umsch_mm_fwlog; 260 261 extern int amdgpu_user_partt_mode; 262 extern int amdgpu_agp; 263 extern int amdgpu_rebar; 264 265 extern int amdgpu_wbrf; 266 extern int amdgpu_user_queue; 267 extern int amdgpu_ptl; 268 269 extern uint amdgpu_hdmi_hpd_debounce_delay_ms; 270 271 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 272 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 273 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 274 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 275 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 276 #define AMDGPUFB_CONN_LIMIT 4 277 #define AMDGPU_BIOS_NUM_SCRATCH 16 278 279 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 280 281 /* hard reset data */ 282 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 283 284 /* reset flags */ 285 #define AMDGPU_RESET_GFX (1 << 0) 286 #define AMDGPU_RESET_COMPUTE (1 << 1) 287 #define AMDGPU_RESET_DMA (1 << 2) 288 #define AMDGPU_RESET_CP (1 << 3) 289 #define AMDGPU_RESET_GRBM (1 << 4) 290 #define AMDGPU_RESET_DMA1 (1 << 5) 291 #define AMDGPU_RESET_RLC (1 << 6) 292 #define AMDGPU_RESET_SEM (1 << 7) 293 #define AMDGPU_RESET_IH (1 << 8) 294 #define AMDGPU_RESET_VMC (1 << 9) 295 #define AMDGPU_RESET_MC (1 << 10) 296 #define AMDGPU_RESET_DISPLAY (1 << 11) 297 #define AMDGPU_RESET_UVD (1 << 12) 298 #define AMDGPU_RESET_VCE (1 << 13) 299 #define AMDGPU_RESET_VCE1 (1 << 14) 300 301 /* reset mask */ 302 #define AMDGPU_RESET_TYPE_FULL (1 << 0) /* full adapter reset, mode1/mode2/BACO/etc. */ 303 #define AMDGPU_RESET_TYPE_SOFT_RECOVERY (1 << 1) /* soft recovery, eg. kill shaders */ 304 #define AMDGPU_RESET_TYPE_PER_QUEUE (1 << 2) /* per queue */ 305 #define AMDGPU_RESET_TYPE_PER_PIPE (1 << 3) /* per pipe */ 306 #define AMDGPU_RESET_TYPE_IP_BLOCK_SOFT_RESET (1 << 4) /* soft-resets an IP block */ 307 308 /* max cursor sizes (in pixels) */ 309 #define CIK_CURSOR_WIDTH 128 310 #define CIK_CURSOR_HEIGHT 128 311 312 /* smart shift bias level limits */ 313 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 314 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 315 316 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */ 317 #define AMDGPU_SWCTF_EXTRA_DELAY 50 318 319 struct amdgpu_xcp_mgr; 320 struct amdgpu_device; 321 struct amdgpu_irq_src; 322 struct amdgpu_fpriv; 323 struct amdgpu_bo_va_mapping; 324 struct kfd_vm_fault_info; 325 struct amdgpu_hive_info; 326 struct amdgpu_reset_context; 327 struct amdgpu_reset_control; 328 struct amdgpu_coredump_info; 329 struct amdgpu_video_codecs; 330 331 enum amdgpu_cp_irq { 332 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 333 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 334 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 335 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 336 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 337 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 338 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 339 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 340 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 341 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 342 343 AMDGPU_CP_IRQ_LAST 344 }; 345 346 enum amdgpu_thermal_irq { 347 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 348 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 349 350 AMDGPU_THERMAL_IRQ_LAST 351 }; 352 353 enum amdgpu_kiq_irq { 354 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 355 AMDGPU_CP_KIQ_IRQ_LAST 356 }; 357 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 358 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 359 #define MAX_KIQ_REG_TRY 1000 360 361 /* 362 * BIOS. 363 */ 364 bool amdgpu_get_bios(struct amdgpu_device *adev); 365 bool amdgpu_read_bios(struct amdgpu_device *adev); 366 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 367 u8 *bios, u32 length_bytes); 368 void amdgpu_bios_release(struct amdgpu_device *adev); 369 /* 370 * Clocks 371 */ 372 373 #define AMDGPU_MAX_PPLL 3 374 375 struct amdgpu_clock { 376 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 377 struct amdgpu_pll spll; 378 struct amdgpu_pll mpll; 379 /* 10 Khz units */ 380 uint32_t default_mclk; 381 uint32_t default_sclk; 382 uint32_t default_dispclk; 383 uint32_t dp_extclk; 384 uint32_t max_pixel_clock; 385 }; 386 387 /* 388 * IRQS. 389 */ 390 391 struct amdgpu_flip_work { 392 struct delayed_work flip_work; 393 struct work_struct unpin_work; 394 struct amdgpu_device *adev; 395 int crtc_id; 396 u32 target_vblank; 397 uint64_t base; 398 struct drm_pending_vblank_event *event; 399 struct amdgpu_bo *old_abo; 400 unsigned shared_count; 401 struct dma_fence **shared; 402 struct dma_fence_cb cb; 403 bool async; 404 }; 405 406 /* 407 * file private structure 408 */ 409 410 struct amdgpu_fpriv { 411 struct amdgpu_vm vm; 412 struct amdgpu_bo_va *prt_va; 413 struct amdgpu_bo_va *csa_va; 414 struct amdgpu_bo_va *seq64_va; 415 struct xarray bo_list_handles; 416 struct amdgpu_ctx_mgr ctx_mgr; 417 struct amdgpu_userq_mgr userq_mgr; 418 419 /* Eviction fence infra */ 420 struct amdgpu_eviction_fence_mgr evf_mgr; 421 422 /** GPU partition selection */ 423 uint32_t xcp_id; 424 }; 425 426 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 427 428 /* 429 * Benchmarking 430 */ 431 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 432 433 /* 434 * ASIC specific functions. 435 */ 436 struct amdgpu_asic_funcs { 437 bool (*read_disabled_bios)(struct amdgpu_device *adev); 438 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 439 u8 *bios, u32 length_bytes); 440 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 441 u32 sh_num, u32 reg_offset, u32 *value); 442 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 443 int (*reset)(struct amdgpu_device *adev); 444 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 445 /* get the reference clock */ 446 u32 (*get_xclk)(struct amdgpu_device *adev); 447 /* MM block clocks */ 448 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 449 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 450 /* static power management */ 451 int (*get_pcie_lanes)(struct amdgpu_device *adev); 452 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 453 /* get config memsize register */ 454 u32 (*get_config_memsize)(struct amdgpu_device *adev); 455 /* flush hdp write queue */ 456 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 457 /* invalidate hdp read cache */ 458 void (*invalidate_hdp)(struct amdgpu_device *adev, 459 struct amdgpu_ring *ring); 460 /* initialize doorbell layout for specific asic*/ 461 void (*init_doorbell_index)(struct amdgpu_device *adev); 462 /* PCIe bandwidth usage */ 463 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 464 uint64_t *count1); 465 /* do we need to reset the asic at init time (e.g., kexec) */ 466 bool (*need_reset_on_init)(struct amdgpu_device *adev); 467 /* PCIe replay counter */ 468 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 469 /* device supports BACO */ 470 int (*supports_baco)(struct amdgpu_device *adev); 471 /* pre asic_init quirks */ 472 void (*pre_asic_init)(struct amdgpu_device *adev); 473 /* enter/exit umd stable pstate */ 474 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 475 /* query video codecs */ 476 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 477 const struct amdgpu_video_codecs **codecs); 478 /* encode "> 32bits" smn addressing */ 479 u64 (*encode_ext_smn_addressing)(int ext_id); 480 481 ssize_t (*get_reg_state)(struct amdgpu_device *adev, 482 enum amdgpu_reg_state reg_state, void *buf, 483 size_t max_size); 484 }; 485 486 /* 487 * IOCTL. 488 */ 489 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 490 struct drm_file *filp); 491 492 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 493 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 494 struct drm_file *filp); 495 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 496 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 497 struct drm_file *filp); 498 499 /* VRAM scratch page for HDP bug, default vram page */ 500 struct amdgpu_mem_scratch { 501 struct amdgpu_bo *robj; 502 uint32_t *ptr; 503 u64 gpu_addr; 504 }; 505 506 /* 507 * CGS 508 */ 509 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 510 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 511 512 /* 513 * Core structure, functions and helpers. 514 */ 515 struct amdgpu_mmio_remap { 516 u32 reg_offset; 517 resource_size_t bus_addr; 518 struct amdgpu_bo *bo; 519 }; 520 521 enum amdgpu_uid_type { 522 AMDGPU_UID_TYPE_XCD, 523 AMDGPU_UID_TYPE_AID, 524 AMDGPU_UID_TYPE_SOC, 525 AMDGPU_UID_TYPE_MID, 526 AMDGPU_UID_TYPE_MAX 527 }; 528 529 #define AMDGPU_UID_INST_MAX 8 /* max number of instances for each UID type */ 530 531 struct amdgpu_uid { 532 uint64_t uid[AMDGPU_UID_TYPE_MAX][AMDGPU_UID_INST_MAX]; 533 struct amdgpu_device *adev; 534 }; 535 536 struct amd_powerplay { 537 void *pp_handle; 538 const struct amd_pm_funcs *pp_funcs; 539 }; 540 541 /* polaris10 kickers */ 542 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 543 ((rid == 0xE3) || \ 544 (rid == 0xE4) || \ 545 (rid == 0xE5) || \ 546 (rid == 0xE7) || \ 547 (rid == 0xEF))) || \ 548 ((did == 0x6FDF) && \ 549 ((rid == 0xE7) || \ 550 (rid == 0xEF) || \ 551 (rid == 0xFF)))) 552 553 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 554 ((rid == 0xE1) || \ 555 (rid == 0xF7))) 556 557 /* polaris11 kickers */ 558 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 559 ((rid == 0xE0) || \ 560 (rid == 0xE5))) || \ 561 ((did == 0x67FF) && \ 562 ((rid == 0xCF) || \ 563 (rid == 0xEF) || \ 564 (rid == 0xFF)))) 565 566 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 567 ((rid == 0xE2))) 568 569 /* polaris12 kickers */ 570 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 571 ((rid == 0xC0) || \ 572 (rid == 0xC1) || \ 573 (rid == 0xC3) || \ 574 (rid == 0xC7))) || \ 575 ((did == 0x6981) && \ 576 ((rid == 0x00) || \ 577 (rid == 0x01) || \ 578 (rid == 0x10)))) 579 580 struct amdgpu_pcie_reset_ctx { 581 bool in_link_reset; 582 bool occurs_dpc; 583 bool audio_suspended; 584 struct pci_dev *swus; 585 struct pci_saved_state *swus_pcistate; 586 struct pci_saved_state *swds_pcistate; 587 }; 588 589 /* 590 * Custom Init levels could be defined for different situations where a full 591 * initialization of all hardware blocks are not expected. Sample cases are 592 * custom init sequences after resume after S0i3/S3, reset on initialization, 593 * partial reset of blocks etc. Presently, this defines only two levels. Levels 594 * are described in corresponding struct definitions - amdgpu_init_default, 595 * amdgpu_init_minimal_xgmi. 596 */ 597 enum amdgpu_init_lvl_id { 598 AMDGPU_INIT_LEVEL_DEFAULT, 599 AMDGPU_INIT_LEVEL_MINIMAL_XGMI, 600 AMDGPU_INIT_LEVEL_RESET_RECOVERY, 601 }; 602 603 struct amdgpu_init_level { 604 enum amdgpu_init_lvl_id level; 605 uint32_t hwini_ip_block_mask; 606 }; 607 608 #define AMDGPU_RESET_MAGIC_NUM 64 609 #define AMDGPU_MAX_DF_PERFMONS 4 610 struct amdgpu_reset_domain; 611 struct amdgpu_fru_info; 612 613 enum amdgpu_enforce_isolation_mode { 614 AMDGPU_ENFORCE_ISOLATION_DISABLE = 0, 615 AMDGPU_ENFORCE_ISOLATION_ENABLE = 1, 616 AMDGPU_ENFORCE_ISOLATION_ENABLE_LEGACY = 2, 617 AMDGPU_ENFORCE_ISOLATION_NO_CLEANER_SHADER = 3, 618 }; 619 620 struct amdgpu_device { 621 struct device *dev; 622 struct pci_dev *pdev; 623 struct drm_device ddev; 624 625 #ifdef CONFIG_DRM_AMD_ACP 626 struct amdgpu_acp acp; 627 #endif 628 struct amdgpu_hive_info *hive; 629 struct amdgpu_xcp_mgr *xcp_mgr; 630 /* ASIC */ 631 enum amd_asic_type asic_type; 632 uint32_t family; 633 uint32_t rev_id; 634 uint32_t external_rev_id; 635 unsigned long flags; 636 unsigned long apu_flags; 637 int usec_timeout; 638 const struct amdgpu_asic_funcs *asic_funcs; 639 bool shutdown; 640 bool need_swiotlb; 641 bool accel_working; 642 struct notifier_block acpi_nb; 643 struct notifier_block pm_nb; 644 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 645 struct debugfs_blob_wrapper debugfs_vbios_blob; 646 struct mutex srbm_mutex; 647 /* GRBM index mutex. Protects concurrent access to GRBM index */ 648 struct mutex grbm_idx_mutex; 649 struct dev_pm_domain vga_pm_domain; 650 bool have_disp_power_ref; 651 bool have_atomics_support; 652 bool is_sw_smu; 653 654 /* BIOS */ 655 bool is_atom_fw; 656 uint8_t *bios; 657 uint32_t bios_size; 658 uint32_t bios_scratch_reg_offset; 659 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 660 661 /* Register/doorbell mmio */ 662 resource_size_t rmmio_base; 663 resource_size_t rmmio_size; 664 void __iomem *rmmio; 665 /* protects concurrent MM_INDEX/DATA based register access */ 666 spinlock_t mmio_idx_lock; 667 struct amdgpu_mmio_remap rmmio_remap; 668 /* Indirect register access blocks */ 669 struct amdgpu_reg_access reg; 670 struct amdgpu_doorbell doorbell; 671 672 /* clock/pll info */ 673 struct amdgpu_clock clock; 674 675 /* MC */ 676 struct amdgpu_gmc gmc; 677 struct amdgpu_gart gart; 678 dma_addr_t dummy_page_addr; 679 struct amdgpu_vm_manager vm_manager; 680 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 681 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS); 682 683 /* memory management */ 684 struct amdgpu_mman mman; 685 struct amdgpu_mem_scratch mem_scratch; 686 struct amdgpu_wb wb; 687 atomic64_t num_bytes_moved; 688 atomic64_t num_evictions; 689 atomic64_t num_vram_cpu_page_faults; 690 atomic_t gpu_reset_counter; 691 atomic_t vram_lost_counter; 692 693 /* data for buffer migration throttling */ 694 struct { 695 spinlock_t lock; 696 s64 last_update_us; 697 s64 accum_us; /* accumulated microseconds */ 698 s64 accum_us_vis; /* for visible VRAM */ 699 u32 log2_max_MBps; 700 } mm_stats; 701 702 /* discovery*/ 703 struct amdgpu_discovery_info discovery; 704 705 /* display */ 706 bool enable_virtual_display; 707 struct amdgpu_vkms_output *amdgpu_vkms_output; 708 struct amdgpu_mode_info mode_info; 709 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 710 struct delayed_work hotplug_work; 711 struct amdgpu_irq_src crtc_irq; 712 struct amdgpu_irq_src vline0_irq; 713 struct amdgpu_irq_src vupdate_irq; 714 struct amdgpu_irq_src pageflip_irq; 715 struct amdgpu_irq_src hpd_irq; 716 struct amdgpu_irq_src dmub_trace_irq; 717 struct amdgpu_irq_src dmub_outbox_irq; 718 719 /* rings */ 720 u64 fence_context; 721 unsigned num_rings; 722 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 723 struct dma_fence __rcu *gang_submit; 724 bool ib_pool_ready; 725 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 726 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 727 728 /* interrupts */ 729 struct amdgpu_irq irq; 730 731 /* powerplay */ 732 struct amd_powerplay powerplay; 733 struct amdgpu_pm pm; 734 u64 cg_flags; 735 u32 pg_flags; 736 737 /* nbio */ 738 struct amdgpu_nbio nbio; 739 740 /* hdp */ 741 struct amdgpu_hdp hdp; 742 743 /* smuio */ 744 struct amdgpu_smuio smuio; 745 746 /* mmhub */ 747 struct amdgpu_mmhub mmhub; 748 749 /* gfxhub */ 750 struct amdgpu_gfxhub gfxhub; 751 752 /* gfx */ 753 struct amdgpu_gfx gfx; 754 755 /* sdma */ 756 struct amdgpu_sdma sdma; 757 758 /* lsdma */ 759 struct amdgpu_lsdma lsdma; 760 761 /* uvd */ 762 struct amdgpu_uvd uvd; 763 764 /* vce */ 765 struct amdgpu_vce vce; 766 767 /* vcn */ 768 struct amdgpu_vcn vcn; 769 770 /* jpeg */ 771 struct amdgpu_jpeg jpeg; 772 773 /* vpe */ 774 struct amdgpu_vpe vpe; 775 776 /* umsch */ 777 struct amdgpu_umsch_mm umsch_mm; 778 bool enable_umsch_mm; 779 780 /* firmwares */ 781 struct amdgpu_firmware firmware; 782 783 /* PSP */ 784 struct psp_context psp; 785 786 /* GDS */ 787 struct amdgpu_gds gds; 788 789 /* for userq and VM fences */ 790 struct amdgpu_seq64 seq64; 791 792 /* UMC */ 793 struct amdgpu_umc umc; 794 795 /* display related functionality */ 796 struct amdgpu_display_manager dm; 797 798 #if defined(CONFIG_DRM_AMD_ISP) 799 /* isp */ 800 struct amdgpu_isp isp; 801 #endif 802 803 /* mes */ 804 bool enable_mes; 805 bool enable_mes_kiq; 806 bool enable_uni_mes; 807 struct amdgpu_mes mes; 808 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 809 const struct amdgpu_userq_funcs *userq_funcs[AMDGPU_HW_IP_NUM]; 810 811 /** 812 * @userq_doorbell_xa: Global user queue map (doorbell index → queue) 813 * Key: doorbell_index (unique global identifier for the queue) 814 * Value: struct amdgpu_usermode_queue 815 */ 816 struct xarray userq_doorbell_xa; 817 818 /* df */ 819 struct amdgpu_df df; 820 821 /* MCA */ 822 struct amdgpu_mca mca; 823 824 /* CPER */ 825 struct amdgpu_cper cper; 826 827 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 828 uint32_t harvest_ip_mask; 829 int num_ip_blocks; 830 struct mutex mn_lock; 831 DECLARE_HASHTABLE(mn_hash, 7); 832 833 /* tracking pinned memory */ 834 atomic64_t vram_pin_size; 835 atomic64_t visible_pin_size; 836 atomic64_t gart_pin_size; 837 838 /* soc15 register offset based on ip, instance and segment */ 839 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 840 struct amdgpu_ip_map_info ip_map; 841 842 /* delayed work_func for deferring clockgating during resume */ 843 struct delayed_work delayed_init_work; 844 845 struct amdgpu_virt virt; 846 847 /* record hw reset is performed */ 848 bool has_hw_reset; 849 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 850 851 /* s3/s4 mask */ 852 bool in_suspend; 853 bool in_s3; 854 bool in_s4; 855 bool in_s0ix; 856 suspend_state_t last_suspend_state; 857 858 enum pp_mp1_state mp1_state; 859 struct amdgpu_doorbell_index doorbell_index; 860 861 struct mutex notifier_lock; 862 863 int asic_reset_res; 864 struct work_struct xgmi_reset_work; 865 struct list_head reset_list; 866 867 long gfx_timeout; 868 long sdma_timeout; 869 long video_timeout; 870 long compute_timeout; 871 long psp_timeout; 872 873 uint64_t unique_id; 874 uint8_t unitid; 875 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 876 877 /* enable runtime pm on the device */ 878 bool in_runpm; 879 bool has_pr3; 880 881 bool ucode_sysfs_en; 882 883 struct amdgpu_fru_info *fru_info; 884 atomic_t throttling_logging_enabled; 885 struct ratelimit_state throttling_logging_rs; 886 uint32_t ras_hw_enabled; 887 uint32_t ras_enabled; 888 bool ras_default_ecc_enabled; 889 890 bool no_hw_access; 891 struct pci_saved_state *pci_state; 892 pci_channel_state_t pci_channel_state; 893 894 struct amdgpu_pcie_reset_ctx pcie_reset_ctx; 895 896 /* Track auto wait count on s_barrier settings */ 897 bool barrier_has_auto_waitcnt; 898 899 struct amdgpu_reset_control *reset_cntl; 900 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 901 902 bool ram_is_direct_mapped; 903 904 struct list_head ras_list; 905 906 struct amdgpu_reset_domain *reset_domain; 907 908 #ifdef CONFIG_DEV_COREDUMP 909 struct amdgpu_coredump_info *coredump; 910 struct work_struct coredump_work; 911 #endif 912 913 struct mutex benchmark_mutex; 914 915 bool scpm_enabled; 916 uint32_t scpm_status; 917 918 struct work_struct reset_work; 919 920 bool dc_enabled; 921 /* Mask of active clusters */ 922 uint32_t aid_mask; 923 924 /* Debug */ 925 bool debug_vm; 926 bool debug_largebar; 927 bool debug_disable_soft_recovery; 928 bool debug_use_vram_fw_buf; 929 bool debug_enable_ras_aca; 930 bool debug_exp_resets; 931 bool debug_disable_gpu_ring_reset; 932 bool debug_vm_userptr; 933 bool debug_disable_ce_logs; 934 bool debug_enable_ce_cs; 935 bool debug_hibernation_thaw_resume_gpu; 936 bool debug_disable_ip_block_soft_reset; 937 938 /* Protection for the following isolation structure */ 939 struct mutex enforce_isolation_mutex; 940 enum amdgpu_enforce_isolation_mode enforce_isolation[MAX_XCP]; 941 struct amdgpu_isolation { 942 void *owner; 943 struct dma_fence *spearhead; 944 struct amdgpu_sync active; 945 struct amdgpu_sync prev; 946 } isolation[MAX_XCP]; 947 948 struct amdgpu_init_level *init_lvl; 949 950 /* This flag is used to determine how VRAM allocations are handled for APUs 951 * in KFD: VRAM or GTT. 952 */ 953 bool apu_prefer_gtt; 954 955 bool userq_halt_for_enforce_isolation; 956 struct amdgpu_uid *uid_info; 957 958 struct amdgpu_uma_carveout_info uma_info; 959 960 /* KFD 961 * Must be last --ends in a flexible-array member. 962 */ 963 struct amdgpu_kfd_dev kfd; 964 }; 965 966 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, 967 uint8_t ip, uint8_t inst) 968 { 969 /* This considers only major/minor/rev and ignores 970 * subrevision/variant fields. 971 */ 972 return adev->ip_versions[ip][inst] & ~0xFFU; 973 } 974 975 static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev, 976 uint8_t ip, uint8_t inst) 977 { 978 /* This returns full version - major/minor/rev/variant/subrevision */ 979 return adev->ip_versions[ip][inst]; 980 } 981 982 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 983 { 984 return container_of(ddev, struct amdgpu_device, ddev); 985 } 986 987 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 988 { 989 return &adev->ddev; 990 } 991 992 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 993 { 994 return container_of(bdev, struct amdgpu_device, mman.bdev); 995 } 996 997 static inline bool amdgpu_is_multi_aid(struct amdgpu_device *adev) 998 { 999 return !!adev->aid_mask; 1000 } 1001 1002 int amdgpu_device_init(struct amdgpu_device *adev, 1003 uint32_t flags); 1004 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1005 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1006 1007 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1008 1009 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1010 void *buf, size_t size, bool write); 1011 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1012 void *buf, size_t size, bool write); 1013 1014 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1015 void *buf, size_t size, bool write); 1016 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev); 1017 bool amdgpu_device_asic_has_dc_support(struct pci_dev *pdev, 1018 enum amd_asic_type asic_type); 1019 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1020 1021 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev); 1022 1023 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1024 struct amdgpu_reset_context *reset_context); 1025 1026 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1027 struct amdgpu_reset_context *reset_context); 1028 1029 int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context); 1030 1031 int emu_soc_asic_init(struct amdgpu_device *adev); 1032 1033 /* 1034 * Registers read & write functions. 1035 */ 1036 #define AMDGPU_REGS_NO_KIQ (1<<1) 1037 #define AMDGPU_REGS_RLC (1<<2) 1038 1039 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1040 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1041 1042 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0) 1043 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0) 1044 1045 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1046 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1047 1048 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1049 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1050 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1051 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1052 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1053 #define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst) 1054 #define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst) 1055 #define RREG32_PCIE(reg) amdgpu_reg_pcie_rd32(adev, (reg)) 1056 #define WREG32_PCIE(reg, v) amdgpu_reg_pcie_wr32(adev, (reg), (v)) 1057 #define RREG32_PCIE_PORT(reg) amdgpu_reg_pciep_rd32(adev, (reg)) 1058 #define WREG32_PCIE_PORT(reg, v) amdgpu_reg_pciep_wr32(adev, (reg), (v)) 1059 #define RREG32_PCIE_EXT(reg) amdgpu_reg_pcie_ext_rd32(adev, (reg)) 1060 #define WREG32_PCIE_EXT(reg, v) amdgpu_reg_pcie_ext_wr32(adev, (reg), (v)) 1061 #define RREG64_PCIE(reg) amdgpu_reg_pcie_rd64(adev, (reg)) 1062 #define WREG64_PCIE(reg, v) amdgpu_reg_pcie_wr64(adev, (reg), (v)) 1063 #define RREG64_PCIE_EXT(reg) amdgpu_reg_pcie_ext_rd64(adev, (reg)) 1064 #define WREG64_PCIE_EXT(reg, v) amdgpu_reg_pcie_ext_wr64(adev, (reg), (v)) 1065 #define RREG32_SMC(reg) amdgpu_reg_smc_rd32(adev, (reg)) 1066 #define WREG32_SMC(reg, v) amdgpu_reg_smc_wr32(adev, (reg), (v)) 1067 #define RREG32_UVD_CTX(reg) amdgpu_reg_uvd_ctx_rd32(adev, (reg)) 1068 #define WREG32_UVD_CTX(reg, v) amdgpu_reg_uvd_ctx_wr32(adev, (reg), (v)) 1069 #define RREG32_DIDT(reg) amdgpu_reg_didt_rd32(adev, (reg)) 1070 #define WREG32_DIDT(reg, v) amdgpu_reg_didt_wr32(adev, (reg), (v)) 1071 #define RREG32_GC_CAC(reg) amdgpu_reg_gc_cac_rd32(adev, (reg)) 1072 #define WREG32_GC_CAC(reg, v) amdgpu_reg_gc_cac_wr32(adev, (reg), (v)) 1073 #define RREG32_SE_CAC(reg) amdgpu_reg_se_cac_rd32(adev, (reg)) 1074 #define WREG32_SE_CAC(reg, v) amdgpu_reg_se_cac_wr32(adev, (reg), (v)) 1075 #define RREG32_AUDIO_ENDPT(block, reg) \ 1076 amdgpu_reg_audio_endpt_rd32(adev, (block), (reg)) 1077 #define WREG32_AUDIO_ENDPT(block, reg, v) \ 1078 amdgpu_reg_audio_endpt_wr32(adev, (block), (reg), (v)) 1079 #define WREG32_P(reg, val, mask) \ 1080 do { \ 1081 uint32_t tmp_ = RREG32(reg); \ 1082 tmp_ &= (mask); \ 1083 tmp_ |= ((val) & ~(mask)); \ 1084 WREG32(reg, tmp_); \ 1085 } while (0) 1086 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1087 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1088 #define WREG32_PLL_P(reg, val, mask) \ 1089 do { \ 1090 uint32_t tmp_ = RREG32_PLL(reg); \ 1091 tmp_ &= (mask); \ 1092 tmp_ |= ((val) & ~(mask)); \ 1093 WREG32_PLL(reg, tmp_); \ 1094 } while (0) 1095 1096 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1097 do { \ 1098 u32 tmp = RREG32_SMC(_Reg); \ 1099 tmp &= (_Mask); \ 1100 tmp |= ((_Val) & ~(_Mask)); \ 1101 WREG32_SMC(_Reg, tmp); \ 1102 } while (0) 1103 1104 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1105 1106 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1107 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1108 1109 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1110 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1111 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1112 1113 #define REG_GET_FIELD(value, reg, field) \ 1114 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1115 1116 #define WREG32_FIELD(reg, field, val) \ 1117 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1118 1119 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1120 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1121 1122 #define AMDGPU_GET_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> (l)) 1123 /* 1124 * BIOS helpers. 1125 */ 1126 #define RBIOS8(i) (adev->bios[i]) 1127 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1128 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1129 1130 #include "amdgpu_reset.h" 1131 1132 /* 1133 * ASICs macro. 1134 */ 1135 #define amdgpu_asic_set_vga_state(adev, state) \ 1136 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0) 1137 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1138 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1139 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1140 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1141 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1142 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1143 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1144 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1145 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1146 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1147 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1148 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1149 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1150 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1151 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1152 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1153 #define amdgpu_asic_supports_baco(adev) \ 1154 ((adev)->asic_funcs->supports_baco ? (adev)->asic_funcs->supports_baco((adev)) : 0) 1155 #define amdgpu_asic_pre_asic_init(adev) \ 1156 { \ 1157 if ((adev)->asic_funcs && (adev)->asic_funcs->pre_asic_init) \ 1158 (adev)->asic_funcs->pre_asic_init((adev)); \ 1159 } 1160 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1161 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1162 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1163 1164 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)) 1165 1166 #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i)) 1167 #define for_each_inst(i, inst_mask) \ 1168 for (i = ffs(inst_mask); i-- != 0; \ 1169 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1))) 1170 1171 /* Common functions */ 1172 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1173 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1174 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1175 struct amdgpu_job *job, 1176 struct amdgpu_reset_context *reset_context); 1177 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1178 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1179 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1180 bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev); 1181 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1182 1183 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1184 u64 num_vis_bytes); 1185 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1186 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1187 const u32 *registers, 1188 const u32 array_size); 1189 1190 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1191 int amdgpu_device_link_reset(struct amdgpu_device *adev); 1192 bool amdgpu_device_supports_atpx(struct amdgpu_device *adev); 1193 bool amdgpu_device_supports_px(struct amdgpu_device *adev); 1194 bool amdgpu_device_supports_boco(struct amdgpu_device *adev); 1195 bool amdgpu_device_supports_smart_shift(struct amdgpu_device *adev); 1196 int amdgpu_device_supports_baco(struct amdgpu_device *adev); 1197 void amdgpu_device_detect_runtime_pm_mode(struct amdgpu_device *adev); 1198 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1199 struct amdgpu_device *peer_adev); 1200 int amdgpu_device_baco_enter(struct amdgpu_device *adev); 1201 int amdgpu_device_baco_exit(struct amdgpu_device *adev); 1202 1203 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1204 struct amdgpu_ring *ring); 1205 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1206 struct amdgpu_ring *ring); 1207 1208 void amdgpu_device_halt(struct amdgpu_device *adev); 1209 struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev); 1210 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1211 struct dma_fence *gang); 1212 struct dma_fence *amdgpu_device_enforce_isolation(struct amdgpu_device *adev, 1213 struct amdgpu_ring *ring, 1214 struct amdgpu_job *job); 1215 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1216 ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring); 1217 ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset); 1218 void amdgpu_sdma_set_vm_pte_scheds(struct amdgpu_device *adev, 1219 const struct amdgpu_vm_pte_funcs *vm_pte_funcs); 1220 void amdgpu_sdma_set_buffer_funcs_scheds(struct amdgpu_device *adev, 1221 const struct amdgpu_buffer_funcs *buffer_funcs); 1222 1223 /* atpx handler */ 1224 #if defined(CONFIG_VGA_SWITCHEROO) 1225 void amdgpu_register_atpx_handler(void); 1226 void amdgpu_unregister_atpx_handler(void); 1227 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1228 bool amdgpu_is_atpx_hybrid(void); 1229 bool amdgpu_has_atpx(void); 1230 #else 1231 static inline void amdgpu_register_atpx_handler(void) {} 1232 static inline void amdgpu_unregister_atpx_handler(void) {} 1233 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1234 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1235 static inline bool amdgpu_has_atpx(void) { return false; } 1236 #endif 1237 1238 /* 1239 * KMS 1240 */ 1241 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1242 extern const int amdgpu_max_kms_ioctl; 1243 1244 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1245 void amdgpu_driver_unload_kms(struct drm_device *dev); 1246 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1247 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1248 struct drm_file *file_priv); 1249 void amdgpu_driver_release_kms(struct drm_device *dev); 1250 1251 int amdgpu_device_prepare(struct drm_device *dev); 1252 void amdgpu_device_complete(struct drm_device *dev); 1253 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1254 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1255 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1256 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1257 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1258 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1259 struct drm_file *filp); 1260 int amdgpu_proc_options_ioctl(struct drm_device *dev, void *data, 1261 struct drm_file *filp); 1262 1263 /* 1264 * functions used by amdgpu_encoder.c 1265 */ 1266 struct amdgpu_afmt_acr { 1267 u32 clock; 1268 1269 int n_32khz; 1270 int cts_32khz; 1271 1272 int n_44_1khz; 1273 int cts_44_1khz; 1274 1275 int n_48khz; 1276 int cts_48khz; 1277 1278 }; 1279 1280 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1281 1282 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1283 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1284 1285 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1286 pci_channel_state_t state); 1287 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1288 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1289 void amdgpu_pci_resume(struct pci_dev *pdev); 1290 1291 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1292 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1293 1294 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1295 1296 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1297 enum amd_clockgating_state state); 1298 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1299 enum amd_powergating_state state); 1300 1301 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1302 { 1303 return amdgpu_gpu_recovery != 0 && 1304 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1305 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1306 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1307 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1308 } 1309 1310 #include "amdgpu_object.h" 1311 1312 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1313 { 1314 return adev->gmc.tmz_enabled; 1315 } 1316 1317 int amdgpu_in_reset(struct amdgpu_device *adev); 1318 1319 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 1320 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 1321 extern const struct attribute_group amdgpu_flash_attr_group; 1322 1323 void amdgpu_set_init_level(struct amdgpu_device *adev, 1324 enum amdgpu_init_lvl_id lvl); 1325 1326 static inline int amdgpu_device_bus_status_check(struct amdgpu_device *adev) 1327 { 1328 u32 status; 1329 int r; 1330 1331 r = pci_read_config_dword(adev->pdev, PCI_COMMAND, &status); 1332 if (r || PCI_POSSIBLE_ERROR(status)) { 1333 dev_err(adev->dev, "device lost from bus!"); 1334 return -ENODEV; 1335 } 1336 1337 return 0; 1338 } 1339 1340 void amdgpu_device_set_uid(struct amdgpu_uid *uid_info, 1341 enum amdgpu_uid_type type, uint8_t inst, 1342 uint64_t uid); 1343 uint64_t amdgpu_device_get_uid(struct amdgpu_uid *uid_info, 1344 enum amdgpu_uid_type type, uint8_t inst); 1345 #endif 1346