1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #include "amdgpu_ctx.h" 38 39 #include <linux/atomic.h> 40 #include <linux/wait.h> 41 #include <linux/list.h> 42 #include <linux/kref.h> 43 #include <linux/rbtree.h> 44 #include <linux/hashtable.h> 45 #include <linux/dma-fence.h> 46 #include <linux/pci.h> 47 #include <linux/xarray.h> 48 49 #include <drm/ttm/ttm_bo.h> 50 #include <drm/ttm/ttm_placement.h> 51 52 #include <drm/amdgpu_drm.h> 53 #include <drm/drm_gem.h> 54 #include <drm/drm_ioctl.h> 55 56 #include <kgd_kfd_interface.h> 57 #include "dm_pp_interface.h" 58 #include "kgd_pp_interface.h" 59 60 #include "amd_shared.h" 61 #include "amdgpu_utils.h" 62 #include "amdgpu_mode.h" 63 #include "amdgpu_ih.h" 64 #include "amdgpu_irq.h" 65 #include "amdgpu_ucode.h" 66 #include "amdgpu_ttm.h" 67 #include "amdgpu_psp.h" 68 #include "amdgpu_gds.h" 69 #include "amdgpu_sync.h" 70 #include "amdgpu_ring.h" 71 #include "amdgpu_vm.h" 72 #include "amdgpu_dpm.h" 73 #include "amdgpu_acp.h" 74 #include "amdgpu_uvd.h" 75 #include "amdgpu_vce.h" 76 #include "amdgpu_vcn.h" 77 #include "amdgpu_jpeg.h" 78 #include "amdgpu_vpe.h" 79 #include "amdgpu_umsch_mm.h" 80 #include "amdgpu_gmc.h" 81 #include "amdgpu_gfx.h" 82 #include "amdgpu_sdma.h" 83 #include "amdgpu_lsdma.h" 84 #include "amdgpu_nbio.h" 85 #include "amdgpu_reg_access.h" 86 #include "amdgpu_hdp.h" 87 #include "amdgpu_dm.h" 88 #include "amdgpu_virt.h" 89 #include "amdgpu_csa.h" 90 #include "amdgpu_mes_ctx.h" 91 #include "amdgpu_gart.h" 92 #include "amdgpu_debugfs.h" 93 #include "amdgpu_job.h" 94 #include "amdgpu_bo_list.h" 95 #include "amdgpu_gem.h" 96 #include "amdgpu_doorbell.h" 97 #include "amdgpu_amdkfd.h" 98 #include "amdgpu_discovery.h" 99 #include "amdgpu_mes.h" 100 #include "amdgpu_umc.h" 101 #include "amdgpu_mmhub.h" 102 #include "amdgpu_gfxhub.h" 103 #include "amdgpu_df.h" 104 #include "amdgpu_smuio.h" 105 #include "amdgpu_fdinfo.h" 106 #include "amdgpu_mca.h" 107 #include "amdgpu_aca.h" 108 #include "amdgpu_ras.h" 109 #include "amdgpu_lockdep.h" 110 #include "amdgpu_cper.h" 111 #include "amdgpu_xcp.h" 112 #include "amdgpu_seq64.h" 113 #include "amdgpu_reg_state.h" 114 #include "amdgpu_userq.h" 115 #include "amdgpu_eviction_fence.h" 116 #include "amdgpu_ip.h" 117 #include "amdgpu_sa.h" 118 #if defined(CONFIG_DRM_AMD_ISP) 119 #include "amdgpu_isp.h" 120 #endif 121 122 #define MAX_GPU_INSTANCE 64 123 124 #define GFX_SLICE_PERIOD_MS 250 125 126 struct amdgpu_gpu_instance { 127 struct amdgpu_device *adev; 128 int mgpu_fan_enabled; 129 }; 130 131 struct amdgpu_mgpu_info { 132 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 133 struct mutex mutex; 134 uint32_t num_gpu; 135 uint32_t num_dgpu; 136 uint32_t num_apu; 137 }; 138 139 enum amdgpu_ss { 140 AMDGPU_SS_DRV_LOAD, 141 AMDGPU_SS_DEV_D0, 142 AMDGPU_SS_DEV_D3, 143 AMDGPU_SS_DRV_UNLOAD 144 }; 145 146 struct amdgpu_hwip_reg_entry { 147 u32 hwip; 148 u32 inst; 149 u32 seg; 150 u32 reg_offset; 151 const char *reg_name; 152 }; 153 154 struct amdgpu_watchdog_timer { 155 bool timeout_fatal_disable; 156 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 157 }; 158 159 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 160 161 /* 162 * Modules parameters. 163 */ 164 extern int amdgpu_modeset; 165 extern unsigned int amdgpu_vram_limit; 166 extern int amdgpu_vis_vram_limit; 167 extern int amdgpu_gart_size; 168 extern int amdgpu_gtt_size; 169 extern int amdgpu_moverate; 170 extern int amdgpu_audio; 171 extern int amdgpu_disp_priority; 172 extern int amdgpu_hw_i2c; 173 extern int amdgpu_pcie_gen2; 174 extern int amdgpu_msi; 175 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 176 extern int amdgpu_dpm; 177 extern int amdgpu_fw_load_type; 178 extern int amdgpu_aspm; 179 extern int amdgpu_runtime_pm; 180 extern uint amdgpu_ip_block_mask; 181 extern int amdgpu_bapm; 182 extern int amdgpu_deep_color; 183 extern int amdgpu_vm_size; 184 extern int amdgpu_vm_block_size; 185 extern int amdgpu_vm_fragment_size; 186 extern int amdgpu_vm_fault_stop; 187 extern int amdgpu_vm_debug; 188 extern int amdgpu_vm_update_mode; 189 extern int amdgpu_exp_hw_support; 190 extern int amdgpu_dc; 191 extern int amdgpu_sched_jobs; 192 extern int amdgpu_sched_hw_submission; 193 extern uint amdgpu_pcie_gen_cap; 194 extern uint amdgpu_pcie_lane_cap; 195 extern u64 amdgpu_cg_mask; 196 extern uint amdgpu_pg_mask; 197 extern uint amdgpu_sdma_phase_quantum; 198 extern char *amdgpu_disable_cu; 199 extern char *amdgpu_virtual_display; 200 extern uint amdgpu_pp_feature_mask; 201 extern uint amdgpu_force_long_training; 202 extern int amdgpu_lbpw; 203 extern int amdgpu_compute_multipipe; 204 extern int amdgpu_gpu_recovery; 205 extern int amdgpu_emu_mode; 206 extern uint amdgpu_smu_memory_pool_size; 207 extern int amdgpu_smu_pptable_id; 208 extern uint amdgpu_dc_feature_mask; 209 extern uint amdgpu_freesync_vid_mode; 210 extern uint amdgpu_dc_debug_mask; 211 extern uint amdgpu_dc_visual_confirm; 212 extern int amdgpu_dm_abm_level; 213 extern int amdgpu_backlight; 214 extern int amdgpu_damage_clips; 215 extern struct amdgpu_mgpu_info mgpu_info; 216 extern int amdgpu_ras_enable; 217 extern uint amdgpu_ras_mask; 218 extern int amdgpu_bad_page_threshold; 219 extern bool amdgpu_ignore_bad_page_threshold; 220 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 221 extern int amdgpu_async_gfx_ring; 222 extern int amdgpu_mcbp; 223 extern int amdgpu_discovery; 224 extern int amdgpu_mes_log_enable; 225 extern int amdgpu_uni_mes; 226 extern int amdgpu_noretry; 227 extern int amdgpu_force_asic_type; 228 extern int amdgpu_smartshift_bias; 229 extern int amdgpu_use_xgmi_p2p; 230 extern int amdgpu_mtype_local; 231 extern int amdgpu_enforce_isolation; 232 #ifdef CONFIG_HSA_AMD 233 extern int sched_policy; 234 extern bool debug_evictions; 235 extern bool no_system_mem_limit; 236 extern int halt_if_hws_hang; 237 extern uint amdgpu_svm_default_granularity; 238 #else 239 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 240 static const bool __maybe_unused debug_evictions; /* = false */ 241 static const bool __maybe_unused no_system_mem_limit; 242 static const int __maybe_unused halt_if_hws_hang; 243 #endif 244 #ifdef CONFIG_HSA_AMD_P2P 245 extern bool pcie_p2p; 246 #endif 247 248 extern int amdgpu_tmz; 249 extern int amdgpu_reset_method; 250 251 #ifdef CONFIG_DRM_AMDGPU_SI 252 extern int amdgpu_si_support; 253 #endif 254 #ifdef CONFIG_DRM_AMDGPU_CIK 255 extern int amdgpu_cik_support; 256 #endif 257 extern int amdgpu_num_kcq; 258 259 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 260 #define AMDGPU_UMSCHFW_LOG_SIZE (32 * 1024) 261 extern int amdgpu_vcnfw_log; 262 extern int amdgpu_sg_display; 263 extern int amdgpu_umsch_mm; 264 extern int amdgpu_seamless; 265 extern int amdgpu_umsch_mm_fwlog; 266 267 extern int amdgpu_user_partt_mode; 268 extern int amdgpu_agp; 269 extern int amdgpu_rebar; 270 271 extern int amdgpu_wbrf; 272 extern int amdgpu_user_queue; 273 extern int amdgpu_ptl; 274 275 extern uint amdgpu_hdmi_hpd_debounce_delay_ms; 276 277 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 278 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 279 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 280 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 281 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 282 #define AMDGPUFB_CONN_LIMIT 4 283 #define AMDGPU_BIOS_NUM_SCRATCH 16 284 285 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 286 287 /* hard reset data */ 288 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 289 290 /* reset flags */ 291 #define AMDGPU_RESET_GFX (1 << 0) 292 #define AMDGPU_RESET_COMPUTE (1 << 1) 293 #define AMDGPU_RESET_DMA (1 << 2) 294 #define AMDGPU_RESET_CP (1 << 3) 295 #define AMDGPU_RESET_GRBM (1 << 4) 296 #define AMDGPU_RESET_DMA1 (1 << 5) 297 #define AMDGPU_RESET_RLC (1 << 6) 298 #define AMDGPU_RESET_SEM (1 << 7) 299 #define AMDGPU_RESET_IH (1 << 8) 300 #define AMDGPU_RESET_VMC (1 << 9) 301 #define AMDGPU_RESET_MC (1 << 10) 302 #define AMDGPU_RESET_DISPLAY (1 << 11) 303 #define AMDGPU_RESET_UVD (1 << 12) 304 #define AMDGPU_RESET_VCE (1 << 13) 305 #define AMDGPU_RESET_VCE1 (1 << 14) 306 307 /* reset mask */ 308 #define AMDGPU_RESET_TYPE_FULL (1 << 0) /* full adapter reset, mode1/mode2/BACO/etc. */ 309 #define AMDGPU_RESET_TYPE_SOFT_RECOVERY (1 << 1) /* soft recovery, eg. kill shaders */ 310 #define AMDGPU_RESET_TYPE_PER_QUEUE (1 << 2) /* per queue */ 311 #define AMDGPU_RESET_TYPE_PER_PIPE (1 << 3) /* per pipe */ 312 #define AMDGPU_RESET_TYPE_IP_BLOCK_SOFT_RESET (1 << 4) /* soft-resets an IP block */ 313 314 /* max cursor sizes (in pixels) */ 315 #define CIK_CURSOR_WIDTH 128 316 #define CIK_CURSOR_HEIGHT 128 317 318 /* smart shift bias level limits */ 319 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 320 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 321 322 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */ 323 #define AMDGPU_SWCTF_EXTRA_DELAY 50 324 325 struct amdgpu_xcp_mgr; 326 struct amdgpu_device; 327 struct amdgpu_irq_src; 328 struct amdgpu_fpriv; 329 struct amdgpu_bo_va_mapping; 330 struct kfd_vm_fault_info; 331 struct amdgpu_hive_info; 332 struct amdgpu_reset_context; 333 struct amdgpu_reset_control; 334 struct amdgpu_coredump_info; 335 336 enum amdgpu_cp_irq { 337 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 338 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 339 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 340 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 341 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 342 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 343 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 344 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 345 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 346 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 347 348 AMDGPU_CP_IRQ_LAST 349 }; 350 351 enum amdgpu_thermal_irq { 352 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 353 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 354 355 AMDGPU_THERMAL_IRQ_LAST 356 }; 357 358 enum amdgpu_kiq_irq { 359 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 360 AMDGPU_CP_KIQ_IRQ_LAST 361 }; 362 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 363 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 364 #define MAX_KIQ_REG_TRY 1000 365 366 /* 367 * BIOS. 368 */ 369 bool amdgpu_get_bios(struct amdgpu_device *adev); 370 bool amdgpu_read_bios(struct amdgpu_device *adev); 371 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 372 u8 *bios, u32 length_bytes); 373 void amdgpu_bios_release(struct amdgpu_device *adev); 374 /* 375 * Clocks 376 */ 377 378 #define AMDGPU_MAX_PPLL 3 379 380 struct amdgpu_clock { 381 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 382 struct amdgpu_pll spll; 383 struct amdgpu_pll mpll; 384 /* 10 Khz units */ 385 uint32_t default_mclk; 386 uint32_t default_sclk; 387 uint32_t default_dispclk; 388 uint32_t dp_extclk; 389 uint32_t max_pixel_clock; 390 }; 391 392 /* 393 * IRQS. 394 */ 395 396 struct amdgpu_flip_work { 397 struct delayed_work flip_work; 398 struct work_struct unpin_work; 399 struct amdgpu_device *adev; 400 int crtc_id; 401 u32 target_vblank; 402 uint64_t base; 403 struct drm_pending_vblank_event *event; 404 struct amdgpu_bo *old_abo; 405 unsigned shared_count; 406 struct dma_fence **shared; 407 struct dma_fence_cb cb; 408 bool async; 409 }; 410 411 /* 412 * file private structure 413 */ 414 415 struct amdgpu_fpriv { 416 struct amdgpu_vm vm; 417 struct amdgpu_bo_va *prt_va; 418 struct amdgpu_bo_va *csa_va; 419 struct amdgpu_bo_va *seq64_va; 420 struct xarray bo_list_handles; 421 struct amdgpu_ctx_mgr ctx_mgr; 422 struct amdgpu_userq_mgr userq_mgr; 423 424 /* Eviction fence infra */ 425 struct amdgpu_eviction_fence_mgr evf_mgr; 426 427 /** GPU partition selection */ 428 uint32_t xcp_id; 429 }; 430 431 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 432 433 /* 434 * Writeback 435 */ 436 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 437 438 /** 439 * struct amdgpu_wb - This struct is used for small GPU memory allocation. 440 * 441 * This struct is used to allocate a small amount of GPU memory that can be 442 * used to shadow certain states into the memory. This is especially useful for 443 * providing easy CPU access to some states without requiring register access 444 * (e.g., if some block is power gated, reading register may be problematic). 445 * 446 * Note: the term writeback was initially used because many of the amdgpu 447 * components had some level of writeback memory, and this struct initially 448 * described those components. 449 */ 450 struct amdgpu_wb { 451 452 /** 453 * @wb_obj: 454 * 455 * Buffer Object used for the writeback memory. 456 */ 457 struct amdgpu_bo *wb_obj; 458 459 /** 460 * @wb: 461 * 462 * Pointer to the first writeback slot. In terms of CPU address 463 * this value can be accessed directly by using the offset as an index. 464 * For the GPU address, it is necessary to use gpu_addr and the offset. 465 */ 466 uint32_t *wb; 467 468 /** 469 * @gpu_addr: 470 * 471 * Writeback base address in the GPU. 472 */ 473 uint64_t gpu_addr; 474 475 /** 476 * @num_wb: 477 * 478 * Number of writeback slots reserved for amdgpu. 479 */ 480 u32 num_wb; 481 482 /** 483 * @used: 484 * 485 * Track the writeback slot already used. 486 */ 487 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 488 489 /** 490 * @lock: 491 * 492 * Protects read and write of the used field array. 493 */ 494 spinlock_t lock; 495 }; 496 497 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 498 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 499 500 /* 501 * Benchmarking 502 */ 503 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 504 505 /* 506 * ASIC specific register table accessible by UMD 507 */ 508 struct amdgpu_allowed_register_entry { 509 uint32_t reg_offset; 510 bool grbm_indexed; 511 }; 512 513 struct amdgpu_video_codec_info { 514 u32 codec_type; 515 u32 max_width; 516 u32 max_height; 517 u32 max_pixels_per_frame; 518 u32 max_level; 519 }; 520 521 #define codec_info_build(type, width, height, level) \ 522 .codec_type = type,\ 523 .max_width = width,\ 524 .max_height = height,\ 525 .max_pixels_per_frame = height * width,\ 526 .max_level = level, 527 528 struct amdgpu_video_codecs { 529 const u32 codec_count; 530 const struct amdgpu_video_codec_info *codec_array; 531 }; 532 533 /* 534 * ASIC specific functions. 535 */ 536 struct amdgpu_asic_funcs { 537 bool (*read_disabled_bios)(struct amdgpu_device *adev); 538 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 539 u8 *bios, u32 length_bytes); 540 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 541 u32 sh_num, u32 reg_offset, u32 *value); 542 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 543 int (*reset)(struct amdgpu_device *adev); 544 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 545 /* get the reference clock */ 546 u32 (*get_xclk)(struct amdgpu_device *adev); 547 /* MM block clocks */ 548 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 549 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 550 /* static power management */ 551 int (*get_pcie_lanes)(struct amdgpu_device *adev); 552 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 553 /* get config memsize register */ 554 u32 (*get_config_memsize)(struct amdgpu_device *adev); 555 /* flush hdp write queue */ 556 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 557 /* invalidate hdp read cache */ 558 void (*invalidate_hdp)(struct amdgpu_device *adev, 559 struct amdgpu_ring *ring); 560 /* initialize doorbell layout for specific asic*/ 561 void (*init_doorbell_index)(struct amdgpu_device *adev); 562 /* PCIe bandwidth usage */ 563 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 564 uint64_t *count1); 565 /* do we need to reset the asic at init time (e.g., kexec) */ 566 bool (*need_reset_on_init)(struct amdgpu_device *adev); 567 /* PCIe replay counter */ 568 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 569 /* device supports BACO */ 570 int (*supports_baco)(struct amdgpu_device *adev); 571 /* pre asic_init quirks */ 572 void (*pre_asic_init)(struct amdgpu_device *adev); 573 /* enter/exit umd stable pstate */ 574 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 575 /* query video codecs */ 576 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 577 const struct amdgpu_video_codecs **codecs); 578 /* encode "> 32bits" smn addressing */ 579 u64 (*encode_ext_smn_addressing)(int ext_id); 580 581 ssize_t (*get_reg_state)(struct amdgpu_device *adev, 582 enum amdgpu_reg_state reg_state, void *buf, 583 size_t max_size); 584 }; 585 586 /* 587 * IOCTL. 588 */ 589 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 590 struct drm_file *filp); 591 592 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 593 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 594 struct drm_file *filp); 595 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 596 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 597 struct drm_file *filp); 598 599 /* VRAM scratch page for HDP bug, default vram page */ 600 struct amdgpu_mem_scratch { 601 struct amdgpu_bo *robj; 602 uint32_t *ptr; 603 u64 gpu_addr; 604 }; 605 606 /* 607 * CGS 608 */ 609 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 610 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 611 612 /* 613 * Core structure, functions and helpers. 614 */ 615 struct amdgpu_mmio_remap { 616 u32 reg_offset; 617 resource_size_t bus_addr; 618 struct amdgpu_bo *bo; 619 }; 620 621 enum amdgpu_uid_type { 622 AMDGPU_UID_TYPE_XCD, 623 AMDGPU_UID_TYPE_AID, 624 AMDGPU_UID_TYPE_SOC, 625 AMDGPU_UID_TYPE_MID, 626 AMDGPU_UID_TYPE_MAX 627 }; 628 629 #define AMDGPU_UID_INST_MAX 8 /* max number of instances for each UID type */ 630 631 struct amdgpu_uid { 632 uint64_t uid[AMDGPU_UID_TYPE_MAX][AMDGPU_UID_INST_MAX]; 633 struct amdgpu_device *adev; 634 }; 635 636 #define MAX_UMA_OPTION_NAME 28 637 #define MAX_UMA_OPTION_ENTRIES 19 638 639 #define AMDGPU_UMA_FLAG_AUTO BIT(1) 640 #define AMDGPU_UMA_FLAG_CUSTOM BIT(0) 641 642 /** 643 * struct amdgpu_uma_carveout_option - single UMA carveout option 644 * @name: Name of the carveout option 645 * @memory_carved_mb: Amount of memory carved in MB 646 * @flags: ATCS flags supported by this option 647 */ 648 struct amdgpu_uma_carveout_option { 649 char name[MAX_UMA_OPTION_NAME]; 650 uint32_t memory_carved_mb; 651 uint8_t flags; 652 }; 653 654 /** 655 * struct amdgpu_uma_carveout_info - table of available UMA carveout options 656 * @num_entries: Number of available options 657 * @uma_option_index: The index of the option currently applied 658 * @update_lock: Lock to serialize changes to the option 659 * @entries: The array of carveout options 660 */ 661 struct amdgpu_uma_carveout_info { 662 uint8_t num_entries; 663 uint8_t uma_option_index; 664 struct mutex update_lock; 665 struct amdgpu_uma_carveout_option entries[MAX_UMA_OPTION_ENTRIES]; 666 }; 667 668 struct amd_powerplay { 669 void *pp_handle; 670 const struct amd_pm_funcs *pp_funcs; 671 }; 672 673 /* polaris10 kickers */ 674 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 675 ((rid == 0xE3) || \ 676 (rid == 0xE4) || \ 677 (rid == 0xE5) || \ 678 (rid == 0xE7) || \ 679 (rid == 0xEF))) || \ 680 ((did == 0x6FDF) && \ 681 ((rid == 0xE7) || \ 682 (rid == 0xEF) || \ 683 (rid == 0xFF)))) 684 685 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 686 ((rid == 0xE1) || \ 687 (rid == 0xF7))) 688 689 /* polaris11 kickers */ 690 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 691 ((rid == 0xE0) || \ 692 (rid == 0xE5))) || \ 693 ((did == 0x67FF) && \ 694 ((rid == 0xCF) || \ 695 (rid == 0xEF) || \ 696 (rid == 0xFF)))) 697 698 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 699 ((rid == 0xE2))) 700 701 /* polaris12 kickers */ 702 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 703 ((rid == 0xC0) || \ 704 (rid == 0xC1) || \ 705 (rid == 0xC3) || \ 706 (rid == 0xC7))) || \ 707 ((did == 0x6981) && \ 708 ((rid == 0x00) || \ 709 (rid == 0x01) || \ 710 (rid == 0x10)))) 711 712 enum amdgpu_mqd_update_flag { 713 AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE = 1, 714 AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE = 2, 715 AMDGPU_UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ 716 }; 717 718 struct amdgpu_mqd_prop { 719 uint64_t mqd_gpu_addr; 720 uint64_t hqd_base_gpu_addr; 721 uint64_t rptr_gpu_addr; 722 uint64_t wptr_gpu_addr; 723 uint32_t queue_size; 724 bool use_doorbell; 725 uint32_t doorbell_index; 726 uint64_t eop_gpu_addr; 727 uint32_t hqd_pipe_priority; 728 uint32_t hqd_queue_priority; 729 uint32_t mqd_stride_size; 730 bool allow_tunneling; 731 bool hqd_active; 732 uint64_t shadow_addr; 733 uint64_t gds_bkup_addr; 734 uint64_t csa_addr; 735 uint64_t fence_address; 736 bool tmz_queue; 737 bool kernel_queue; 738 uint32_t *cu_mask; 739 uint32_t cu_mask_count; 740 uint32_t cu_flags; 741 bool is_user_cu_masked; 742 }; 743 744 struct amdgpu_mqd { 745 unsigned mqd_size; 746 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 747 struct amdgpu_mqd_prop *p); 748 }; 749 750 struct amdgpu_pcie_reset_ctx { 751 bool in_link_reset; 752 bool occurs_dpc; 753 bool audio_suspended; 754 struct pci_dev *swus; 755 struct pci_saved_state *swus_pcistate; 756 struct pci_saved_state *swds_pcistate; 757 }; 758 759 /* 760 * Custom Init levels could be defined for different situations where a full 761 * initialization of all hardware blocks are not expected. Sample cases are 762 * custom init sequences after resume after S0i3/S3, reset on initialization, 763 * partial reset of blocks etc. Presently, this defines only two levels. Levels 764 * are described in corresponding struct definitions - amdgpu_init_default, 765 * amdgpu_init_minimal_xgmi. 766 */ 767 enum amdgpu_init_lvl_id { 768 AMDGPU_INIT_LEVEL_DEFAULT, 769 AMDGPU_INIT_LEVEL_MINIMAL_XGMI, 770 AMDGPU_INIT_LEVEL_RESET_RECOVERY, 771 }; 772 773 struct amdgpu_init_level { 774 enum amdgpu_init_lvl_id level; 775 uint32_t hwini_ip_block_mask; 776 }; 777 778 #define AMDGPU_RESET_MAGIC_NUM 64 779 #define AMDGPU_MAX_DF_PERFMONS 4 780 struct amdgpu_reset_domain; 781 struct amdgpu_fru_info; 782 783 enum amdgpu_enforce_isolation_mode { 784 AMDGPU_ENFORCE_ISOLATION_DISABLE = 0, 785 AMDGPU_ENFORCE_ISOLATION_ENABLE = 1, 786 AMDGPU_ENFORCE_ISOLATION_ENABLE_LEGACY = 2, 787 AMDGPU_ENFORCE_ISOLATION_NO_CLEANER_SHADER = 3, 788 }; 789 790 struct amdgpu_device { 791 struct device *dev; 792 struct pci_dev *pdev; 793 struct drm_device ddev; 794 795 #ifdef CONFIG_DRM_AMD_ACP 796 struct amdgpu_acp acp; 797 #endif 798 struct amdgpu_hive_info *hive; 799 struct amdgpu_xcp_mgr *xcp_mgr; 800 /* ASIC */ 801 enum amd_asic_type asic_type; 802 uint32_t family; 803 uint32_t rev_id; 804 uint32_t external_rev_id; 805 unsigned long flags; 806 unsigned long apu_flags; 807 int usec_timeout; 808 const struct amdgpu_asic_funcs *asic_funcs; 809 bool shutdown; 810 bool need_swiotlb; 811 bool accel_working; 812 struct notifier_block acpi_nb; 813 struct notifier_block pm_nb; 814 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 815 struct debugfs_blob_wrapper debugfs_vbios_blob; 816 struct mutex srbm_mutex; 817 /* GRBM index mutex. Protects concurrent access to GRBM index */ 818 struct mutex grbm_idx_mutex; 819 struct dev_pm_domain vga_pm_domain; 820 bool have_disp_power_ref; 821 bool have_atomics_support; 822 823 /* BIOS */ 824 bool is_atom_fw; 825 uint8_t *bios; 826 uint32_t bios_size; 827 uint32_t bios_scratch_reg_offset; 828 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 829 830 /* Register/doorbell mmio */ 831 resource_size_t rmmio_base; 832 resource_size_t rmmio_size; 833 void __iomem *rmmio; 834 /* protects concurrent MM_INDEX/DATA based register access */ 835 spinlock_t mmio_idx_lock; 836 struct amdgpu_mmio_remap rmmio_remap; 837 /* Indirect register access blocks */ 838 struct amdgpu_reg_access reg; 839 struct amdgpu_doorbell doorbell; 840 841 /* clock/pll info */ 842 struct amdgpu_clock clock; 843 844 /* MC */ 845 struct amdgpu_gmc gmc; 846 struct amdgpu_gart gart; 847 dma_addr_t dummy_page_addr; 848 struct amdgpu_vm_manager vm_manager; 849 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 850 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS); 851 852 /* memory management */ 853 struct amdgpu_mman mman; 854 struct amdgpu_mem_scratch mem_scratch; 855 struct amdgpu_wb wb; 856 atomic64_t num_bytes_moved; 857 atomic64_t num_evictions; 858 atomic64_t num_vram_cpu_page_faults; 859 atomic_t gpu_reset_counter; 860 atomic_t vram_lost_counter; 861 862 /* data for buffer migration throttling */ 863 struct { 864 spinlock_t lock; 865 s64 last_update_us; 866 s64 accum_us; /* accumulated microseconds */ 867 s64 accum_us_vis; /* for visible VRAM */ 868 u32 log2_max_MBps; 869 } mm_stats; 870 871 /* discovery*/ 872 struct amdgpu_discovery_info discovery; 873 874 /* display */ 875 bool enable_virtual_display; 876 struct amdgpu_vkms_output *amdgpu_vkms_output; 877 struct amdgpu_mode_info mode_info; 878 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 879 struct delayed_work hotplug_work; 880 struct amdgpu_irq_src crtc_irq; 881 struct amdgpu_irq_src vline0_irq; 882 struct amdgpu_irq_src vupdate_irq; 883 struct amdgpu_irq_src pageflip_irq; 884 struct amdgpu_irq_src hpd_irq; 885 struct amdgpu_irq_src dmub_trace_irq; 886 struct amdgpu_irq_src dmub_outbox_irq; 887 888 /* rings */ 889 u64 fence_context; 890 unsigned num_rings; 891 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 892 struct dma_fence __rcu *gang_submit; 893 bool ib_pool_ready; 894 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 895 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 896 897 /* interrupts */ 898 struct amdgpu_irq irq; 899 900 /* powerplay */ 901 struct amd_powerplay powerplay; 902 struct amdgpu_pm pm; 903 u64 cg_flags; 904 u32 pg_flags; 905 906 /* nbio */ 907 struct amdgpu_nbio nbio; 908 909 /* hdp */ 910 struct amdgpu_hdp hdp; 911 912 /* smuio */ 913 struct amdgpu_smuio smuio; 914 915 /* mmhub */ 916 struct amdgpu_mmhub mmhub; 917 918 /* gfxhub */ 919 struct amdgpu_gfxhub gfxhub; 920 921 /* gfx */ 922 struct amdgpu_gfx gfx; 923 924 /* sdma */ 925 struct amdgpu_sdma sdma; 926 927 /* lsdma */ 928 struct amdgpu_lsdma lsdma; 929 930 /* uvd */ 931 struct amdgpu_uvd uvd; 932 933 /* vce */ 934 struct amdgpu_vce vce; 935 936 /* vcn */ 937 struct amdgpu_vcn vcn; 938 939 /* jpeg */ 940 struct amdgpu_jpeg jpeg; 941 942 /* vpe */ 943 struct amdgpu_vpe vpe; 944 945 /* umsch */ 946 struct amdgpu_umsch_mm umsch_mm; 947 bool enable_umsch_mm; 948 949 /* firmwares */ 950 struct amdgpu_firmware firmware; 951 952 /* PSP */ 953 struct psp_context psp; 954 955 /* GDS */ 956 struct amdgpu_gds gds; 957 958 /* for userq and VM fences */ 959 struct amdgpu_seq64 seq64; 960 961 /* UMC */ 962 struct amdgpu_umc umc; 963 964 /* display related functionality */ 965 struct amdgpu_display_manager dm; 966 967 #if defined(CONFIG_DRM_AMD_ISP) 968 /* isp */ 969 struct amdgpu_isp isp; 970 #endif 971 972 /* mes */ 973 bool enable_mes; 974 bool enable_mes_kiq; 975 bool enable_uni_mes; 976 struct amdgpu_mes mes; 977 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 978 const struct amdgpu_userq_funcs *userq_funcs[AMDGPU_HW_IP_NUM]; 979 980 /** 981 * @userq_doorbell_xa: Global user queue map (doorbell index → queue) 982 * Key: doorbell_index (unique global identifier for the queue) 983 * Value: struct amdgpu_usermode_queue 984 */ 985 struct xarray userq_doorbell_xa; 986 987 /* df */ 988 struct amdgpu_df df; 989 990 /* MCA */ 991 struct amdgpu_mca mca; 992 993 /* ACA */ 994 struct amdgpu_aca aca; 995 996 /* CPER */ 997 struct amdgpu_cper cper; 998 999 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1000 uint32_t harvest_ip_mask; 1001 int num_ip_blocks; 1002 struct mutex mn_lock; 1003 DECLARE_HASHTABLE(mn_hash, 7); 1004 1005 /* tracking pinned memory */ 1006 atomic64_t vram_pin_size; 1007 atomic64_t visible_pin_size; 1008 atomic64_t gart_pin_size; 1009 1010 /* soc15 register offset based on ip, instance and segment */ 1011 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1012 struct amdgpu_ip_map_info ip_map; 1013 1014 /* delayed work_func for deferring clockgating during resume */ 1015 struct delayed_work delayed_init_work; 1016 1017 struct amdgpu_virt virt; 1018 1019 /* record hw reset is performed */ 1020 bool has_hw_reset; 1021 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1022 1023 /* s3/s4 mask */ 1024 bool in_suspend; 1025 bool in_s3; 1026 bool in_s4; 1027 bool in_s0ix; 1028 suspend_state_t last_suspend_state; 1029 1030 enum pp_mp1_state mp1_state; 1031 struct amdgpu_doorbell_index doorbell_index; 1032 1033 struct mutex notifier_lock; 1034 1035 int asic_reset_res; 1036 struct work_struct xgmi_reset_work; 1037 struct list_head reset_list; 1038 1039 long gfx_timeout; 1040 long sdma_timeout; 1041 long video_timeout; 1042 long compute_timeout; 1043 long psp_timeout; 1044 1045 uint64_t unique_id; 1046 uint8_t unitid; 1047 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1048 1049 /* enable runtime pm on the device */ 1050 bool in_runpm; 1051 bool has_pr3; 1052 1053 bool ucode_sysfs_en; 1054 1055 struct amdgpu_fru_info *fru_info; 1056 atomic_t throttling_logging_enabled; 1057 struct ratelimit_state throttling_logging_rs; 1058 uint32_t ras_hw_enabled; 1059 uint32_t ras_enabled; 1060 bool ras_default_ecc_enabled; 1061 1062 bool no_hw_access; 1063 struct pci_saved_state *pci_state; 1064 pci_channel_state_t pci_channel_state; 1065 1066 struct amdgpu_pcie_reset_ctx pcie_reset_ctx; 1067 1068 /* Track auto wait count on s_barrier settings */ 1069 bool barrier_has_auto_waitcnt; 1070 1071 struct amdgpu_reset_control *reset_cntl; 1072 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1073 1074 bool ram_is_direct_mapped; 1075 1076 struct list_head ras_list; 1077 1078 struct amdgpu_reset_domain *reset_domain; 1079 1080 #ifdef CONFIG_DEV_COREDUMP 1081 struct amdgpu_coredump_info *coredump; 1082 struct work_struct coredump_work; 1083 #endif 1084 1085 struct mutex benchmark_mutex; 1086 1087 bool scpm_enabled; 1088 uint32_t scpm_status; 1089 1090 struct work_struct reset_work; 1091 1092 bool dc_enabled; 1093 /* Mask of active clusters */ 1094 uint32_t aid_mask; 1095 1096 /* Debug */ 1097 bool debug_vm; 1098 bool debug_largebar; 1099 bool debug_disable_soft_recovery; 1100 bool debug_use_vram_fw_buf; 1101 bool debug_enable_ras_aca; 1102 bool debug_exp_resets; 1103 bool debug_disable_gpu_ring_reset; 1104 bool debug_vm_userptr; 1105 bool debug_disable_ce_logs; 1106 bool debug_enable_ce_cs; 1107 bool debug_hibernation_thaw_resume_gpu; 1108 bool debug_disable_ip_block_soft_reset; 1109 1110 /* Protection for the following isolation structure */ 1111 struct mutex enforce_isolation_mutex; 1112 enum amdgpu_enforce_isolation_mode enforce_isolation[MAX_XCP]; 1113 struct amdgpu_isolation { 1114 void *owner; 1115 struct dma_fence *spearhead; 1116 struct amdgpu_sync active; 1117 struct amdgpu_sync prev; 1118 } isolation[MAX_XCP]; 1119 1120 struct amdgpu_init_level *init_lvl; 1121 1122 /* This flag is used to determine how VRAM allocations are handled for APUs 1123 * in KFD: VRAM or GTT. 1124 */ 1125 bool apu_prefer_gtt; 1126 1127 bool userq_halt_for_enforce_isolation; 1128 struct amdgpu_uid *uid_info; 1129 1130 struct amdgpu_uma_carveout_info uma_info; 1131 1132 /* KFD 1133 * Must be last --ends in a flexible-array member. 1134 */ 1135 struct amdgpu_kfd_dev kfd; 1136 }; 1137 1138 /* 1139 * MES FW uses address(mqd_addr + sizeof(struct mqd) + 3*sizeof(uint32_t)) 1140 * as fence address and writes a 32 bit fence value to this address. 1141 * Driver needs to allocate at least 4 DWs extra memory in addition to 1142 * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE for safety. 1143 */ 1144 #define AMDGPU_MQD_SIZE_ALIGN(mqd_size) AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32)) 1145 1146 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, 1147 uint8_t ip, uint8_t inst) 1148 { 1149 /* This considers only major/minor/rev and ignores 1150 * subrevision/variant fields. 1151 */ 1152 return adev->ip_versions[ip][inst] & ~0xFFU; 1153 } 1154 1155 static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev, 1156 uint8_t ip, uint8_t inst) 1157 { 1158 /* This returns full version - major/minor/rev/variant/subrevision */ 1159 return adev->ip_versions[ip][inst]; 1160 } 1161 1162 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1163 { 1164 return container_of(ddev, struct amdgpu_device, ddev); 1165 } 1166 1167 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1168 { 1169 return &adev->ddev; 1170 } 1171 1172 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1173 { 1174 return container_of(bdev, struct amdgpu_device, mman.bdev); 1175 } 1176 1177 static inline bool amdgpu_is_multi_aid(struct amdgpu_device *adev) 1178 { 1179 return !!adev->aid_mask; 1180 } 1181 1182 int amdgpu_device_init(struct amdgpu_device *adev, 1183 uint32_t flags); 1184 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1185 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1186 1187 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1188 1189 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1190 void *buf, size_t size, bool write); 1191 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1192 void *buf, size_t size, bool write); 1193 1194 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1195 void *buf, size_t size, bool write); 1196 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev); 1197 bool amdgpu_device_asic_has_dc_support(struct pci_dev *pdev, 1198 enum amd_asic_type asic_type); 1199 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1200 1201 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev); 1202 1203 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1204 struct amdgpu_reset_context *reset_context); 1205 1206 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1207 struct amdgpu_reset_context *reset_context); 1208 1209 int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context); 1210 1211 int emu_soc_asic_init(struct amdgpu_device *adev); 1212 1213 /* 1214 * Registers read & write functions. 1215 */ 1216 #define AMDGPU_REGS_NO_KIQ (1<<1) 1217 #define AMDGPU_REGS_RLC (1<<2) 1218 1219 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1220 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1221 1222 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0) 1223 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0) 1224 1225 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1226 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1227 1228 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1229 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1230 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1231 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1232 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1233 #define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst) 1234 #define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst) 1235 #define RREG32_PCIE(reg) amdgpu_reg_pcie_rd32(adev, (reg)) 1236 #define WREG32_PCIE(reg, v) amdgpu_reg_pcie_wr32(adev, (reg), (v)) 1237 #define RREG32_PCIE_PORT(reg) amdgpu_reg_pciep_rd32(adev, (reg)) 1238 #define WREG32_PCIE_PORT(reg, v) amdgpu_reg_pciep_wr32(adev, (reg), (v)) 1239 #define RREG32_PCIE_EXT(reg) amdgpu_reg_pcie_ext_rd32(adev, (reg)) 1240 #define WREG32_PCIE_EXT(reg, v) amdgpu_reg_pcie_ext_wr32(adev, (reg), (v)) 1241 #define RREG64_PCIE(reg) amdgpu_reg_pcie_rd64(adev, (reg)) 1242 #define WREG64_PCIE(reg, v) amdgpu_reg_pcie_wr64(adev, (reg), (v)) 1243 #define RREG64_PCIE_EXT(reg) amdgpu_reg_pcie_ext_rd64(adev, (reg)) 1244 #define WREG64_PCIE_EXT(reg, v) amdgpu_reg_pcie_ext_wr64(adev, (reg), (v)) 1245 #define RREG32_SMC(reg) amdgpu_reg_smc_rd32(adev, (reg)) 1246 #define WREG32_SMC(reg, v) amdgpu_reg_smc_wr32(adev, (reg), (v)) 1247 #define RREG32_UVD_CTX(reg) amdgpu_reg_uvd_ctx_rd32(adev, (reg)) 1248 #define WREG32_UVD_CTX(reg, v) amdgpu_reg_uvd_ctx_wr32(adev, (reg), (v)) 1249 #define RREG32_DIDT(reg) amdgpu_reg_didt_rd32(adev, (reg)) 1250 #define WREG32_DIDT(reg, v) amdgpu_reg_didt_wr32(adev, (reg), (v)) 1251 #define RREG32_GC_CAC(reg) amdgpu_reg_gc_cac_rd32(adev, (reg)) 1252 #define WREG32_GC_CAC(reg, v) amdgpu_reg_gc_cac_wr32(adev, (reg), (v)) 1253 #define RREG32_SE_CAC(reg) amdgpu_reg_se_cac_rd32(adev, (reg)) 1254 #define WREG32_SE_CAC(reg, v) amdgpu_reg_se_cac_wr32(adev, (reg), (v)) 1255 #define RREG32_AUDIO_ENDPT(block, reg) \ 1256 amdgpu_reg_audio_endpt_rd32(adev, (block), (reg)) 1257 #define WREG32_AUDIO_ENDPT(block, reg, v) \ 1258 amdgpu_reg_audio_endpt_wr32(adev, (block), (reg), (v)) 1259 #define WREG32_P(reg, val, mask) \ 1260 do { \ 1261 uint32_t tmp_ = RREG32(reg); \ 1262 tmp_ &= (mask); \ 1263 tmp_ |= ((val) & ~(mask)); \ 1264 WREG32(reg, tmp_); \ 1265 } while (0) 1266 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1267 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1268 #define WREG32_PLL_P(reg, val, mask) \ 1269 do { \ 1270 uint32_t tmp_ = RREG32_PLL(reg); \ 1271 tmp_ &= (mask); \ 1272 tmp_ |= ((val) & ~(mask)); \ 1273 WREG32_PLL(reg, tmp_); \ 1274 } while (0) 1275 1276 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1277 do { \ 1278 u32 tmp = RREG32_SMC(_Reg); \ 1279 tmp &= (_Mask); \ 1280 tmp |= ((_Val) & ~(_Mask)); \ 1281 WREG32_SMC(_Reg, tmp); \ 1282 } while (0) 1283 1284 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1285 1286 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1287 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1288 1289 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1290 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1291 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1292 1293 #define REG_GET_FIELD(value, reg, field) \ 1294 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1295 1296 #define WREG32_FIELD(reg, field, val) \ 1297 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1298 1299 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1300 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1301 1302 #define AMDGPU_GET_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> (l)) 1303 /* 1304 * BIOS helpers. 1305 */ 1306 #define RBIOS8(i) (adev->bios[i]) 1307 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1308 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1309 1310 #include "amdgpu_reset.h" 1311 1312 /* 1313 * ASICs macro. 1314 */ 1315 #define amdgpu_asic_set_vga_state(adev, state) \ 1316 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0) 1317 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1318 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1319 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1320 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1321 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1322 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1323 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1324 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1325 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1326 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1327 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1328 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1329 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1330 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1331 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1332 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1333 #define amdgpu_asic_supports_baco(adev) \ 1334 ((adev)->asic_funcs->supports_baco ? (adev)->asic_funcs->supports_baco((adev)) : 0) 1335 #define amdgpu_asic_pre_asic_init(adev) \ 1336 { \ 1337 if ((adev)->asic_funcs && (adev)->asic_funcs->pre_asic_init) \ 1338 (adev)->asic_funcs->pre_asic_init((adev)); \ 1339 } 1340 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1341 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1342 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1343 1344 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)) 1345 1346 #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i)) 1347 #define for_each_inst(i, inst_mask) \ 1348 for (i = ffs(inst_mask); i-- != 0; \ 1349 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1))) 1350 1351 /* Common functions */ 1352 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1353 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1354 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1355 struct amdgpu_job *job, 1356 struct amdgpu_reset_context *reset_context); 1357 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1358 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1359 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1360 bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev); 1361 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1362 1363 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1364 u64 num_vis_bytes); 1365 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1366 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1367 const u32 *registers, 1368 const u32 array_size); 1369 1370 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1371 int amdgpu_device_link_reset(struct amdgpu_device *adev); 1372 bool amdgpu_device_supports_atpx(struct amdgpu_device *adev); 1373 bool amdgpu_device_supports_px(struct amdgpu_device *adev); 1374 bool amdgpu_device_supports_boco(struct amdgpu_device *adev); 1375 bool amdgpu_device_supports_smart_shift(struct amdgpu_device *adev); 1376 int amdgpu_device_supports_baco(struct amdgpu_device *adev); 1377 void amdgpu_device_detect_runtime_pm_mode(struct amdgpu_device *adev); 1378 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1379 struct amdgpu_device *peer_adev); 1380 int amdgpu_device_baco_enter(struct amdgpu_device *adev); 1381 int amdgpu_device_baco_exit(struct amdgpu_device *adev); 1382 1383 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1384 struct amdgpu_ring *ring); 1385 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1386 struct amdgpu_ring *ring); 1387 1388 void amdgpu_device_halt(struct amdgpu_device *adev); 1389 struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev); 1390 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1391 struct dma_fence *gang); 1392 struct dma_fence *amdgpu_device_enforce_isolation(struct amdgpu_device *adev, 1393 struct amdgpu_ring *ring, 1394 struct amdgpu_job *job); 1395 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1396 ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring); 1397 ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset); 1398 void amdgpu_sdma_set_vm_pte_scheds(struct amdgpu_device *adev, 1399 const struct amdgpu_vm_pte_funcs *vm_pte_funcs); 1400 void amdgpu_sdma_set_buffer_funcs_scheds(struct amdgpu_device *adev, 1401 const struct amdgpu_buffer_funcs *buffer_funcs); 1402 1403 /* atpx handler */ 1404 #if defined(CONFIG_VGA_SWITCHEROO) 1405 void amdgpu_register_atpx_handler(void); 1406 void amdgpu_unregister_atpx_handler(void); 1407 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1408 bool amdgpu_is_atpx_hybrid(void); 1409 bool amdgpu_has_atpx(void); 1410 #else 1411 static inline void amdgpu_register_atpx_handler(void) {} 1412 static inline void amdgpu_unregister_atpx_handler(void) {} 1413 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1414 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1415 static inline bool amdgpu_has_atpx(void) { return false; } 1416 #endif 1417 1418 /* 1419 * KMS 1420 */ 1421 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1422 extern const int amdgpu_max_kms_ioctl; 1423 1424 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1425 void amdgpu_driver_unload_kms(struct drm_device *dev); 1426 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1427 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1428 struct drm_file *file_priv); 1429 void amdgpu_driver_release_kms(struct drm_device *dev); 1430 1431 int amdgpu_device_prepare(struct drm_device *dev); 1432 void amdgpu_device_complete(struct drm_device *dev); 1433 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1434 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1435 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1436 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1437 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1438 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1439 struct drm_file *filp); 1440 int amdgpu_proc_options_ioctl(struct drm_device *dev, void *data, 1441 struct drm_file *filp); 1442 1443 /* 1444 * functions used by amdgpu_encoder.c 1445 */ 1446 struct amdgpu_afmt_acr { 1447 u32 clock; 1448 1449 int n_32khz; 1450 int cts_32khz; 1451 1452 int n_44_1khz; 1453 int cts_44_1khz; 1454 1455 int n_48khz; 1456 int cts_48khz; 1457 1458 }; 1459 1460 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1461 1462 /* amdgpu_acpi.c */ 1463 1464 struct amdgpu_numa_info { 1465 uint64_t size; 1466 int pxm; 1467 int nid; 1468 }; 1469 1470 /* ATCS Device/Driver State */ 1471 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1472 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1473 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1474 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1475 1476 #if defined(CONFIG_ACPI) 1477 int amdgpu_acpi_init(struct amdgpu_device *adev); 1478 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1479 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1480 bool amdgpu_acpi_is_power_shift_control_supported(void); 1481 bool amdgpu_acpi_is_set_uma_allocation_size_supported(void); 1482 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1483 u8 perf_req, bool advertise); 1484 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1485 u8 dev_state, bool drv_state); 1486 int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev, 1487 enum amdgpu_ss ss_state); 1488 int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type); 1489 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1490 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, 1491 u64 *tmr_size); 1492 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, 1493 struct amdgpu_numa_info *numa_info); 1494 1495 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1496 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1497 void amdgpu_acpi_detect(void); 1498 void amdgpu_acpi_release(void); 1499 #else 1500 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1501 static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, 1502 u64 *tmr_offset, u64 *tmr_size) 1503 { 1504 return -EINVAL; 1505 } 1506 static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, 1507 int xcc_id, 1508 struct amdgpu_numa_info *numa_info) 1509 { 1510 return -EINVAL; 1511 } 1512 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1513 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1514 static inline void amdgpu_acpi_detect(void) { } 1515 static inline void amdgpu_acpi_release(void) { } 1516 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1517 static inline bool amdgpu_acpi_is_set_uma_allocation_size_supported(void) { return false; } 1518 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1519 u8 dev_state, bool drv_state) { return 0; } 1520 static inline int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev, 1521 enum amdgpu_ss ss_state) 1522 { 1523 return 0; 1524 } 1525 static inline int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type) 1526 { 1527 return -EINVAL; 1528 } 1529 static inline void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps) { } 1530 #endif 1531 1532 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1533 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1534 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1535 #else 1536 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1537 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1538 #endif 1539 1540 #if defined(CONFIG_DRM_AMD_ISP) 1541 int amdgpu_acpi_get_isp4_dev(struct acpi_device **dev); 1542 #endif 1543 1544 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1545 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1546 1547 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1548 pci_channel_state_t state); 1549 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1550 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1551 void amdgpu_pci_resume(struct pci_dev *pdev); 1552 1553 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1554 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1555 1556 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1557 1558 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1559 enum amd_clockgating_state state); 1560 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1561 enum amd_powergating_state state); 1562 1563 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1564 { 1565 return amdgpu_gpu_recovery != 0 && 1566 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1567 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1568 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1569 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1570 } 1571 1572 #include "amdgpu_object.h" 1573 1574 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1575 { 1576 return adev->gmc.tmz_enabled; 1577 } 1578 1579 int amdgpu_in_reset(struct amdgpu_device *adev); 1580 1581 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 1582 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 1583 extern const struct attribute_group amdgpu_flash_attr_group; 1584 1585 void amdgpu_set_init_level(struct amdgpu_device *adev, 1586 enum amdgpu_init_lvl_id lvl); 1587 1588 static inline int amdgpu_device_bus_status_check(struct amdgpu_device *adev) 1589 { 1590 u32 status; 1591 int r; 1592 1593 r = pci_read_config_dword(adev->pdev, PCI_COMMAND, &status); 1594 if (r || PCI_POSSIBLE_ERROR(status)) { 1595 dev_err(adev->dev, "device lost from bus!"); 1596 return -ENODEV; 1597 } 1598 1599 return 0; 1600 } 1601 1602 void amdgpu_device_set_uid(struct amdgpu_uid *uid_info, 1603 enum amdgpu_uid_type type, uint8_t inst, 1604 uint64_t uid); 1605 uint64_t amdgpu_device_get_uid(struct amdgpu_uid *uid_info, 1606 enum amdgpu_uid_type type, uint8_t inst); 1607 #endif 1608