1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 54 #include <drm/ttm/ttm_bo.h> 55 #include <drm/ttm/ttm_placement.h> 56 57 #include <drm/amdgpu_drm.h> 58 #include <drm/drm_gem.h> 59 #include <drm/drm_ioctl.h> 60 61 #include <kgd_kfd_interface.h> 62 #include "dm_pp_interface.h" 63 #include "kgd_pp_interface.h" 64 65 #include "amd_shared.h" 66 #include "amdgpu_mode.h" 67 #include "amdgpu_ih.h" 68 #include "amdgpu_irq.h" 69 #include "amdgpu_ucode.h" 70 #include "amdgpu_ttm.h" 71 #include "amdgpu_psp.h" 72 #include "amdgpu_gds.h" 73 #include "amdgpu_sync.h" 74 #include "amdgpu_ring.h" 75 #include "amdgpu_vm.h" 76 #include "amdgpu_dpm.h" 77 #include "amdgpu_acp.h" 78 #include "amdgpu_uvd.h" 79 #include "amdgpu_vce.h" 80 #include "amdgpu_vcn.h" 81 #include "amdgpu_jpeg.h" 82 #include "amdgpu_vpe.h" 83 #include "amdgpu_umsch_mm.h" 84 #include "amdgpu_gmc.h" 85 #include "amdgpu_gfx.h" 86 #include "amdgpu_sdma.h" 87 #include "amdgpu_lsdma.h" 88 #include "amdgpu_nbio.h" 89 #include "amdgpu_hdp.h" 90 #include "amdgpu_dm.h" 91 #include "amdgpu_virt.h" 92 #include "amdgpu_csa.h" 93 #include "amdgpu_mes_ctx.h" 94 #include "amdgpu_gart.h" 95 #include "amdgpu_debugfs.h" 96 #include "amdgpu_job.h" 97 #include "amdgpu_bo_list.h" 98 #include "amdgpu_gem.h" 99 #include "amdgpu_doorbell.h" 100 #include "amdgpu_amdkfd.h" 101 #include "amdgpu_discovery.h" 102 #include "amdgpu_mes.h" 103 #include "amdgpu_umc.h" 104 #include "amdgpu_mmhub.h" 105 #include "amdgpu_gfxhub.h" 106 #include "amdgpu_df.h" 107 #include "amdgpu_smuio.h" 108 #include "amdgpu_fdinfo.h" 109 #include "amdgpu_mca.h" 110 #include "amdgpu_ras.h" 111 #include "amdgpu_xcp.h" 112 #include "amdgpu_seq64.h" 113 #include "amdgpu_reg_state.h" 114 115 #define MAX_GPU_INSTANCE 64 116 117 struct amdgpu_gpu_instance 118 { 119 struct amdgpu_device *adev; 120 int mgpu_fan_enabled; 121 }; 122 123 struct amdgpu_mgpu_info 124 { 125 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 126 struct mutex mutex; 127 uint32_t num_gpu; 128 uint32_t num_dgpu; 129 uint32_t num_apu; 130 131 /* delayed reset_func for XGMI configuration if necessary */ 132 struct delayed_work delayed_reset_work; 133 bool pending_reset; 134 }; 135 136 enum amdgpu_ss { 137 AMDGPU_SS_DRV_LOAD, 138 AMDGPU_SS_DEV_D0, 139 AMDGPU_SS_DEV_D3, 140 AMDGPU_SS_DRV_UNLOAD 141 }; 142 143 struct amdgpu_watchdog_timer 144 { 145 bool timeout_fatal_disable; 146 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 147 }; 148 149 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 150 151 /* 152 * Modules parameters. 153 */ 154 extern int amdgpu_modeset; 155 extern unsigned int amdgpu_vram_limit; 156 extern int amdgpu_vis_vram_limit; 157 extern int amdgpu_gart_size; 158 extern int amdgpu_gtt_size; 159 extern int amdgpu_moverate; 160 extern int amdgpu_audio; 161 extern int amdgpu_disp_priority; 162 extern int amdgpu_hw_i2c; 163 extern int amdgpu_pcie_gen2; 164 extern int amdgpu_msi; 165 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 166 extern int amdgpu_dpm; 167 extern int amdgpu_fw_load_type; 168 extern int amdgpu_aspm; 169 extern int amdgpu_runtime_pm; 170 extern uint amdgpu_ip_block_mask; 171 extern int amdgpu_bapm; 172 extern int amdgpu_deep_color; 173 extern int amdgpu_vm_size; 174 extern int amdgpu_vm_block_size; 175 extern int amdgpu_vm_fragment_size; 176 extern int amdgpu_vm_fault_stop; 177 extern int amdgpu_vm_debug; 178 extern int amdgpu_vm_update_mode; 179 extern int amdgpu_exp_hw_support; 180 extern int amdgpu_dc; 181 extern int amdgpu_sched_jobs; 182 extern int amdgpu_sched_hw_submission; 183 extern uint amdgpu_pcie_gen_cap; 184 extern uint amdgpu_pcie_lane_cap; 185 extern u64 amdgpu_cg_mask; 186 extern uint amdgpu_pg_mask; 187 extern uint amdgpu_sdma_phase_quantum; 188 extern char *amdgpu_disable_cu; 189 extern char *amdgpu_virtual_display; 190 extern uint amdgpu_pp_feature_mask; 191 extern uint amdgpu_force_long_training; 192 extern int amdgpu_lbpw; 193 extern int amdgpu_compute_multipipe; 194 extern int amdgpu_gpu_recovery; 195 extern int amdgpu_emu_mode; 196 extern uint amdgpu_smu_memory_pool_size; 197 extern int amdgpu_smu_pptable_id; 198 extern uint amdgpu_dc_feature_mask; 199 extern uint amdgpu_dc_debug_mask; 200 extern uint amdgpu_dc_visual_confirm; 201 extern uint amdgpu_dm_abm_level; 202 extern int amdgpu_backlight; 203 extern struct amdgpu_mgpu_info mgpu_info; 204 extern int amdgpu_ras_enable; 205 extern uint amdgpu_ras_mask; 206 extern int amdgpu_bad_page_threshold; 207 extern bool amdgpu_ignore_bad_page_threshold; 208 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 209 extern int amdgpu_async_gfx_ring; 210 extern int amdgpu_mcbp; 211 extern int amdgpu_discovery; 212 extern int amdgpu_mes; 213 extern int amdgpu_mes_kiq; 214 extern int amdgpu_noretry; 215 extern int amdgpu_force_asic_type; 216 extern int amdgpu_smartshift_bias; 217 extern int amdgpu_use_xgmi_p2p; 218 extern int amdgpu_mtype_local; 219 extern bool enforce_isolation; 220 #ifdef CONFIG_HSA_AMD 221 extern int sched_policy; 222 extern bool debug_evictions; 223 extern bool no_system_mem_limit; 224 extern int halt_if_hws_hang; 225 #else 226 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 227 static const bool __maybe_unused debug_evictions; /* = false */ 228 static const bool __maybe_unused no_system_mem_limit; 229 static const int __maybe_unused halt_if_hws_hang; 230 #endif 231 #ifdef CONFIG_HSA_AMD_P2P 232 extern bool pcie_p2p; 233 #endif 234 235 extern int amdgpu_tmz; 236 extern int amdgpu_reset_method; 237 238 #ifdef CONFIG_DRM_AMDGPU_SI 239 extern int amdgpu_si_support; 240 #endif 241 #ifdef CONFIG_DRM_AMDGPU_CIK 242 extern int amdgpu_cik_support; 243 #endif 244 extern int amdgpu_num_kcq; 245 246 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 247 extern int amdgpu_vcnfw_log; 248 extern int amdgpu_sg_display; 249 extern int amdgpu_umsch_mm; 250 extern int amdgpu_seamless; 251 252 extern int amdgpu_user_partt_mode; 253 extern int amdgpu_agp; 254 255 #define AMDGPU_VM_MAX_NUM_CTX 4096 256 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 257 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 258 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 259 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 260 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 261 #define AMDGPUFB_CONN_LIMIT 4 262 #define AMDGPU_BIOS_NUM_SCRATCH 16 263 264 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 265 266 /* hard reset data */ 267 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 268 269 /* reset flags */ 270 #define AMDGPU_RESET_GFX (1 << 0) 271 #define AMDGPU_RESET_COMPUTE (1 << 1) 272 #define AMDGPU_RESET_DMA (1 << 2) 273 #define AMDGPU_RESET_CP (1 << 3) 274 #define AMDGPU_RESET_GRBM (1 << 4) 275 #define AMDGPU_RESET_DMA1 (1 << 5) 276 #define AMDGPU_RESET_RLC (1 << 6) 277 #define AMDGPU_RESET_SEM (1 << 7) 278 #define AMDGPU_RESET_IH (1 << 8) 279 #define AMDGPU_RESET_VMC (1 << 9) 280 #define AMDGPU_RESET_MC (1 << 10) 281 #define AMDGPU_RESET_DISPLAY (1 << 11) 282 #define AMDGPU_RESET_UVD (1 << 12) 283 #define AMDGPU_RESET_VCE (1 << 13) 284 #define AMDGPU_RESET_VCE1 (1 << 14) 285 286 /* max cursor sizes (in pixels) */ 287 #define CIK_CURSOR_WIDTH 128 288 #define CIK_CURSOR_HEIGHT 128 289 290 /* smart shift bias level limits */ 291 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 292 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 293 294 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */ 295 #define AMDGPU_SWCTF_EXTRA_DELAY 50 296 297 struct amdgpu_xcp_mgr; 298 struct amdgpu_device; 299 struct amdgpu_irq_src; 300 struct amdgpu_fpriv; 301 struct amdgpu_bo_va_mapping; 302 struct kfd_vm_fault_info; 303 struct amdgpu_hive_info; 304 struct amdgpu_reset_context; 305 struct amdgpu_reset_control; 306 307 enum amdgpu_cp_irq { 308 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 309 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 310 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 311 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 312 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 313 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 314 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 315 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 316 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 317 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 318 319 AMDGPU_CP_IRQ_LAST 320 }; 321 322 enum amdgpu_thermal_irq { 323 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 324 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 325 326 AMDGPU_THERMAL_IRQ_LAST 327 }; 328 329 enum amdgpu_kiq_irq { 330 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 331 AMDGPU_CP_KIQ_IRQ_LAST 332 }; 333 #define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */ 334 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 335 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 336 #define MAX_KIQ_REG_TRY 1000 337 338 int amdgpu_device_ip_set_clockgating_state(void *dev, 339 enum amd_ip_block_type block_type, 340 enum amd_clockgating_state state); 341 int amdgpu_device_ip_set_powergating_state(void *dev, 342 enum amd_ip_block_type block_type, 343 enum amd_powergating_state state); 344 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 345 u64 *flags); 346 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 347 enum amd_ip_block_type block_type); 348 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 349 enum amd_ip_block_type block_type); 350 351 #define AMDGPU_MAX_IP_NUM 16 352 353 struct amdgpu_ip_block_status { 354 bool valid; 355 bool sw; 356 bool hw; 357 bool late_initialized; 358 bool hang; 359 }; 360 361 struct amdgpu_ip_block_version { 362 const enum amd_ip_block_type type; 363 const u32 major; 364 const u32 minor; 365 const u32 rev; 366 const struct amd_ip_funcs *funcs; 367 }; 368 369 struct amdgpu_ip_block { 370 struct amdgpu_ip_block_status status; 371 const struct amdgpu_ip_block_version *version; 372 }; 373 374 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 375 enum amd_ip_block_type type, 376 u32 major, u32 minor); 377 378 struct amdgpu_ip_block * 379 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 380 enum amd_ip_block_type type); 381 382 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 383 const struct amdgpu_ip_block_version *ip_block_version); 384 385 /* 386 * BIOS. 387 */ 388 bool amdgpu_get_bios(struct amdgpu_device *adev); 389 bool amdgpu_read_bios(struct amdgpu_device *adev); 390 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 391 u8 *bios, u32 length_bytes); 392 /* 393 * Clocks 394 */ 395 396 #define AMDGPU_MAX_PPLL 3 397 398 struct amdgpu_clock { 399 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 400 struct amdgpu_pll spll; 401 struct amdgpu_pll mpll; 402 /* 10 Khz units */ 403 uint32_t default_mclk; 404 uint32_t default_sclk; 405 uint32_t default_dispclk; 406 uint32_t current_dispclk; 407 uint32_t dp_extclk; 408 uint32_t max_pixel_clock; 409 }; 410 411 /* sub-allocation manager, it has to be protected by another lock. 412 * By conception this is an helper for other part of the driver 413 * like the indirect buffer or semaphore, which both have their 414 * locking. 415 * 416 * Principe is simple, we keep a list of sub allocation in offset 417 * order (first entry has offset == 0, last entry has the highest 418 * offset). 419 * 420 * When allocating new object we first check if there is room at 421 * the end total_size - (last_object_offset + last_object_size) >= 422 * alloc_size. If so we allocate new object there. 423 * 424 * When there is not enough room at the end, we start waiting for 425 * each sub object until we reach object_offset+object_size >= 426 * alloc_size, this object then become the sub object we return. 427 * 428 * Alignment can't be bigger than page size. 429 * 430 * Hole are not considered for allocation to keep things simple. 431 * Assumption is that there won't be hole (all object on same 432 * alignment). 433 */ 434 435 struct amdgpu_sa_manager { 436 struct drm_suballoc_manager base; 437 struct amdgpu_bo *bo; 438 uint64_t gpu_addr; 439 void *cpu_ptr; 440 }; 441 442 int amdgpu_fence_slab_init(void); 443 void amdgpu_fence_slab_fini(void); 444 445 /* 446 * IRQS. 447 */ 448 449 struct amdgpu_flip_work { 450 struct delayed_work flip_work; 451 struct work_struct unpin_work; 452 struct amdgpu_device *adev; 453 int crtc_id; 454 u32 target_vblank; 455 uint64_t base; 456 struct drm_pending_vblank_event *event; 457 struct amdgpu_bo *old_abo; 458 unsigned shared_count; 459 struct dma_fence **shared; 460 struct dma_fence_cb cb; 461 bool async; 462 }; 463 464 465 /* 466 * file private structure 467 */ 468 469 struct amdgpu_fpriv { 470 struct amdgpu_vm vm; 471 struct amdgpu_bo_va *prt_va; 472 struct amdgpu_bo_va *csa_va; 473 struct amdgpu_bo_va *seq64_va; 474 struct mutex bo_list_lock; 475 struct idr bo_list_handles; 476 struct amdgpu_ctx_mgr ctx_mgr; 477 /** GPU partition selection */ 478 uint32_t xcp_id; 479 }; 480 481 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 482 483 /* 484 * Writeback 485 */ 486 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 487 488 struct amdgpu_wb { 489 struct amdgpu_bo *wb_obj; 490 volatile uint32_t *wb; 491 uint64_t gpu_addr; 492 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 493 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 494 }; 495 496 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 497 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 498 499 /* 500 * Benchmarking 501 */ 502 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 503 504 /* 505 * ASIC specific register table accessible by UMD 506 */ 507 struct amdgpu_allowed_register_entry { 508 uint32_t reg_offset; 509 bool grbm_indexed; 510 }; 511 512 /** 513 * enum amd_reset_method - Methods for resetting AMD GPU devices 514 * 515 * @AMD_RESET_METHOD_NONE: The device will not be reset. 516 * @AMD_RESET_LEGACY: Method reserved for SI, CIK and VI ASICs. 517 * @AMD_RESET_MODE0: Reset the entire ASIC. Not currently available for the 518 * any device. 519 * @AMD_RESET_MODE1: Resets all IP blocks on the ASIC (SDMA, GFX, VCN, etc.) 520 * individually. Suitable only for some discrete GPU, not 521 * available for all ASICs. 522 * @AMD_RESET_MODE2: Resets a lesser level of IPs compared to MODE1. Which IPs 523 * are reset depends on the ASIC. Notably doesn't reset IPs 524 * shared with the CPU on APUs or the memory controllers (so 525 * VRAM is not lost). Not available on all ASICs. 526 * @AMD_RESET_BACO: BACO (Bus Alive, Chip Off) method powers off and on the card 527 * but without powering off the PCI bus. Suitable only for 528 * discrete GPUs. 529 * @AMD_RESET_PCI: Does a full bus reset using core Linux subsystem PCI reset 530 * and does a secondary bus reset or FLR, depending on what the 531 * underlying hardware supports. 532 * 533 * Methods available for AMD GPU driver for resetting the device. Not all 534 * methods are suitable for every device. User can override the method using 535 * module parameter `reset_method`. 536 */ 537 enum amd_reset_method { 538 AMD_RESET_METHOD_NONE = -1, 539 AMD_RESET_METHOD_LEGACY = 0, 540 AMD_RESET_METHOD_MODE0, 541 AMD_RESET_METHOD_MODE1, 542 AMD_RESET_METHOD_MODE2, 543 AMD_RESET_METHOD_BACO, 544 AMD_RESET_METHOD_PCI, 545 }; 546 547 struct amdgpu_video_codec_info { 548 u32 codec_type; 549 u32 max_width; 550 u32 max_height; 551 u32 max_pixels_per_frame; 552 u32 max_level; 553 }; 554 555 #define codec_info_build(type, width, height, level) \ 556 .codec_type = type,\ 557 .max_width = width,\ 558 .max_height = height,\ 559 .max_pixels_per_frame = height * width,\ 560 .max_level = level, 561 562 struct amdgpu_video_codecs { 563 const u32 codec_count; 564 const struct amdgpu_video_codec_info *codec_array; 565 }; 566 567 /* 568 * ASIC specific functions. 569 */ 570 struct amdgpu_asic_funcs { 571 bool (*read_disabled_bios)(struct amdgpu_device *adev); 572 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 573 u8 *bios, u32 length_bytes); 574 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 575 u32 sh_num, u32 reg_offset, u32 *value); 576 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 577 int (*reset)(struct amdgpu_device *adev); 578 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 579 /* get the reference clock */ 580 u32 (*get_xclk)(struct amdgpu_device *adev); 581 /* MM block clocks */ 582 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 583 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 584 /* static power management */ 585 int (*get_pcie_lanes)(struct amdgpu_device *adev); 586 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 587 /* get config memsize register */ 588 u32 (*get_config_memsize)(struct amdgpu_device *adev); 589 /* flush hdp write queue */ 590 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 591 /* invalidate hdp read cache */ 592 void (*invalidate_hdp)(struct amdgpu_device *adev, 593 struct amdgpu_ring *ring); 594 /* check if the asic needs a full reset of if soft reset will work */ 595 bool (*need_full_reset)(struct amdgpu_device *adev); 596 /* initialize doorbell layout for specific asic*/ 597 void (*init_doorbell_index)(struct amdgpu_device *adev); 598 /* PCIe bandwidth usage */ 599 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 600 uint64_t *count1); 601 /* do we need to reset the asic at init time (e.g., kexec) */ 602 bool (*need_reset_on_init)(struct amdgpu_device *adev); 603 /* PCIe replay counter */ 604 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 605 /* device supports BACO */ 606 bool (*supports_baco)(struct amdgpu_device *adev); 607 /* pre asic_init quirks */ 608 void (*pre_asic_init)(struct amdgpu_device *adev); 609 /* enter/exit umd stable pstate */ 610 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 611 /* query video codecs */ 612 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 613 const struct amdgpu_video_codecs **codecs); 614 /* encode "> 32bits" smn addressing */ 615 u64 (*encode_ext_smn_addressing)(int ext_id); 616 617 ssize_t (*get_reg_state)(struct amdgpu_device *adev, 618 enum amdgpu_reg_state reg_state, void *buf, 619 size_t max_size); 620 }; 621 622 /* 623 * IOCTL. 624 */ 625 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 626 struct drm_file *filp); 627 628 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 629 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 630 struct drm_file *filp); 631 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 632 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 633 struct drm_file *filp); 634 635 /* VRAM scratch page for HDP bug, default vram page */ 636 struct amdgpu_mem_scratch { 637 struct amdgpu_bo *robj; 638 volatile uint32_t *ptr; 639 u64 gpu_addr; 640 }; 641 642 /* 643 * CGS 644 */ 645 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 646 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 647 648 /* 649 * Core structure, functions and helpers. 650 */ 651 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 652 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 653 654 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t); 655 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t); 656 657 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 658 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 659 660 typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device*, uint64_t); 661 typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device*, uint64_t, uint64_t); 662 663 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 664 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 665 666 struct amdgpu_mmio_remap { 667 u32 reg_offset; 668 resource_size_t bus_addr; 669 }; 670 671 /* Define the HW IP blocks will be used in driver , add more if necessary */ 672 enum amd_hw_ip_block_type { 673 GC_HWIP = 1, 674 HDP_HWIP, 675 SDMA0_HWIP, 676 SDMA1_HWIP, 677 SDMA2_HWIP, 678 SDMA3_HWIP, 679 SDMA4_HWIP, 680 SDMA5_HWIP, 681 SDMA6_HWIP, 682 SDMA7_HWIP, 683 LSDMA_HWIP, 684 MMHUB_HWIP, 685 ATHUB_HWIP, 686 NBIO_HWIP, 687 MP0_HWIP, 688 MP1_HWIP, 689 UVD_HWIP, 690 VCN_HWIP = UVD_HWIP, 691 JPEG_HWIP = VCN_HWIP, 692 VCN1_HWIP, 693 VCE_HWIP, 694 VPE_HWIP, 695 DF_HWIP, 696 DCE_HWIP, 697 OSSSYS_HWIP, 698 SMUIO_HWIP, 699 PWR_HWIP, 700 NBIF_HWIP, 701 THM_HWIP, 702 CLK_HWIP, 703 UMC_HWIP, 704 RSMU_HWIP, 705 XGMI_HWIP, 706 DCI_HWIP, 707 PCIE_HWIP, 708 MAX_HWIP 709 }; 710 711 #define HWIP_MAX_INSTANCE 44 712 713 #define HW_ID_MAX 300 714 #define IP_VERSION_FULL(mj, mn, rv, var, srev) \ 715 (((mj) << 24) | ((mn) << 16) | ((rv) << 8) | ((var) << 4) | (srev)) 716 #define IP_VERSION(mj, mn, rv) IP_VERSION_FULL(mj, mn, rv, 0, 0) 717 #define IP_VERSION_MAJ(ver) ((ver) >> 24) 718 #define IP_VERSION_MIN(ver) (((ver) >> 16) & 0xFF) 719 #define IP_VERSION_REV(ver) (((ver) >> 8) & 0xFF) 720 #define IP_VERSION_VARIANT(ver) (((ver) >> 4) & 0xF) 721 #define IP_VERSION_SUBREV(ver) ((ver) & 0xF) 722 #define IP_VERSION_MAJ_MIN_REV(ver) ((ver) >> 8) 723 724 struct amdgpu_ip_map_info { 725 /* Map of logical to actual dev instances/mask */ 726 uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE]; 727 int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev, 728 enum amd_hw_ip_block_type block, 729 int8_t inst); 730 uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev, 731 enum amd_hw_ip_block_type block, 732 uint32_t mask); 733 }; 734 735 struct amd_powerplay { 736 void *pp_handle; 737 const struct amd_pm_funcs *pp_funcs; 738 }; 739 740 struct ip_discovery_top; 741 742 /* polaris10 kickers */ 743 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 744 ((rid == 0xE3) || \ 745 (rid == 0xE4) || \ 746 (rid == 0xE5) || \ 747 (rid == 0xE7) || \ 748 (rid == 0xEF))) || \ 749 ((did == 0x6FDF) && \ 750 ((rid == 0xE7) || \ 751 (rid == 0xEF) || \ 752 (rid == 0xFF)))) 753 754 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 755 ((rid == 0xE1) || \ 756 (rid == 0xF7))) 757 758 /* polaris11 kickers */ 759 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 760 ((rid == 0xE0) || \ 761 (rid == 0xE5))) || \ 762 ((did == 0x67FF) && \ 763 ((rid == 0xCF) || \ 764 (rid == 0xEF) || \ 765 (rid == 0xFF)))) 766 767 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 768 ((rid == 0xE2))) 769 770 /* polaris12 kickers */ 771 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 772 ((rid == 0xC0) || \ 773 (rid == 0xC1) || \ 774 (rid == 0xC3) || \ 775 (rid == 0xC7))) || \ 776 ((did == 0x6981) && \ 777 ((rid == 0x00) || \ 778 (rid == 0x01) || \ 779 (rid == 0x10)))) 780 781 struct amdgpu_mqd_prop { 782 uint64_t mqd_gpu_addr; 783 uint64_t hqd_base_gpu_addr; 784 uint64_t rptr_gpu_addr; 785 uint64_t wptr_gpu_addr; 786 uint32_t queue_size; 787 bool use_doorbell; 788 uint32_t doorbell_index; 789 uint64_t eop_gpu_addr; 790 uint32_t hqd_pipe_priority; 791 uint32_t hqd_queue_priority; 792 bool hqd_active; 793 }; 794 795 struct amdgpu_mqd { 796 unsigned mqd_size; 797 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 798 struct amdgpu_mqd_prop *p); 799 }; 800 801 #define AMDGPU_RESET_MAGIC_NUM 64 802 #define AMDGPU_MAX_DF_PERFMONS 4 803 struct amdgpu_reset_domain; 804 struct amdgpu_fru_info; 805 806 struct amdgpu_reset_info { 807 /* reset dump register */ 808 u32 *reset_dump_reg_list; 809 u32 *reset_dump_reg_value; 810 int num_regs; 811 812 #ifdef CONFIG_DEV_COREDUMP 813 struct amdgpu_coredump_info *coredump_info; 814 #endif 815 }; 816 817 /* 818 * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise. 819 */ 820 #define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size) 821 822 struct amdgpu_device { 823 struct device *dev; 824 struct pci_dev *pdev; 825 struct drm_device ddev; 826 827 #ifdef CONFIG_DRM_AMD_ACP 828 struct amdgpu_acp acp; 829 #endif 830 struct amdgpu_hive_info *hive; 831 struct amdgpu_xcp_mgr *xcp_mgr; 832 /* ASIC */ 833 enum amd_asic_type asic_type; 834 uint32_t family; 835 uint32_t rev_id; 836 uint32_t external_rev_id; 837 unsigned long flags; 838 unsigned long apu_flags; 839 int usec_timeout; 840 const struct amdgpu_asic_funcs *asic_funcs; 841 bool shutdown; 842 bool need_swiotlb; 843 bool accel_working; 844 struct notifier_block acpi_nb; 845 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 846 struct debugfs_blob_wrapper debugfs_vbios_blob; 847 struct debugfs_blob_wrapper debugfs_discovery_blob; 848 struct mutex srbm_mutex; 849 /* GRBM index mutex. Protects concurrent access to GRBM index */ 850 struct mutex grbm_idx_mutex; 851 struct dev_pm_domain vga_pm_domain; 852 bool have_disp_power_ref; 853 bool have_atomics_support; 854 855 /* BIOS */ 856 bool is_atom_fw; 857 uint8_t *bios; 858 uint32_t bios_size; 859 uint32_t bios_scratch_reg_offset; 860 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 861 862 /* Register/doorbell mmio */ 863 resource_size_t rmmio_base; 864 resource_size_t rmmio_size; 865 void __iomem *rmmio; 866 /* protects concurrent MM_INDEX/DATA based register access */ 867 spinlock_t mmio_idx_lock; 868 struct amdgpu_mmio_remap rmmio_remap; 869 /* protects concurrent SMC based register access */ 870 spinlock_t smc_idx_lock; 871 amdgpu_rreg_t smc_rreg; 872 amdgpu_wreg_t smc_wreg; 873 /* protects concurrent PCIE register access */ 874 spinlock_t pcie_idx_lock; 875 amdgpu_rreg_t pcie_rreg; 876 amdgpu_wreg_t pcie_wreg; 877 amdgpu_rreg_t pciep_rreg; 878 amdgpu_wreg_t pciep_wreg; 879 amdgpu_rreg_ext_t pcie_rreg_ext; 880 amdgpu_wreg_ext_t pcie_wreg_ext; 881 amdgpu_rreg64_t pcie_rreg64; 882 amdgpu_wreg64_t pcie_wreg64; 883 amdgpu_rreg64_ext_t pcie_rreg64_ext; 884 amdgpu_wreg64_ext_t pcie_wreg64_ext; 885 /* protects concurrent UVD register access */ 886 spinlock_t uvd_ctx_idx_lock; 887 amdgpu_rreg_t uvd_ctx_rreg; 888 amdgpu_wreg_t uvd_ctx_wreg; 889 /* protects concurrent DIDT register access */ 890 spinlock_t didt_idx_lock; 891 amdgpu_rreg_t didt_rreg; 892 amdgpu_wreg_t didt_wreg; 893 /* protects concurrent gc_cac register access */ 894 spinlock_t gc_cac_idx_lock; 895 amdgpu_rreg_t gc_cac_rreg; 896 amdgpu_wreg_t gc_cac_wreg; 897 /* protects concurrent se_cac register access */ 898 spinlock_t se_cac_idx_lock; 899 amdgpu_rreg_t se_cac_rreg; 900 amdgpu_wreg_t se_cac_wreg; 901 /* protects concurrent ENDPOINT (audio) register access */ 902 spinlock_t audio_endpt_idx_lock; 903 amdgpu_block_rreg_t audio_endpt_rreg; 904 amdgpu_block_wreg_t audio_endpt_wreg; 905 struct amdgpu_doorbell doorbell; 906 907 /* clock/pll info */ 908 struct amdgpu_clock clock; 909 910 /* MC */ 911 struct amdgpu_gmc gmc; 912 struct amdgpu_gart gart; 913 dma_addr_t dummy_page_addr; 914 struct amdgpu_vm_manager vm_manager; 915 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 916 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS); 917 918 /* memory management */ 919 struct amdgpu_mman mman; 920 struct amdgpu_mem_scratch mem_scratch; 921 struct amdgpu_wb wb; 922 atomic64_t num_bytes_moved; 923 atomic64_t num_evictions; 924 atomic64_t num_vram_cpu_page_faults; 925 atomic_t gpu_reset_counter; 926 atomic_t vram_lost_counter; 927 928 /* data for buffer migration throttling */ 929 struct { 930 spinlock_t lock; 931 s64 last_update_us; 932 s64 accum_us; /* accumulated microseconds */ 933 s64 accum_us_vis; /* for visible VRAM */ 934 u32 log2_max_MBps; 935 } mm_stats; 936 937 /* display */ 938 bool enable_virtual_display; 939 struct amdgpu_vkms_output *amdgpu_vkms_output; 940 struct amdgpu_mode_info mode_info; 941 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 942 struct delayed_work hotplug_work; 943 struct amdgpu_irq_src crtc_irq; 944 struct amdgpu_irq_src vline0_irq; 945 struct amdgpu_irq_src vupdate_irq; 946 struct amdgpu_irq_src pageflip_irq; 947 struct amdgpu_irq_src hpd_irq; 948 struct amdgpu_irq_src dmub_trace_irq; 949 struct amdgpu_irq_src dmub_outbox_irq; 950 951 /* rings */ 952 u64 fence_context; 953 unsigned num_rings; 954 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 955 struct dma_fence __rcu *gang_submit; 956 bool ib_pool_ready; 957 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 958 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 959 960 /* interrupts */ 961 struct amdgpu_irq irq; 962 963 /* powerplay */ 964 struct amd_powerplay powerplay; 965 struct amdgpu_pm pm; 966 u64 cg_flags; 967 u32 pg_flags; 968 969 /* nbio */ 970 struct amdgpu_nbio nbio; 971 972 /* hdp */ 973 struct amdgpu_hdp hdp; 974 975 /* smuio */ 976 struct amdgpu_smuio smuio; 977 978 /* mmhub */ 979 struct amdgpu_mmhub mmhub; 980 981 /* gfxhub */ 982 struct amdgpu_gfxhub gfxhub; 983 984 /* gfx */ 985 struct amdgpu_gfx gfx; 986 987 /* sdma */ 988 struct amdgpu_sdma sdma; 989 990 /* lsdma */ 991 struct amdgpu_lsdma lsdma; 992 993 /* uvd */ 994 struct amdgpu_uvd uvd; 995 996 /* vce */ 997 struct amdgpu_vce vce; 998 999 /* vcn */ 1000 struct amdgpu_vcn vcn; 1001 1002 /* jpeg */ 1003 struct amdgpu_jpeg jpeg; 1004 1005 /* vpe */ 1006 struct amdgpu_vpe vpe; 1007 1008 /* umsch */ 1009 struct amdgpu_umsch_mm umsch_mm; 1010 bool enable_umsch_mm; 1011 1012 /* firmwares */ 1013 struct amdgpu_firmware firmware; 1014 1015 /* PSP */ 1016 struct psp_context psp; 1017 1018 /* GDS */ 1019 struct amdgpu_gds gds; 1020 1021 /* for userq and VM fences */ 1022 struct amdgpu_seq64 seq64; 1023 1024 /* KFD */ 1025 struct amdgpu_kfd_dev kfd; 1026 1027 /* UMC */ 1028 struct amdgpu_umc umc; 1029 1030 /* display related functionality */ 1031 struct amdgpu_display_manager dm; 1032 1033 /* mes */ 1034 bool enable_mes; 1035 bool enable_mes_kiq; 1036 struct amdgpu_mes mes; 1037 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 1038 1039 /* df */ 1040 struct amdgpu_df df; 1041 1042 /* MCA */ 1043 struct amdgpu_mca mca; 1044 1045 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1046 uint32_t harvest_ip_mask; 1047 int num_ip_blocks; 1048 struct mutex mn_lock; 1049 DECLARE_HASHTABLE(mn_hash, 7); 1050 1051 /* tracking pinned memory */ 1052 atomic64_t vram_pin_size; 1053 atomic64_t visible_pin_size; 1054 atomic64_t gart_pin_size; 1055 1056 /* soc15 register offset based on ip, instance and segment */ 1057 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1058 struct amdgpu_ip_map_info ip_map; 1059 1060 /* delayed work_func for deferring clockgating during resume */ 1061 struct delayed_work delayed_init_work; 1062 1063 struct amdgpu_virt virt; 1064 1065 /* link all shadow bo */ 1066 struct list_head shadow_list; 1067 struct mutex shadow_list_lock; 1068 1069 /* record hw reset is performed */ 1070 bool has_hw_reset; 1071 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1072 1073 /* s3/s4 mask */ 1074 bool in_suspend; 1075 bool in_s3; 1076 bool in_s4; 1077 bool in_s0ix; 1078 1079 enum pp_mp1_state mp1_state; 1080 struct amdgpu_doorbell_index doorbell_index; 1081 1082 struct mutex notifier_lock; 1083 1084 int asic_reset_res; 1085 struct work_struct xgmi_reset_work; 1086 struct list_head reset_list; 1087 1088 long gfx_timeout; 1089 long sdma_timeout; 1090 long video_timeout; 1091 long compute_timeout; 1092 1093 uint64_t unique_id; 1094 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1095 1096 /* enable runtime pm on the device */ 1097 bool in_runpm; 1098 bool has_pr3; 1099 1100 bool ucode_sysfs_en; 1101 1102 struct amdgpu_fru_info *fru_info; 1103 atomic_t throttling_logging_enabled; 1104 struct ratelimit_state throttling_logging_rs; 1105 uint32_t ras_hw_enabled; 1106 uint32_t ras_enabled; 1107 1108 bool no_hw_access; 1109 struct pci_saved_state *pci_state; 1110 pci_channel_state_t pci_channel_state; 1111 1112 /* Track auto wait count on s_barrier settings */ 1113 bool barrier_has_auto_waitcnt; 1114 1115 struct amdgpu_reset_control *reset_cntl; 1116 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1117 1118 bool ram_is_direct_mapped; 1119 1120 struct list_head ras_list; 1121 1122 struct ip_discovery_top *ip_top; 1123 1124 struct amdgpu_reset_domain *reset_domain; 1125 1126 struct mutex benchmark_mutex; 1127 1128 struct amdgpu_reset_info reset_info; 1129 1130 bool scpm_enabled; 1131 uint32_t scpm_status; 1132 1133 struct work_struct reset_work; 1134 1135 bool job_hang; 1136 bool dc_enabled; 1137 /* Mask of active clusters */ 1138 uint32_t aid_mask; 1139 1140 /* Debug */ 1141 bool debug_vm; 1142 bool debug_largebar; 1143 bool debug_disable_soft_recovery; 1144 }; 1145 1146 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, 1147 uint8_t ip, uint8_t inst) 1148 { 1149 /* This considers only major/minor/rev and ignores 1150 * subrevision/variant fields. 1151 */ 1152 return adev->ip_versions[ip][inst] & ~0xFFU; 1153 } 1154 1155 static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev, 1156 uint8_t ip, uint8_t inst) 1157 { 1158 /* This returns full version - major/minor/rev/variant/subrevision */ 1159 return adev->ip_versions[ip][inst]; 1160 } 1161 1162 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1163 { 1164 return container_of(ddev, struct amdgpu_device, ddev); 1165 } 1166 1167 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1168 { 1169 return &adev->ddev; 1170 } 1171 1172 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1173 { 1174 return container_of(bdev, struct amdgpu_device, mman.bdev); 1175 } 1176 1177 int amdgpu_device_init(struct amdgpu_device *adev, 1178 uint32_t flags); 1179 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1180 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1181 1182 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1183 1184 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1185 void *buf, size_t size, bool write); 1186 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1187 void *buf, size_t size, bool write); 1188 1189 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1190 void *buf, size_t size, bool write); 1191 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, 1192 uint32_t inst, uint32_t reg_addr, char reg_name[], 1193 uint32_t expected_value, uint32_t mask); 1194 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1195 uint32_t reg, uint32_t acc_flags); 1196 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, 1197 u64 reg_addr); 1198 uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, 1199 uint32_t reg, uint32_t acc_flags, 1200 uint32_t xcc_id); 1201 void amdgpu_device_wreg(struct amdgpu_device *adev, 1202 uint32_t reg, uint32_t v, 1203 uint32_t acc_flags); 1204 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, 1205 u64 reg_addr, u32 reg_data); 1206 void amdgpu_device_xcc_wreg(struct amdgpu_device *adev, 1207 uint32_t reg, uint32_t v, 1208 uint32_t acc_flags, 1209 uint32_t xcc_id); 1210 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1211 uint32_t reg, uint32_t v, uint32_t xcc_id); 1212 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1213 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1214 1215 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1216 u32 reg_addr); 1217 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1218 u32 reg_addr); 1219 u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, 1220 u64 reg_addr); 1221 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1222 u32 reg_addr, u32 reg_data); 1223 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1224 u32 reg_addr, u64 reg_data); 1225 void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, 1226 u64 reg_addr, u64 reg_data); 1227 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev); 1228 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1229 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1230 1231 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev); 1232 1233 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1234 struct amdgpu_reset_context *reset_context); 1235 1236 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1237 struct amdgpu_reset_context *reset_context); 1238 1239 int emu_soc_asic_init(struct amdgpu_device *adev); 1240 1241 /* 1242 * Registers read & write functions. 1243 */ 1244 #define AMDGPU_REGS_NO_KIQ (1<<1) 1245 #define AMDGPU_REGS_RLC (1<<2) 1246 1247 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1248 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1249 1250 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0) 1251 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0) 1252 1253 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1254 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1255 1256 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1257 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1258 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1259 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1260 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1261 #define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst) 1262 #define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst) 1263 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1264 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1265 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1266 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1267 #define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg)) 1268 #define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v)) 1269 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1270 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1271 #define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg)) 1272 #define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v)) 1273 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1274 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1275 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1276 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1277 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1278 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1279 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1280 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1281 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1282 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1283 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1284 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1285 #define WREG32_P(reg, val, mask) \ 1286 do { \ 1287 uint32_t tmp_ = RREG32(reg); \ 1288 tmp_ &= (mask); \ 1289 tmp_ |= ((val) & ~(mask)); \ 1290 WREG32(reg, tmp_); \ 1291 } while (0) 1292 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1293 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1294 #define WREG32_PLL_P(reg, val, mask) \ 1295 do { \ 1296 uint32_t tmp_ = RREG32_PLL(reg); \ 1297 tmp_ &= (mask); \ 1298 tmp_ |= ((val) & ~(mask)); \ 1299 WREG32_PLL(reg, tmp_); \ 1300 } while (0) 1301 1302 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1303 do { \ 1304 u32 tmp = RREG32_SMC(_Reg); \ 1305 tmp &= (_Mask); \ 1306 tmp |= ((_Val) & ~(_Mask)); \ 1307 WREG32_SMC(_Reg, tmp); \ 1308 } while (0) 1309 1310 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1311 1312 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1313 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1314 1315 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1316 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1317 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1318 1319 #define REG_GET_FIELD(value, reg, field) \ 1320 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1321 1322 #define WREG32_FIELD(reg, field, val) \ 1323 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1324 1325 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1326 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1327 1328 /* 1329 * BIOS helpers. 1330 */ 1331 #define RBIOS8(i) (adev->bios[i]) 1332 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1333 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1334 1335 /* 1336 * ASICs macro. 1337 */ 1338 #define amdgpu_asic_set_vga_state(adev, state) \ 1339 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0) 1340 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1341 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1342 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1343 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1344 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1345 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1346 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1347 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1348 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1349 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1350 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1351 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1352 #define amdgpu_asic_flush_hdp(adev, r) \ 1353 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1354 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1355 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \ 1356 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0)) 1357 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1358 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1359 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1360 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1361 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1362 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1363 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1364 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1365 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1366 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1367 1368 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)) 1369 1370 #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i)) 1371 #define for_each_inst(i, inst_mask) \ 1372 for (i = ffs(inst_mask); i-- != 0; \ 1373 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1))) 1374 1375 /* Common functions */ 1376 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1377 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1378 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1379 struct amdgpu_job *job, 1380 struct amdgpu_reset_context *reset_context); 1381 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1382 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1383 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1384 bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev); 1385 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1386 1387 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1388 u64 num_vis_bytes); 1389 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1390 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1391 const u32 *registers, 1392 const u32 array_size); 1393 1394 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1395 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1396 bool amdgpu_device_supports_px(struct drm_device *dev); 1397 bool amdgpu_device_supports_boco(struct drm_device *dev); 1398 bool amdgpu_device_supports_smart_shift(struct drm_device *dev); 1399 bool amdgpu_device_supports_baco(struct drm_device *dev); 1400 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1401 struct amdgpu_device *peer_adev); 1402 int amdgpu_device_baco_enter(struct drm_device *dev); 1403 int amdgpu_device_baco_exit(struct drm_device *dev); 1404 1405 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1406 struct amdgpu_ring *ring); 1407 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1408 struct amdgpu_ring *ring); 1409 1410 void amdgpu_device_halt(struct amdgpu_device *adev); 1411 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, 1412 u32 reg); 1413 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, 1414 u32 reg, u32 v); 1415 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1416 struct dma_fence *gang); 1417 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1418 1419 /* atpx handler */ 1420 #if defined(CONFIG_VGA_SWITCHEROO) 1421 void amdgpu_register_atpx_handler(void); 1422 void amdgpu_unregister_atpx_handler(void); 1423 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1424 bool amdgpu_is_atpx_hybrid(void); 1425 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1426 bool amdgpu_has_atpx(void); 1427 #else 1428 static inline void amdgpu_register_atpx_handler(void) {} 1429 static inline void amdgpu_unregister_atpx_handler(void) {} 1430 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1431 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1432 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1433 static inline bool amdgpu_has_atpx(void) { return false; } 1434 #endif 1435 1436 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1437 void *amdgpu_atpx_get_dhandle(void); 1438 #else 1439 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1440 #endif 1441 1442 /* 1443 * KMS 1444 */ 1445 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1446 extern const int amdgpu_max_kms_ioctl; 1447 1448 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1449 void amdgpu_driver_unload_kms(struct drm_device *dev); 1450 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1451 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1452 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1453 struct drm_file *file_priv); 1454 void amdgpu_driver_release_kms(struct drm_device *dev); 1455 1456 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1457 int amdgpu_device_prepare(struct drm_device *dev); 1458 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1459 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1460 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1461 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1462 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1463 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1464 struct drm_file *filp); 1465 1466 /* 1467 * functions used by amdgpu_encoder.c 1468 */ 1469 struct amdgpu_afmt_acr { 1470 u32 clock; 1471 1472 int n_32khz; 1473 int cts_32khz; 1474 1475 int n_44_1khz; 1476 int cts_44_1khz; 1477 1478 int n_48khz; 1479 int cts_48khz; 1480 1481 }; 1482 1483 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1484 1485 /* amdgpu_acpi.c */ 1486 1487 struct amdgpu_numa_info { 1488 uint64_t size; 1489 int pxm; 1490 int nid; 1491 }; 1492 1493 /* ATCS Device/Driver State */ 1494 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1495 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1496 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1497 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1498 1499 #if defined(CONFIG_ACPI) 1500 int amdgpu_acpi_init(struct amdgpu_device *adev); 1501 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1502 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1503 bool amdgpu_acpi_is_power_shift_control_supported(void); 1504 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1505 u8 perf_req, bool advertise); 1506 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1507 u8 dev_state, bool drv_state); 1508 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state); 1509 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1510 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, 1511 u64 *tmr_size); 1512 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, 1513 struct amdgpu_numa_info *numa_info); 1514 1515 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1516 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1517 void amdgpu_acpi_detect(void); 1518 void amdgpu_acpi_release(void); 1519 #else 1520 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1521 static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, 1522 u64 *tmr_offset, u64 *tmr_size) 1523 { 1524 return -EINVAL; 1525 } 1526 static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, 1527 int xcc_id, 1528 struct amdgpu_numa_info *numa_info) 1529 { 1530 return -EINVAL; 1531 } 1532 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1533 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1534 static inline void amdgpu_acpi_detect(void) { } 1535 static inline void amdgpu_acpi_release(void) { } 1536 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1537 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1538 u8 dev_state, bool drv_state) { return 0; } 1539 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, 1540 enum amdgpu_ss ss_state) { return 0; } 1541 #endif 1542 1543 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1544 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1545 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1546 #else 1547 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1548 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1549 #endif 1550 1551 #if defined(CONFIG_DRM_AMD_DC) 1552 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1553 #else 1554 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1555 #endif 1556 1557 1558 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1559 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1560 1561 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1562 pci_channel_state_t state); 1563 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1564 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1565 void amdgpu_pci_resume(struct pci_dev *pdev); 1566 1567 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1568 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1569 1570 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1571 1572 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1573 enum amd_clockgating_state state); 1574 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1575 enum amd_powergating_state state); 1576 1577 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1578 { 1579 return amdgpu_gpu_recovery != 0 && 1580 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1581 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1582 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1583 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1584 } 1585 1586 #include "amdgpu_object.h" 1587 1588 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1589 { 1590 return adev->gmc.tmz_enabled; 1591 } 1592 1593 int amdgpu_in_reset(struct amdgpu_device *adev); 1594 1595 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 1596 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 1597 extern const struct attribute_group amdgpu_flash_attr_group; 1598 1599 #endif 1600