1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include <linux/atomic.h> 32 #include <linux/wait.h> 33 #include <linux/list.h> 34 #include <linux/kref.h> 35 #include <linux/interval_tree.h> 36 #include <linux/hashtable.h> 37 #include <linux/fence.h> 38 39 #include <ttm/ttm_bo_api.h> 40 #include <ttm/ttm_bo_driver.h> 41 #include <ttm/ttm_placement.h> 42 #include <ttm/ttm_module.h> 43 #include <ttm/ttm_execbuf_util.h> 44 45 #include <drm/drmP.h> 46 #include <drm/drm_gem.h> 47 #include <drm/amdgpu_drm.h> 48 49 #include "amd_shared.h" 50 #include "amdgpu_mode.h" 51 #include "amdgpu_ih.h" 52 #include "amdgpu_irq.h" 53 #include "amdgpu_ucode.h" 54 #include "amdgpu_gds.h" 55 #include "amd_powerplay.h" 56 #include "amdgpu_acp.h" 57 58 #include "gpu_scheduler.h" 59 60 /* 61 * Modules parameters. 62 */ 63 extern int amdgpu_modeset; 64 extern int amdgpu_vram_limit; 65 extern int amdgpu_gart_size; 66 extern int amdgpu_benchmarking; 67 extern int amdgpu_testing; 68 extern int amdgpu_audio; 69 extern int amdgpu_disp_priority; 70 extern int amdgpu_hw_i2c; 71 extern int amdgpu_pcie_gen2; 72 extern int amdgpu_msi; 73 extern int amdgpu_lockup_timeout; 74 extern int amdgpu_dpm; 75 extern int amdgpu_smc_load_fw; 76 extern int amdgpu_aspm; 77 extern int amdgpu_runtime_pm; 78 extern unsigned amdgpu_ip_block_mask; 79 extern int amdgpu_bapm; 80 extern int amdgpu_deep_color; 81 extern int amdgpu_vm_size; 82 extern int amdgpu_vm_block_size; 83 extern int amdgpu_vm_fault_stop; 84 extern int amdgpu_vm_debug; 85 extern int amdgpu_sched_jobs; 86 extern int amdgpu_sched_hw_submission; 87 extern int amdgpu_powerplay; 88 89 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 90 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 91 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 92 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 93 #define AMDGPU_IB_POOL_SIZE 16 94 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 95 #define AMDGPUFB_CONN_LIMIT 4 96 #define AMDGPU_BIOS_NUM_SCRATCH 8 97 98 /* max number of rings */ 99 #define AMDGPU_MAX_RINGS 16 100 #define AMDGPU_MAX_GFX_RINGS 1 101 #define AMDGPU_MAX_COMPUTE_RINGS 8 102 #define AMDGPU_MAX_VCE_RINGS 2 103 104 /* max number of IP instances */ 105 #define AMDGPU_MAX_SDMA_INSTANCES 2 106 107 /* number of hw syncs before falling back on blocking */ 108 #define AMDGPU_NUM_SYNCS 4 109 110 /* hardcode that limit for now */ 111 #define AMDGPU_VA_RESERVED_SIZE (8 << 20) 112 113 /* hard reset data */ 114 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 115 116 /* reset flags */ 117 #define AMDGPU_RESET_GFX (1 << 0) 118 #define AMDGPU_RESET_COMPUTE (1 << 1) 119 #define AMDGPU_RESET_DMA (1 << 2) 120 #define AMDGPU_RESET_CP (1 << 3) 121 #define AMDGPU_RESET_GRBM (1 << 4) 122 #define AMDGPU_RESET_DMA1 (1 << 5) 123 #define AMDGPU_RESET_RLC (1 << 6) 124 #define AMDGPU_RESET_SEM (1 << 7) 125 #define AMDGPU_RESET_IH (1 << 8) 126 #define AMDGPU_RESET_VMC (1 << 9) 127 #define AMDGPU_RESET_MC (1 << 10) 128 #define AMDGPU_RESET_DISPLAY (1 << 11) 129 #define AMDGPU_RESET_UVD (1 << 12) 130 #define AMDGPU_RESET_VCE (1 << 13) 131 #define AMDGPU_RESET_VCE1 (1 << 14) 132 133 /* CG block flags */ 134 #define AMDGPU_CG_BLOCK_GFX (1 << 0) 135 #define AMDGPU_CG_BLOCK_MC (1 << 1) 136 #define AMDGPU_CG_BLOCK_SDMA (1 << 2) 137 #define AMDGPU_CG_BLOCK_UVD (1 << 3) 138 #define AMDGPU_CG_BLOCK_VCE (1 << 4) 139 #define AMDGPU_CG_BLOCK_HDP (1 << 5) 140 #define AMDGPU_CG_BLOCK_BIF (1 << 6) 141 142 /* CG flags */ 143 #define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0) 144 #define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1) 145 #define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2) 146 #define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3) 147 #define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4) 148 #define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 149 #define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6) 150 #define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7) 151 #define AMDGPU_CG_SUPPORT_MC_LS (1 << 8) 152 #define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9) 153 #define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10) 154 #define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11) 155 #define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12) 156 #define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13) 157 #define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14) 158 #define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15) 159 #define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16) 160 161 /* PG flags */ 162 #define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0) 163 #define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1) 164 #define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2) 165 #define AMDGPU_PG_SUPPORT_UVD (1 << 3) 166 #define AMDGPU_PG_SUPPORT_VCE (1 << 4) 167 #define AMDGPU_PG_SUPPORT_CP (1 << 5) 168 #define AMDGPU_PG_SUPPORT_GDS (1 << 6) 169 #define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7) 170 #define AMDGPU_PG_SUPPORT_SDMA (1 << 8) 171 #define AMDGPU_PG_SUPPORT_ACP (1 << 9) 172 #define AMDGPU_PG_SUPPORT_SAMU (1 << 10) 173 174 /* GFX current status */ 175 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 176 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 177 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 178 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 179 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 180 181 /* max cursor sizes (in pixels) */ 182 #define CIK_CURSOR_WIDTH 128 183 #define CIK_CURSOR_HEIGHT 128 184 185 struct amdgpu_device; 186 struct amdgpu_fence; 187 struct amdgpu_ib; 188 struct amdgpu_vm; 189 struct amdgpu_ring; 190 struct amdgpu_cs_parser; 191 struct amdgpu_job; 192 struct amdgpu_irq_src; 193 struct amdgpu_fpriv; 194 195 enum amdgpu_cp_irq { 196 AMDGPU_CP_IRQ_GFX_EOP = 0, 197 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 198 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 199 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 200 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 201 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 202 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 203 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 204 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 205 206 AMDGPU_CP_IRQ_LAST 207 }; 208 209 enum amdgpu_sdma_irq { 210 AMDGPU_SDMA_IRQ_TRAP0 = 0, 211 AMDGPU_SDMA_IRQ_TRAP1, 212 213 AMDGPU_SDMA_IRQ_LAST 214 }; 215 216 enum amdgpu_thermal_irq { 217 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 218 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 219 220 AMDGPU_THERMAL_IRQ_LAST 221 }; 222 223 int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 224 enum amd_ip_block_type block_type, 225 enum amd_clockgating_state state); 226 int amdgpu_set_powergating_state(struct amdgpu_device *adev, 227 enum amd_ip_block_type block_type, 228 enum amd_powergating_state state); 229 230 struct amdgpu_ip_block_version { 231 enum amd_ip_block_type type; 232 u32 major; 233 u32 minor; 234 u32 rev; 235 const struct amd_ip_funcs *funcs; 236 }; 237 238 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 239 enum amd_ip_block_type type, 240 u32 major, u32 minor); 241 242 const struct amdgpu_ip_block_version * amdgpu_get_ip_block( 243 struct amdgpu_device *adev, 244 enum amd_ip_block_type type); 245 246 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 247 struct amdgpu_buffer_funcs { 248 /* maximum bytes in a single operation */ 249 uint32_t copy_max_bytes; 250 251 /* number of dw to reserve per operation */ 252 unsigned copy_num_dw; 253 254 /* used for buffer migration */ 255 void (*emit_copy_buffer)(struct amdgpu_ib *ib, 256 /* src addr in bytes */ 257 uint64_t src_offset, 258 /* dst addr in bytes */ 259 uint64_t dst_offset, 260 /* number of byte to transfer */ 261 uint32_t byte_count); 262 263 /* maximum bytes in a single operation */ 264 uint32_t fill_max_bytes; 265 266 /* number of dw to reserve per operation */ 267 unsigned fill_num_dw; 268 269 /* used for buffer clearing */ 270 void (*emit_fill_buffer)(struct amdgpu_ib *ib, 271 /* value to write to memory */ 272 uint32_t src_data, 273 /* dst addr in bytes */ 274 uint64_t dst_offset, 275 /* number of byte to fill */ 276 uint32_t byte_count); 277 }; 278 279 /* provided by hw blocks that can write ptes, e.g., sdma */ 280 struct amdgpu_vm_pte_funcs { 281 /* copy pte entries from GART */ 282 void (*copy_pte)(struct amdgpu_ib *ib, 283 uint64_t pe, uint64_t src, 284 unsigned count); 285 /* write pte one entry at a time with addr mapping */ 286 void (*write_pte)(struct amdgpu_ib *ib, 287 const dma_addr_t *pages_addr, uint64_t pe, 288 uint64_t addr, unsigned count, 289 uint32_t incr, uint32_t flags); 290 /* for linear pte/pde updates without addr mapping */ 291 void (*set_pte_pde)(struct amdgpu_ib *ib, 292 uint64_t pe, 293 uint64_t addr, unsigned count, 294 uint32_t incr, uint32_t flags); 295 /* pad the indirect buffer to the necessary number of dw */ 296 void (*pad_ib)(struct amdgpu_ib *ib); 297 }; 298 299 /* provided by the gmc block */ 300 struct amdgpu_gart_funcs { 301 /* flush the vm tlb via mmio */ 302 void (*flush_gpu_tlb)(struct amdgpu_device *adev, 303 uint32_t vmid); 304 /* write pte/pde updates using the cpu */ 305 int (*set_pte_pde)(struct amdgpu_device *adev, 306 void *cpu_pt_addr, /* cpu addr of page table */ 307 uint32_t gpu_page_idx, /* pte/pde to update */ 308 uint64_t addr, /* addr to write into pte/pde */ 309 uint32_t flags); /* access flags */ 310 }; 311 312 /* provided by the ih block */ 313 struct amdgpu_ih_funcs { 314 /* ring read/write ptr handling, called from interrupt context */ 315 u32 (*get_wptr)(struct amdgpu_device *adev); 316 void (*decode_iv)(struct amdgpu_device *adev, 317 struct amdgpu_iv_entry *entry); 318 void (*set_rptr)(struct amdgpu_device *adev); 319 }; 320 321 /* provided by hw blocks that expose a ring buffer for commands */ 322 struct amdgpu_ring_funcs { 323 /* ring read/write ptr handling */ 324 u32 (*get_rptr)(struct amdgpu_ring *ring); 325 u32 (*get_wptr)(struct amdgpu_ring *ring); 326 void (*set_wptr)(struct amdgpu_ring *ring); 327 /* validating and patching of IBs */ 328 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); 329 /* command emit functions */ 330 void (*emit_ib)(struct amdgpu_ring *ring, 331 struct amdgpu_ib *ib); 332 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 333 uint64_t seq, unsigned flags); 334 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id, 335 uint64_t pd_addr); 336 void (*emit_hdp_flush)(struct amdgpu_ring *ring); 337 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, 338 uint32_t gds_base, uint32_t gds_size, 339 uint32_t gws_base, uint32_t gws_size, 340 uint32_t oa_base, uint32_t oa_size); 341 /* testing functions */ 342 int (*test_ring)(struct amdgpu_ring *ring); 343 int (*test_ib)(struct amdgpu_ring *ring); 344 /* insert NOP packets */ 345 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); 346 }; 347 348 /* 349 * BIOS. 350 */ 351 bool amdgpu_get_bios(struct amdgpu_device *adev); 352 bool amdgpu_read_bios(struct amdgpu_device *adev); 353 354 /* 355 * Dummy page 356 */ 357 struct amdgpu_dummy_page { 358 struct page *page; 359 dma_addr_t addr; 360 }; 361 int amdgpu_dummy_page_init(struct amdgpu_device *adev); 362 void amdgpu_dummy_page_fini(struct amdgpu_device *adev); 363 364 365 /* 366 * Clocks 367 */ 368 369 #define AMDGPU_MAX_PPLL 3 370 371 struct amdgpu_clock { 372 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 373 struct amdgpu_pll spll; 374 struct amdgpu_pll mpll; 375 /* 10 Khz units */ 376 uint32_t default_mclk; 377 uint32_t default_sclk; 378 uint32_t default_dispclk; 379 uint32_t current_dispclk; 380 uint32_t dp_extclk; 381 uint32_t max_pixel_clock; 382 }; 383 384 /* 385 * Fences. 386 */ 387 struct amdgpu_fence_driver { 388 uint64_t gpu_addr; 389 volatile uint32_t *cpu_addr; 390 /* sync_seq is protected by ring emission lock */ 391 uint64_t sync_seq; 392 atomic64_t last_seq; 393 bool initialized; 394 struct amdgpu_irq_src *irq_src; 395 unsigned irq_type; 396 struct timer_list fallback_timer; 397 wait_queue_head_t fence_queue; 398 }; 399 400 /* some special values for the owner field */ 401 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul) 402 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul) 403 404 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) 405 #define AMDGPU_FENCE_FLAG_INT (1 << 1) 406 407 struct amdgpu_fence { 408 struct fence base; 409 410 /* RB, DMA, etc. */ 411 struct amdgpu_ring *ring; 412 uint64_t seq; 413 414 /* filp or special value for fence creator */ 415 void *owner; 416 417 wait_queue_t fence_wake; 418 }; 419 420 struct amdgpu_user_fence { 421 /* write-back bo */ 422 struct amdgpu_bo *bo; 423 /* write-back address offset to bo start */ 424 uint32_t offset; 425 }; 426 427 int amdgpu_fence_driver_init(struct amdgpu_device *adev); 428 void amdgpu_fence_driver_fini(struct amdgpu_device *adev); 429 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev); 430 431 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring); 432 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 433 struct amdgpu_irq_src *irq_src, 434 unsigned irq_type); 435 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev); 436 void amdgpu_fence_driver_resume(struct amdgpu_device *adev); 437 int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner, 438 struct amdgpu_fence **fence); 439 void amdgpu_fence_process(struct amdgpu_ring *ring); 440 int amdgpu_fence_wait_next(struct amdgpu_ring *ring); 441 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 442 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 443 444 /* 445 * TTM. 446 */ 447 struct amdgpu_mman { 448 struct ttm_bo_global_ref bo_global_ref; 449 struct drm_global_reference mem_global_ref; 450 struct ttm_bo_device bdev; 451 bool mem_global_referenced; 452 bool initialized; 453 454 #if defined(CONFIG_DEBUG_FS) 455 struct dentry *vram; 456 struct dentry *gtt; 457 #endif 458 459 /* buffer handling */ 460 const struct amdgpu_buffer_funcs *buffer_funcs; 461 struct amdgpu_ring *buffer_funcs_ring; 462 }; 463 464 int amdgpu_copy_buffer(struct amdgpu_ring *ring, 465 uint64_t src_offset, 466 uint64_t dst_offset, 467 uint32_t byte_count, 468 struct reservation_object *resv, 469 struct fence **fence); 470 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); 471 472 struct amdgpu_bo_list_entry { 473 struct amdgpu_bo *robj; 474 struct ttm_validate_buffer tv; 475 struct amdgpu_bo_va *bo_va; 476 uint32_t priority; 477 }; 478 479 struct amdgpu_bo_va_mapping { 480 struct list_head list; 481 struct interval_tree_node it; 482 uint64_t offset; 483 uint32_t flags; 484 }; 485 486 /* bo virtual addresses in a specific vm */ 487 struct amdgpu_bo_va { 488 struct mutex mutex; 489 /* protected by bo being reserved */ 490 struct list_head bo_list; 491 struct fence *last_pt_update; 492 unsigned ref_count; 493 494 /* protected by vm mutex and spinlock */ 495 struct list_head vm_status; 496 497 /* mappings for this bo_va */ 498 struct list_head invalids; 499 struct list_head valids; 500 501 /* constant after initialization */ 502 struct amdgpu_vm *vm; 503 struct amdgpu_bo *bo; 504 }; 505 506 #define AMDGPU_GEM_DOMAIN_MAX 0x3 507 508 struct amdgpu_bo { 509 /* Protected by gem.mutex */ 510 struct list_head list; 511 /* Protected by tbo.reserved */ 512 u32 prefered_domains; 513 u32 allowed_domains; 514 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 515 struct ttm_placement placement; 516 struct ttm_buffer_object tbo; 517 struct ttm_bo_kmap_obj kmap; 518 u64 flags; 519 unsigned pin_count; 520 void *kptr; 521 u64 tiling_flags; 522 u64 metadata_flags; 523 void *metadata; 524 u32 metadata_size; 525 /* list of all virtual address to which this bo 526 * is associated to 527 */ 528 struct list_head va; 529 /* Constant after initialization */ 530 struct amdgpu_device *adev; 531 struct drm_gem_object gem_base; 532 struct amdgpu_bo *parent; 533 534 struct ttm_bo_kmap_obj dma_buf_vmap; 535 pid_t pid; 536 struct amdgpu_mn *mn; 537 struct list_head mn_list; 538 }; 539 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) 540 541 void amdgpu_gem_object_free(struct drm_gem_object *obj); 542 int amdgpu_gem_object_open(struct drm_gem_object *obj, 543 struct drm_file *file_priv); 544 void amdgpu_gem_object_close(struct drm_gem_object *obj, 545 struct drm_file *file_priv); 546 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 547 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); 548 struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev, 549 struct dma_buf_attachment *attach, 550 struct sg_table *sg); 551 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, 552 struct drm_gem_object *gobj, 553 int flags); 554 int amdgpu_gem_prime_pin(struct drm_gem_object *obj); 555 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); 556 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); 557 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); 558 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 559 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); 560 561 /* sub-allocation manager, it has to be protected by another lock. 562 * By conception this is an helper for other part of the driver 563 * like the indirect buffer or semaphore, which both have their 564 * locking. 565 * 566 * Principe is simple, we keep a list of sub allocation in offset 567 * order (first entry has offset == 0, last entry has the highest 568 * offset). 569 * 570 * When allocating new object we first check if there is room at 571 * the end total_size - (last_object_offset + last_object_size) >= 572 * alloc_size. If so we allocate new object there. 573 * 574 * When there is not enough room at the end, we start waiting for 575 * each sub object until we reach object_offset+object_size >= 576 * alloc_size, this object then become the sub object we return. 577 * 578 * Alignment can't be bigger than page size. 579 * 580 * Hole are not considered for allocation to keep things simple. 581 * Assumption is that there won't be hole (all object on same 582 * alignment). 583 */ 584 struct amdgpu_sa_manager { 585 wait_queue_head_t wq; 586 struct amdgpu_bo *bo; 587 struct list_head *hole; 588 struct list_head flist[AMDGPU_MAX_RINGS]; 589 struct list_head olist; 590 unsigned size; 591 uint64_t gpu_addr; 592 void *cpu_ptr; 593 uint32_t domain; 594 uint32_t align; 595 }; 596 597 struct amdgpu_sa_bo; 598 599 /* sub-allocation buffer */ 600 struct amdgpu_sa_bo { 601 struct list_head olist; 602 struct list_head flist; 603 struct amdgpu_sa_manager *manager; 604 unsigned soffset; 605 unsigned eoffset; 606 struct fence *fence; 607 }; 608 609 /* 610 * GEM objects. 611 */ 612 struct amdgpu_gem { 613 struct mutex mutex; 614 struct list_head objects; 615 }; 616 617 int amdgpu_gem_init(struct amdgpu_device *adev); 618 void amdgpu_gem_fini(struct amdgpu_device *adev); 619 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 620 int alignment, u32 initial_domain, 621 u64 flags, bool kernel, 622 struct drm_gem_object **obj); 623 624 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 625 struct drm_device *dev, 626 struct drm_mode_create_dumb *args); 627 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 628 struct drm_device *dev, 629 uint32_t handle, uint64_t *offset_p); 630 /* 631 * Synchronization 632 */ 633 struct amdgpu_sync { 634 DECLARE_HASHTABLE(fences, 4); 635 struct fence *last_vm_update; 636 }; 637 638 void amdgpu_sync_create(struct amdgpu_sync *sync); 639 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, 640 struct fence *f); 641 int amdgpu_sync_resv(struct amdgpu_device *adev, 642 struct amdgpu_sync *sync, 643 struct reservation_object *resv, 644 void *owner); 645 struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync); 646 int amdgpu_sync_wait(struct amdgpu_sync *sync); 647 void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync, 648 struct fence *fence); 649 650 /* 651 * GART structures, functions & helpers 652 */ 653 struct amdgpu_mc; 654 655 #define AMDGPU_GPU_PAGE_SIZE 4096 656 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) 657 #define AMDGPU_GPU_PAGE_SHIFT 12 658 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) 659 660 struct amdgpu_gart { 661 dma_addr_t table_addr; 662 struct amdgpu_bo *robj; 663 void *ptr; 664 unsigned num_gpu_pages; 665 unsigned num_cpu_pages; 666 unsigned table_size; 667 struct page **pages; 668 dma_addr_t *pages_addr; 669 bool ready; 670 const struct amdgpu_gart_funcs *gart_funcs; 671 }; 672 673 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); 674 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); 675 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); 676 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); 677 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); 678 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); 679 int amdgpu_gart_init(struct amdgpu_device *adev); 680 void amdgpu_gart_fini(struct amdgpu_device *adev); 681 void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset, 682 int pages); 683 int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset, 684 int pages, struct page **pagelist, 685 dma_addr_t *dma_addr, uint32_t flags); 686 687 /* 688 * GPU MC structures, functions & helpers 689 */ 690 struct amdgpu_mc { 691 resource_size_t aper_size; 692 resource_size_t aper_base; 693 resource_size_t agp_base; 694 /* for some chips with <= 32MB we need to lie 695 * about vram size near mc fb location */ 696 u64 mc_vram_size; 697 u64 visible_vram_size; 698 u64 gtt_size; 699 u64 gtt_start; 700 u64 gtt_end; 701 u64 vram_start; 702 u64 vram_end; 703 unsigned vram_width; 704 u64 real_vram_size; 705 int vram_mtrr; 706 u64 gtt_base_align; 707 u64 mc_mask; 708 const struct firmware *fw; /* MC firmware */ 709 uint32_t fw_version; 710 struct amdgpu_irq_src vm_fault; 711 uint32_t vram_type; 712 }; 713 714 /* 715 * GPU doorbell structures, functions & helpers 716 */ 717 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 718 { 719 AMDGPU_DOORBELL_KIQ = 0x000, 720 AMDGPU_DOORBELL_HIQ = 0x001, 721 AMDGPU_DOORBELL_DIQ = 0x002, 722 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 723 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 724 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 725 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 726 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 727 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 728 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 729 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 730 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 731 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 732 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 733 AMDGPU_DOORBELL_IH = 0x1E8, 734 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 735 AMDGPU_DOORBELL_INVALID = 0xFFFF 736 } AMDGPU_DOORBELL_ASSIGNMENT; 737 738 struct amdgpu_doorbell { 739 /* doorbell mmio */ 740 resource_size_t base; 741 resource_size_t size; 742 u32 __iomem *ptr; 743 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 744 }; 745 746 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 747 phys_addr_t *aperture_base, 748 size_t *aperture_size, 749 size_t *start_offset); 750 751 /* 752 * IRQS. 753 */ 754 755 struct amdgpu_flip_work { 756 struct work_struct flip_work; 757 struct work_struct unpin_work; 758 struct amdgpu_device *adev; 759 int crtc_id; 760 uint64_t base; 761 struct drm_pending_vblank_event *event; 762 struct amdgpu_bo *old_rbo; 763 struct fence *excl; 764 unsigned shared_count; 765 struct fence **shared; 766 }; 767 768 769 /* 770 * CP & rings. 771 */ 772 773 struct amdgpu_ib { 774 struct amdgpu_sa_bo *sa_bo; 775 uint32_t length_dw; 776 uint64_t gpu_addr; 777 uint32_t *ptr; 778 struct amdgpu_ring *ring; 779 struct amdgpu_fence *fence; 780 struct amdgpu_user_fence *user; 781 bool grabbed_vmid; 782 struct amdgpu_vm *vm; 783 struct amdgpu_ctx *ctx; 784 struct amdgpu_sync sync; 785 uint32_t gds_base, gds_size; 786 uint32_t gws_base, gws_size; 787 uint32_t oa_base, oa_size; 788 uint32_t flags; 789 /* resulting sequence number */ 790 uint64_t sequence; 791 }; 792 793 enum amdgpu_ring_type { 794 AMDGPU_RING_TYPE_GFX, 795 AMDGPU_RING_TYPE_COMPUTE, 796 AMDGPU_RING_TYPE_SDMA, 797 AMDGPU_RING_TYPE_UVD, 798 AMDGPU_RING_TYPE_VCE 799 }; 800 801 extern struct amd_sched_backend_ops amdgpu_sched_ops; 802 803 int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev, 804 struct amdgpu_ring *ring, 805 struct amdgpu_ib *ibs, 806 unsigned num_ibs, 807 int (*free_job)(struct amdgpu_job *), 808 void *owner, 809 struct fence **fence); 810 811 struct amdgpu_ring { 812 struct amdgpu_device *adev; 813 const struct amdgpu_ring_funcs *funcs; 814 struct amdgpu_fence_driver fence_drv; 815 struct amd_gpu_scheduler sched; 816 817 spinlock_t fence_lock; 818 struct amdgpu_bo *ring_obj; 819 volatile uint32_t *ring; 820 unsigned rptr_offs; 821 u64 next_rptr_gpu_addr; 822 volatile u32 *next_rptr_cpu_addr; 823 unsigned wptr; 824 unsigned wptr_old; 825 unsigned ring_size; 826 unsigned max_dw; 827 int count_dw; 828 uint64_t gpu_addr; 829 uint32_t align_mask; 830 uint32_t ptr_mask; 831 bool ready; 832 u32 nop; 833 u32 idx; 834 u32 me; 835 u32 pipe; 836 u32 queue; 837 struct amdgpu_bo *mqd_obj; 838 u32 doorbell_index; 839 bool use_doorbell; 840 unsigned wptr_offs; 841 unsigned next_rptr_offs; 842 unsigned fence_offs; 843 struct amdgpu_ctx *current_ctx; 844 enum amdgpu_ring_type type; 845 char name[16]; 846 bool is_pte_ring; 847 }; 848 849 /* 850 * VM 851 */ 852 853 /* maximum number of VMIDs */ 854 #define AMDGPU_NUM_VM 16 855 856 /* number of entries in page table */ 857 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size) 858 859 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 860 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768 861 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1) 862 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK) 863 864 #define AMDGPU_PTE_VALID (1 << 0) 865 #define AMDGPU_PTE_SYSTEM (1 << 1) 866 #define AMDGPU_PTE_SNOOPED (1 << 2) 867 868 /* VI only */ 869 #define AMDGPU_PTE_EXECUTABLE (1 << 4) 870 871 #define AMDGPU_PTE_READABLE (1 << 5) 872 #define AMDGPU_PTE_WRITEABLE (1 << 6) 873 874 /* PTE (Page Table Entry) fragment field for different page sizes */ 875 #define AMDGPU_PTE_FRAG_4KB (0 << 7) 876 #define AMDGPU_PTE_FRAG_64KB (4 << 7) 877 #define AMDGPU_LOG2_PAGES_PER_FRAG 4 878 879 /* How to programm VM fault handling */ 880 #define AMDGPU_VM_FAULT_STOP_NEVER 0 881 #define AMDGPU_VM_FAULT_STOP_FIRST 1 882 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 883 884 struct amdgpu_vm_pt { 885 struct amdgpu_bo_list_entry entry; 886 uint64_t addr; 887 }; 888 889 struct amdgpu_vm_id { 890 unsigned id; 891 uint64_t pd_gpu_addr; 892 /* last flushed PD/PT update */ 893 struct fence *flushed_updates; 894 }; 895 896 struct amdgpu_vm { 897 /* tree of virtual addresses mapped */ 898 spinlock_t it_lock; 899 struct rb_root va; 900 901 /* protecting invalidated */ 902 spinlock_t status_lock; 903 904 /* BOs moved, but not yet updated in the PT */ 905 struct list_head invalidated; 906 907 /* BOs cleared in the PT because of a move */ 908 struct list_head cleared; 909 910 /* BO mappings freed, but not yet updated in the PT */ 911 struct list_head freed; 912 913 /* contains the page directory */ 914 struct amdgpu_bo *page_directory; 915 unsigned max_pde_used; 916 struct fence *page_directory_fence; 917 918 /* array of page tables, one for each page directory entry */ 919 struct amdgpu_vm_pt *page_tables; 920 921 /* for id and flush management per ring */ 922 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS]; 923 924 /* protecting freed */ 925 spinlock_t freed_lock; 926 }; 927 928 struct amdgpu_vm_manager_id { 929 struct list_head list; 930 struct fence *active; 931 atomic_long_t owner; 932 }; 933 934 struct amdgpu_vm_manager { 935 /* Handling of VMIDs */ 936 struct mutex lock; 937 unsigned num_ids; 938 struct list_head ids_lru; 939 struct amdgpu_vm_manager_id ids[AMDGPU_NUM_VM]; 940 941 uint32_t max_pfn; 942 /* vram base address for page table entry */ 943 u64 vram_base_offset; 944 /* is vm enabled? */ 945 bool enabled; 946 /* vm pte handling */ 947 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 948 struct amdgpu_ring *vm_pte_funcs_ring; 949 }; 950 951 void amdgpu_vm_manager_init(struct amdgpu_device *adev); 952 void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 953 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); 954 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 955 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, 956 struct list_head *validated, 957 struct amdgpu_bo_list_entry *entry); 958 void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates); 959 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, 960 struct amdgpu_vm *vm); 961 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, 962 struct amdgpu_sync *sync, struct fence *fence); 963 void amdgpu_vm_flush(struct amdgpu_ring *ring, 964 struct amdgpu_vm *vm, 965 struct fence *updates); 966 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); 967 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, 968 struct amdgpu_vm *vm); 969 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 970 struct amdgpu_vm *vm); 971 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm, 972 struct amdgpu_sync *sync); 973 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 974 struct amdgpu_bo_va *bo_va, 975 struct ttm_mem_reg *mem); 976 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 977 struct amdgpu_bo *bo); 978 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 979 struct amdgpu_bo *bo); 980 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 981 struct amdgpu_vm *vm, 982 struct amdgpu_bo *bo); 983 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 984 struct amdgpu_bo_va *bo_va, 985 uint64_t addr, uint64_t offset, 986 uint64_t size, uint32_t flags); 987 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 988 struct amdgpu_bo_va *bo_va, 989 uint64_t addr); 990 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, 991 struct amdgpu_bo_va *bo_va); 992 int amdgpu_vm_free_job(struct amdgpu_job *job); 993 994 /* 995 * context related structures 996 */ 997 998 struct amdgpu_ctx_ring { 999 uint64_t sequence; 1000 struct fence **fences; 1001 struct amd_sched_entity entity; 1002 }; 1003 1004 struct amdgpu_ctx { 1005 struct kref refcount; 1006 struct amdgpu_device *adev; 1007 unsigned reset_counter; 1008 spinlock_t ring_lock; 1009 struct fence **fences; 1010 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; 1011 }; 1012 1013 struct amdgpu_ctx_mgr { 1014 struct amdgpu_device *adev; 1015 struct mutex lock; 1016 /* protected by lock */ 1017 struct idr ctx_handles; 1018 }; 1019 1020 int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri, 1021 struct amdgpu_ctx *ctx); 1022 void amdgpu_ctx_fini(struct amdgpu_ctx *ctx); 1023 1024 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 1025 int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 1026 1027 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 1028 struct fence *fence); 1029 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 1030 struct amdgpu_ring *ring, uint64_t seq); 1031 1032 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 1033 struct drm_file *filp); 1034 1035 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 1036 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 1037 1038 /* 1039 * file private structure 1040 */ 1041 1042 struct amdgpu_fpriv { 1043 struct amdgpu_vm vm; 1044 struct mutex bo_list_lock; 1045 struct idr bo_list_handles; 1046 struct amdgpu_ctx_mgr ctx_mgr; 1047 }; 1048 1049 /* 1050 * residency list 1051 */ 1052 1053 struct amdgpu_bo_list { 1054 struct mutex lock; 1055 struct amdgpu_bo *gds_obj; 1056 struct amdgpu_bo *gws_obj; 1057 struct amdgpu_bo *oa_obj; 1058 bool has_userptr; 1059 unsigned num_entries; 1060 struct amdgpu_bo_list_entry *array; 1061 }; 1062 1063 struct amdgpu_bo_list * 1064 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); 1065 void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list, 1066 struct list_head *validated); 1067 void amdgpu_bo_list_put(struct amdgpu_bo_list *list); 1068 void amdgpu_bo_list_free(struct amdgpu_bo_list *list); 1069 1070 /* 1071 * GFX stuff 1072 */ 1073 #include "clearstate_defs.h" 1074 1075 struct amdgpu_rlc { 1076 /* for power gating */ 1077 struct amdgpu_bo *save_restore_obj; 1078 uint64_t save_restore_gpu_addr; 1079 volatile uint32_t *sr_ptr; 1080 const u32 *reg_list; 1081 u32 reg_list_size; 1082 /* for clear state */ 1083 struct amdgpu_bo *clear_state_obj; 1084 uint64_t clear_state_gpu_addr; 1085 volatile uint32_t *cs_ptr; 1086 const struct cs_section_def *cs_data; 1087 u32 clear_state_size; 1088 /* for cp tables */ 1089 struct amdgpu_bo *cp_table_obj; 1090 uint64_t cp_table_gpu_addr; 1091 volatile uint32_t *cp_table_ptr; 1092 u32 cp_table_size; 1093 }; 1094 1095 struct amdgpu_mec { 1096 struct amdgpu_bo *hpd_eop_obj; 1097 u64 hpd_eop_gpu_addr; 1098 u32 num_pipe; 1099 u32 num_mec; 1100 u32 num_queue; 1101 }; 1102 1103 /* 1104 * GPU scratch registers structures, functions & helpers 1105 */ 1106 struct amdgpu_scratch { 1107 unsigned num_reg; 1108 uint32_t reg_base; 1109 bool free[32]; 1110 uint32_t reg[32]; 1111 }; 1112 1113 /* 1114 * GFX configurations 1115 */ 1116 struct amdgpu_gca_config { 1117 unsigned max_shader_engines; 1118 unsigned max_tile_pipes; 1119 unsigned max_cu_per_sh; 1120 unsigned max_sh_per_se; 1121 unsigned max_backends_per_se; 1122 unsigned max_texture_channel_caches; 1123 unsigned max_gprs; 1124 unsigned max_gs_threads; 1125 unsigned max_hw_contexts; 1126 unsigned sc_prim_fifo_size_frontend; 1127 unsigned sc_prim_fifo_size_backend; 1128 unsigned sc_hiz_tile_fifo_size; 1129 unsigned sc_earlyz_tile_fifo_size; 1130 1131 unsigned num_tile_pipes; 1132 unsigned backend_enable_mask; 1133 unsigned mem_max_burst_length_bytes; 1134 unsigned mem_row_size_in_kb; 1135 unsigned shader_engine_tile_size; 1136 unsigned num_gpus; 1137 unsigned multi_gpu_tile_size; 1138 unsigned mc_arb_ramcfg; 1139 unsigned gb_addr_config; 1140 1141 uint32_t tile_mode_array[32]; 1142 uint32_t macrotile_mode_array[16]; 1143 }; 1144 1145 struct amdgpu_gfx { 1146 struct mutex gpu_clock_mutex; 1147 struct amdgpu_gca_config config; 1148 struct amdgpu_rlc rlc; 1149 struct amdgpu_mec mec; 1150 struct amdgpu_scratch scratch; 1151 const struct firmware *me_fw; /* ME firmware */ 1152 uint32_t me_fw_version; 1153 const struct firmware *pfp_fw; /* PFP firmware */ 1154 uint32_t pfp_fw_version; 1155 const struct firmware *ce_fw; /* CE firmware */ 1156 uint32_t ce_fw_version; 1157 const struct firmware *rlc_fw; /* RLC firmware */ 1158 uint32_t rlc_fw_version; 1159 const struct firmware *mec_fw; /* MEC firmware */ 1160 uint32_t mec_fw_version; 1161 const struct firmware *mec2_fw; /* MEC2 firmware */ 1162 uint32_t mec2_fw_version; 1163 uint32_t me_feature_version; 1164 uint32_t ce_feature_version; 1165 uint32_t pfp_feature_version; 1166 uint32_t rlc_feature_version; 1167 uint32_t mec_feature_version; 1168 uint32_t mec2_feature_version; 1169 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 1170 unsigned num_gfx_rings; 1171 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 1172 unsigned num_compute_rings; 1173 struct amdgpu_irq_src eop_irq; 1174 struct amdgpu_irq_src priv_reg_irq; 1175 struct amdgpu_irq_src priv_inst_irq; 1176 /* gfx status */ 1177 uint32_t gfx_current_status; 1178 /* ce ram size*/ 1179 unsigned ce_ram_size; 1180 }; 1181 1182 int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm, 1183 unsigned size, struct amdgpu_ib *ib); 1184 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib); 1185 int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, 1186 struct amdgpu_ib *ib, void *owner); 1187 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 1188 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 1189 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 1190 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 1191 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 1192 void amdgpu_ring_commit(struct amdgpu_ring *ring); 1193 void amdgpu_ring_undo(struct amdgpu_ring *ring); 1194 unsigned amdgpu_ring_backup(struct amdgpu_ring *ring, 1195 uint32_t **data); 1196 int amdgpu_ring_restore(struct amdgpu_ring *ring, 1197 unsigned size, uint32_t *data); 1198 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 1199 unsigned ring_size, u32 nop, u32 align_mask, 1200 struct amdgpu_irq_src *irq_src, unsigned irq_type, 1201 enum amdgpu_ring_type ring_type); 1202 void amdgpu_ring_fini(struct amdgpu_ring *ring); 1203 struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f); 1204 1205 /* 1206 * CS. 1207 */ 1208 struct amdgpu_cs_chunk { 1209 uint32_t chunk_id; 1210 uint32_t length_dw; 1211 uint32_t *kdata; 1212 }; 1213 1214 struct amdgpu_cs_parser { 1215 struct amdgpu_device *adev; 1216 struct drm_file *filp; 1217 struct amdgpu_ctx *ctx; 1218 1219 /* chunks */ 1220 unsigned nchunks; 1221 struct amdgpu_cs_chunk *chunks; 1222 1223 /* indirect buffers */ 1224 uint32_t num_ibs; 1225 struct amdgpu_ib *ibs; 1226 1227 /* buffer objects */ 1228 struct ww_acquire_ctx ticket; 1229 struct amdgpu_bo_list *bo_list; 1230 struct amdgpu_bo_list_entry vm_pd; 1231 struct list_head validated; 1232 struct fence *fence; 1233 uint64_t bytes_moved_threshold; 1234 uint64_t bytes_moved; 1235 1236 /* user fence */ 1237 struct amdgpu_user_fence uf; 1238 struct amdgpu_bo_list_entry uf_entry; 1239 }; 1240 1241 struct amdgpu_job { 1242 struct amd_sched_job base; 1243 struct amdgpu_device *adev; 1244 struct amdgpu_ib *ibs; 1245 uint32_t num_ibs; 1246 void *owner; 1247 struct amdgpu_user_fence uf; 1248 int (*free_job)(struct amdgpu_job *job); 1249 }; 1250 #define to_amdgpu_job(sched_job) \ 1251 container_of((sched_job), struct amdgpu_job, base) 1252 1253 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx) 1254 { 1255 return p->ibs[ib_idx].ptr[idx]; 1256 } 1257 1258 /* 1259 * Writeback 1260 */ 1261 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 1262 1263 struct amdgpu_wb { 1264 struct amdgpu_bo *wb_obj; 1265 volatile uint32_t *wb; 1266 uint64_t gpu_addr; 1267 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 1268 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 1269 }; 1270 1271 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); 1272 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); 1273 1274 1275 1276 enum amdgpu_int_thermal_type { 1277 THERMAL_TYPE_NONE, 1278 THERMAL_TYPE_EXTERNAL, 1279 THERMAL_TYPE_EXTERNAL_GPIO, 1280 THERMAL_TYPE_RV6XX, 1281 THERMAL_TYPE_RV770, 1282 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1283 THERMAL_TYPE_EVERGREEN, 1284 THERMAL_TYPE_SUMO, 1285 THERMAL_TYPE_NI, 1286 THERMAL_TYPE_SI, 1287 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1288 THERMAL_TYPE_CI, 1289 THERMAL_TYPE_KV, 1290 }; 1291 1292 enum amdgpu_dpm_auto_throttle_src { 1293 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, 1294 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1295 }; 1296 1297 enum amdgpu_dpm_event_src { 1298 AMDGPU_DPM_EVENT_SRC_ANALOG = 0, 1299 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1, 1300 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2, 1301 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1302 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1303 }; 1304 1305 #define AMDGPU_MAX_VCE_LEVELS 6 1306 1307 enum amdgpu_vce_level { 1308 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1309 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1310 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1311 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1312 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1313 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1314 }; 1315 1316 struct amdgpu_ps { 1317 u32 caps; /* vbios flags */ 1318 u32 class; /* vbios flags */ 1319 u32 class2; /* vbios flags */ 1320 /* UVD clocks */ 1321 u32 vclk; 1322 u32 dclk; 1323 /* VCE clocks */ 1324 u32 evclk; 1325 u32 ecclk; 1326 bool vce_active; 1327 enum amdgpu_vce_level vce_level; 1328 /* asic priv */ 1329 void *ps_priv; 1330 }; 1331 1332 struct amdgpu_dpm_thermal { 1333 /* thermal interrupt work */ 1334 struct work_struct work; 1335 /* low temperature threshold */ 1336 int min_temp; 1337 /* high temperature threshold */ 1338 int max_temp; 1339 /* was last interrupt low to high or high to low */ 1340 bool high_to_low; 1341 /* interrupt source */ 1342 struct amdgpu_irq_src irq; 1343 }; 1344 1345 enum amdgpu_clk_action 1346 { 1347 AMDGPU_SCLK_UP = 1, 1348 AMDGPU_SCLK_DOWN 1349 }; 1350 1351 struct amdgpu_blacklist_clocks 1352 { 1353 u32 sclk; 1354 u32 mclk; 1355 enum amdgpu_clk_action action; 1356 }; 1357 1358 struct amdgpu_clock_and_voltage_limits { 1359 u32 sclk; 1360 u32 mclk; 1361 u16 vddc; 1362 u16 vddci; 1363 }; 1364 1365 struct amdgpu_clock_array { 1366 u32 count; 1367 u32 *values; 1368 }; 1369 1370 struct amdgpu_clock_voltage_dependency_entry { 1371 u32 clk; 1372 u16 v; 1373 }; 1374 1375 struct amdgpu_clock_voltage_dependency_table { 1376 u32 count; 1377 struct amdgpu_clock_voltage_dependency_entry *entries; 1378 }; 1379 1380 union amdgpu_cac_leakage_entry { 1381 struct { 1382 u16 vddc; 1383 u32 leakage; 1384 }; 1385 struct { 1386 u16 vddc1; 1387 u16 vddc2; 1388 u16 vddc3; 1389 }; 1390 }; 1391 1392 struct amdgpu_cac_leakage_table { 1393 u32 count; 1394 union amdgpu_cac_leakage_entry *entries; 1395 }; 1396 1397 struct amdgpu_phase_shedding_limits_entry { 1398 u16 voltage; 1399 u32 sclk; 1400 u32 mclk; 1401 }; 1402 1403 struct amdgpu_phase_shedding_limits_table { 1404 u32 count; 1405 struct amdgpu_phase_shedding_limits_entry *entries; 1406 }; 1407 1408 struct amdgpu_uvd_clock_voltage_dependency_entry { 1409 u32 vclk; 1410 u32 dclk; 1411 u16 v; 1412 }; 1413 1414 struct amdgpu_uvd_clock_voltage_dependency_table { 1415 u8 count; 1416 struct amdgpu_uvd_clock_voltage_dependency_entry *entries; 1417 }; 1418 1419 struct amdgpu_vce_clock_voltage_dependency_entry { 1420 u32 ecclk; 1421 u32 evclk; 1422 u16 v; 1423 }; 1424 1425 struct amdgpu_vce_clock_voltage_dependency_table { 1426 u8 count; 1427 struct amdgpu_vce_clock_voltage_dependency_entry *entries; 1428 }; 1429 1430 struct amdgpu_ppm_table { 1431 u8 ppm_design; 1432 u16 cpu_core_number; 1433 u32 platform_tdp; 1434 u32 small_ac_platform_tdp; 1435 u32 platform_tdc; 1436 u32 small_ac_platform_tdc; 1437 u32 apu_tdp; 1438 u32 dgpu_tdp; 1439 u32 dgpu_ulv_power; 1440 u32 tj_max; 1441 }; 1442 1443 struct amdgpu_cac_tdp_table { 1444 u16 tdp; 1445 u16 configurable_tdp; 1446 u16 tdc; 1447 u16 battery_power_limit; 1448 u16 small_power_limit; 1449 u16 low_cac_leakage; 1450 u16 high_cac_leakage; 1451 u16 maximum_power_delivery_limit; 1452 }; 1453 1454 struct amdgpu_dpm_dynamic_state { 1455 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; 1456 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; 1457 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; 1458 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1459 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1460 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1461 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1462 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1463 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1464 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; 1465 struct amdgpu_clock_array valid_sclk_values; 1466 struct amdgpu_clock_array valid_mclk_values; 1467 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; 1468 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; 1469 u32 mclk_sclk_ratio; 1470 u32 sclk_mclk_delta; 1471 u16 vddc_vddci_delta; 1472 u16 min_vddc_for_pcie_gen2; 1473 struct amdgpu_cac_leakage_table cac_leakage_table; 1474 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; 1475 struct amdgpu_ppm_table *ppm_table; 1476 struct amdgpu_cac_tdp_table *cac_tdp_table; 1477 }; 1478 1479 struct amdgpu_dpm_fan { 1480 u16 t_min; 1481 u16 t_med; 1482 u16 t_high; 1483 u16 pwm_min; 1484 u16 pwm_med; 1485 u16 pwm_high; 1486 u8 t_hyst; 1487 u32 cycle_delay; 1488 u16 t_max; 1489 u8 control_mode; 1490 u16 default_max_fan_pwm; 1491 u16 default_fan_output_sensitivity; 1492 u16 fan_output_sensitivity; 1493 bool ucode_fan_control; 1494 }; 1495 1496 enum amdgpu_pcie_gen { 1497 AMDGPU_PCIE_GEN1 = 0, 1498 AMDGPU_PCIE_GEN2 = 1, 1499 AMDGPU_PCIE_GEN3 = 2, 1500 AMDGPU_PCIE_GEN_INVALID = 0xffff 1501 }; 1502 1503 enum amdgpu_dpm_forced_level { 1504 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0, 1505 AMDGPU_DPM_FORCED_LEVEL_LOW = 1, 1506 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2, 1507 AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3, 1508 }; 1509 1510 struct amdgpu_vce_state { 1511 /* vce clocks */ 1512 u32 evclk; 1513 u32 ecclk; 1514 /* gpu clocks */ 1515 u32 sclk; 1516 u32 mclk; 1517 u8 clk_idx; 1518 u8 pstate; 1519 }; 1520 1521 struct amdgpu_dpm_funcs { 1522 int (*get_temperature)(struct amdgpu_device *adev); 1523 int (*pre_set_power_state)(struct amdgpu_device *adev); 1524 int (*set_power_state)(struct amdgpu_device *adev); 1525 void (*post_set_power_state)(struct amdgpu_device *adev); 1526 void (*display_configuration_changed)(struct amdgpu_device *adev); 1527 u32 (*get_sclk)(struct amdgpu_device *adev, bool low); 1528 u32 (*get_mclk)(struct amdgpu_device *adev, bool low); 1529 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps); 1530 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m); 1531 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level); 1532 bool (*vblank_too_short)(struct amdgpu_device *adev); 1533 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate); 1534 void (*powergate_vce)(struct amdgpu_device *adev, bool gate); 1535 void (*enable_bapm)(struct amdgpu_device *adev, bool enable); 1536 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode); 1537 u32 (*get_fan_control_mode)(struct amdgpu_device *adev); 1538 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed); 1539 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed); 1540 }; 1541 1542 struct amdgpu_dpm { 1543 struct amdgpu_ps *ps; 1544 /* number of valid power states */ 1545 int num_ps; 1546 /* current power state that is active */ 1547 struct amdgpu_ps *current_ps; 1548 /* requested power state */ 1549 struct amdgpu_ps *requested_ps; 1550 /* boot up power state */ 1551 struct amdgpu_ps *boot_ps; 1552 /* default uvd power state */ 1553 struct amdgpu_ps *uvd_ps; 1554 /* vce requirements */ 1555 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS]; 1556 enum amdgpu_vce_level vce_level; 1557 enum amd_pm_state_type state; 1558 enum amd_pm_state_type user_state; 1559 u32 platform_caps; 1560 u32 voltage_response_time; 1561 u32 backbias_response_time; 1562 void *priv; 1563 u32 new_active_crtcs; 1564 int new_active_crtc_count; 1565 u32 current_active_crtcs; 1566 int current_active_crtc_count; 1567 struct amdgpu_dpm_dynamic_state dyn_state; 1568 struct amdgpu_dpm_fan fan; 1569 u32 tdp_limit; 1570 u32 near_tdp_limit; 1571 u32 near_tdp_limit_adjusted; 1572 u32 sq_ramping_threshold; 1573 u32 cac_leakage; 1574 u16 tdp_od_limit; 1575 u32 tdp_adjustment; 1576 u16 load_line_slope; 1577 bool power_control; 1578 bool ac_power; 1579 /* special states active */ 1580 bool thermal_active; 1581 bool uvd_active; 1582 bool vce_active; 1583 /* thermal handling */ 1584 struct amdgpu_dpm_thermal thermal; 1585 /* forced levels */ 1586 enum amdgpu_dpm_forced_level forced_level; 1587 }; 1588 1589 struct amdgpu_pm { 1590 struct mutex mutex; 1591 u32 current_sclk; 1592 u32 current_mclk; 1593 u32 default_sclk; 1594 u32 default_mclk; 1595 struct amdgpu_i2c_chan *i2c_bus; 1596 /* internal thermal controller on rv6xx+ */ 1597 enum amdgpu_int_thermal_type int_thermal_type; 1598 struct device *int_hwmon_dev; 1599 /* fan control parameters */ 1600 bool no_fan; 1601 u8 fan_pulses_per_revolution; 1602 u8 fan_min_rpm; 1603 u8 fan_max_rpm; 1604 /* dpm */ 1605 bool dpm_enabled; 1606 bool sysfs_initialized; 1607 struct amdgpu_dpm dpm; 1608 const struct firmware *fw; /* SMC firmware */ 1609 uint32_t fw_version; 1610 const struct amdgpu_dpm_funcs *funcs; 1611 uint32_t pcie_gen_mask; 1612 uint32_t pcie_mlw_mask; 1613 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */ 1614 }; 1615 1616 void amdgpu_get_pcie_info(struct amdgpu_device *adev); 1617 1618 /* 1619 * UVD 1620 */ 1621 #define AMDGPU_MAX_UVD_HANDLES 10 1622 #define AMDGPU_UVD_STACK_SIZE (1024*1024) 1623 #define AMDGPU_UVD_HEAP_SIZE (1024*1024) 1624 #define AMDGPU_UVD_FIRMWARE_OFFSET 256 1625 1626 struct amdgpu_uvd { 1627 struct amdgpu_bo *vcpu_bo; 1628 void *cpu_addr; 1629 uint64_t gpu_addr; 1630 atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; 1631 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; 1632 struct delayed_work idle_work; 1633 const struct firmware *fw; /* UVD firmware */ 1634 struct amdgpu_ring ring; 1635 struct amdgpu_irq_src irq; 1636 bool address_64_bit; 1637 }; 1638 1639 /* 1640 * VCE 1641 */ 1642 #define AMDGPU_MAX_VCE_HANDLES 16 1643 #define AMDGPU_VCE_FIRMWARE_OFFSET 256 1644 1645 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0) 1646 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1) 1647 1648 struct amdgpu_vce { 1649 struct amdgpu_bo *vcpu_bo; 1650 uint64_t gpu_addr; 1651 unsigned fw_version; 1652 unsigned fb_version; 1653 atomic_t handles[AMDGPU_MAX_VCE_HANDLES]; 1654 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES]; 1655 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES]; 1656 struct delayed_work idle_work; 1657 const struct firmware *fw; /* VCE firmware */ 1658 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS]; 1659 struct amdgpu_irq_src irq; 1660 unsigned harvest_config; 1661 }; 1662 1663 /* 1664 * SDMA 1665 */ 1666 struct amdgpu_sdma_instance { 1667 /* SDMA firmware */ 1668 const struct firmware *fw; 1669 uint32_t fw_version; 1670 uint32_t feature_version; 1671 1672 struct amdgpu_ring ring; 1673 bool burst_nop; 1674 }; 1675 1676 struct amdgpu_sdma { 1677 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 1678 struct amdgpu_irq_src trap_irq; 1679 struct amdgpu_irq_src illegal_inst_irq; 1680 int num_instances; 1681 }; 1682 1683 /* 1684 * Firmware 1685 */ 1686 struct amdgpu_firmware { 1687 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 1688 bool smu_load; 1689 struct amdgpu_bo *fw_buf; 1690 unsigned int fw_size; 1691 }; 1692 1693 /* 1694 * Benchmarking 1695 */ 1696 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 1697 1698 1699 /* 1700 * Testing 1701 */ 1702 void amdgpu_test_moves(struct amdgpu_device *adev); 1703 void amdgpu_test_ring_sync(struct amdgpu_device *adev, 1704 struct amdgpu_ring *cpA, 1705 struct amdgpu_ring *cpB); 1706 void amdgpu_test_syncing(struct amdgpu_device *adev); 1707 1708 /* 1709 * MMU Notifier 1710 */ 1711 #if defined(CONFIG_MMU_NOTIFIER) 1712 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); 1713 void amdgpu_mn_unregister(struct amdgpu_bo *bo); 1714 #else 1715 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) 1716 { 1717 return -ENODEV; 1718 } 1719 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} 1720 #endif 1721 1722 /* 1723 * Debugfs 1724 */ 1725 struct amdgpu_debugfs { 1726 struct drm_info_list *files; 1727 unsigned num_files; 1728 }; 1729 1730 int amdgpu_debugfs_add_files(struct amdgpu_device *adev, 1731 struct drm_info_list *files, 1732 unsigned nfiles); 1733 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); 1734 1735 #if defined(CONFIG_DEBUG_FS) 1736 int amdgpu_debugfs_init(struct drm_minor *minor); 1737 void amdgpu_debugfs_cleanup(struct drm_minor *minor); 1738 #endif 1739 1740 /* 1741 * amdgpu smumgr functions 1742 */ 1743 struct amdgpu_smumgr_funcs { 1744 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 1745 int (*request_smu_load_fw)(struct amdgpu_device *adev); 1746 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 1747 }; 1748 1749 /* 1750 * amdgpu smumgr 1751 */ 1752 struct amdgpu_smumgr { 1753 struct amdgpu_bo *toc_buf; 1754 struct amdgpu_bo *smu_buf; 1755 /* asic priv smu data */ 1756 void *priv; 1757 spinlock_t smu_lock; 1758 /* smumgr functions */ 1759 const struct amdgpu_smumgr_funcs *smumgr_funcs; 1760 /* ucode loading complete flag */ 1761 uint32_t fw_flags; 1762 }; 1763 1764 /* 1765 * ASIC specific register table accessible by UMD 1766 */ 1767 struct amdgpu_allowed_register_entry { 1768 uint32_t reg_offset; 1769 bool untouched; 1770 bool grbm_indexed; 1771 }; 1772 1773 struct amdgpu_cu_info { 1774 uint32_t number; /* total active CU number */ 1775 uint32_t ao_cu_mask; 1776 uint32_t bitmap[4][4]; 1777 }; 1778 1779 1780 /* 1781 * ASIC specific functions. 1782 */ 1783 struct amdgpu_asic_funcs { 1784 bool (*read_disabled_bios)(struct amdgpu_device *adev); 1785 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 1786 u8 *bios, u32 length_bytes); 1787 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 1788 u32 sh_num, u32 reg_offset, u32 *value); 1789 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 1790 int (*reset)(struct amdgpu_device *adev); 1791 /* wait for mc_idle */ 1792 int (*wait_for_mc_idle)(struct amdgpu_device *adev); 1793 /* get the reference clock */ 1794 u32 (*get_xclk)(struct amdgpu_device *adev); 1795 /* get the gpu clock counter */ 1796 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 1797 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info); 1798 /* MM block clocks */ 1799 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 1800 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 1801 }; 1802 1803 /* 1804 * IOCTL. 1805 */ 1806 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 1807 struct drm_file *filp); 1808 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 1809 struct drm_file *filp); 1810 1811 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 1812 struct drm_file *filp); 1813 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 1814 struct drm_file *filp); 1815 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 1816 struct drm_file *filp); 1817 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1818 struct drm_file *filp); 1819 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 1820 struct drm_file *filp); 1821 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 1822 struct drm_file *filp); 1823 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1824 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1825 1826 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 1827 struct drm_file *filp); 1828 1829 /* VRAM scratch page for HDP bug, default vram page */ 1830 struct amdgpu_vram_scratch { 1831 struct amdgpu_bo *robj; 1832 volatile uint32_t *ptr; 1833 u64 gpu_addr; 1834 }; 1835 1836 /* 1837 * ACPI 1838 */ 1839 struct amdgpu_atif_notification_cfg { 1840 bool enabled; 1841 int command_code; 1842 }; 1843 1844 struct amdgpu_atif_notifications { 1845 bool display_switch; 1846 bool expansion_mode_change; 1847 bool thermal_state; 1848 bool forced_power_state; 1849 bool system_power_state; 1850 bool display_conf_change; 1851 bool px_gfx_switch; 1852 bool brightness_change; 1853 bool dgpu_display_event; 1854 }; 1855 1856 struct amdgpu_atif_functions { 1857 bool system_params; 1858 bool sbios_requests; 1859 bool select_active_disp; 1860 bool lid_state; 1861 bool get_tv_standard; 1862 bool set_tv_standard; 1863 bool get_panel_expansion_mode; 1864 bool set_panel_expansion_mode; 1865 bool temperature_change; 1866 bool graphics_device_types; 1867 }; 1868 1869 struct amdgpu_atif { 1870 struct amdgpu_atif_notifications notifications; 1871 struct amdgpu_atif_functions functions; 1872 struct amdgpu_atif_notification_cfg notification_cfg; 1873 struct amdgpu_encoder *encoder_for_bl; 1874 }; 1875 1876 struct amdgpu_atcs_functions { 1877 bool get_ext_state; 1878 bool pcie_perf_req; 1879 bool pcie_dev_rdy; 1880 bool pcie_bus_width; 1881 }; 1882 1883 struct amdgpu_atcs { 1884 struct amdgpu_atcs_functions functions; 1885 }; 1886 1887 /* 1888 * CGS 1889 */ 1890 void *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1891 void amdgpu_cgs_destroy_device(void *cgs_device); 1892 1893 1894 /* 1895 * CGS 1896 */ 1897 void *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1898 void amdgpu_cgs_destroy_device(void *cgs_device); 1899 1900 1901 /* 1902 * Core structure, functions and helpers. 1903 */ 1904 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 1905 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1906 1907 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1908 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 1909 1910 struct amdgpu_ip_block_status { 1911 bool valid; 1912 bool sw; 1913 bool hw; 1914 }; 1915 1916 struct amdgpu_device { 1917 struct device *dev; 1918 struct drm_device *ddev; 1919 struct pci_dev *pdev; 1920 1921 #ifdef CONFIG_DRM_AMD_ACP 1922 struct amdgpu_acp acp; 1923 #endif 1924 1925 /* ASIC */ 1926 enum amd_asic_type asic_type; 1927 uint32_t family; 1928 uint32_t rev_id; 1929 uint32_t external_rev_id; 1930 unsigned long flags; 1931 int usec_timeout; 1932 const struct amdgpu_asic_funcs *asic_funcs; 1933 bool shutdown; 1934 bool suspend; 1935 bool need_dma32; 1936 bool accel_working; 1937 struct work_struct reset_work; 1938 struct notifier_block acpi_nb; 1939 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 1940 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1941 unsigned debugfs_count; 1942 #if defined(CONFIG_DEBUG_FS) 1943 struct dentry *debugfs_regs; 1944 #endif 1945 struct amdgpu_atif atif; 1946 struct amdgpu_atcs atcs; 1947 struct mutex srbm_mutex; 1948 /* GRBM index mutex. Protects concurrent access to GRBM index */ 1949 struct mutex grbm_idx_mutex; 1950 struct dev_pm_domain vga_pm_domain; 1951 bool have_disp_power_ref; 1952 1953 /* BIOS */ 1954 uint8_t *bios; 1955 bool is_atom_bios; 1956 uint16_t bios_header_start; 1957 struct amdgpu_bo *stollen_vga_memory; 1958 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 1959 1960 /* Register/doorbell mmio */ 1961 resource_size_t rmmio_base; 1962 resource_size_t rmmio_size; 1963 void __iomem *rmmio; 1964 /* protects concurrent MM_INDEX/DATA based register access */ 1965 spinlock_t mmio_idx_lock; 1966 /* protects concurrent SMC based register access */ 1967 spinlock_t smc_idx_lock; 1968 amdgpu_rreg_t smc_rreg; 1969 amdgpu_wreg_t smc_wreg; 1970 /* protects concurrent PCIE register access */ 1971 spinlock_t pcie_idx_lock; 1972 amdgpu_rreg_t pcie_rreg; 1973 amdgpu_wreg_t pcie_wreg; 1974 /* protects concurrent UVD register access */ 1975 spinlock_t uvd_ctx_idx_lock; 1976 amdgpu_rreg_t uvd_ctx_rreg; 1977 amdgpu_wreg_t uvd_ctx_wreg; 1978 /* protects concurrent DIDT register access */ 1979 spinlock_t didt_idx_lock; 1980 amdgpu_rreg_t didt_rreg; 1981 amdgpu_wreg_t didt_wreg; 1982 /* protects concurrent ENDPOINT (audio) register access */ 1983 spinlock_t audio_endpt_idx_lock; 1984 amdgpu_block_rreg_t audio_endpt_rreg; 1985 amdgpu_block_wreg_t audio_endpt_wreg; 1986 void __iomem *rio_mem; 1987 resource_size_t rio_mem_size; 1988 struct amdgpu_doorbell doorbell; 1989 1990 /* clock/pll info */ 1991 struct amdgpu_clock clock; 1992 1993 /* MC */ 1994 struct amdgpu_mc mc; 1995 struct amdgpu_gart gart; 1996 struct amdgpu_dummy_page dummy_page; 1997 struct amdgpu_vm_manager vm_manager; 1998 1999 /* memory management */ 2000 struct amdgpu_mman mman; 2001 struct amdgpu_gem gem; 2002 struct amdgpu_vram_scratch vram_scratch; 2003 struct amdgpu_wb wb; 2004 atomic64_t vram_usage; 2005 atomic64_t vram_vis_usage; 2006 atomic64_t gtt_usage; 2007 atomic64_t num_bytes_moved; 2008 atomic_t gpu_reset_counter; 2009 2010 /* display */ 2011 struct amdgpu_mode_info mode_info; 2012 struct work_struct hotplug_work; 2013 struct amdgpu_irq_src crtc_irq; 2014 struct amdgpu_irq_src pageflip_irq; 2015 struct amdgpu_irq_src hpd_irq; 2016 2017 /* rings */ 2018 unsigned fence_context; 2019 unsigned num_rings; 2020 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 2021 bool ib_pool_ready; 2022 struct amdgpu_sa_manager ring_tmp_bo; 2023 2024 /* interrupts */ 2025 struct amdgpu_irq irq; 2026 2027 /* powerplay */ 2028 struct amd_powerplay powerplay; 2029 bool pp_enabled; 2030 bool pp_force_state_enabled; 2031 2032 /* dpm */ 2033 struct amdgpu_pm pm; 2034 u32 cg_flags; 2035 u32 pg_flags; 2036 2037 /* amdgpu smumgr */ 2038 struct amdgpu_smumgr smu; 2039 2040 /* gfx */ 2041 struct amdgpu_gfx gfx; 2042 2043 /* sdma */ 2044 struct amdgpu_sdma sdma; 2045 2046 /* uvd */ 2047 bool has_uvd; 2048 struct amdgpu_uvd uvd; 2049 2050 /* vce */ 2051 struct amdgpu_vce vce; 2052 2053 /* firmwares */ 2054 struct amdgpu_firmware firmware; 2055 2056 /* GDS */ 2057 struct amdgpu_gds gds; 2058 2059 const struct amdgpu_ip_block_version *ip_blocks; 2060 int num_ip_blocks; 2061 struct amdgpu_ip_block_status *ip_block_status; 2062 struct mutex mn_lock; 2063 DECLARE_HASHTABLE(mn_hash, 7); 2064 2065 /* tracking pinned memory */ 2066 u64 vram_pin_size; 2067 u64 gart_pin_size; 2068 2069 /* amdkfd interface */ 2070 struct kfd_dev *kfd; 2071 2072 /* kernel conext for IB submission */ 2073 struct amdgpu_ctx kernel_ctx; 2074 }; 2075 2076 bool amdgpu_device_is_px(struct drm_device *dev); 2077 int amdgpu_device_init(struct amdgpu_device *adev, 2078 struct drm_device *ddev, 2079 struct pci_dev *pdev, 2080 uint32_t flags); 2081 void amdgpu_device_fini(struct amdgpu_device *adev); 2082 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 2083 2084 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 2085 bool always_indirect); 2086 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 2087 bool always_indirect); 2088 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 2089 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 2090 2091 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 2092 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 2093 2094 /* 2095 * Cast helper 2096 */ 2097 extern const struct fence_ops amdgpu_fence_ops; 2098 static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f) 2099 { 2100 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base); 2101 2102 if (__f->base.ops == &amdgpu_fence_ops) 2103 return __f; 2104 2105 return NULL; 2106 } 2107 2108 /* 2109 * Registers read & write functions. 2110 */ 2111 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false) 2112 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true) 2113 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false)) 2114 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false) 2115 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true) 2116 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2117 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2118 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 2119 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 2120 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 2121 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 2122 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 2123 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 2124 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 2125 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 2126 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 2127 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 2128 #define WREG32_P(reg, val, mask) \ 2129 do { \ 2130 uint32_t tmp_ = RREG32(reg); \ 2131 tmp_ &= (mask); \ 2132 tmp_ |= ((val) & ~(mask)); \ 2133 WREG32(reg, tmp_); \ 2134 } while (0) 2135 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2136 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2137 #define WREG32_PLL_P(reg, val, mask) \ 2138 do { \ 2139 uint32_t tmp_ = RREG32_PLL(reg); \ 2140 tmp_ &= (mask); \ 2141 tmp_ |= ((val) & ~(mask)); \ 2142 WREG32_PLL(reg, tmp_); \ 2143 } while (0) 2144 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 2145 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 2146 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 2147 2148 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 2149 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 2150 2151 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 2152 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 2153 2154 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 2155 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 2156 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 2157 2158 #define REG_GET_FIELD(value, reg, field) \ 2159 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 2160 2161 /* 2162 * BIOS helpers. 2163 */ 2164 #define RBIOS8(i) (adev->bios[i]) 2165 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2166 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2167 2168 /* 2169 * RING helpers. 2170 */ 2171 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 2172 { 2173 if (ring->count_dw <= 0) 2174 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 2175 ring->ring[ring->wptr++] = v; 2176 ring->wptr &= ring->ptr_mask; 2177 ring->count_dw--; 2178 } 2179 2180 static inline struct amdgpu_sdma_instance * 2181 amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 2182 { 2183 struct amdgpu_device *adev = ring->adev; 2184 int i; 2185 2186 for (i = 0; i < adev->sdma.num_instances; i++) 2187 if (&adev->sdma.instance[i].ring == ring) 2188 break; 2189 2190 if (i < AMDGPU_MAX_SDMA_INSTANCES) 2191 return &adev->sdma.instance[i]; 2192 else 2193 return NULL; 2194 } 2195 2196 /* 2197 * ASICs macro. 2198 */ 2199 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 2200 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 2201 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev)) 2202 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 2203 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 2204 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 2205 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 2206 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 2207 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 2208 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 2209 #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info)) 2210 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) 2211 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) 2212 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 2213 #define amdgpu_vm_write_pte(adev, ib, pa, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pa), (pe), (addr), (count), (incr), (flags))) 2214 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 2215 #define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib))) 2216 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 2217 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 2218 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r)) 2219 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 2220 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 2221 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 2222 #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib)) 2223 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 2224 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 2225 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 2226 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 2227 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) 2228 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) 2229 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) 2230 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) 2231 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 2232 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) 2233 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev)) 2234 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 2235 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 2236 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 2237 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) 2238 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) 2239 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) 2240 #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base)) 2241 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) 2242 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) 2243 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) 2244 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s)) 2245 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) 2246 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 2247 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 2248 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev)) 2249 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev)) 2250 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev)) 2251 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev)) 2252 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps)) 2253 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev)) 2254 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e)) 2255 2256 #define amdgpu_dpm_get_temperature(adev) \ 2257 ((adev)->pp_enabled ? \ 2258 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \ 2259 (adev)->pm.funcs->get_temperature((adev))) 2260 2261 #define amdgpu_dpm_set_fan_control_mode(adev, m) \ 2262 ((adev)->pp_enabled ? \ 2263 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \ 2264 (adev)->pm.funcs->set_fan_control_mode((adev), (m))) 2265 2266 #define amdgpu_dpm_get_fan_control_mode(adev) \ 2267 ((adev)->pp_enabled ? \ 2268 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \ 2269 (adev)->pm.funcs->get_fan_control_mode((adev))) 2270 2271 #define amdgpu_dpm_set_fan_speed_percent(adev, s) \ 2272 ((adev)->pp_enabled ? \ 2273 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ 2274 (adev)->pm.funcs->set_fan_speed_percent((adev), (s))) 2275 2276 #define amdgpu_dpm_get_fan_speed_percent(adev, s) \ 2277 ((adev)->pp_enabled ? \ 2278 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ 2279 (adev)->pm.funcs->get_fan_speed_percent((adev), (s))) 2280 2281 #define amdgpu_dpm_get_sclk(adev, l) \ 2282 ((adev)->pp_enabled ? \ 2283 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \ 2284 (adev)->pm.funcs->get_sclk((adev), (l))) 2285 2286 #define amdgpu_dpm_get_mclk(adev, l) \ 2287 ((adev)->pp_enabled ? \ 2288 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \ 2289 (adev)->pm.funcs->get_mclk((adev), (l))) 2290 2291 2292 #define amdgpu_dpm_force_performance_level(adev, l) \ 2293 ((adev)->pp_enabled ? \ 2294 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \ 2295 (adev)->pm.funcs->force_performance_level((adev), (l))) 2296 2297 #define amdgpu_dpm_powergate_uvd(adev, g) \ 2298 ((adev)->pp_enabled ? \ 2299 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \ 2300 (adev)->pm.funcs->powergate_uvd((adev), (g))) 2301 2302 #define amdgpu_dpm_powergate_vce(adev, g) \ 2303 ((adev)->pp_enabled ? \ 2304 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \ 2305 (adev)->pm.funcs->powergate_vce((adev), (g))) 2306 2307 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \ 2308 ((adev)->pp_enabled ? \ 2309 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \ 2310 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))) 2311 2312 #define amdgpu_dpm_get_current_power_state(adev) \ 2313 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle) 2314 2315 #define amdgpu_dpm_get_performance_level(adev) \ 2316 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle) 2317 2318 #define amdgpu_dpm_get_pp_num_states(adev, data) \ 2319 (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data) 2320 2321 #define amdgpu_dpm_get_pp_table(adev, table) \ 2322 (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table) 2323 2324 #define amdgpu_dpm_set_pp_table(adev, buf, size) \ 2325 (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size) 2326 2327 #define amdgpu_dpm_print_clock_levels(adev, type, buf) \ 2328 (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf) 2329 2330 #define amdgpu_dpm_force_clock_level(adev, type, level) \ 2331 (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level) 2332 2333 #define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \ 2334 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output)) 2335 2336 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) 2337 2338 /* Common functions */ 2339 int amdgpu_gpu_reset(struct amdgpu_device *adev); 2340 void amdgpu_pci_config_reset(struct amdgpu_device *adev); 2341 bool amdgpu_card_posted(struct amdgpu_device *adev); 2342 void amdgpu_update_display_priority(struct amdgpu_device *adev); 2343 bool amdgpu_boot_test_post_card(struct amdgpu_device *adev); 2344 2345 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); 2346 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 2347 u32 ip_instance, u32 ring, 2348 struct amdgpu_ring **out_ring); 2349 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain); 2350 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 2351 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2352 uint32_t flags); 2353 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 2354 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 2355 unsigned long end); 2356 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 2357 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 2358 struct ttm_mem_reg *mem); 2359 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); 2360 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); 2361 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); 2362 void amdgpu_program_register_sequence(struct amdgpu_device *adev, 2363 const u32 *registers, 2364 const u32 array_size); 2365 2366 bool amdgpu_device_is_px(struct drm_device *dev); 2367 /* atpx handler */ 2368 #if defined(CONFIG_VGA_SWITCHEROO) 2369 void amdgpu_register_atpx_handler(void); 2370 void amdgpu_unregister_atpx_handler(void); 2371 #else 2372 static inline void amdgpu_register_atpx_handler(void) {} 2373 static inline void amdgpu_unregister_atpx_handler(void) {} 2374 #endif 2375 2376 /* 2377 * KMS 2378 */ 2379 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 2380 extern int amdgpu_max_kms_ioctl; 2381 2382 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 2383 int amdgpu_driver_unload_kms(struct drm_device *dev); 2384 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 2385 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 2386 void amdgpu_driver_postclose_kms(struct drm_device *dev, 2387 struct drm_file *file_priv); 2388 void amdgpu_driver_preclose_kms(struct drm_device *dev, 2389 struct drm_file *file_priv); 2390 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2391 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2392 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 2393 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 2394 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 2395 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, 2396 int *max_error, 2397 struct timeval *vblank_time, 2398 unsigned flags); 2399 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 2400 unsigned long arg); 2401 2402 /* 2403 * functions used by amdgpu_encoder.c 2404 */ 2405 struct amdgpu_afmt_acr { 2406 u32 clock; 2407 2408 int n_32khz; 2409 int cts_32khz; 2410 2411 int n_44_1khz; 2412 int cts_44_1khz; 2413 2414 int n_48khz; 2415 int cts_48khz; 2416 2417 }; 2418 2419 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 2420 2421 /* amdgpu_acpi.c */ 2422 #if defined(CONFIG_ACPI) 2423 int amdgpu_acpi_init(struct amdgpu_device *adev); 2424 void amdgpu_acpi_fini(struct amdgpu_device *adev); 2425 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 2426 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 2427 u8 perf_req, bool advertise); 2428 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 2429 #else 2430 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 2431 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 2432 #endif 2433 2434 struct amdgpu_bo_va_mapping * 2435 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 2436 uint64_t addr, struct amdgpu_bo **bo); 2437 2438 #include "amdgpu_object.h" 2439 2440 #endif 2441